1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2020 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <debug_uart.h> 8 #include <dm.h> 9 #include <dt-structs.h> 10 #include <ram.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/rk_atags.h> 17 #include <asm/arch/timer.h> 18 #include <asm/arch/grf_rk3308.h> 19 #include <asm/arch/sdram.h> 20 #include <asm/arch/sdram_rk3308.h> 21 #include <asm/arch/sdram_rv1108_pctl_phy.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define CRU_BASE 0xff500000 26 #define GRF_BASE 0xff000000 27 #define SGRF_BASE 0xff2b0000 28 #define DDR_PHY_BASE 0xff530000 29 #define DDR_PCTL_BASE 0xff010000 30 #define DDR_STANDBY_BASE 0xff030000 31 #define PMU_BASS_ADDR 0xff520000 32 #define SERVICE_MSCH_BASE 0xff5c8000 33 34 struct rk3308_ddr_gd ddr_gd = { 35 #include "sdram-rk3308-ddr-skew.inc" 36 }; 37 38 struct sdram_params sdram_configs[] = { 39 #if (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 3) 40 #include "sdram_inc/rk3308/sdram-rk3308-ddr3-detect-589.inc" 41 #elif (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 2) 42 #include "sdram_inc/rk3308/sdram-rk3308-ddr2-detect-451.inc" 43 #elif (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 5) 44 #include "sdram_inc/rk3308/sdram-rk3308-lpddr2-detect-451.inc" 45 #endif 46 }; 47 48 #define DDR3_DDR2_ODT_DISABLE_FREQ (666) 49 50 #define DDR2_TRFC_256MBIT (75) 51 #define DDR2_TRFC_512MBIT (105) 52 #define DDR2_TRFC_1GBIT (128) 53 #define DDR2_TRFC_2GBIT (195) 54 #define DDR2_TRFC_4GBIT (328) 55 56 #define DDR3_TRFC_512MBIT (90) 57 #define DDR3_TRFC_1GBIT (110) 58 #define DDR3_TRFC_2GBIT (160) 59 #define DDR3_TRFC_4GBIT (300) 60 #define DDR3_TRFC_8GBIT (350) 61 62 #define LPDDR2_TRFC_8GBIT (210) /*ns*/ 63 #define LPDDR2_TRFC_4GBIT (130) /*ns*/ 64 #define LPDDR2_TREC_512MBIT (90) /*ns*/ 65 66 void enable_ddr_io_ret(struct dram_info *priv) 67 { 68 rk_clrsetreg(&priv->pmu->sft_con_lo, DDR_IO_RET_CFG_MASK, 69 DDR_IO_RET_CFG << DDR_IO_RET_CFG_SHIFT); 70 71 rk_clrsetreg(&priv->grf->upctl_con0, GRF_DDR_16BIT_EN_MASK, 72 GRF_DDR_16BIT_EN << GRF_DDR_16BIT_EN_SHIFT); 73 } 74 75 void pll_set(u32 pll_type, struct dram_info *priv, 76 struct rockchip_pll_rate_table *pll_priv) 77 { 78 /* pll power down */ 79 rk_clrsetreg(&priv->cru->pll[pll_type].con1, PLLPD0_MASK, 80 PLLPD0_POWER_DOWN << PLLPD0_SHIFT); 81 rk_clrsetreg(&priv->cru->pll[pll_type].con1, 82 DSMPD_MASK, pll_priv->dsmpd << DSMPD_SHIFT); 83 84 /* set pll freq */ 85 rk_clrsetreg(&priv->cru->pll[pll_type].con0, 86 FBDIV_MASK | POSTDIV1_MASK, 87 pll_priv->fbdiv << FBDIV_SHIFT | 88 pll_priv->postdiv1 << POSTDIV1_SHIFT); 89 rk_clrsetreg(&priv->cru->pll[pll_type].con1, 90 POSTDIV2_MASK | REFDIV_MASK, 91 pll_priv->postdiv2 << POSTDIV2_SHIFT | 92 pll_priv->refdiv << REFDIV_SHIFT); 93 writel(pll_priv->frac << FRACDIV_SHIFT, 94 &priv->cru->pll[pll_type].con2); 95 /* pll power up */ 96 rk_clrsetreg(&priv->cru->pll[pll_type].con1, PLLPD0_MASK, 97 PLLPD0_NO_POWER_DOWN << PLLPD0_SHIFT); 98 99 /* wait until pll lock */ 100 while (!(readl(&priv->cru->pll[pll_type].con1) & 101 (1u << PLL_LOCK_SHIFT))) 102 udelay(1); 103 } 104 105 void rkdclk_init(struct dram_info *priv, 106 struct sdram_params *params_priv) 107 { 108 u32 ddr_pll_sel; 109 u32 ddr_phy_div_con; 110 u32 uart_div[5] = {15, 15, 15, 15, 15}; 111 struct rockchip_pll_rate_table rk3308_pll_div; 112 113 /* DPLL VPLL0 VPLL1 mode in 24MHz*/ 114 rk_clrsetreg(&priv->cru->mode, VPLL1_WORK_MODE_MASK, 115 VPLL1_WORK_MODE_XIN_OSC0 << VPLL1_WORK_MODE_SHIFT); 116 rk_clrsetreg(&priv->cru->mode, VPLL0_WORK_MODE_MASK, 117 VPLL0_WORK_MODE_XIN_OSC0 << VPLL0_WORK_MODE_SHIFT); 118 rk_clrsetreg(&priv->cru->mode, DPLL_WORK_MODE_MASK, 119 DPLL_WORK_MODE_XIN_OSC0 << DPLL_WORK_MODE_SHIFT); 120 121 /* set PLL without level shift */ 122 rk_clrsetreg(&priv->cru->mode, VPLL1_CLK_SEL_MASK, 123 VPLL1_CLK_SEL_WITHOUT_LVL_SHIFT << VPLL1_CLK_SEL_SHIFT); 124 rk_clrsetreg(&priv->cru->mode, VPLL0_CLK_SEL_MASK, 125 VPLL0_CLK_SEL_WITHOUT_LVL_SHIFT << VPLL0_CLK_SEL_SHIFT); 126 rk_clrsetreg(&priv->cru->mode, DPLL_CLK_SEL_MASK, 127 DPLL_CLK_SEL_WITHOUT_LVL_SHIFT << DPLL_CLK_SEL_SHIFT); 128 129 /* set vpll1 in 903.168MHz vco = 1.806GHz */ 130 rk3308_pll_div.refdiv = 2; 131 rk3308_pll_div.fbdiv = 150; 132 rk3308_pll_div.postdiv1 = 2; 133 rk3308_pll_div.postdiv2 = 1; 134 rk3308_pll_div.frac = 0x872B02; 135 rk3308_pll_div.dsmpd = 0; 136 pll_set(VPLL1, priv, &rk3308_pll_div); 137 138 if (params_priv->ddr_timing_t.freq == 393) { 139 /* set vpll0 in 786.432MHz vco = 3.146GHz */ 140 rk3308_pll_div.refdiv = 2; 141 rk3308_pll_div.fbdiv = 262; 142 rk3308_pll_div.postdiv1 = 4; 143 rk3308_pll_div.postdiv2 = 1; 144 rk3308_pll_div.frac = 0x24DD2F; 145 rk3308_pll_div.dsmpd = 0; 146 } else { 147 /* set vpll0 in 1179.648MHz, vco = 2.359GHz*/ 148 rk3308_pll_div.refdiv = 2; 149 rk3308_pll_div.fbdiv = 196; 150 rk3308_pll_div.postdiv1 = 2; 151 rk3308_pll_div.postdiv2 = 1; 152 rk3308_pll_div.frac = 0x9BA5E3; 153 rk3308_pll_div.dsmpd = 0; 154 } 155 pll_set(VPLL0, priv, &rk3308_pll_div); 156 157 if (params_priv->ddr_timing_t.freq == 800) { 158 ddr_pll_sel = 0; 159 ddr_phy_div_con = 0; 160 } else if (params_priv->ddr_timing_t.freq == 589) { 161 ddr_pll_sel = 1; 162 ddr_phy_div_con = 0; 163 } else if (params_priv->ddr_timing_t.freq == 451) { 164 ddr_pll_sel = 2; 165 ddr_phy_div_con = 0; 166 } else if (params_priv->ddr_timing_t.freq == 393) { 167 ddr_pll_sel = 1; 168 ddr_phy_div_con = 0; 169 } else if (params_priv->ddr_timing_t.freq == 294) { 170 ddr_pll_sel = 1; 171 ddr_phy_div_con = 1; 172 } else if (params_priv->ddr_timing_t.freq == 225) { 173 ddr_pll_sel = 2; 174 ddr_phy_div_con = 1; 175 } else { 176 printascii("err\n"); 177 while (1) 178 ; 179 } 180 181 /* dpll default set in 1300MHz */ 182 if (params_priv->ddr_timing_t.freq == 800) { 183 /* set dpll in 1584 MHz ,vco=3.168G*/ 184 rk3308_pll_div.refdiv = 1; 185 rk3308_pll_div.fbdiv = 132; 186 rk3308_pll_div.postdiv1 = 2; 187 rk3308_pll_div.postdiv2 = 1; 188 rk3308_pll_div.frac = 0; 189 rk3308_pll_div.dsmpd = 1; 190 } else { 191 /* 1300000000,vco = 1.3GHz */ 192 rk3308_pll_div.refdiv = 6; 193 rk3308_pll_div.fbdiv = 325; 194 rk3308_pll_div.postdiv1 = 1; 195 rk3308_pll_div.postdiv2 = 1; 196 rk3308_pll_div.frac = 0; 197 rk3308_pll_div.dsmpd = 1; 198 } 199 200 pll_set(DPLL, priv, &rk3308_pll_div); 201 202 /* set ddrphy freq */ 203 rk_clrsetreg(&priv->cru->clksel_con[1], 204 DDRPHY4X_PLL_CLK_SEL_MASK | DDRPHY4X_DIV_CON_MASK, 205 ddr_pll_sel << DDRPHY4X_PLL_CLK_SEL_SHIFT | 206 ddr_phy_div_con << DDRPHY4X_DIV_CON_SIHFT); 207 208 /* set aclk_bus 216.7MHz */ 209 rk_clrsetreg(&priv->cru->clksel_con[5], 210 A_H_PCLK_BUS_PLL_SEL_MASK | ACLK_BUS_DIV_CON_MASK, 211 A_H_PCLK_BUS_PLL_SEL_DPLL << A_H_PCLK_BUS_PLL_SEL_SHIFT | 212 ACLK_BUS_DIV_CON_5 << ACLK_BUS_DIV_CON_SHIFT); 213 /* set pclk_bus 50MHz,hclk_bus 92.857MHz */ 214 rk_clrsetreg(&priv->cru->clksel_con[6], 215 PCLK_BUS_DIV_CON_MASK | HCLK_BUS_DIV_CON_MASK, 216 PCLK_BUS_DIV_CON_25 << PCLK_BUS_DIV_CON_SHIFT | 217 HCLK_BUS_DIV_CON_13 << HCLK_BUS_DIV_CON_SHIFT); 218 /* set crypto 92.857MHz,crypto_apk 92.857MHz */ 219 rk_clrsetreg(&priv->cru->clksel_con[7], 220 CLK_CRYPTO_APK_SEL_MASK | CLK_CRYPTO_APK_DIV_MASK | 221 CLK_CRYPTO_PLL_SEL_MASK | CLK_CRYPTO_DIV_CON_MASK, 222 CLK_CRYPTO_APK_SEL_DPLL << CLK_CRYPTO_APK_SEL_SHIFT | 223 CLK_CRYPTO_APK_DIV_13 << CLK_CRYPTO_APK_DIV_SHIFT | 224 CLK_CRYPTO_PLL_SEL_DPLL << CLK_CRYPTO_PLL_SEL_SHIFT | 225 CLK_CRYPTO_DIV_CON_13 << CLK_CRYPTO_DIV_CON_SHIFT); 226 /* set aclk_peri 216.7MHz */ 227 rk_clrsetreg(&priv->cru->clksel_con[36], 228 A_H_P_PERI_PLL_SEL_MASK | ACLK_PERI_DIV_CON_MASK, 229 A_H_P_PERI_PLL_SEL_DPLL << A_H_P_PERI_PLL_SEL_SHIFT | 230 ACLK_PERI_DIV_CON_5 << ACLK_PERI_DIV_CON_SHIFT); 231 /* set hclk_peri 92.857MHz,pclk_peri 46.428MHz */ 232 rk_clrsetreg(&priv->cru->clksel_con[37], 233 PCLK_PERI_DIV_CON_MASK | HCLK_PERI_DIV_CON_MASK, 234 PCLK_PERI_DIV_CON_27 << PCLK_PERI_DIV_CON_SHIFT | 235 HCLK_PERI_DIV_CON_13 << HCLK_PERI_DIV_CON_SHIFT); 236 /* set NANDC 92.857MHz */ 237 rk_clrsetreg(&priv->cru->clksel_con[38], 238 CLK_NANDC_PLL_SEL_MASK | 239 CLK_NANDC_DIV_CON_MASK, 240 CLK_NANDC_PLL_SEL_DPLL << CLK_NANDC_PLL_SEL_SHIFT | 241 CLK_NANDC_DIV_CON_13 << CLK_NANDC_DIV_CON_SHIFT); 242 /* set SDMMC 46.4/(internal freq_div 2)=23.2MHz */ 243 rk_clrsetreg(&priv->cru->clksel_con[39], 244 CLK_SDMMC_PLL_SEL_MASK | 245 CLK_SDMMC_DIV_CON_MASK, 246 CLK_SDMMC_PLL_SEL_DPLL << CLK_SDMMC_PLL_SEL_SHIFT | 247 CLK_SDMMC_DIV_CON_27 << CLK_SDMMC_DIV_CON_SHIFT); 248 /* set emmc 46.4/(internal freq_div 2)=23.2MHz */ 249 rk_clrsetreg(&priv->cru->clksel_con[41], 250 CLK_EMMC_PLL_SEL_MASK | 251 CLK_EMMC_DIV_CON_MASK, 252 CLK_EMMC_PLL_SEL_DPLL << CLK_EMMC_PLL_SEL_SHIFT | 253 CLK_EMMC_DIV_CON_27 << CLK_EMMC_DIV_CON_SHIFT); 254 /* set SFC 24.07/(internal freq_div 2)=12.0MHz */ 255 rk_clrsetreg(&priv->cru->clksel_con[42], 256 CLK_SFC_PLL_SEL_MASK | CLK_SFC_DIV_CON_MASK, 257 CLK_SFC_PLL_SEL_DPLL << CLK_SFC_PLL_SEL_SHIFT | 258 CLK_SFC_DIV_CON_53 << CLK_SFC_DIV_CON_SHIFT); 259 #if defined(CONFIG_DPLL_FREQ_1200MHZ) 260 /*vco=1.2GHz*/ 261 rk3308_pll_div.refdiv = 2; 262 rk3308_pll_div.fbdiv = 100; 263 rk3308_pll_div.postdiv1 = 1; 264 rk3308_pll_div.postdiv2 = 1; 265 rk3308_pll_div.frac = 0; 266 267 /* set dpll in 1200 MHz */ 268 pll_set(DPLL, priv, &rk3308_pll_div); 269 270 /* set aclk_bus 200MHz */ 271 rk_clrsetreg(&priv->cru->clksel_con[5], 272 A_H_PCLK_BUS_PLL_SEL_MASK | ACLK_BUS_DIV_CON_MASK, 273 A_H_PCLK_BUS_PLL_SEL_DPLL << A_H_PCLK_BUS_PLL_SEL_SHIFT | 274 ACLK_BUS_DIV_CON_5 << ACLK_BUS_DIV_CON_SHIFT); 275 /* set pclk_bus 46.15MHz,hclk_bus 100MHz */ 276 rk_clrsetreg(&priv->cru->clksel_con[6], 277 PCLK_BUS_DIV_CON_MASK | HCLK_BUS_DIV_CON_MASK, 278 PCLK_BUS_DIV_CON_25 << PCLK_BUS_DIV_CON_SHIFT | 279 HCLK_BUS_DIV_CON_11 << HCLK_BUS_DIV_CON_SHIFT); 280 /* set crypto,crypto_apk 100MHz */ 281 rk_clrsetreg(&priv->cru->clksel_con[7], 282 CLK_CRYPTO_APK_SEL_MASK | CLK_CRYPTO_APK_DIV_MASK | 283 CLK_CRYPTO_PLL_SEL_MASK | CLK_CRYPTO_DIV_CON_MASK, 284 CLK_CRYPTO_APK_SEL_DPLL << CLK_CRYPTO_APK_SEL_SHIFT | 285 CLK_CRYPTO_APK_DIV_11 << CLK_CRYPTO_APK_DIV_SHIFT | 286 CLK_CRYPTO_PLL_SEL_DPLL << CLK_CRYPTO_PLL_SEL_SHIFT | 287 CLK_CRYPTO_DIV_CON_11 << CLK_CRYPTO_DIV_CON_SHIFT); 288 /* set aclk_peri 200MHz */ 289 rk_clrsetreg(&priv->cru->clksel_con[36], 290 A_H_P_PERI_PLL_SEL_MASK | ACLK_PERI_DIV_CON_MASK, 291 A_H_P_PERI_PLL_SEL_DPLL << A_H_P_PERI_PLL_SEL_SHIFT | 292 ACLK_PERI_DIV_CON_5 << ACLK_PERI_DIV_CON_SHIFT); 293 /* set hclk_peri 100MHz,pclk_peri 50MHz */ 294 rk_clrsetreg(&priv->cru->clksel_con[37], 295 PCLK_PERI_DIV_CON_MASK | HCLK_PERI_DIV_CON_MASK, 296 PCLK_PERI_DIV_CON_23 << PCLK_PERI_DIV_CON_SHIFT | 297 HCLK_PERI_DIV_CON_11 << HCLK_PERI_DIV_CON_SHIFT); 298 /* set NANDC 100MHz */ 299 rk_clrsetreg(&priv->cru->clksel_con[38], 300 CLK_NANDC_PLL_SEL_MASK | 301 CLK_NANDC_DIV_CON_MASK, 302 CLK_NANDC_PLL_SEL_DPLL << CLK_NANDC_PLL_SEL_SHIFT | 303 CLK_NANDC_DIV_CON_11 << CLK_NANDC_DIV_CON_SHIFT); 304 /* set SDMMC 50MHz */ 305 rk_clrsetreg(&priv->cru->clksel_con[39], 306 CLK_SDMMC_PLL_SEL_MASK | 307 CLK_SDMMC_DIV_CON_MASK, 308 CLK_SDMMC_PLL_SEL_DPLL << CLK_SDMMC_PLL_SEL_SHIFT | 309 CLK_SDMMC_DIV_CON_23 << CLK_SDMMC_DIV_CON_SHIFT); 310 /* set emmc 50MHz */ 311 rk_clrsetreg(&priv->cru->clksel_con[41], 312 CLK_EMMC_PLL_SEL_MASK | 313 CLK_EMMC_DIV_CON_MASK, 314 CLK_EMMC_PLL_SEL_DPLL << CLK_EMMC_PLL_SEL_SHIFT | 315 CLK_EMMC_DIV_CON_23 << CLK_EMMC_DIV_CON_SHIFT); 316 /* set SFC 24MHz */ 317 rk_clrsetreg(&priv->cru->clksel_con[42], 318 CLK_SFC_PLL_SEL_MASK | CLK_SFC_DIV_CON_MASK, 319 CLK_SFC_PLL_SEL_DPLL << CLK_SFC_PLL_SEL_SHIFT | 320 CLK_SFC_DIV_CON_49 << CLK_SFC_DIV_CON_SHIFT); 321 322 #elif defined(CONFIG_DPLL_FREQ_748MHZ) 323 /*vco=1.5GHz*/ 324 rk3308_pll_div.refdiv = 6; 325 rk3308_pll_div.fbdiv = 374; 326 rk3308_pll_div.postdiv1 = 2; 327 rk3308_pll_div.postdiv2 = 1; 328 rk3308_pll_div.frac = 0; 329 330 /* set dpll in 748 MHz */ 331 pll_set(DPLL, priv, &rk3308_pll_div); 332 333 /* set aclk_bus 187MHz */ 334 rk_clrsetreg(&priv->cru->clksel_con[5], 335 A_H_PCLK_BUS_PLL_SEL_MASK | ACLK_BUS_DIV_CON_MASK, 336 A_H_PCLK_BUS_PLL_SEL_DPLL << A_H_PCLK_BUS_PLL_SEL_SHIFT | 337 ACLK_BUS_DIV_CON_3 << ACLK_BUS_DIV_CON_SHIFT); 338 /* set pclk_bus 46.75MHz,hclk_bus 93.5MHz */ 339 rk_clrsetreg(&priv->cru->clksel_con[6], 340 PCLK_BUS_DIV_CON_MASK | HCLK_BUS_DIV_CON_MASK, 341 PCLK_BUS_DIV_CON_15 << PCLK_BUS_DIV_CON_SHIFT | 342 HCLK_BUS_DIV_CON_7 << HCLK_BUS_DIV_CON_SHIFT); 343 /* set crypto,crypto_apk 93.5MHz */ 344 rk_clrsetreg(&priv->cru->clksel_con[7], 345 CLK_CRYPTO_APK_SEL_MASK | CLK_CRYPTO_APK_DIV_MASK | 346 CLK_CRYPTO_PLL_SEL_MASK | CLK_CRYPTO_DIV_CON_MASK, 347 CLK_CRYPTO_APK_SEL_DPLL << CLK_CRYPTO_APK_SEL_SHIFT | 348 CLK_CRYPTO_APK_DIV_7 << CLK_CRYPTO_APK_DIV_SHIFT | 349 CLK_CRYPTO_PLL_SEL_DPLL << CLK_CRYPTO_PLL_SEL_SHIFT | 350 CLK_CRYPTO_DIV_CON_7 << CLK_CRYPTO_DIV_CON_SHIFT); 351 /* set aclk_peri 187MHz */ 352 rk_clrsetreg(&priv->cru->clksel_con[36], 353 A_H_P_PERI_PLL_SEL_MASK | ACLK_PERI_DIV_CON_MASK, 354 A_H_P_PERI_PLL_SEL_DPLL << A_H_P_PERI_PLL_SEL_SHIFT | 355 ACLK_PERI_DIV_CON_3 << ACLK_PERI_DIV_CON_SHIFT); 356 /* set hclk_peri 93.5MHz,pclk_peri 46.75MHz */ 357 rk_clrsetreg(&priv->cru->clksel_con[37], 358 PCLK_PERI_DIV_CON_MASK | HCLK_PERI_DIV_CON_MASK, 359 PCLK_PERI_DIV_CON_15 << PCLK_PERI_DIV_CON_SHIFT | 360 HCLK_PERI_DIV_CON_7 << HCLK_PERI_DIV_CON_SHIFT); 361 /* set NANDC 93.5MHz */ 362 rk_clrsetreg(&priv->cru->clksel_con[38], 363 CLK_NANDC_PLL_SEL_MASK | 364 CLK_NANDC_DIV_CON_MASK, 365 CLK_NANDC_SEL50_ALWAYS << CLK_NANDC_SEL50_SHIFT | 366 CLK_NANDC_PLL_SEL_DPLL << CLK_NANDC_PLL_SEL_SHIFT | 367 CLK_NANDC_DIV_CON_7 << CLK_NANDC_DIV_CON_SHIFT); 368 /* set NANDC 46.75MHz */ 369 rk_clrsetreg(&priv->cru->clksel_con[39], 370 CLK_SDMMC_PLL_SEL_MASK | 371 CLK_SDMMC_DIV_CON_MASK, 372 CLK_SDMMC_PLL_SEL_DPLL << CLK_SDMMC_PLL_SEL_SHIFT | 373 CLK_SDMMC_DIV_CON_15 << CLK_SDMMC_DIV_CON_SHIFT); 374 /* set emmc 46.75MHz */ 375 rk_clrsetreg(&priv->cru->clksel_con[41], 376 CLK_EMMC_PLL_SEL_MASK | 377 CLK_EMMC_DIV_CON_MASK, 378 CLK_EMMC_PLL_SEL_DPLL << CLK_EMMC_PLL_SEL_SHIFT | 379 CLK_EMMC_DIV_CON_15 << CLK_EMMC_DIV_CON_SHIFT); 380 /* set SFC 23.375MHz */ 381 rk_clrsetreg(&priv->cru->clksel_con[42], 382 CLK_SFC_PLL_SEL_MASK | CLK_SFC_DIV_CON_MASK, 383 CLK_SFC_PLL_SEL_DPLL << CLK_SFC_PLL_SEL_SHIFT | 384 CLK_SFC_DIV_CON_31 << CLK_SFC_DIV_CON_SHIFT); 385 386 #endif 387 /* set spdif tx lower than 100Mhz */ 388 rk_clrsetreg(&priv->cru->clksel_con[48], 389 CLK_SPDIFTX_DIV_CON_MASK, 390 CLK_SPDIFTX_DIV_CON_15 << CLK_SPDIFTX_DIV_CON_SHIFT); 391 392 if (UART_INFO_ID(ddr_gd.head_info.g_uart_info) < 5) 393 uart_div[UART_INFO_ID(ddr_gd.head_info.g_uart_info)] = 0; 394 395 /* set uart0~4 lower than 100Mhz */ 396 rk_clrsetreg(&priv->cru->clksel_con[10], 397 CLK_UART0_DIV_CON_MASK, 398 uart_div[0] << CLK_UART0_DIV_CON_SHIFT); 399 rk_clrsetreg(&priv->cru->clksel_con[13], 400 CLK_UART1_DIV_CON_MASK, 401 uart_div[1] << CLK_UART1_DIV_CON_SHIFT); 402 rk_clrsetreg(&priv->cru->clksel_con[16], 403 CLK_UART2_DIV_CON_MASK, 404 uart_div[2] << CLK_UART2_DIV_CON_SHIFT); 405 rk_clrsetreg(&priv->cru->clksel_con[19], 406 CLK_UART3_DIV_CON_MASK, 407 uart_div[3] << CLK_UART3_DIV_CON_SHIFT); 408 rk_clrsetreg(&priv->cru->clksel_con[22], 409 CLK_UART4_DIV_CON_MASK, 410 uart_div[4] << CLK_UART4_DIV_CON_SHIFT); 411 412 /* pll clk in pll out */ 413 rk_clrsetreg(&priv->cru->mode, VPLL1_WORK_MODE_MASK, 414 VPLL1_WORK_MODE_PLL << VPLL1_WORK_MODE_SHIFT); 415 rk_clrsetreg(&priv->cru->mode, VPLL0_WORK_MODE_MASK, 416 VPLL0_WORK_MODE_PLL << VPLL0_WORK_MODE_SHIFT); 417 rk_clrsetreg(&priv->cru->mode, DPLL_WORK_MODE_MASK, 418 DPLL_WORK_MODE_PLL << DPLL_WORK_MODE_SHIFT); 419 } 420 421 void phy_pctrl_reset_cru(struct dram_info *priv) 422 { 423 rk_clrsetreg(&priv->cru->softrst_con[1], 424 PRESETN_DDRPHY_REQ_MASK | RESETN_DDRPHYDIV_REQ_MASK | 425 RESETN_DDRPHY_REQ_MASK | PRESETN_DDRUPCTL_REQ_MASK | 426 RESETN_DDRUPCTL_REQ_MASK, 427 PRESETN_DDRPHY_REQ_EN << PRESETN_DDRPHY_REQ_SHIFT | 428 RESETN_DDRPHYDIV_REQ_EN << RESETN_DDRPHYDIV_REQ_SHIFT | 429 RESETN_DDRPHY_REQ_EN << RESETN_DDRPHY_REQ_SHIFT | 430 PRESETN_DDRUPCTL_REQ_EN << PRESETN_DDRUPCTL_REQ_SHIFT | 431 RESETN_DDRUPCTL_REQ_EN << RESETN_DDRUPCTL_REQ_SHIFT); 432 udelay(10); 433 434 rk_clrsetreg(&priv->cru->softrst_con[1], 435 PRESETN_DDRPHY_REQ_MASK | RESETN_DDRPHYDIV_REQ_MASK | 436 RESETN_DDRPHY_REQ_MASK, 437 PRESETN_DDRPHY_REQ_DIS << PRESETN_DDRPHY_REQ_SHIFT | 438 RESETN_DDRPHYDIV_REQ_DIS << RESETN_DDRPHYDIV_REQ_SHIFT | 439 RESETN_DDRPHY_REQ_DIS << RESETN_DDRPHY_REQ_SHIFT); 440 udelay(10); 441 442 rk_clrsetreg(&priv->cru->softrst_con[1], 443 PRESETN_DDRUPCTL_REQ_MASK | RESETN_DDRUPCTL_REQ_MASK, 444 PRESETN_DDRUPCTL_REQ_DIS << PRESETN_DDRUPCTL_REQ_SHIFT | 445 RESETN_DDRUPCTL_REQ_DIS << RESETN_DDRUPCTL_REQ_SHIFT); 446 udelay(10); 447 } 448 449 void pctl_cfg_grf(struct dram_info *priv, 450 struct sdram_params *params_priv) 451 { 452 if (params_priv->ddr_config_t.ddr_type == DDR3 || 453 params_priv->ddr_config_t.ddr_type == DDR2) 454 rk_clrsetreg(&priv->grf->soc_con12, NOC_MSCH_MAINDDR3_MASK, 455 NOC_MSCH_MAINDDR3_EN << NOC_MSCH_MAINDDR3_SHIFT); 456 else 457 rk_clrsetreg(&priv->grf->soc_con12, NOC_MSCH_MAINDDR3_MASK, 458 NOC_MSCH_MAINDDR3_DIS << NOC_MSCH_MAINDDR3_SHIFT); 459 } 460 461 void ddr_msch_cfg(struct dram_info *priv, 462 struct sdram_params *params_priv) 463 { 464 writel(BWRATIO_HALF_BW | params_priv->ddr_timing_t.noc_timing.d32, 465 &priv->service_msch->ddrtiming); 466 writel(params_priv->ddr_timing_t.readlatency, 467 &priv->service_msch->readlatency); 468 } 469 470 void ddr_msch_cfg_rbc(struct sdram_params *params_priv, 471 struct dram_info *priv) 472 { 473 int i = 0; 474 475 if (params_priv->ddr_config_t.bank == 3) { 476 /* bank = 8 */ 477 if (params_priv->ddr_config_t.col == 10) 478 i = 1; 479 else if (params_priv->ddr_config_t.col == 11) 480 i = 2; 481 else 482 goto msch_err; 483 484 } else if (params_priv->ddr_config_t.bank == 2) { 485 /* bank = 4 */ 486 i = 0; 487 } else { 488 goto msch_err; 489 } 490 491 writel(i, &priv->service_msch->ddrconf); 492 return; 493 494 msch_err: 495 printascii("msch_err\n"); 496 while (1) 497 ; 498 } 499 500 void ddr_phy_skew_cfg(struct dram_info *priv) 501 { 502 copy_to_reg(&priv->phy->phy_reg_ca_skew[0], 503 &ddr_gd.ddr_skew.a0_a1_skew[0], 14 * 4); 504 copy_to_reg(&priv->phy->phy_reg_skew_cs0data[0], 505 &ddr_gd.ddr_skew.cs0_dm0_skew[0], 22 * 4); 506 507 writel(PHY_TX_DE_SKEW_EN << PHY_TX_DE_SKEW_SHIFT, 508 &priv->phy->phy_reg2); 509 } 510 511 void set_ds_odt(struct dram_info *priv, 512 struct sdram_params *params_priv) 513 { 514 /* set phy drive resistance */ 515 writel(PHY_RON_RTT_56OHM, &priv->phy->phy_reg11); 516 clrsetbits_le32(&priv->phy->phy_reg12, CMD_PRCOMP_MASK, 517 PHY_RON_RTT_56OHM << CMD_PRCOMP_SHIFT); 518 519 writel(PHY_RON_RTT_45OHM, &priv->phy->phy_reg16); 520 writel(PHY_RON_RTT_45OHM, &priv->phy->phy_reg18); 521 writel(PHY_RON_RTT_56OHM, &priv->phy->phy_reg20); 522 writel(PHY_RON_RTT_56OHM, &priv->phy->phy_reg2f); 523 writel(PHY_RON_RTT_56OHM, &priv->phy->phy_reg30); 524 writel(PHY_RON_RTT_56OHM, &priv->phy->phy_reg3f); 525 if (params_priv->ddr_config_t.ddr_type == LPDDR2) { 526 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg21); 527 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg2e); 528 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg31); 529 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg3e); 530 } else { 531 if (params_priv->ddr_timing_t.freq > 532 DDR3_DDR2_ODT_DISABLE_FREQ) { 533 /*set phy odt*/ 534 writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg21); 535 writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg2e); 536 writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg31); 537 writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg3e); 538 } else { 539 /*disable phy odt*/ 540 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg21); 541 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg2e); 542 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg31); 543 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg3e); 544 } 545 } 546 } 547 548 void ddr_phy_dqs_rx_dll_cfg(struct dram_info *priv, u32 freq) 549 { 550 if (freq > 736) { 551 /* 22.5 degree delay */ 552 writel(LEFT_CHN_A_READ_DQS_22_5_DELAY, &priv->phy->phy_reg28); 553 writel(RIGHT_CHN_A_READ_DQS_22_5_DELAY, &priv->phy->phy_reg38); 554 } else if (freq > 441) { 555 /* 45 degree delay */ 556 writel(LEFT_CHN_A_READ_DQS_45_DELAY, &priv->phy->phy_reg28); 557 writel(RIGHT_CHN_A_READ_DQS_45_DELAY, &priv->phy->phy_reg38); 558 } 559 } 560 561 void ddr_msch_get_max_col(struct dram_info *priv, 562 struct ddr_schedule *sch_priv) 563 { 564 writel(2, &priv->service_msch->ddrconf); 565 sch_priv->col = 11; 566 sch_priv->bank = 3; 567 } 568 569 void ddr_msch_get_max_row(struct dram_info *priv, 570 struct ddr_schedule *sch_priv) 571 { 572 writel(1, &priv->service_msch->ddrconf); 573 sch_priv->row = 15; 574 sch_priv->col = 10; 575 sch_priv->bank = 3; 576 } 577 578 void enable_ddr_standby(struct dram_info *priv, 579 struct sdram_params *params_priv) 580 { 581 rk_clrsetreg(&priv->grf->upctl_con0, CYSYREQ_UPCTL_DDRSTDBY_MASK, 582 CYSYREQ_UPCTL_DDRSTDBY_EN << 583 CYSYREQ_UPCTL_DDRSTDBY_SHIFT); 584 585 /* CG_EXIT_TH is equal phy dll lock time when we gate phy 4x clk */ 586 writel(CG_EXIT_TH << CG_EXIT_TH_SHIFT, &priv->standby->con1); 587 588 if (params_priv->stdby_idle == 128) { 589 if (params_priv->ddr_timing_t.freq == 451) 590 params_priv->stdby_idle = 105; 591 else if (params_priv->ddr_timing_t.freq == 393) 592 params_priv->stdby_idle = 10; 593 } 594 writel(params_priv->stdby_idle << IDLE_TH_SHIFT | 595 DDRPHY4X_GATE_EN << DDRPHY4X_GATE_SHIFT | 596 UPCTL_CORE_CLK_GATE_EN << UPCTL_CORE_CLK_GATE_SHIFT | 597 UPCTL_ACLK_GATE_EN << UPCTL_ACLK_GATE_SHIFT | 598 CTL_IDLR_EN << CTL_IDLR_SHIFT | 599 STDBY_EN << STDBY_EN_SHIFT, &priv->standby->con0); 600 601 while (1) { 602 if ((readl(&priv->standby->status0) & 603 STDBY_STATUS_MASK) == ST_STDBY) { 604 break; 605 } 606 } 607 } 608 609 void ddr_set_atags(void) 610 { 611 struct tag_serial t_serial; 612 613 memset(&t_serial, 0, sizeof(struct tag_serial)); 614 #ifdef CONFIG_DRAM_INIT_BUILD 615 u32 uart_info; 616 617 t_serial.version = 0; 618 uart_info = ddr_gd.head_info.g_uart_info; 619 if (UART_INFO_ID(uart_info) >= MAX_UART_NUMBER_) { 620 t_serial.enable = 0; 621 } else { 622 t_serial.enable = 1; 623 t_serial.baudrate = UART_INFO_BAUD(uart_info); 624 t_serial.m_mode = UART_INFO_IOMUX(uart_info); 625 t_serial.id = UART_INFO_ID(uart_info); 626 if (UART_INFO_ID(uart_info) == 0) 627 t_serial.addr = UART0_BASE; 628 else if (UART_INFO_ID(uart_info) == 1) 629 t_serial.addr = UART1_BASE; 630 else if (UART_INFO_ID(uart_info) == 2) 631 t_serial.addr = UART2_BASE; 632 else if (UART_INFO_ID(uart_info) == 3) 633 t_serial.addr = UART3_BASE; 634 else 635 t_serial.addr = UART4_BASE; 636 } 637 #else 638 /* set serial data to &t_serial */ 639 #if defined(CONFIG_DEBUG_UART_BASE) 640 t_serial.version = 0; 641 t_serial.enable = 1; 642 t_serial.addr = CONFIG_DEBUG_UART_BASE; 643 t_serial.baudrate = CONFIG_BAUDRATE; 644 645 #if (CONFIG_DEBUG_UART_BASE == 0xFF0A0000) 646 /* uart0 as debug uart */ 647 t_serial.m_mode = SERIAL_M_MODE_M0; 648 t_serial.id = 0; 649 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0B0000) 650 /* uart1 as debug uart */ 651 t_serial.m_mode = SERIAL_M_MODE_M0; 652 t_serial.id = 1; 653 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0C0000) 654 #if (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0) 655 t_serial.m_mode = SERIAL_M_MODE_M0; 656 #elif (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1) 657 /* uart2 m1 as debug uart */ 658 t_serial.m_mode = SERIAL_M_MODE_M1; 659 #else 660 #error "Please select M0 or M1 for uart2 !!!" 661 #endif 662 t_serial.id = 2; 663 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0D0000) 664 /* uart3 as debug uart */ 665 t_serial.m_mode = SERIAL_M_MODE_M0; 666 t_serial.id = 3; 667 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0E0000) 668 /* uart4 as debug uart */ 669 t_serial.m_mode = SERIAL_M_MODE_M0; 670 t_serial.id = 4; 671 #else 672 #error "Please select proper uart as debug uart !!!" 673 #endif 674 675 #endif /* defined(CONFIG_DEBUG_UART_BASE) */ 676 #endif /* CONFIG_DRAM_INIT_BUILD */ 677 678 /* First pre-loader must call it before atags_set_tag() */ 679 atags_destroy(); 680 atags_set_tag(ATAG_SERIAL, &t_serial); 681 } 682 683 static void modify_sdram_params(struct dram_info *priv, 684 struct sdram_params *params_priv) 685 { 686 u32 tmp = 0; 687 u32 bw = 1; 688 u32 nMHz = params_priv->ddr_timing_t.freq; 689 690 size_t size = 1llu << (bw + 691 params_priv->ddr_config_t.col + 692 params_priv->ddr_config_t.cs0_row + 693 params_priv->ddr_config_t.bank); 694 695 move_to_config_state(priv); 696 switch (params_priv->ddr_config_t.ddr_type) { 697 case DDR2: 698 if (size <= 0x4000000) 699 tmp = DDR2_TRFC_512MBIT; 700 else if (size <= 0x8000000) 701 tmp = DDR2_TRFC_1GBIT; 702 else if (size <= 0x10000000) 703 tmp = DDR2_TRFC_2GBIT; 704 else 705 tmp = DDR2_TRFC_4GBIT; 706 707 priv->pctl->trfc = (tmp * nMHz + 999) / 1000; 708 tmp = (((tmp + 10) * nMHz + 999) / 1000); 709 if (tmp < 200) 710 tmp = 200; 711 priv->pctl->texsr = tmp & 0x3FF; 712 break; 713 case DDR3: 714 if (size <= 0x4000000) 715 tmp = DDR3_TRFC_512MBIT; 716 else if (size <= 0x8000000) 717 tmp = DDR3_TRFC_1GBIT; 718 else if (size <= 0x10000000) 719 tmp = DDR3_TRFC_2GBIT; 720 else if (size <= 0x20000000) 721 tmp = DDR3_TRFC_4GBIT; 722 else 723 tmp = DDR3_TRFC_8GBIT; 724 priv->pctl->trfc = (tmp * nMHz + 999) / 1000; 725 break; 726 case LPDDR2: 727 if (size <= 0x4000000) 728 tmp = LPDDR2_TREC_512MBIT; 729 else if (size <= 0x20000000) 730 tmp = LPDDR2_TRFC_4GBIT; 731 else 732 tmp = LPDDR2_TRFC_8GBIT; 733 734 priv->pctl->trfc = (tmp * nMHz + 999) / 1000; 735 tmp = (((tmp + 10) * nMHz + 999) / 1000); 736 if (tmp < 2) 737 tmp = 2; 738 priv->pctl->texsr = tmp & 0x3FF; 739 break; 740 } 741 move_to_access_state(priv); 742 } 743 744 int check_rd_gate(struct dram_info *priv) 745 { 746 u32 max_val = 0; 747 u32 min_val = 0xff; 748 u32 gate[2]; 749 750 gate[0] = readl(&priv->phy->phy_regfb); 751 gate[1] = readl(&priv->phy->phy_regfc); 752 max_val = max(gate[0], gate[1]); 753 min_val = min(gate[0], gate[1]); 754 755 if (max_val > 0x80 || min_val < 0x20) 756 return -1; 757 else 758 return 0; 759 } 760 761 static u32 dram_test(u32 i, u32 dqs) 762 { 763 for (phys_addr_t j = 4 * dqs; j < 0x2000; j += 8) 764 writel(PATTERN + i, j); 765 766 for (phys_addr_t j = 4 * dqs; j < 0x2000; j += 8) 767 if ((PATTERN + i) != readl(j)) 768 return 1; 769 770 return 0; 771 } 772 773 /** 774 * modify_data_training() - Setting DQS gating calibration bypass, 775 * scanning data training range and then select center one. 776 */ 777 #define PHY_REG3C(n) (0x10 * (n)) 778 779 void modify_data_training(struct dram_info *priv, 780 struct sdram_params *params_priv) 781 { 782 u32 value = 0; 783 u32 i = 0, dqs = 0; 784 u32 max_value = 0, min_value = 0; 785 786 writel(readl(&priv->phy->phy_regfb), &priv->phy->phy_reg2c); 787 writel(readl(&priv->phy->phy_regfc), &priv->phy->phy_reg3c); 788 789 /* DQS gating calibration bypass */ 790 setbits_le32(&priv->phy->phy_reg2, BIT(1)); 791 792 /* rk3308 only support DQS0, DQS1 */ 793 for (dqs = 0; dqs < 2; dqs++) { 794 value = readl(&priv->phy->phy_regfb + dqs); 795 i = 0; 796 while (dram_test(i, dqs) == 0) { 797 i++; 798 writel(value + i, 799 &priv->phy->phy_reg2c + PHY_REG3C(dqs)); 800 } 801 max_value = value + i - 1; 802 803 i = 1; 804 writel(value - i, &priv->phy->phy_reg2c + PHY_REG3C(dqs)); 805 while (dram_test(i, dqs) == 0) { 806 i++; 807 writel(value - i, 808 &priv->phy->phy_reg2c + PHY_REG3C(dqs)); 809 } 810 min_value = value - i + 1; 811 812 /* select center one as gate training result */ 813 writel((max_value + min_value + 1) / 2, 814 &priv->phy->phy_reg2c + PHY_REG3C(dqs)); 815 } 816 printascii("REG2C: 0x"); 817 printhex8(readl(&priv->phy->phy_reg2c)); 818 printascii(", 0x"); 819 printhex8(readl(&priv->phy->phy_reg3c)); 820 printascii("\n"); 821 } 822 823 void enable_low_power(struct dram_info *priv, 824 struct sdram_params *params_priv) 825 { 826 move_to_config_state(priv); 827 828 if (params_priv->idle_pd == 48 && params_priv->idle_sr == 10) { 829 if (params_priv->ddr_timing_t.freq == 451) { 830 params_priv->idle_sr = 28; 831 params_priv->idle_pd = 7; 832 } else if (params_priv->ddr_timing_t.freq == 393) { 833 params_priv->idle_sr = 31; 834 params_priv->idle_pd = 15; 835 } 836 } 837 clrsetbits_le32(&priv->pctl->mcfg, PD_IDLE_MASK, 838 params_priv->idle_pd << PD_IDLE_SHIFT); 839 clrsetbits_le32(&priv->pctl->mcfg1, 840 SR_IDLE_MASK | HW_EXIT_IDLE_EN_MASK, 841 params_priv->idle_sr | HW_EXIT_IDLE_EN); 842 843 /* uPCTL in low_power status because of auto self-refresh */ 844 writel(GO_STATE, &priv->pctl->sctl); 845 } 846 847 int get_uart_config(void) 848 { 849 return ddr_gd.head_info.g_uart_info; 850 } 851 852 int sdram_init(void) 853 { 854 struct dram_info sdram_priv; 855 struct sdram_params *params = sdram_configs; 856 857 sdram_priv.cru = (void *)CRU_BASE; 858 sdram_priv.grf = (void *)GRF_BASE; 859 sdram_priv.sgrf = (void *)SGRF_BASE; 860 sdram_priv.phy = (void *)DDR_PHY_BASE; 861 sdram_priv.pctl = (void *)DDR_PCTL_BASE; 862 sdram_priv.standby = (void *)DDR_STANDBY_BASE; 863 sdram_priv.pmu = (void *)PMU_BASS_ADDR; 864 sdram_priv.service_msch = (void *)SERVICE_MSCH_BASE; 865 params->idle_pd = PD_INFO(ddr_gd.head_info.g_sr_pd_idle); 866 params->idle_sr = SR_INFO(ddr_gd.head_info.g_sr_pd_idle); 867 params->ddr_2t_en = DDR_2T_INFO(ddr_gd.head_info.g_2t_info); 868 params->stdby_idle = STANDBY_IDLE(ddr_gd.head_info.g_ch_info); 869 870 rv1108_sdram_init(&sdram_priv, params); 871 872 modify_sdram_params(&sdram_priv, params); 873 874 if (params->idle_pd != 0 && params->idle_sr != 0) 875 enable_ddr_standby(&sdram_priv, params); 876 ddr_set_atags(); 877 printascii("OUT\n"); 878 879 return 0; 880 } 881