1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2020 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 8 #ifdef CONFIG_TPL_BUILD 9 #include <debug_uart.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <ram.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/rk_atags.h> 19 #include <asm/arch/timer.h> 20 #include <asm/arch/grf_rk3308.h> 21 #include <asm/arch/sdram.h> 22 #include <asm/arch/sdram_rk3308.h> 23 #include <asm/arch/sdram_rv1108_pctl_phy.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define CRU_BASE 0xff500000 28 #define GRF_BASE 0xff000000 29 #define SGRF_BASE 0xff2b0000 30 #define DDR_PHY_BASE 0xff530000 31 #define DDR_PCTL_BASE 0xff010000 32 #define DDR_STANDBY_BASE 0xff030000 33 #define PMU_BASS_ADDR 0xff520000 34 #define SERVICE_MSCH_BASE 0xff5c8000 35 36 struct rk3308_ddr_gd ddr_gd = { 37 #include "sdram-rk3308-ddr-skew.inc" 38 }; 39 40 struct sdram_params sdram_configs[] = { 41 #if (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 3) 42 #include "sdram_inc/rk3308/sdram-rk3308-ddr3-detect-589.inc" 43 #elif (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 2) 44 #include "sdram_inc/rk3308/sdram-rk3308-ddr2-detect-451.inc" 45 #elif (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 5) 46 #include "sdram_inc/rk3308/sdram-rk3308-lpddr2-detect-451.inc" 47 #endif 48 }; 49 50 #define DDR3_DDR2_ODT_DISABLE_FREQ (666) 51 52 #define DDR2_TRFC_256MBIT (75) 53 #define DDR2_TRFC_512MBIT (105) 54 #define DDR2_TRFC_1GBIT (128) 55 #define DDR2_TRFC_2GBIT (195) 56 #define DDR2_TRFC_4GBIT (328) 57 58 #define DDR3_TRFC_512MBIT (90) 59 #define DDR3_TRFC_1GBIT (110) 60 #define DDR3_TRFC_2GBIT (160) 61 #define DDR3_TRFC_4GBIT (300) 62 #define DDR3_TRFC_8GBIT (350) 63 64 #define LPDDR2_TRFC_8GBIT (210) /*ns*/ 65 #define LPDDR2_TRFC_4GBIT (130) /*ns*/ 66 #define LPDDR2_TREC_512MBIT (90) /*ns*/ 67 68 void enable_ddr_io_ret(struct dram_info *priv) 69 { 70 rk_clrsetreg(&priv->pmu->sft_con_lo, DDR_IO_RET_CFG_MASK, 71 DDR_IO_RET_CFG << DDR_IO_RET_CFG_SHIFT); 72 73 rk_clrsetreg(&priv->grf->upctl_con0, GRF_DDR_16BIT_EN_MASK, 74 GRF_DDR_16BIT_EN << GRF_DDR_16BIT_EN_SHIFT); 75 } 76 77 void pll_set(u32 pll_type, struct dram_info *priv, 78 struct rockchip_pll_rate_table *pll_priv) 79 { 80 /* pll power down */ 81 rk_clrsetreg(&priv->cru->pll[pll_type].con1, PLLPD0_MASK, 82 PLLPD0_POWER_DOWN << PLLPD0_SHIFT); 83 rk_clrsetreg(&priv->cru->pll[pll_type].con1, 84 DSMPD_MASK, pll_priv->dsmpd << DSMPD_SHIFT); 85 86 /* set pll freq */ 87 rk_clrsetreg(&priv->cru->pll[pll_type].con0, 88 FBDIV_MASK | POSTDIV1_MASK, 89 pll_priv->fbdiv << FBDIV_SHIFT | 90 pll_priv->postdiv1 << POSTDIV1_SHIFT); 91 rk_clrsetreg(&priv->cru->pll[pll_type].con1, 92 POSTDIV2_MASK | REFDIV_MASK, 93 pll_priv->postdiv2 << POSTDIV2_SHIFT | 94 pll_priv->refdiv << REFDIV_SHIFT); 95 writel(pll_priv->frac << FRACDIV_SHIFT, 96 &priv->cru->pll[pll_type].con2); 97 /* pll power up */ 98 rk_clrsetreg(&priv->cru->pll[pll_type].con1, PLLPD0_MASK, 99 PLLPD0_NO_POWER_DOWN << PLLPD0_SHIFT); 100 101 /* wait until pll lock */ 102 while (!(readl(&priv->cru->pll[pll_type].con1) & 103 (1u << PLL_LOCK_SHIFT))) 104 udelay(1); 105 } 106 107 void rkdclk_init(struct dram_info *priv, 108 struct sdram_params *params_priv) 109 { 110 u32 ddr_pll_sel; 111 u32 ddr_phy_div_con; 112 u32 uart_div[5] = {15, 15, 15, 15, 15}; 113 struct rockchip_pll_rate_table rk3308_pll_div; 114 115 /* DPLL VPLL0 VPLL1 mode in 24MHz*/ 116 rk_clrsetreg(&priv->cru->mode, VPLL1_WORK_MODE_MASK, 117 VPLL1_WORK_MODE_XIN_OSC0 << VPLL1_WORK_MODE_SHIFT); 118 rk_clrsetreg(&priv->cru->mode, VPLL0_WORK_MODE_MASK, 119 VPLL0_WORK_MODE_XIN_OSC0 << VPLL0_WORK_MODE_SHIFT); 120 rk_clrsetreg(&priv->cru->mode, DPLL_WORK_MODE_MASK, 121 DPLL_WORK_MODE_XIN_OSC0 << DPLL_WORK_MODE_SHIFT); 122 123 /* set PLL without level shift */ 124 rk_clrsetreg(&priv->cru->mode, VPLL1_CLK_SEL_MASK, 125 VPLL1_CLK_SEL_WITHOUT_LVL_SHIFT << VPLL1_CLK_SEL_SHIFT); 126 rk_clrsetreg(&priv->cru->mode, VPLL0_CLK_SEL_MASK, 127 VPLL0_CLK_SEL_WITHOUT_LVL_SHIFT << VPLL0_CLK_SEL_SHIFT); 128 rk_clrsetreg(&priv->cru->mode, DPLL_CLK_SEL_MASK, 129 DPLL_CLK_SEL_WITHOUT_LVL_SHIFT << DPLL_CLK_SEL_SHIFT); 130 131 /* set vpll1 in 903.168MHz vco = 1.806GHz */ 132 rk3308_pll_div.refdiv = 2; 133 rk3308_pll_div.fbdiv = 150; 134 rk3308_pll_div.postdiv1 = 2; 135 rk3308_pll_div.postdiv2 = 1; 136 rk3308_pll_div.frac = 0x872B02; 137 rk3308_pll_div.dsmpd = 0; 138 pll_set(VPLL1, priv, &rk3308_pll_div); 139 140 if (params_priv->ddr_timing_t.freq == 393) { 141 /* set vpll0 in 786.432MHz vco = 3.146GHz */ 142 rk3308_pll_div.refdiv = 2; 143 rk3308_pll_div.fbdiv = 262; 144 rk3308_pll_div.postdiv1 = 4; 145 rk3308_pll_div.postdiv2 = 1; 146 rk3308_pll_div.frac = 0x24DD2F; 147 rk3308_pll_div.dsmpd = 0; 148 } else { 149 /* set vpll0 in 1179.648MHz, vco = 2.359GHz*/ 150 rk3308_pll_div.refdiv = 2; 151 rk3308_pll_div.fbdiv = 196; 152 rk3308_pll_div.postdiv1 = 2; 153 rk3308_pll_div.postdiv2 = 1; 154 rk3308_pll_div.frac = 0x9BA5E3; 155 rk3308_pll_div.dsmpd = 0; 156 } 157 pll_set(VPLL0, priv, &rk3308_pll_div); 158 159 if (params_priv->ddr_timing_t.freq == 800) { 160 ddr_pll_sel = 0; 161 ddr_phy_div_con = 0; 162 } else if (params_priv->ddr_timing_t.freq == 589) { 163 ddr_pll_sel = 1; 164 ddr_phy_div_con = 0; 165 } else if (params_priv->ddr_timing_t.freq == 451) { 166 ddr_pll_sel = 2; 167 ddr_phy_div_con = 0; 168 } else if (params_priv->ddr_timing_t.freq == 393) { 169 ddr_pll_sel = 1; 170 ddr_phy_div_con = 0; 171 } else if (params_priv->ddr_timing_t.freq == 294) { 172 ddr_pll_sel = 1; 173 ddr_phy_div_con = 1; 174 } else if (params_priv->ddr_timing_t.freq == 225) { 175 ddr_pll_sel = 2; 176 ddr_phy_div_con = 1; 177 } else { 178 printascii("err\n"); 179 while (1) 180 ; 181 } 182 183 /* dpll default set in 1300MHz */ 184 if (params_priv->ddr_timing_t.freq == 800) { 185 /* set dpll in 1584 MHz ,vco=3.168G*/ 186 rk3308_pll_div.refdiv = 1; 187 rk3308_pll_div.fbdiv = 132; 188 rk3308_pll_div.postdiv1 = 2; 189 rk3308_pll_div.postdiv2 = 1; 190 rk3308_pll_div.frac = 0; 191 rk3308_pll_div.dsmpd = 1; 192 } else { 193 /* 1300000000,vco = 1.3GHz */ 194 rk3308_pll_div.refdiv = 6; 195 rk3308_pll_div.fbdiv = 325; 196 rk3308_pll_div.postdiv1 = 1; 197 rk3308_pll_div.postdiv2 = 1; 198 rk3308_pll_div.frac = 0; 199 rk3308_pll_div.dsmpd = 1; 200 } 201 202 pll_set(DPLL, priv, &rk3308_pll_div); 203 204 /* set ddrphy freq */ 205 rk_clrsetreg(&priv->cru->clksel_con[1], 206 DDRPHY4X_PLL_CLK_SEL_MASK | DDRPHY4X_DIV_CON_MASK, 207 ddr_pll_sel << DDRPHY4X_PLL_CLK_SEL_SHIFT | 208 ddr_phy_div_con << DDRPHY4X_DIV_CON_SIHFT); 209 210 /* set aclk_bus 216.7MHz */ 211 rk_clrsetreg(&priv->cru->clksel_con[5], 212 A_H_PCLK_BUS_PLL_SEL_MASK | ACLK_BUS_DIV_CON_MASK, 213 A_H_PCLK_BUS_PLL_SEL_DPLL << A_H_PCLK_BUS_PLL_SEL_SHIFT | 214 ACLK_BUS_DIV_CON_5 << ACLK_BUS_DIV_CON_SHIFT); 215 /* set pclk_bus 50MHz,hclk_bus 92.857MHz */ 216 rk_clrsetreg(&priv->cru->clksel_con[6], 217 PCLK_BUS_DIV_CON_MASK | HCLK_BUS_DIV_CON_MASK, 218 PCLK_BUS_DIV_CON_25 << PCLK_BUS_DIV_CON_SHIFT | 219 HCLK_BUS_DIV_CON_13 << HCLK_BUS_DIV_CON_SHIFT); 220 /* set crypto 92.857MHz,crypto_apk 92.857MHz */ 221 rk_clrsetreg(&priv->cru->clksel_con[7], 222 CLK_CRYPTO_APK_SEL_MASK | CLK_CRYPTO_APK_DIV_MASK | 223 CLK_CRYPTO_PLL_SEL_MASK | CLK_CRYPTO_DIV_CON_MASK, 224 CLK_CRYPTO_APK_SEL_DPLL << CLK_CRYPTO_APK_SEL_SHIFT | 225 CLK_CRYPTO_APK_DIV_13 << CLK_CRYPTO_APK_DIV_SHIFT | 226 CLK_CRYPTO_PLL_SEL_DPLL << CLK_CRYPTO_PLL_SEL_SHIFT | 227 CLK_CRYPTO_DIV_CON_13 << CLK_CRYPTO_DIV_CON_SHIFT); 228 /* set aclk_peri 216.7MHz */ 229 rk_clrsetreg(&priv->cru->clksel_con[36], 230 A_H_P_PERI_PLL_SEL_MASK | ACLK_PERI_DIV_CON_MASK, 231 A_H_P_PERI_PLL_SEL_DPLL << A_H_P_PERI_PLL_SEL_SHIFT | 232 ACLK_PERI_DIV_CON_5 << ACLK_PERI_DIV_CON_SHIFT); 233 /* set hclk_peri 92.857MHz,pclk_peri 46.428MHz */ 234 rk_clrsetreg(&priv->cru->clksel_con[37], 235 PCLK_PERI_DIV_CON_MASK | HCLK_PERI_DIV_CON_MASK, 236 PCLK_PERI_DIV_CON_27 << PCLK_PERI_DIV_CON_SHIFT | 237 HCLK_PERI_DIV_CON_13 << HCLK_PERI_DIV_CON_SHIFT); 238 /* set NANDC 92.857MHz */ 239 rk_clrsetreg(&priv->cru->clksel_con[38], 240 CLK_NANDC_PLL_SEL_MASK | 241 CLK_NANDC_DIV_CON_MASK, 242 CLK_NANDC_PLL_SEL_DPLL << CLK_NANDC_PLL_SEL_SHIFT | 243 CLK_NANDC_DIV_CON_13 << CLK_NANDC_DIV_CON_SHIFT); 244 /* set SDMMC 46.4/(internal freq_div 2)=23.2MHz */ 245 rk_clrsetreg(&priv->cru->clksel_con[39], 246 CLK_SDMMC_PLL_SEL_MASK | 247 CLK_SDMMC_DIV_CON_MASK, 248 CLK_SDMMC_PLL_SEL_DPLL << CLK_SDMMC_PLL_SEL_SHIFT | 249 CLK_SDMMC_DIV_CON_27 << CLK_SDMMC_DIV_CON_SHIFT); 250 /* set emmc 46.4/(internal freq_div 2)=23.2MHz */ 251 rk_clrsetreg(&priv->cru->clksel_con[41], 252 CLK_EMMC_PLL_SEL_MASK | 253 CLK_EMMC_DIV_CON_MASK, 254 CLK_EMMC_PLL_SEL_DPLL << CLK_EMMC_PLL_SEL_SHIFT | 255 CLK_EMMC_DIV_CON_27 << CLK_EMMC_DIV_CON_SHIFT); 256 /* set SFC 24.07/(internal freq_div 2)=12.0MHz */ 257 rk_clrsetreg(&priv->cru->clksel_con[42], 258 CLK_SFC_PLL_SEL_MASK | CLK_SFC_DIV_CON_MASK, 259 CLK_SFC_PLL_SEL_DPLL << CLK_SFC_PLL_SEL_SHIFT | 260 CLK_SFC_DIV_CON_53 << CLK_SFC_DIV_CON_SHIFT); 261 #if defined(CONFIG_DPLL_FREQ_1200MHZ) 262 /*vco=1.2GHz*/ 263 rk3308_pll_div.refdiv = 2; 264 rk3308_pll_div.fbdiv = 100; 265 rk3308_pll_div.postdiv1 = 1; 266 rk3308_pll_div.postdiv2 = 1; 267 rk3308_pll_div.frac = 0; 268 269 /* set dpll in 1200 MHz */ 270 pll_set(DPLL, priv, &rk3308_pll_div); 271 272 /* set aclk_bus 200MHz */ 273 rk_clrsetreg(&priv->cru->clksel_con[5], 274 A_H_PCLK_BUS_PLL_SEL_MASK | ACLK_BUS_DIV_CON_MASK, 275 A_H_PCLK_BUS_PLL_SEL_DPLL << A_H_PCLK_BUS_PLL_SEL_SHIFT | 276 ACLK_BUS_DIV_CON_5 << ACLK_BUS_DIV_CON_SHIFT); 277 /* set pclk_bus 46.15MHz,hclk_bus 100MHz */ 278 rk_clrsetreg(&priv->cru->clksel_con[6], 279 PCLK_BUS_DIV_CON_MASK | HCLK_BUS_DIV_CON_MASK, 280 PCLK_BUS_DIV_CON_25 << PCLK_BUS_DIV_CON_SHIFT | 281 HCLK_BUS_DIV_CON_11 << HCLK_BUS_DIV_CON_SHIFT); 282 /* set crypto,crypto_apk 100MHz */ 283 rk_clrsetreg(&priv->cru->clksel_con[7], 284 CLK_CRYPTO_APK_SEL_MASK | CLK_CRYPTO_APK_DIV_MASK | 285 CLK_CRYPTO_PLL_SEL_MASK | CLK_CRYPTO_DIV_CON_MASK, 286 CLK_CRYPTO_APK_SEL_DPLL << CLK_CRYPTO_APK_SEL_SHIFT | 287 CLK_CRYPTO_APK_DIV_11 << CLK_CRYPTO_APK_DIV_SHIFT | 288 CLK_CRYPTO_PLL_SEL_DPLL << CLK_CRYPTO_PLL_SEL_SHIFT | 289 CLK_CRYPTO_DIV_CON_11 << CLK_CRYPTO_DIV_CON_SHIFT); 290 /* set aclk_peri 200MHz */ 291 rk_clrsetreg(&priv->cru->clksel_con[36], 292 A_H_P_PERI_PLL_SEL_MASK | ACLK_PERI_DIV_CON_MASK, 293 A_H_P_PERI_PLL_SEL_DPLL << A_H_P_PERI_PLL_SEL_SHIFT | 294 ACLK_PERI_DIV_CON_5 << ACLK_PERI_DIV_CON_SHIFT); 295 /* set hclk_peri 100MHz,pclk_peri 50MHz */ 296 rk_clrsetreg(&priv->cru->clksel_con[37], 297 PCLK_PERI_DIV_CON_MASK | HCLK_PERI_DIV_CON_MASK, 298 PCLK_PERI_DIV_CON_23 << PCLK_PERI_DIV_CON_SHIFT | 299 HCLK_PERI_DIV_CON_11 << HCLK_PERI_DIV_CON_SHIFT); 300 /* set NANDC 100MHz */ 301 rk_clrsetreg(&priv->cru->clksel_con[38], 302 CLK_NANDC_PLL_SEL_MASK | 303 CLK_NANDC_DIV_CON_MASK, 304 CLK_NANDC_PLL_SEL_DPLL << CLK_NANDC_PLL_SEL_SHIFT | 305 CLK_NANDC_DIV_CON_11 << CLK_NANDC_DIV_CON_SHIFT); 306 /* set SDMMC 50MHz */ 307 rk_clrsetreg(&priv->cru->clksel_con[39], 308 CLK_SDMMC_PLL_SEL_MASK | 309 CLK_SDMMC_DIV_CON_MASK, 310 CLK_SDMMC_PLL_SEL_DPLL << CLK_SDMMC_PLL_SEL_SHIFT | 311 CLK_SDMMC_DIV_CON_23 << CLK_SDMMC_DIV_CON_SHIFT); 312 /* set emmc 50MHz */ 313 rk_clrsetreg(&priv->cru->clksel_con[41], 314 CLK_EMMC_PLL_SEL_MASK | 315 CLK_EMMC_DIV_CON_MASK, 316 CLK_EMMC_PLL_SEL_DPLL << CLK_EMMC_PLL_SEL_SHIFT | 317 CLK_EMMC_DIV_CON_23 << CLK_EMMC_DIV_CON_SHIFT); 318 /* set SFC 24MHz */ 319 rk_clrsetreg(&priv->cru->clksel_con[42], 320 CLK_SFC_PLL_SEL_MASK | CLK_SFC_DIV_CON_MASK, 321 CLK_SFC_PLL_SEL_DPLL << CLK_SFC_PLL_SEL_SHIFT | 322 CLK_SFC_DIV_CON_49 << CLK_SFC_DIV_CON_SHIFT); 323 324 #elif defined(CONFIG_DPLL_FREQ_748MHZ) 325 /*vco=1.5GHz*/ 326 rk3308_pll_div.refdiv = 6; 327 rk3308_pll_div.fbdiv = 374; 328 rk3308_pll_div.postdiv1 = 2; 329 rk3308_pll_div.postdiv2 = 1; 330 rk3308_pll_div.frac = 0; 331 332 /* set dpll in 748 MHz */ 333 pll_set(DPLL, priv, &rk3308_pll_div); 334 335 /* set aclk_bus 187MHz */ 336 rk_clrsetreg(&priv->cru->clksel_con[5], 337 A_H_PCLK_BUS_PLL_SEL_MASK | ACLK_BUS_DIV_CON_MASK, 338 A_H_PCLK_BUS_PLL_SEL_DPLL << A_H_PCLK_BUS_PLL_SEL_SHIFT | 339 ACLK_BUS_DIV_CON_3 << ACLK_BUS_DIV_CON_SHIFT); 340 /* set pclk_bus 46.75MHz,hclk_bus 93.5MHz */ 341 rk_clrsetreg(&priv->cru->clksel_con[6], 342 PCLK_BUS_DIV_CON_MASK | HCLK_BUS_DIV_CON_MASK, 343 PCLK_BUS_DIV_CON_15 << PCLK_BUS_DIV_CON_SHIFT | 344 HCLK_BUS_DIV_CON_7 << HCLK_BUS_DIV_CON_SHIFT); 345 /* set crypto,crypto_apk 93.5MHz */ 346 rk_clrsetreg(&priv->cru->clksel_con[7], 347 CLK_CRYPTO_APK_SEL_MASK | CLK_CRYPTO_APK_DIV_MASK | 348 CLK_CRYPTO_PLL_SEL_MASK | CLK_CRYPTO_DIV_CON_MASK, 349 CLK_CRYPTO_APK_SEL_DPLL << CLK_CRYPTO_APK_SEL_SHIFT | 350 CLK_CRYPTO_APK_DIV_7 << CLK_CRYPTO_APK_DIV_SHIFT | 351 CLK_CRYPTO_PLL_SEL_DPLL << CLK_CRYPTO_PLL_SEL_SHIFT | 352 CLK_CRYPTO_DIV_CON_7 << CLK_CRYPTO_DIV_CON_SHIFT); 353 /* set aclk_peri 187MHz */ 354 rk_clrsetreg(&priv->cru->clksel_con[36], 355 A_H_P_PERI_PLL_SEL_MASK | ACLK_PERI_DIV_CON_MASK, 356 A_H_P_PERI_PLL_SEL_DPLL << A_H_P_PERI_PLL_SEL_SHIFT | 357 ACLK_PERI_DIV_CON_3 << ACLK_PERI_DIV_CON_SHIFT); 358 /* set hclk_peri 93.5MHz,pclk_peri 46.75MHz */ 359 rk_clrsetreg(&priv->cru->clksel_con[37], 360 PCLK_PERI_DIV_CON_MASK | HCLK_PERI_DIV_CON_MASK, 361 PCLK_PERI_DIV_CON_15 << PCLK_PERI_DIV_CON_SHIFT | 362 HCLK_PERI_DIV_CON_7 << HCLK_PERI_DIV_CON_SHIFT); 363 /* set NANDC 93.5MHz */ 364 rk_clrsetreg(&priv->cru->clksel_con[38], 365 CLK_NANDC_PLL_SEL_MASK | 366 CLK_NANDC_DIV_CON_MASK, 367 CLK_NANDC_SEL50_ALWAYS << CLK_NANDC_SEL50_SHIFT | 368 CLK_NANDC_PLL_SEL_DPLL << CLK_NANDC_PLL_SEL_SHIFT | 369 CLK_NANDC_DIV_CON_7 << CLK_NANDC_DIV_CON_SHIFT); 370 /* set NANDC 46.75MHz */ 371 rk_clrsetreg(&priv->cru->clksel_con[39], 372 CLK_SDMMC_PLL_SEL_MASK | 373 CLK_SDMMC_DIV_CON_MASK, 374 CLK_SDMMC_PLL_SEL_DPLL << CLK_SDMMC_PLL_SEL_SHIFT | 375 CLK_SDMMC_DIV_CON_15 << CLK_SDMMC_DIV_CON_SHIFT); 376 /* set emmc 46.75MHz */ 377 rk_clrsetreg(&priv->cru->clksel_con[41], 378 CLK_EMMC_PLL_SEL_MASK | 379 CLK_EMMC_DIV_CON_MASK, 380 CLK_EMMC_PLL_SEL_DPLL << CLK_EMMC_PLL_SEL_SHIFT | 381 CLK_EMMC_DIV_CON_15 << CLK_EMMC_DIV_CON_SHIFT); 382 /* set SFC 23.375MHz */ 383 rk_clrsetreg(&priv->cru->clksel_con[42], 384 CLK_SFC_PLL_SEL_MASK | CLK_SFC_DIV_CON_MASK, 385 CLK_SFC_PLL_SEL_DPLL << CLK_SFC_PLL_SEL_SHIFT | 386 CLK_SFC_DIV_CON_31 << CLK_SFC_DIV_CON_SHIFT); 387 388 #endif 389 /* set spdif tx lower than 100Mhz */ 390 rk_clrsetreg(&priv->cru->clksel_con[48], 391 CLK_SPDIFTX_DIV_CON_MASK, 392 CLK_SPDIFTX_DIV_CON_15 << CLK_SPDIFTX_DIV_CON_SHIFT); 393 394 if (UART_INFO_ID(ddr_gd.head_info.g_uart_info) < 5) 395 uart_div[UART_INFO_ID(ddr_gd.head_info.g_uart_info)] = 0; 396 397 /* set uart0~4 lower than 100Mhz */ 398 rk_clrsetreg(&priv->cru->clksel_con[10], 399 CLK_UART0_DIV_CON_MASK, 400 uart_div[0] << CLK_UART0_DIV_CON_SHIFT); 401 rk_clrsetreg(&priv->cru->clksel_con[13], 402 CLK_UART1_DIV_CON_MASK, 403 uart_div[1] << CLK_UART1_DIV_CON_SHIFT); 404 rk_clrsetreg(&priv->cru->clksel_con[16], 405 CLK_UART2_DIV_CON_MASK, 406 uart_div[2] << CLK_UART2_DIV_CON_SHIFT); 407 rk_clrsetreg(&priv->cru->clksel_con[19], 408 CLK_UART3_DIV_CON_MASK, 409 uart_div[3] << CLK_UART3_DIV_CON_SHIFT); 410 rk_clrsetreg(&priv->cru->clksel_con[22], 411 CLK_UART4_DIV_CON_MASK, 412 uart_div[4] << CLK_UART4_DIV_CON_SHIFT); 413 414 /* pll clk in pll out */ 415 rk_clrsetreg(&priv->cru->mode, VPLL1_WORK_MODE_MASK, 416 VPLL1_WORK_MODE_PLL << VPLL1_WORK_MODE_SHIFT); 417 rk_clrsetreg(&priv->cru->mode, VPLL0_WORK_MODE_MASK, 418 VPLL0_WORK_MODE_PLL << VPLL0_WORK_MODE_SHIFT); 419 rk_clrsetreg(&priv->cru->mode, DPLL_WORK_MODE_MASK, 420 DPLL_WORK_MODE_PLL << DPLL_WORK_MODE_SHIFT); 421 } 422 423 void phy_pctrl_reset_cru(struct dram_info *priv) 424 { 425 rk_clrsetreg(&priv->cru->softrst_con[1], 426 PRESETN_DDRPHY_REQ_MASK | RESETN_DDRPHYDIV_REQ_MASK | 427 RESETN_DDRPHY_REQ_MASK | PRESETN_DDRUPCTL_REQ_MASK | 428 RESETN_DDRUPCTL_REQ_MASK, 429 PRESETN_DDRPHY_REQ_EN << PRESETN_DDRPHY_REQ_SHIFT | 430 RESETN_DDRPHYDIV_REQ_EN << RESETN_DDRPHYDIV_REQ_SHIFT | 431 RESETN_DDRPHY_REQ_EN << RESETN_DDRPHY_REQ_SHIFT | 432 PRESETN_DDRUPCTL_REQ_EN << PRESETN_DDRUPCTL_REQ_SHIFT | 433 RESETN_DDRUPCTL_REQ_EN << RESETN_DDRUPCTL_REQ_SHIFT); 434 udelay(10); 435 436 rk_clrsetreg(&priv->cru->softrst_con[1], 437 PRESETN_DDRPHY_REQ_MASK | RESETN_DDRPHYDIV_REQ_MASK | 438 RESETN_DDRPHY_REQ_MASK, 439 PRESETN_DDRPHY_REQ_DIS << PRESETN_DDRPHY_REQ_SHIFT | 440 RESETN_DDRPHYDIV_REQ_DIS << RESETN_DDRPHYDIV_REQ_SHIFT | 441 RESETN_DDRPHY_REQ_DIS << RESETN_DDRPHY_REQ_SHIFT); 442 udelay(10); 443 444 rk_clrsetreg(&priv->cru->softrst_con[1], 445 PRESETN_DDRUPCTL_REQ_MASK | RESETN_DDRUPCTL_REQ_MASK, 446 PRESETN_DDRUPCTL_REQ_DIS << PRESETN_DDRUPCTL_REQ_SHIFT | 447 RESETN_DDRUPCTL_REQ_DIS << RESETN_DDRUPCTL_REQ_SHIFT); 448 udelay(10); 449 } 450 451 void pctl_cfg_grf(struct dram_info *priv, 452 struct sdram_params *params_priv) 453 { 454 if (params_priv->ddr_config_t.ddr_type == DDR3 || 455 params_priv->ddr_config_t.ddr_type == DDR2) 456 rk_clrsetreg(&priv->grf->soc_con12, NOC_MSCH_MAINDDR3_MASK, 457 NOC_MSCH_MAINDDR3_EN << NOC_MSCH_MAINDDR3_SHIFT); 458 else 459 rk_clrsetreg(&priv->grf->soc_con12, NOC_MSCH_MAINDDR3_MASK, 460 NOC_MSCH_MAINDDR3_DIS << NOC_MSCH_MAINDDR3_SHIFT); 461 } 462 463 void ddr_msch_cfg(struct dram_info *priv, 464 struct sdram_params *params_priv) 465 { 466 writel(BWRATIO_HALF_BW | params_priv->ddr_timing_t.noc_timing.d32, 467 &priv->service_msch->ddrtiming); 468 writel(params_priv->ddr_timing_t.readlatency, 469 &priv->service_msch->readlatency); 470 } 471 472 void ddr_msch_cfg_rbc(struct sdram_params *params_priv, 473 struct dram_info *priv) 474 { 475 int i = 0; 476 477 if (params_priv->ddr_config_t.bank == 3) { 478 /* bank = 8 */ 479 if (params_priv->ddr_config_t.col == 10) 480 i = 1; 481 else if (params_priv->ddr_config_t.col == 11) 482 i = 2; 483 else 484 goto msch_err; 485 486 } else if (params_priv->ddr_config_t.bank == 2) { 487 /* bank = 4 */ 488 i = 0; 489 } else { 490 goto msch_err; 491 } 492 493 writel(i, &priv->service_msch->ddrconf); 494 return; 495 496 msch_err: 497 printascii("msch_err\n"); 498 while (1) 499 ; 500 } 501 502 void ddr_phy_skew_cfg(struct dram_info *priv) 503 { 504 copy_to_reg(&priv->phy->phy_reg_ca_skew[0], 505 &ddr_gd.ddr_skew.a0_a1_skew[0], 14 * 4); 506 copy_to_reg(&priv->phy->phy_reg_skew_cs0data[0], 507 &ddr_gd.ddr_skew.cs0_dm0_skew[0], 22 * 4); 508 509 writel(PHY_TX_DE_SKEW_EN << PHY_TX_DE_SKEW_SHIFT, 510 &priv->phy->phy_reg2); 511 } 512 513 void set_ds_odt(struct dram_info *priv, 514 struct sdram_params *params_priv) 515 { 516 /* set phy drive resistance */ 517 writel(PHY_RON_RTT_56OHM, &priv->phy->phy_reg11); 518 clrsetbits_le32(&priv->phy->phy_reg12, CMD_PRCOMP_MASK, 519 PHY_RON_RTT_56OHM << CMD_PRCOMP_SHIFT); 520 521 writel(PHY_RON_RTT_45OHM, &priv->phy->phy_reg16); 522 writel(PHY_RON_RTT_45OHM, &priv->phy->phy_reg18); 523 writel(PHY_RON_RTT_56OHM, &priv->phy->phy_reg20); 524 writel(PHY_RON_RTT_56OHM, &priv->phy->phy_reg2f); 525 writel(PHY_RON_RTT_56OHM, &priv->phy->phy_reg30); 526 writel(PHY_RON_RTT_56OHM, &priv->phy->phy_reg3f); 527 if (params_priv->ddr_config_t.ddr_type == LPDDR2) { 528 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg21); 529 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg2e); 530 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg31); 531 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg3e); 532 } else { 533 if (params_priv->ddr_timing_t.freq > 534 DDR3_DDR2_ODT_DISABLE_FREQ) { 535 /*set phy odt*/ 536 writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg21); 537 writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg2e); 538 writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg31); 539 writel(PHY_RON_RTT_225OHM, &priv->phy->phy_reg3e); 540 } else { 541 /*disable phy odt*/ 542 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg21); 543 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg2e); 544 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg31); 545 writel(PHY_RON_RTT_DISABLE, &priv->phy->phy_reg3e); 546 } 547 } 548 } 549 550 void ddr_phy_dqs_rx_dll_cfg(struct dram_info *priv, u32 freq) 551 { 552 if (freq > 736) { 553 /* 22.5 degree delay */ 554 writel(LEFT_CHN_A_READ_DQS_22_5_DELAY, &priv->phy->phy_reg28); 555 writel(RIGHT_CHN_A_READ_DQS_22_5_DELAY, &priv->phy->phy_reg38); 556 } else { 557 /* 45 degree delay */ 558 writel(LEFT_CHN_A_READ_DQS_45_DELAY, &priv->phy->phy_reg28); 559 writel(RIGHT_CHN_A_READ_DQS_45_DELAY, &priv->phy->phy_reg38); 560 } 561 } 562 563 void ddr_msch_get_max_col(struct dram_info *priv, 564 struct ddr_schedule *sch_priv) 565 { 566 writel(2, &priv->service_msch->ddrconf); 567 sch_priv->col = 11; 568 sch_priv->bank = 3; 569 } 570 571 void ddr_msch_get_max_row(struct dram_info *priv, 572 struct ddr_schedule *sch_priv) 573 { 574 writel(1, &priv->service_msch->ddrconf); 575 sch_priv->row = 15; 576 sch_priv->col = 10; 577 sch_priv->bank = 3; 578 } 579 580 void enable_ddr_standby(struct dram_info *priv, 581 struct sdram_params *params_priv) 582 { 583 rk_clrsetreg(&priv->grf->upctl_con0, CYSYREQ_UPCTL_DDRSTDBY_MASK, 584 CYSYREQ_UPCTL_DDRSTDBY_EN << 585 CYSYREQ_UPCTL_DDRSTDBY_SHIFT); 586 587 /* CG_EXIT_TH is equal phy dll lock time when we gate phy 4x clk */ 588 writel(CG_EXIT_TH << CG_EXIT_TH_SHIFT, &priv->standby->con1); 589 590 if (params_priv->stdby_idle == 128) { 591 if (params_priv->ddr_timing_t.freq == 451) 592 params_priv->stdby_idle = 105; 593 else if (params_priv->ddr_timing_t.freq == 393) 594 params_priv->stdby_idle = 10; 595 } 596 writel(params_priv->stdby_idle << IDLE_TH_SHIFT | 597 DDRPHY4X_GATE_EN << DDRPHY4X_GATE_SHIFT | 598 UPCTL_CORE_CLK_GATE_EN << UPCTL_CORE_CLK_GATE_SHIFT | 599 UPCTL_ACLK_GATE_EN << UPCTL_ACLK_GATE_SHIFT | 600 CTL_IDLR_EN << CTL_IDLR_SHIFT | 601 STDBY_EN << STDBY_EN_SHIFT, &priv->standby->con0); 602 603 while (1) { 604 if ((readl(&priv->standby->status0) & 605 STDBY_STATUS_MASK) == ST_STDBY) { 606 break; 607 } 608 } 609 } 610 611 void ddr_set_atags(void) 612 { 613 struct tag_serial t_serial; 614 615 memset(&t_serial, 0, sizeof(struct tag_serial)); 616 #ifdef CONFIG_DRAM_INIT_BUILD 617 u32 uart_info; 618 619 t_serial.version = 0; 620 uart_info = ddr_gd.head_info.g_uart_info; 621 if (UART_INFO_ID(uart_info) >= MAX_UART_NUMBER_) { 622 t_serial.enable = 0; 623 } else { 624 t_serial.enable = 1; 625 t_serial.baudrate = UART_INFO_BAUD(uart_info); 626 t_serial.m_mode = UART_INFO_IOMUX(uart_info); 627 t_serial.id = UART_INFO_ID(uart_info); 628 if (UART_INFO_ID(uart_info) == 0) 629 t_serial.addr = UART0_BASE; 630 else if (UART_INFO_ID(uart_info) == 1) 631 t_serial.addr = UART1_BASE; 632 else if (UART_INFO_ID(uart_info) == 2) 633 t_serial.addr = UART2_BASE; 634 else if (UART_INFO_ID(uart_info) == 3) 635 t_serial.addr = UART3_BASE; 636 else 637 t_serial.addr = UART4_BASE; 638 } 639 #else 640 /* set serial data to &t_serial */ 641 #if defined(CONFIG_DEBUG_UART_BASE) 642 t_serial.version = 0; 643 t_serial.enable = 1; 644 t_serial.addr = CONFIG_DEBUG_UART_BASE; 645 t_serial.baudrate = CONFIG_BAUDRATE; 646 647 #if (CONFIG_DEBUG_UART_BASE == 0xFF0A0000) 648 /* uart0 as debug uart */ 649 t_serial.m_mode = SERIAL_M_MODE_M0; 650 t_serial.id = 0; 651 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0B0000) 652 /* uart1 as debug uart */ 653 t_serial.m_mode = SERIAL_M_MODE_M0; 654 t_serial.id = 1; 655 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0C0000) 656 #if (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0) 657 t_serial.m_mode = SERIAL_M_MODE_M0; 658 #elif (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1) 659 /* uart2 m1 as debug uart */ 660 t_serial.m_mode = SERIAL_M_MODE_M1; 661 #else 662 #error "Please select M0 or M1 for uart2 !!!" 663 #endif 664 t_serial.id = 2; 665 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0D0000) 666 /* uart3 as debug uart */ 667 t_serial.m_mode = SERIAL_M_MODE_M0; 668 t_serial.id = 3; 669 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0E0000) 670 /* uart4 as debug uart */ 671 t_serial.m_mode = SERIAL_M_MODE_M0; 672 t_serial.id = 4; 673 #else 674 #error "Please select proper uart as debug uart !!!" 675 #endif 676 677 #endif /* defined(CONFIG_DEBUG_UART_BASE) */ 678 #endif /* CONFIG_DRAM_INIT_BUILD */ 679 680 /* First pre-loader must call it before atags_set_tag() */ 681 atags_destroy(); 682 atags_set_tag(ATAG_SERIAL, &t_serial); 683 } 684 685 static void modify_sdram_params(struct dram_info *priv, 686 struct sdram_params *params_priv) 687 { 688 u32 tmp = 0; 689 u32 bw = 1; 690 u32 nMHz = params_priv->ddr_timing_t.freq; 691 692 size_t size = 1llu << (bw + 693 params_priv->ddr_config_t.col + 694 params_priv->ddr_config_t.cs0_row + 695 params_priv->ddr_config_t.bank); 696 697 move_to_config_state(priv); 698 switch (params_priv->ddr_config_t.ddr_type) { 699 case DDR2: 700 if (size <= 0x4000000) 701 tmp = DDR2_TRFC_512MBIT; 702 else if (size <= 0x8000000) 703 tmp = DDR2_TRFC_1GBIT; 704 else if (size <= 0x10000000) 705 tmp = DDR2_TRFC_2GBIT; 706 else 707 tmp = DDR2_TRFC_4GBIT; 708 709 priv->pctl->trfc = (tmp * nMHz + 999) / 1000; 710 tmp = (((tmp + 10) * nMHz + 999) / 1000); 711 if (tmp < 200) 712 tmp = 200; 713 priv->pctl->texsr = tmp & 0x3FF; 714 break; 715 case DDR3: 716 if (size <= 0x4000000) 717 tmp = DDR3_TRFC_512MBIT; 718 else if (size <= 0x8000000) 719 tmp = DDR3_TRFC_1GBIT; 720 else if (size <= 0x10000000) 721 tmp = DDR3_TRFC_2GBIT; 722 else if (size <= 0x20000000) 723 tmp = DDR3_TRFC_4GBIT; 724 else 725 tmp = DDR3_TRFC_8GBIT; 726 priv->pctl->trfc = (tmp * nMHz + 999) / 1000; 727 break; 728 case LPDDR2: 729 if (size <= 0x4000000) 730 tmp = LPDDR2_TREC_512MBIT; 731 else if (size <= 0x20000000) 732 tmp = LPDDR2_TRFC_4GBIT; 733 else 734 tmp = LPDDR2_TRFC_8GBIT; 735 736 priv->pctl->trfc = (tmp * nMHz + 999) / 1000; 737 tmp = (((tmp + 10) * nMHz + 999) / 1000); 738 if (tmp < 2) 739 tmp = 2; 740 priv->pctl->texsr = tmp & 0x3FF; 741 break; 742 } 743 move_to_access_state(priv); 744 } 745 746 int check_rd_gate(struct dram_info *priv) 747 { 748 u32 max_val = 0; 749 u32 min_val = 0xff; 750 u32 gate[2]; 751 752 gate[0] = readl(&priv->phy->phy_regfb); 753 gate[1] = readl(&priv->phy->phy_regfc); 754 max_val = max(gate[0], gate[1]); 755 min_val = min(gate[0], gate[1]); 756 757 if (max_val > 0x80 || min_val < 0x20) 758 return -1; 759 else 760 return 0; 761 } 762 763 static u32 dram_test(u32 i, u32 dqs) 764 { 765 for (phys_addr_t j = 4 * dqs; j < 0x2000; j += 8) 766 writel(PATTERN + i, j); 767 768 for (phys_addr_t j = 4 * dqs; j < 0x2000; j += 8) 769 if ((PATTERN + i) != readl(j)) 770 return 1; 771 772 return 0; 773 } 774 775 /** 776 * modify_data_training() - Setting DQS gating calibration bypass, 777 * scanning data training range and then select center one. 778 */ 779 #define PHY_REG3C(n) (0x10 * (n)) 780 781 void modify_data_training(struct dram_info *priv, 782 struct sdram_params *params_priv) 783 { 784 u32 value = 0; 785 u32 i = 0, dqs = 0; 786 u32 max_value = 0, min_value = 0; 787 788 writel(readl(&priv->phy->phy_regfb), &priv->phy->phy_reg2c); 789 writel(readl(&priv->phy->phy_regfc), &priv->phy->phy_reg3c); 790 791 /* DQS gating calibration bypass */ 792 setbits_le32(&priv->phy->phy_reg2, BIT(1)); 793 794 /* rk3308 only support DQS0, DQS1 */ 795 for (dqs = 0; dqs < 2; dqs++) { 796 value = readl(&priv->phy->phy_regfb + dqs); 797 i = 0; 798 while (dram_test(i, dqs) == 0) { 799 i++; 800 writel(value + i, 801 &priv->phy->phy_reg2c + PHY_REG3C(dqs)); 802 } 803 max_value = value + i - 1; 804 805 i = 1; 806 writel(value - i, &priv->phy->phy_reg2c + PHY_REG3C(dqs)); 807 while (dram_test(i, dqs) == 0) { 808 i++; 809 writel(value - i, 810 &priv->phy->phy_reg2c + PHY_REG3C(dqs)); 811 } 812 min_value = value - i + 1; 813 814 /* select center one as gate training result */ 815 writel((max_value + min_value + 1) / 2, 816 &priv->phy->phy_reg2c + PHY_REG3C(dqs)); 817 } 818 printascii("REG2C: 0x"); 819 printhex8(readl(&priv->phy->phy_reg2c)); 820 printascii(", 0x"); 821 printhex8(readl(&priv->phy->phy_reg3c)); 822 printascii("\n"); 823 } 824 825 void enable_low_power(struct dram_info *priv, 826 struct sdram_params *params_priv) 827 { 828 move_to_config_state(priv); 829 830 if (params_priv->idle_pd == 48 && params_priv->idle_sr == 10) { 831 if (params_priv->ddr_timing_t.freq == 451) { 832 params_priv->idle_sr = 28; 833 params_priv->idle_pd = 7; 834 } else if (params_priv->ddr_timing_t.freq == 393) { 835 params_priv->idle_sr = 31; 836 params_priv->idle_pd = 15; 837 } 838 } 839 clrsetbits_le32(&priv->pctl->mcfg, PD_IDLE_MASK, 840 params_priv->idle_pd << PD_IDLE_SHIFT); 841 clrsetbits_le32(&priv->pctl->mcfg1, 842 SR_IDLE_MASK | HW_EXIT_IDLE_EN_MASK, 843 params_priv->idle_sr | HW_EXIT_IDLE_EN); 844 845 /* uPCTL in low_power status because of auto self-refresh */ 846 writel(GO_STATE, &priv->pctl->sctl); 847 } 848 849 int get_uart_config(void) 850 { 851 return ddr_gd.head_info.g_uart_info; 852 } 853 854 int sdram_init(void) 855 { 856 struct dram_info sdram_priv; 857 struct sdram_params *params = sdram_configs; 858 859 sdram_priv.cru = (void *)CRU_BASE; 860 sdram_priv.grf = (void *)GRF_BASE; 861 sdram_priv.sgrf = (void *)SGRF_BASE; 862 sdram_priv.phy = (void *)DDR_PHY_BASE; 863 sdram_priv.pctl = (void *)DDR_PCTL_BASE; 864 sdram_priv.standby = (void *)DDR_STANDBY_BASE; 865 sdram_priv.pmu = (void *)PMU_BASS_ADDR; 866 sdram_priv.service_msch = (void *)SERVICE_MSCH_BASE; 867 params->idle_pd = PD_INFO(ddr_gd.head_info.g_sr_pd_idle); 868 params->idle_sr = SR_INFO(ddr_gd.head_info.g_sr_pd_idle); 869 params->ddr_2t_en = DDR_2T_INFO(ddr_gd.head_info.g_2t_info); 870 params->stdby_idle = STANDBY_IDLE(ddr_gd.head_info.g_ch_info); 871 872 rv1108_sdram_init(&sdram_priv, params); 873 874 modify_sdram_params(&sdram_priv, params); 875 876 if (params->idle_pd != 0 && params->idle_sr != 0) 877 enable_ddr_standby(&sdram_priv, params); 878 ddr_set_atags(); 879 printascii("OUT\n"); 880 881 return 0; 882 } 883 884 #else 885 886 /* return: 0 = success, other = fail */ 887 int sdram_init(void) 888 { 889 return (-1); 890 } 891 892 #endif /* CONFIG_TPL_BUILD */ 893