1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 4 */ 5 6 #include <common.h> 7 #include <debug_uart.h> 8 #include <dm.h> 9 #include <ram.h> 10 #include <syscon.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/cru_px30.h> 14 #include <asm/arch/grf_px30.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/sdram.h> 17 #include <asm/arch/sdram_px30.h> 18 19 /* 20 * Because px30 sram size is small, so need define CONFIG_TPL_TINY_FRAMEWORK 21 * to reduce TPL size when build TPL firmware. 22 */ 23 #ifdef CONFIG_TPL_BUILD 24 #ifndef CONFIG_TPL_TINY_FRAMEWORK 25 #error please defined CONFIG_TPL_TINY_FRAMEWORK for px30 !!! 26 #endif 27 #endif 28 29 #ifdef CONFIG_TPL_BUILD 30 31 DECLARE_GLOBAL_DATA_PTR; 32 struct dram_info { 33 struct ddr_pctl_regs *pctl; 34 struct ddr_phy_regs *phy; 35 struct px30_cru *cru; 36 struct msch_regs *msch; 37 struct px30_ddr_grf_regs *ddr_grf; 38 struct px30_grf *grf; 39 struct ram_info info; 40 struct px30_pmugrf *pmugrf; 41 }; 42 43 #define PMUGRF_BASE_ADDR 0xFF010000 44 #define CRU_BASE_ADDR 0xFF2B0000 45 #define GRF_BASE_ADDR 0xFF140000 46 #define DDRC_BASE_ADDR 0xFF600000 47 #define DDR_PHY_BASE_ADDR 0xFF2A0000 48 #define SERVER_MSCH0_BASE_ADDR 0xFF530000 49 #define DDR_GRF_BASE_ADDR 0xff630000 50 51 struct dram_info dram_info; 52 53 struct px30_sdram_params sdram_configs[] = { 54 #include "sdram-px30-ddr3-detect-333.inc" 55 }; 56 57 struct ddr_phy_skew skew = { 58 #include "sdram-px30-ddr_skew.inc" 59 }; 60 61 static void rkclk_ddr_reset(struct dram_info *dram, 62 u32 ctl_srstn, u32 ctl_psrstn, 63 u32 phy_srstn, u32 phy_psrstn) 64 { 65 writel(upctl2_srstn_req(ctl_srstn) | upctl2_psrstn_req(ctl_psrstn) | 66 upctl2_asrstn_req(ctl_srstn), 67 &dram->cru->softrst_con[1]); 68 writel(ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn), 69 &dram->cru->softrst_con[2]); 70 } 71 72 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) 73 { 74 unsigned int refdiv, postdiv1, postdiv2, fbdiv; 75 int delay = 1000; 76 u32 mhz = hz / MHz; 77 78 refdiv = 1; 79 if (mhz <= 300) { 80 postdiv1 = 4; 81 postdiv2 = 2; 82 } else if (mhz <= 400) { 83 postdiv1 = 6; 84 postdiv2 = 1; 85 } else if (mhz <= 600) { 86 postdiv1 = 4; 87 postdiv2 = 1; 88 } else if (mhz <= 800) { 89 postdiv1 = 3; 90 postdiv2 = 1; 91 } else if (mhz <= 1600) { 92 postdiv1 = 2; 93 postdiv2 = 1; 94 } else { 95 postdiv1 = 1; 96 postdiv2 = 1; 97 } 98 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; 99 100 writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); 101 102 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); 103 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), 104 &dram->cru->pll[1].con1); 105 106 while (delay > 0) { 107 udelay(1); 108 if (LOCK(readl(&dram->cru->pll[1].con1))) 109 break; 110 delay--; 111 } 112 113 writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode); 114 } 115 116 static void rkclk_configure_ddr(struct dram_info *dram, 117 struct px30_sdram_params *sdram_params) 118 { 119 /* for inno ddr phy need 2*freq */ 120 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHz * 2); 121 } 122 123 /* return ddrconfig value 124 * (-1), find ddrconfig fail 125 * other, the ddrconfig value 126 * only support cs0_row >= cs1_row 127 */ 128 static unsigned int calculate_ddrconfig(struct px30_sdram_params *sdram_params) 129 { 130 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 131 u32 bw, die_bw, col, bank; 132 u32 i, tmp; 133 u32 ddrconf = -1; 134 135 bw = cap_info->bw; 136 die_bw = cap_info->dbw; 137 col = cap_info->col; 138 bank = cap_info->bk; 139 140 if (sdram_params->base.dramtype == DDR4) { 141 if (die_bw == 0) 142 ddrconf = 7 + bw; 143 else 144 ddrconf = 12 - bw; 145 ddrconf = d4_rbc_2_d3_rbc[ddrconf - 7]; 146 } else { 147 tmp = ((bank - 2) << 3) | (col + bw - 10); 148 for (i = 0; i < 7; i++) 149 if ((ddr_cfg_2_rbc[i] & 0xf) == tmp) { 150 ddrconf = i; 151 break; 152 } 153 if (i > 6) 154 printascii("calculate ddrconfig error\n"); 155 } 156 157 return ddrconf; 158 } 159 160 /* 161 * calculate controller dram address map, and setting to register. 162 * argument sdram_params->ch.ddrconf must be right value before 163 * call this function. 164 */ 165 static void set_ctl_address_map(struct dram_info *dram, 166 struct px30_sdram_params *sdram_params) 167 { 168 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 169 void __iomem *pctl_base = dram->pctl; 170 u32 cs_pst, bg, max_row, ddrconf; 171 u32 i; 172 173 if (sdram_params->base.dramtype == DDR4) 174 /* 175 * DDR4 8bit dram BG = 2(4bank groups), 176 * 16bit dram BG = 1 (2 bank groups) 177 */ 178 bg = (cap_info->dbw == 0) ? 2 : 1; 179 else 180 bg = 0; 181 182 cs_pst = cap_info->bw + cap_info->col + 183 bg + cap_info->bk + cap_info->cs0_row; 184 if (cs_pst >= 32 || cap_info->rank == 1) 185 writel(0x1f, pctl_base + DDR_PCTL2_ADDRMAP0); 186 else 187 writel(cs_pst - 8, pctl_base + DDR_PCTL2_ADDRMAP0); 188 189 ddrconf = cap_info->ddrconfig; 190 if (sdram_params->base.dramtype == DDR4) { 191 for (i = 0; i < ARRAY_SIZE(d4_rbc_2_d3_rbc); i++) { 192 if (d4_rbc_2_d3_rbc[i] == ddrconf) { 193 ddrconf = 7 + i; 194 break; 195 } 196 } 197 } 198 199 sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP1), 200 &addrmap[ddrconf][0], 8 * 4); 201 max_row = cs_pst - 1 - 8 - (addrmap[ddrconf][5] & 0xf); 202 203 if (max_row < 12) 204 printascii("set addrmap fail\n"); 205 /* need to disable row ahead of rank by set to 0xf */ 206 for (i = 17; i > max_row; i--) 207 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 + 208 ((i - 12) * 8 / 32) * 4, 209 0xf << ((i - 12) * 8 % 32), 210 0xf << ((i - 12) * 8 % 32)); 211 212 if ((sdram_params->base.dramtype == LPDDR3 || 213 sdram_params->base.dramtype == LPDDR2) && 214 cap_info->row_3_4) 215 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); 216 if (sdram_params->base.dramtype == DDR4 && cap_info->bw != 0x2) 217 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); 218 } 219 220 /* 221 * rank = 1: cs0 222 * rank = 2: cs1 223 */ 224 int read_mr(struct dram_info *dram, u32 rank, u32 mr_num) 225 { 226 void __iomem *ddr_grf_base = dram->ddr_grf; 227 228 pctl_read_mr(dram->pctl, rank, mr_num); 229 230 return (readl(ddr_grf_base + DDR_GRF_STATUS(0)) & 0xff); 231 } 232 233 #define MIN(a, b) (((a) > (b)) ? (b) : (a)) 234 #define MAX(a, b) (((a) > (b)) ? (a) : (b)) 235 static u32 check_rd_gate(struct dram_info *dram) 236 { 237 void __iomem *phy_base = dram->phy; 238 239 u32 max_val = 0; 240 u32 min_val = 0xff; 241 u32 gate[4]; 242 u32 i, bw; 243 244 bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf; 245 switch (bw) { 246 case 0x1: 247 bw = 1; 248 break; 249 case 0x3: 250 bw = 2; 251 break; 252 case 0xf: 253 default: 254 bw = 4; 255 break; 256 } 257 258 for (i = 0; i < bw; i++) { 259 gate[i] = readl(PHY_REG(phy_base, 0xfb + i)); 260 max_val = MAX(max_val, gate[i]); 261 min_val = MIN(min_val, gate[i]); 262 } 263 264 if (max_val > 0x80 || min_val < 0x20) 265 return -1; 266 else 267 return 0; 268 } 269 270 static int data_training(struct dram_info *dram, u32 cs, u32 dramtype) 271 { 272 void __iomem *pctl_base = dram->pctl; 273 u32 dis_auto_zq = 0; 274 u32 pwrctl; 275 u32 ret; 276 277 /* disable auto low-power */ 278 pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); 279 writel(0, pctl_base + DDR_PCTL2_PWRCTL); 280 281 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); 282 283 ret = phy_data_training(dram->phy, cs, dramtype); 284 285 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); 286 287 /* restore auto low-power */ 288 writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); 289 290 return ret; 291 } 292 293 static void dram_set_bw(struct dram_info *dram, u32 bw) 294 { 295 phy_dram_set_bw(dram->phy, bw); 296 } 297 298 static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig) 299 { 300 writel(ddrconfig | (ddrconfig << 8), &dram->msch->deviceconf); 301 rk_clrsetreg(&dram->grf->soc_noc_con[1], 0x3 << 14, 0 << 14); 302 } 303 304 static void sdram_msch_config(struct msch_regs *msch, 305 struct sdram_msch_timings *noc_timings, 306 struct sdram_cap_info *cap_info, 307 struct sdram_base_params *base) 308 { 309 u64 cs_cap[2]; 310 311 cs_cap[0] = sdram_get_cs_cap(cap_info, 0, base->dramtype); 312 cs_cap[1] = sdram_get_cs_cap(cap_info, 1, base->dramtype); 313 writel(((((cs_cap[1] >> 20) / 64) & 0xff) << 8) | 314 (((cs_cap[0] >> 20) / 64) & 0xff), 315 &msch->devicesize); 316 317 writel(noc_timings->ddrtiminga0.d32, 318 &msch->ddrtiminga0); 319 writel(noc_timings->ddrtimingb0.d32, 320 &msch->ddrtimingb0); 321 writel(noc_timings->ddrtimingc0.d32, 322 &msch->ddrtimingc0); 323 writel(noc_timings->devtodev0.d32, 324 &msch->devtodev0); 325 writel(noc_timings->ddrmode.d32, &msch->ddrmode); 326 writel(noc_timings->ddr4timing.d32, 327 &msch->ddr4timing); 328 writel(noc_timings->agingx0, &msch->agingx0); 329 writel(noc_timings->agingx0, &msch->aging0); 330 writel(noc_timings->agingx0, &msch->aging1); 331 writel(noc_timings->agingx0, &msch->aging2); 332 writel(noc_timings->agingx0, &msch->aging3); 333 } 334 335 static void dram_all_config(struct dram_info *dram, 336 struct px30_sdram_params *sdram_params) 337 { 338 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 339 u32 sys_reg2 = 0; 340 u32 sys_reg3 = 0; 341 342 set_ddrconfig(dram, cap_info->ddrconfig); 343 sdram_org_config(cap_info, &sdram_params->base, &sys_reg2, 344 &sys_reg3, 0); 345 writel(sys_reg2, &dram->pmugrf->os_reg[2]); 346 writel(sys_reg3, &dram->pmugrf->os_reg[3]); 347 sdram_msch_config(dram->msch, &sdram_params->ch.noc_timings, cap_info, 348 &sdram_params->base); 349 } 350 351 static void enable_low_power(struct dram_info *dram, 352 struct px30_sdram_params *sdram_params) 353 { 354 void __iomem *pctl_base = dram->pctl; 355 void __iomem *phy_base = dram->phy; 356 void __iomem *ddr_grf_base = dram->ddr_grf; 357 u32 grf_lp_con; 358 359 /* 360 * bit0: grf_upctl_axi_cg_en = 1 enable upctl2 axi clk auto gating 361 * bit1: grf_upctl_apb_cg_en = 1 ungated axi,core clk for apb access 362 * bit2: grf_upctl_core_cg_en = 1 enable upctl2 core clk auto gating 363 * bit3: grf_selfref_type2_en = 0 disable core clk gating when type2 sr 364 * bit4: grf_upctl_syscreq_cg_en = 1 365 * ungating coreclk when c_sysreq assert 366 * bit8-11: grf_auto_sr_dly = 6 367 */ 368 writel(0x1f1f0617, &dram->ddr_grf->ddr_grf_con[1]); 369 370 if (sdram_params->base.dramtype == DDR4) 371 grf_lp_con = (0x7 << 16) | (1 << 1); 372 else if (sdram_params->base.dramtype == DDR3) 373 grf_lp_con = (0x7 << 16) | (1 << 0); 374 else 375 grf_lp_con = (0x7 << 16) | (1 << 2); 376 377 /* en lpckdis_en */ 378 grf_lp_con = grf_lp_con | (0x1 << (9 + 16)) | (0x1 << 9); 379 writel(grf_lp_con, ddr_grf_base + DDR_GRF_LP_CON); 380 381 /* off digit module clock when enter power down */ 382 setbits_le32(PHY_REG(phy_base, 7), 1 << 7); 383 384 /* enable sr, pd */ 385 if (PD_IDLE == 0) 386 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); 387 else 388 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); 389 if (SR_IDLE == 0) 390 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); 391 else 392 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); 393 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3)); 394 } 395 396 /* 397 * pre_init: 0: pre init for dram cap detect 398 * 1: detect correct cap(except cs1 row)info, than reinit 399 * 2: after reinit, we detect cs1_row, if cs1_row not equal 400 * to cs0_row and cs is in middle on ddrconf map, we need 401 * to reinit dram, than set the correct ddrconf. 402 */ 403 static int sdram_init_(struct dram_info *dram, 404 struct px30_sdram_params *sdram_params, u32 pre_init) 405 { 406 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 407 void __iomem *pctl_base = dram->pctl; 408 409 rkclk_ddr_reset(dram, 1, 1, 1, 1); 410 udelay(10); 411 /* 412 * dereset ddr phy psrstn to config pll, 413 * if using phy pll psrstn must be dereset 414 * before config pll 415 */ 416 rkclk_ddr_reset(dram, 1, 1, 1, 0); 417 rkclk_configure_ddr(dram, sdram_params); 418 419 /* release phy srst to provide clk to ctrl */ 420 rkclk_ddr_reset(dram, 1, 1, 0, 0); 421 udelay(10); 422 phy_soft_reset(dram->phy); 423 /* release ctrl presetn, and config ctl registers */ 424 rkclk_ddr_reset(dram, 1, 0, 0, 0); 425 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE); 426 cap_info->ddrconfig = calculate_ddrconfig(sdram_params); 427 set_ctl_address_map(dram, sdram_params); 428 phy_cfg(dram->phy, &sdram_params->phy_regs, sdram_params->skew, 429 &sdram_params->base, cap_info->bw); 430 431 /* enable dfi_init_start to init phy after ctl srstn deassert */ 432 setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4)); 433 434 rkclk_ddr_reset(dram, 0, 0, 0, 0); 435 /* wait for dfi_init_done and dram init complete */ 436 while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) 437 continue; 438 439 if (sdram_params->base.dramtype == LPDDR3) 440 pctl_write_mr(dram->pctl, 3, 11, 3, LPDDR3); 441 442 /* do ddr gate training */ 443 redo_cs0_training: 444 if (data_training(dram, 0, sdram_params->base.dramtype) != 0) { 445 if (pre_init != 0) 446 printascii("DTT cs0 error\n"); 447 return -1; 448 } 449 if (check_rd_gate(dram)) { 450 printascii("re training cs0"); 451 goto redo_cs0_training; 452 } 453 454 if (sdram_params->base.dramtype == LPDDR3) { 455 if ((read_mr(dram, 1, 8) & 0x3) != 0x3) 456 return -1; 457 } else if (sdram_params->base.dramtype == LPDDR2) { 458 if ((read_mr(dram, 1, 8) & 0x3) != 0x0) 459 return -1; 460 } 461 /* for px30: when 2cs, both 2 cs should be training */ 462 if (pre_init != 0 && cap_info->rank == 2) { 463 redo_cs1_training: 464 if (data_training(dram, 1, sdram_params->base.dramtype) != 0) { 465 printascii("DTT cs1 error\n"); 466 return -1; 467 } 468 if (check_rd_gate(dram)) { 469 printascii("re training cs1"); 470 goto redo_cs1_training; 471 } 472 } 473 474 if (sdram_params->base.dramtype == DDR4) 475 pctl_write_vrefdq(dram->pctl, 0x3, 5670, 476 sdram_params->base.dramtype); 477 478 dram_all_config(dram, sdram_params); 479 enable_low_power(dram, sdram_params); 480 481 return 0; 482 } 483 484 static int dram_detect_cap(struct dram_info *dram, 485 struct px30_sdram_params *sdram_params, 486 unsigned char channel) 487 { 488 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 489 490 /* 491 * for ddr3: ddrconf = 3 492 * for ddr4: ddrconf = 12 493 * for lpddr3: ddrconf = 3 494 * default bw = 1 495 */ 496 u32 bk, bktmp; 497 u32 col, coltmp; 498 u32 rowtmp; 499 u32 cs; 500 u32 bw = 1; 501 u32 dram_type = sdram_params->base.dramtype; 502 503 if (dram_type != DDR4) { 504 /* detect col and bk for ddr3/lpddr3 */ 505 coltmp = 12; 506 bktmp = 3; 507 if (dram_type == LPDDR2) 508 rowtmp = 15; 509 else 510 rowtmp = 16; 511 512 if (sdram_detect_col(cap_info, coltmp) != 0) 513 goto cap_err; 514 sdram_detect_bank(cap_info, coltmp, bktmp); 515 sdram_detect_dbw(cap_info, dram_type); 516 } else { 517 /* detect bg for ddr4 */ 518 coltmp = 10; 519 bktmp = 4; 520 rowtmp = 17; 521 522 col = 10; 523 bk = 2; 524 cap_info->col = col; 525 cap_info->bk = bk; 526 sdram_detect_bg(cap_info, coltmp); 527 } 528 529 /* detect row */ 530 if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0) 531 goto cap_err; 532 533 /* detect row_3_4 */ 534 sdram_detect_row_3_4(cap_info, coltmp, bktmp); 535 536 /* bw and cs detect using data training */ 537 if (data_training(dram, 1, dram_type) == 0) 538 cs = 1; 539 else 540 cs = 0; 541 cap_info->rank = cs + 1; 542 543 dram_set_bw(dram, 2); 544 if (data_training(dram, 0, dram_type) == 0) 545 bw = 2; 546 else 547 bw = 1; 548 cap_info->bw = bw; 549 550 cap_info->cs0_high16bit_row = cap_info->cs0_row; 551 if (cs) { 552 cap_info->cs1_row = cap_info->cs0_row; 553 cap_info->cs1_high16bit_row = cap_info->cs0_row; 554 } else { 555 cap_info->cs1_row = 0; 556 cap_info->cs1_high16bit_row = 0; 557 } 558 559 return 0; 560 cap_err: 561 return -1; 562 } 563 564 void get_ddr_param(struct px30_sdram_params *sdram_params, 565 struct ddr_param *ddr_param) 566 { 567 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 568 u32 dram_type = sdram_params->base.dramtype; 569 u64 cs_cap[2]; 570 571 cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dram_type); 572 cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dram_type); 573 574 if (cap_info->row_3_4) { 575 cs_cap[0] = cs_cap[0] * 3 / 4; 576 cs_cap[1] = cs_cap[1] * 3 / 4; 577 } 578 579 if (cap_info->row_3_4 && cap_info->rank == 2) { 580 ddr_param->count = 2; 581 ddr_param->para[0] = 0; 582 ddr_param->para[1] = cs_cap[0] * 4 / 3; 583 ddr_param->para[2] = cs_cap[0]; 584 ddr_param->para[3] = cs_cap[1]; 585 } else { 586 ddr_param->count = 1; 587 ddr_param->para[0] = 0; 588 ddr_param->para[1] = (u64)cs_cap[0] + (u64)cs_cap[1]; 589 } 590 } 591 592 /* return: 0 = success, other = fail */ 593 static int sdram_init_detect(struct dram_info *dram, 594 struct px30_sdram_params *sdram_params) 595 { 596 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 597 u32 ret; 598 u32 sys_reg = 0; 599 u32 sys_reg3 = 0; 600 601 if (sdram_init_(dram, sdram_params, 0) != 0) 602 return -1; 603 604 if (dram_detect_cap(dram, sdram_params, 0) != 0) 605 return -1; 606 607 /* modify bw, cs related timing */ 608 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, 609 sdram_params->base.dramtype); 610 /* reinit sdram by real dram cap */ 611 ret = sdram_init_(dram, sdram_params, 1); 612 if (ret != 0) 613 goto out; 614 615 /* redetect cs1 row */ 616 sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); 617 if (cap_info->cs1_row) { 618 sys_reg = readl(&dram->pmugrf->os_reg[2]); 619 sys_reg3 = readl(&dram->pmugrf->os_reg[3]); 620 SYS_REG_ENC_CS1_ROW(cap_info->cs1_row, 621 sys_reg, sys_reg3, 0); 622 writel(sys_reg, &dram->pmugrf->os_reg[2]); 623 writel(sys_reg3, &dram->pmugrf->os_reg[3]); 624 } 625 626 ret = sdram_detect_high_row(cap_info); 627 628 out: 629 return ret; 630 } 631 632 struct px30_sdram_params 633 *get_default_sdram_config(void) 634 { 635 sdram_configs[0].skew = &skew; 636 637 return &sdram_configs[0]; 638 } 639 640 /* return: 0 = success, other = fail */ 641 int sdram_init(void) 642 { 643 struct px30_sdram_params *sdram_params; 644 int ret = 0; 645 struct ddr_param ddr_param; 646 647 dram_info.phy = (void *)DDR_PHY_BASE_ADDR; 648 dram_info.pctl = (void *)DDRC_BASE_ADDR; 649 dram_info.grf = (void *)GRF_BASE_ADDR; 650 dram_info.cru = (void *)CRU_BASE_ADDR; 651 dram_info.msch = (void *)SERVER_MSCH0_BASE_ADDR; 652 dram_info.ddr_grf = (void *)DDR_GRF_BASE_ADDR; 653 dram_info.pmugrf = (void *)PMUGRF_BASE_ADDR; 654 655 sdram_params = get_default_sdram_config(); 656 ret = sdram_init_detect(&dram_info, sdram_params); 657 658 if (ret) 659 goto error; 660 661 get_ddr_param(sdram_params, &ddr_param); 662 rockchip_setup_ddr_param(&ddr_param); 663 sdram_print_ddr_info(&sdram_params->ch.cap_info, 664 &sdram_params->base, 0); 665 666 printascii("out\n"); 667 return ret; 668 error: 669 return (-1); 670 } 671 #endif /* CONFIG_TPL_BUILD */ 672