1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 4 */ 5 #include <asm/arch/rockchip_smccc.h> 6 #include <asm/arch/rockchip_dmc.h> 7 #include <asm/io.h> 8 #include <asm/psci.h> 9 #include <common.h> 10 #include <clk.h> 11 #include <dm.h> 12 #include <dm/of_access.h> 13 #include <dt-structs.h> 14 #include <linux/arm-smccc.h> 15 #include <linux/err.h> 16 #include <linux/errno.h> 17 #include <ram.h> 18 #include <regmap.h> 19 20 #define DTS_PAR_OFFSET (4096) 21 22 struct share_params { 23 u32 hz; 24 u32 lcdc_type; 25 u32 vop; 26 u32 vop_dclk_mode; 27 u32 sr_idle_en; 28 u32 addr_mcu_el3; 29 /* 30 * 1: need to wait flag1 31 * 0: never wait flag1 32 */ 33 u32 wait_flag1; 34 /* 35 * 1: need to wait flag1 36 * 0: never wait flag1 37 */ 38 u32 wait_flag0; 39 u32 complt_hwirq; 40 /* if need, add parameter after */ 41 }; 42 43 static struct share_params *ddr_psci_param; 44 45 /* hope this define can adapt all future platfor */ 46 static const char * const rk3328_dts_timing[] = { 47 "ddr3_speed_bin", 48 "ddr4_speed_bin", 49 "pd_idle", 50 "sr_idle", 51 "sr_mc_gate_idle", 52 "srpd_lite_idle", 53 "standby_idle", 54 55 "auto_pd_dis_freq", 56 "auto_sr_dis_freq", 57 "ddr3_dll_dis_freq", 58 "ddr4_dll_dis_freq", 59 "phy_dll_dis_freq", 60 61 "ddr3_odt_dis_freq", 62 "phy_ddr3_odt_dis_freq", 63 "ddr3_drv", 64 "ddr3_odt", 65 "phy_ddr3_ca_drv", 66 "phy_ddr3_ck_drv", 67 "phy_ddr3_dq_drv", 68 "phy_ddr3_odt", 69 70 "lpddr3_odt_dis_freq", 71 "phy_lpddr3_odt_dis_freq", 72 "lpddr3_drv", 73 "lpddr3_odt", 74 "phy_lpddr3_ca_drv", 75 "phy_lpddr3_ck_drv", 76 "phy_lpddr3_dq_drv", 77 "phy_lpddr3_odt", 78 79 "lpddr4_odt_dis_freq", 80 "phy_lpddr4_odt_dis_freq", 81 "lpddr4_drv", 82 "lpddr4_dq_odt", 83 "lpddr4_ca_odt", 84 "phy_lpddr4_ca_drv", 85 "phy_lpddr4_ck_cs_drv", 86 "phy_lpddr4_dq_drv", 87 "phy_lpddr4_odt", 88 89 "ddr4_odt_dis_freq", 90 "phy_ddr4_odt_dis_freq", 91 "ddr4_drv", 92 "ddr4_odt", 93 "phy_ddr4_ca_drv", 94 "phy_ddr4_ck_drv", 95 "phy_ddr4_dq_drv", 96 "phy_ddr4_odt", 97 }; 98 99 static const char * const px30_dts_timing[] = { 100 "ddr2_speed_bin", 101 "ddr3_speed_bin", 102 "ddr4_speed_bin", 103 "pd_idle", 104 "sr_idle", 105 "sr_mc_gate_idle", 106 "srpd_lite_idle", 107 "standby_idle", 108 109 "auto_pd_dis_freq", 110 "auto_sr_dis_freq", 111 "ddr2_dll_dis_freq", 112 "ddr3_dll_dis_freq", 113 "ddr4_dll_dis_freq", 114 "phy_dll_dis_freq", 115 116 "ddr2_odt_dis_freq", 117 "phy_ddr2_odt_dis_freq", 118 "ddr2_drv", 119 "ddr2_odt", 120 "phy_ddr2_ca_drv", 121 "phy_ddr2_ck_drv", 122 "phy_ddr2_dq_drv", 123 "phy_ddr2_odt", 124 125 "ddr3_odt_dis_freq", 126 "phy_ddr3_odt_dis_freq", 127 "ddr3_drv", 128 "ddr3_odt", 129 "phy_ddr3_ca_drv", 130 "phy_ddr3_ck_drv", 131 "phy_ddr3_dq_drv", 132 "phy_ddr3_odt", 133 134 "phy_lpddr2_odt_dis_freq", 135 "lpddr2_drv", 136 "phy_lpddr2_ca_drv", 137 "phy_lpddr2_ck_drv", 138 "phy_lpddr2_dq_drv", 139 "phy_lpddr2_odt", 140 141 "lpddr3_odt_dis_freq", 142 "phy_lpddr3_odt_dis_freq", 143 "lpddr3_drv", 144 "lpddr3_odt", 145 "phy_lpddr3_ca_drv", 146 "phy_lpddr3_ck_drv", 147 "phy_lpddr3_dq_drv", 148 "phy_lpddr3_odt", 149 150 "lpddr4_odt_dis_freq", 151 "phy_lpddr4_odt_dis_freq", 152 "lpddr4_drv", 153 "lpddr4_dq_odt", 154 "lpddr4_ca_odt", 155 "phy_lpddr4_ca_drv", 156 "phy_lpddr4_ck_cs_drv", 157 "phy_lpddr4_dq_drv", 158 "phy_lpddr4_odt", 159 160 "ddr4_odt_dis_freq", 161 "phy_ddr4_odt_dis_freq", 162 "ddr4_drv", 163 "ddr4_odt", 164 "phy_ddr4_ca_drv", 165 "phy_ddr4_ck_drv", 166 "phy_ddr4_dq_drv", 167 "phy_ddr4_odt", 168 }; 169 170 static const char * const rk3328_dts_ca_timing[] = { 171 "ddr3a1_ddr4a9_de-skew", 172 "ddr3a0_ddr4a10_de-skew", 173 "ddr3a3_ddr4a6_de-skew", 174 "ddr3a2_ddr4a4_de-skew", 175 "ddr3a5_ddr4a8_de-skew", 176 "ddr3a4_ddr4a5_de-skew", 177 "ddr3a7_ddr4a11_de-skew", 178 "ddr3a6_ddr4a7_de-skew", 179 "ddr3a9_ddr4a0_de-skew", 180 "ddr3a8_ddr4a13_de-skew", 181 "ddr3a11_ddr4a3_de-skew", 182 "ddr3a10_ddr4cs0_de-skew", 183 "ddr3a13_ddr4a2_de-skew", 184 "ddr3a12_ddr4ba1_de-skew", 185 "ddr3a15_ddr4odt0_de-skew", 186 "ddr3a14_ddr4a1_de-skew", 187 "ddr3ba1_ddr4a15_de-skew", 188 "ddr3ba0_ddr4bg0_de-skew", 189 "ddr3ras_ddr4cke_de-skew", 190 "ddr3ba2_ddr4ba0_de-skew", 191 "ddr3we_ddr4bg1_de-skew", 192 "ddr3cas_ddr4a12_de-skew", 193 "ddr3ckn_ddr4ckn_de-skew", 194 "ddr3ckp_ddr4ckp_de-skew", 195 "ddr3cke_ddr4a16_de-skew", 196 "ddr3odt0_ddr4a14_de-skew", 197 "ddr3cs0_ddr4act_de-skew", 198 "ddr3reset_ddr4reset_de-skew", 199 "ddr3cs1_ddr4cs1_de-skew", 200 "ddr3odt1_ddr4odt1_de-skew", 201 }; 202 203 static const char * const rk3328_dts_cs0_timing[] = { 204 "cs0_dm0_rx_de-skew", 205 "cs0_dm0_tx_de-skew", 206 "cs0_dq0_rx_de-skew", 207 "cs0_dq0_tx_de-skew", 208 "cs0_dq1_rx_de-skew", 209 "cs0_dq1_tx_de-skew", 210 "cs0_dq2_rx_de-skew", 211 "cs0_dq2_tx_de-skew", 212 "cs0_dq3_rx_de-skew", 213 "cs0_dq3_tx_de-skew", 214 "cs0_dq4_rx_de-skew", 215 "cs0_dq4_tx_de-skew", 216 "cs0_dq5_rx_de-skew", 217 "cs0_dq5_tx_de-skew", 218 "cs0_dq6_rx_de-skew", 219 "cs0_dq6_tx_de-skew", 220 "cs0_dq7_rx_de-skew", 221 "cs0_dq7_tx_de-skew", 222 "cs0_dqs0_rx_de-skew", 223 "cs0_dqs0p_tx_de-skew", 224 "cs0_dqs0n_tx_de-skew", 225 226 "cs0_dm1_rx_de-skew", 227 "cs0_dm1_tx_de-skew", 228 "cs0_dq8_rx_de-skew", 229 "cs0_dq8_tx_de-skew", 230 "cs0_dq9_rx_de-skew", 231 "cs0_dq9_tx_de-skew", 232 "cs0_dq10_rx_de-skew", 233 "cs0_dq10_tx_de-skew", 234 "cs0_dq11_rx_de-skew", 235 "cs0_dq11_tx_de-skew", 236 "cs0_dq12_rx_de-skew", 237 "cs0_dq12_tx_de-skew", 238 "cs0_dq13_rx_de-skew", 239 "cs0_dq13_tx_de-skew", 240 "cs0_dq14_rx_de-skew", 241 "cs0_dq14_tx_de-skew", 242 "cs0_dq15_rx_de-skew", 243 "cs0_dq15_tx_de-skew", 244 "cs0_dqs1_rx_de-skew", 245 "cs0_dqs1p_tx_de-skew", 246 "cs0_dqs1n_tx_de-skew", 247 248 "cs0_dm2_rx_de-skew", 249 "cs0_dm2_tx_de-skew", 250 "cs0_dq16_rx_de-skew", 251 "cs0_dq16_tx_de-skew", 252 "cs0_dq17_rx_de-skew", 253 "cs0_dq17_tx_de-skew", 254 "cs0_dq18_rx_de-skew", 255 "cs0_dq18_tx_de-skew", 256 "cs0_dq19_rx_de-skew", 257 "cs0_dq19_tx_de-skew", 258 "cs0_dq20_rx_de-skew", 259 "cs0_dq20_tx_de-skew", 260 "cs0_dq21_rx_de-skew", 261 "cs0_dq21_tx_de-skew", 262 "cs0_dq22_rx_de-skew", 263 "cs0_dq22_tx_de-skew", 264 "cs0_dq23_rx_de-skew", 265 "cs0_dq23_tx_de-skew", 266 "cs0_dqs2_rx_de-skew", 267 "cs0_dqs2p_tx_de-skew", 268 "cs0_dqs2n_tx_de-skew", 269 270 "cs0_dm3_rx_de-skew", 271 "cs0_dm3_tx_de-skew", 272 "cs0_dq24_rx_de-skew", 273 "cs0_dq24_tx_de-skew", 274 "cs0_dq25_rx_de-skew", 275 "cs0_dq25_tx_de-skew", 276 "cs0_dq26_rx_de-skew", 277 "cs0_dq26_tx_de-skew", 278 "cs0_dq27_rx_de-skew", 279 "cs0_dq27_tx_de-skew", 280 "cs0_dq28_rx_de-skew", 281 "cs0_dq28_tx_de-skew", 282 "cs0_dq29_rx_de-skew", 283 "cs0_dq29_tx_de-skew", 284 "cs0_dq30_rx_de-skew", 285 "cs0_dq30_tx_de-skew", 286 "cs0_dq31_rx_de-skew", 287 "cs0_dq31_tx_de-skew", 288 "cs0_dqs3_rx_de-skew", 289 "cs0_dqs3p_tx_de-skew", 290 "cs0_dqs3n_tx_de-skew", 291 }; 292 293 static const char * const rk3328_dts_cs1_timing[] = { 294 "cs1_dm0_rx_de-skew", 295 "cs1_dm0_tx_de-skew", 296 "cs1_dq0_rx_de-skew", 297 "cs1_dq0_tx_de-skew", 298 "cs1_dq1_rx_de-skew", 299 "cs1_dq1_tx_de-skew", 300 "cs1_dq2_rx_de-skew", 301 "cs1_dq2_tx_de-skew", 302 "cs1_dq3_rx_de-skew", 303 "cs1_dq3_tx_de-skew", 304 "cs1_dq4_rx_de-skew", 305 "cs1_dq4_tx_de-skew", 306 "cs1_dq5_rx_de-skew", 307 "cs1_dq5_tx_de-skew", 308 "cs1_dq6_rx_de-skew", 309 "cs1_dq6_tx_de-skew", 310 "cs1_dq7_rx_de-skew", 311 "cs1_dq7_tx_de-skew", 312 "cs1_dqs0_rx_de-skew", 313 "cs1_dqs0p_tx_de-skew", 314 "cs1_dqs0n_tx_de-skew", 315 316 "cs1_dm1_rx_de-skew", 317 "cs1_dm1_tx_de-skew", 318 "cs1_dq8_rx_de-skew", 319 "cs1_dq8_tx_de-skew", 320 "cs1_dq9_rx_de-skew", 321 "cs1_dq9_tx_de-skew", 322 "cs1_dq10_rx_de-skew", 323 "cs1_dq10_tx_de-skew", 324 "cs1_dq11_rx_de-skew", 325 "cs1_dq11_tx_de-skew", 326 "cs1_dq12_rx_de-skew", 327 "cs1_dq12_tx_de-skew", 328 "cs1_dq13_rx_de-skew", 329 "cs1_dq13_tx_de-skew", 330 "cs1_dq14_rx_de-skew", 331 "cs1_dq14_tx_de-skew", 332 "cs1_dq15_rx_de-skew", 333 "cs1_dq15_tx_de-skew", 334 "cs1_dqs1_rx_de-skew", 335 "cs1_dqs1p_tx_de-skew", 336 "cs1_dqs1n_tx_de-skew", 337 338 "cs1_dm2_rx_de-skew", 339 "cs1_dm2_tx_de-skew", 340 "cs1_dq16_rx_de-skew", 341 "cs1_dq16_tx_de-skew", 342 "cs1_dq17_rx_de-skew", 343 "cs1_dq17_tx_de-skew", 344 "cs1_dq18_rx_de-skew", 345 "cs1_dq18_tx_de-skew", 346 "cs1_dq19_rx_de-skew", 347 "cs1_dq19_tx_de-skew", 348 "cs1_dq20_rx_de-skew", 349 "cs1_dq20_tx_de-skew", 350 "cs1_dq21_rx_de-skew", 351 "cs1_dq21_tx_de-skew", 352 "cs1_dq22_rx_de-skew", 353 "cs1_dq22_tx_de-skew", 354 "cs1_dq23_rx_de-skew", 355 "cs1_dq23_tx_de-skew", 356 "cs1_dqs2_rx_de-skew", 357 "cs1_dqs2p_tx_de-skew", 358 "cs1_dqs2n_tx_de-skew", 359 360 "cs1_dm3_rx_de-skew", 361 "cs1_dm3_tx_de-skew", 362 "cs1_dq24_rx_de-skew", 363 "cs1_dq24_tx_de-skew", 364 "cs1_dq25_rx_de-skew", 365 "cs1_dq25_tx_de-skew", 366 "cs1_dq26_rx_de-skew", 367 "cs1_dq26_tx_de-skew", 368 "cs1_dq27_rx_de-skew", 369 "cs1_dq27_tx_de-skew", 370 "cs1_dq28_rx_de-skew", 371 "cs1_dq28_tx_de-skew", 372 "cs1_dq29_rx_de-skew", 373 "cs1_dq29_tx_de-skew", 374 "cs1_dq30_rx_de-skew", 375 "cs1_dq30_tx_de-skew", 376 "cs1_dq31_rx_de-skew", 377 "cs1_dq31_tx_de-skew", 378 "cs1_dqs3_rx_de-skew", 379 "cs1_dqs3p_tx_de-skew", 380 "cs1_dqs3n_tx_de-skew", 381 }; 382 383 struct rk3328_ddr_dts_config_timing { 384 unsigned int ddr3_speed_bin; 385 unsigned int ddr4_speed_bin; 386 unsigned int pd_idle; 387 unsigned int sr_idle; 388 unsigned int sr_mc_gate_idle; 389 unsigned int srpd_lite_idle; 390 unsigned int standby_idle; 391 392 unsigned int auto_pd_dis_freq; 393 unsigned int auto_sr_dis_freq; 394 /* for ddr3 only */ 395 unsigned int ddr3_dll_dis_freq; 396 /* for ddr4 only */ 397 unsigned int ddr4_dll_dis_freq; 398 unsigned int phy_dll_dis_freq; 399 400 unsigned int ddr3_odt_dis_freq; 401 unsigned int phy_ddr3_odt_dis_freq; 402 unsigned int ddr3_drv; 403 unsigned int ddr3_odt; 404 unsigned int phy_ddr3_ca_drv; 405 unsigned int phy_ddr3_ck_drv; 406 unsigned int phy_ddr3_dq_drv; 407 unsigned int phy_ddr3_odt; 408 409 unsigned int lpddr3_odt_dis_freq; 410 unsigned int phy_lpddr3_odt_dis_freq; 411 unsigned int lpddr3_drv; 412 unsigned int lpddr3_odt; 413 unsigned int phy_lpddr3_ca_drv; 414 unsigned int phy_lpddr3_ck_drv; 415 unsigned int phy_lpddr3_dq_drv; 416 unsigned int phy_lpddr3_odt; 417 418 unsigned int lpddr4_odt_dis_freq; 419 unsigned int phy_lpddr4_odt_dis_freq; 420 unsigned int lpddr4_drv; 421 unsigned int lpddr4_dq_odt; 422 unsigned int lpddr4_ca_odt; 423 unsigned int phy_lpddr4_ca_drv; 424 unsigned int phy_lpddr4_ck_cs_drv; 425 unsigned int phy_lpddr4_dq_drv; 426 unsigned int phy_lpddr4_odt; 427 428 unsigned int ddr4_odt_dis_freq; 429 unsigned int phy_ddr4_odt_dis_freq; 430 unsigned int ddr4_drv; 431 unsigned int ddr4_odt; 432 unsigned int phy_ddr4_ca_drv; 433 unsigned int phy_ddr4_ck_drv; 434 unsigned int phy_ddr4_dq_drv; 435 unsigned int phy_ddr4_odt; 436 437 unsigned int ca_skew[15]; 438 unsigned int cs0_skew[44]; 439 unsigned int cs1_skew[44]; 440 441 unsigned int available; 442 }; 443 444 struct px30_ddr_dts_config_timing { 445 unsigned int ddr2_speed_bin; 446 unsigned int ddr3_speed_bin; 447 unsigned int ddr4_speed_bin; 448 unsigned int pd_idle; 449 unsigned int sr_idle; 450 unsigned int sr_mc_gate_idle; 451 unsigned int srpd_lite_idle; 452 unsigned int standby_idle; 453 454 unsigned int auto_pd_dis_freq; 455 unsigned int auto_sr_dis_freq; 456 /* for ddr2 only */ 457 unsigned int ddr2_dll_dis_freq; 458 /* for ddr3 only */ 459 unsigned int ddr3_dll_dis_freq; 460 /* for ddr4 only */ 461 unsigned int ddr4_dll_dis_freq; 462 unsigned int phy_dll_dis_freq; 463 464 unsigned int ddr2_odt_dis_freq; 465 unsigned int phy_ddr2_odt_dis_freq; 466 unsigned int ddr2_drv; 467 unsigned int ddr2_odt; 468 unsigned int phy_ddr2_ca_drv; 469 unsigned int phy_ddr2_ck_drv; 470 unsigned int phy_ddr2_dq_drv; 471 unsigned int phy_ddr2_odt; 472 473 unsigned int ddr3_odt_dis_freq; 474 unsigned int phy_ddr3_odt_dis_freq; 475 unsigned int ddr3_drv; 476 unsigned int ddr3_odt; 477 unsigned int phy_ddr3_ca_drv; 478 unsigned int phy_ddr3_ck_drv; 479 unsigned int phy_ddr3_dq_drv; 480 unsigned int phy_ddr3_odt; 481 482 unsigned int phy_lpddr2_odt_dis_freq; 483 unsigned int lpddr2_drv; 484 unsigned int phy_lpddr2_ca_drv; 485 unsigned int phy_lpddr2_ck_drv; 486 unsigned int phy_lpddr2_dq_drv; 487 unsigned int phy_lpddr2_odt; 488 489 unsigned int lpddr3_odt_dis_freq; 490 unsigned int phy_lpddr3_odt_dis_freq; 491 unsigned int lpddr3_drv; 492 unsigned int lpddr3_odt; 493 unsigned int phy_lpddr3_ca_drv; 494 unsigned int phy_lpddr3_ck_drv; 495 unsigned int phy_lpddr3_dq_drv; 496 unsigned int phy_lpddr3_odt; 497 498 unsigned int lpddr4_odt_dis_freq; 499 unsigned int phy_lpddr4_odt_dis_freq; 500 unsigned int lpddr4_drv; 501 unsigned int lpddr4_dq_odt; 502 unsigned int lpddr4_ca_odt; 503 unsigned int phy_lpddr4_ca_drv; 504 unsigned int phy_lpddr4_ck_cs_drv; 505 unsigned int phy_lpddr4_dq_drv; 506 unsigned int phy_lpddr4_odt; 507 508 unsigned int ddr4_odt_dis_freq; 509 unsigned int phy_ddr4_odt_dis_freq; 510 unsigned int ddr4_drv; 511 unsigned int ddr4_odt; 512 unsigned int phy_ddr4_ca_drv; 513 unsigned int phy_ddr4_ck_drv; 514 unsigned int phy_ddr4_dq_drv; 515 unsigned int phy_ddr4_odt; 516 517 unsigned int ca_skew[15]; 518 unsigned int cs0_skew[44]; 519 unsigned int cs1_skew[44]; 520 521 unsigned int available; 522 }; 523 524 struct rk3328_ddr_de_skew_setting { 525 unsigned int ca_de_skew[30]; 526 unsigned int cs0_de_skew[84]; 527 unsigned int cs1_de_skew[84]; 528 }; 529 530 static void 531 rk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew, 532 struct rk3328_ddr_dts_config_timing *tim) 533 { 534 u32 n; 535 u32 offset; 536 u32 shift; 537 538 memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew)); 539 memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew)); 540 memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew)); 541 542 /* CA de-skew */ 543 for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) { 544 offset = n / 2; 545 shift = n % 2; 546 /* 0 => 4; 1 => 0 */ 547 shift = (shift == 0) ? 4 : 0; 548 tim->ca_skew[offset] &= ~(0xf << shift); 549 tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift); 550 } 551 552 /* CS0 data de-skew */ 553 for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) { 554 offset = ((n / 21) * 11) + ((n % 21) / 2); 555 shift = ((n % 21) % 2); 556 if ((n % 21) == 20) 557 shift = 0; 558 else 559 /* 0 => 4; 1 => 0 */ 560 shift = (shift == 0) ? 4 : 0; 561 tim->cs0_skew[offset] &= ~(0xf << shift); 562 tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift); 563 } 564 565 /* CS1 data de-skew */ 566 for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) { 567 offset = ((n / 21) * 11) + ((n % 21) / 2); 568 shift = ((n % 21) % 2); 569 if ((n % 21) == 20) 570 shift = 0; 571 else 572 /* 0 => 4; 1 => 0 */ 573 shift = (shift == 0) ? 4 : 0; 574 tim->cs1_skew[offset] &= ~(0xf << shift); 575 tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift); 576 } 577 } 578 579 static void px30_de_skew_set_2_reg(struct rk3328_ddr_de_skew_setting *de_skew, 580 struct px30_ddr_dts_config_timing *tim) 581 { 582 u32 n; 583 u32 offset; 584 u32 shift; 585 586 memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew)); 587 memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew)); 588 memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew)); 589 590 /* CA de-skew */ 591 for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) { 592 offset = n / 2; 593 shift = n % 2; 594 /* 0 => 4; 1 => 0 */ 595 shift = (shift == 0) ? 4 : 0; 596 tim->ca_skew[offset] &= ~(0xf << shift); 597 tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift); 598 } 599 600 /* CS0 data de-skew */ 601 for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) { 602 offset = ((n / 21) * 11) + ((n % 21) / 2); 603 shift = ((n % 21) % 2); 604 if ((n % 21) == 20) 605 shift = 0; 606 else 607 /* 0 => 4; 1 => 0 */ 608 shift = (shift == 0) ? 4 : 0; 609 tim->cs0_skew[offset] &= ~(0xf << shift); 610 tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift); 611 } 612 613 /* CS1 data de-skew */ 614 for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) { 615 offset = ((n / 21) * 11) + ((n % 21) / 2); 616 shift = ((n % 21) % 2); 617 if ((n % 21) == 20) 618 shift = 0; 619 else 620 /* 0 => 4; 1 => 0 */ 621 shift = (shift == 0) ? 4 : 0; 622 tim->cs1_skew[offset] &= ~(0xf << shift); 623 tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift); 624 } 625 } 626 627 static void of_get_rk3328_timings(struct udevice *dev, uint32_t *timing) 628 { 629 struct device_node *np_tim; 630 u32 *p; 631 struct rk3328_ddr_dts_config_timing *dts_timing; 632 struct rk3328_ddr_de_skew_setting *de_skew; 633 int ret = 0; 634 u32 i; 635 636 dts_timing = 637 (struct rk3328_ddr_dts_config_timing *)(timing + 638 DTS_PAR_OFFSET / 4); 639 640 np_tim = of_parse_phandle(ofnode_to_np(dev_ofnode(dev)), 641 "ddr_timing", 0); 642 if (!np_tim) { 643 ret = -EINVAL; 644 goto end; 645 } 646 de_skew = malloc(sizeof(*de_skew)); 647 if (!de_skew) { 648 ret = -ENOMEM; 649 goto end; 650 } 651 p = (u32 *)dts_timing; 652 for (i = 0; i < ARRAY_SIZE(rk3328_dts_timing); i++) 653 ret |= ofnode_read_u32(np_to_ofnode(np_tim), 654 rk3328_dts_timing[i], p + i); 655 656 p = (u32 *)de_skew->ca_de_skew; 657 for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) 658 ret |= ofnode_read_u32(np_to_ofnode(np_tim), 659 rk3328_dts_ca_timing[i], p + i); 660 p = (u32 *)de_skew->cs0_de_skew; 661 for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) 662 ret |= ofnode_read_u32(np_to_ofnode(np_tim), 663 rk3328_dts_cs0_timing[i], p + i); 664 p = (u32 *)de_skew->cs1_de_skew; 665 for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) 666 ret |= ofnode_read_u32(np_to_ofnode(np_tim), 667 rk3328_dts_cs1_timing[i], p + i); 668 669 if (!ret) 670 rk3328_de_skew_setting_2_register(de_skew, dts_timing); 671 free(de_skew); 672 end: 673 if (!ret) { 674 dts_timing->available = 1; 675 } else { 676 dts_timing->available = 0; 677 printf("of_get_ddr_timings: fail\n"); 678 } 679 } 680 681 static void of_get_px30_timings(struct udevice *dev, uint32_t *timing) 682 { 683 struct device_node *np_tim; 684 u32 *p; 685 struct px30_ddr_dts_config_timing *dts_timing; 686 struct rk3328_ddr_de_skew_setting *de_skew; 687 int ret = 0; 688 u32 i; 689 690 dts_timing = 691 (struct px30_ddr_dts_config_timing *)(timing + 692 DTS_PAR_OFFSET / 4); 693 694 np_tim = of_parse_phandle(ofnode_to_np(dev_ofnode(dev)), 695 "ddr_timing", 0); 696 if (!np_tim) { 697 ret = -EINVAL; 698 goto end; 699 } 700 de_skew = malloc(sizeof(*de_skew)); 701 if (!de_skew) { 702 ret = -ENOMEM; 703 goto end; 704 } 705 p = (u32 *)dts_timing; 706 for (i = 0; i < ARRAY_SIZE(px30_dts_timing); i++) 707 ret |= ofnode_read_u32(np_to_ofnode(np_tim), px30_dts_timing[i], 708 p + i); 709 p = (u32 *)de_skew->ca_de_skew; 710 for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) 711 ret |= ofnode_read_u32(np_to_ofnode(np_tim), 712 rk3328_dts_ca_timing[i], p + i); 713 p = (u32 *)de_skew->cs0_de_skew; 714 for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) 715 ret |= ofnode_read_u32(np_to_ofnode(np_tim), 716 rk3328_dts_cs0_timing[i], p + i); 717 p = (u32 *)de_skew->cs1_de_skew; 718 for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) 719 ret |= ofnode_read_u32(np_to_ofnode(np_tim), 720 rk3328_dts_cs1_timing[i], p + i); 721 if (!ret) 722 px30_de_skew_set_2_reg(de_skew, dts_timing); 723 free(de_skew); 724 end: 725 if (!ret) { 726 dts_timing->available = 1; 727 } else { 728 dts_timing->available = 0; 729 printf("of_get_ddr_timings: fail\n"); 730 } 731 } 732 733 static __maybe_unused int rk3328_devfreq_init(struct udevice *dev) 734 { 735 struct arm_smccc_res res; 736 u32 size; 737 738 res = sip_smc_dram(0, 0, 739 ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION); 740 printf("current ATF version 0x%lx!\n", res.a1); 741 if (res.a0 || res.a1 < 0x101) { 742 printf("trusted firmware need to update or is invalid!\n"); 743 return -ENXIO; 744 } 745 746 printf("read tf version 0x%lx!\n", res.a1); 747 748 /* 749 * first 4KB is used for interface parameters 750 * after 4KB * N is dts parameters 751 */ 752 size = sizeof(struct rk3328_ddr_dts_config_timing); 753 res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1, 754 SHARE_PAGE_TYPE_DDR); 755 if (res.a0 != 0) { 756 printf("no ATF memory for init\n"); 757 return -ENOMEM; 758 } 759 ddr_psci_param = (struct share_params *)res.a1; 760 of_get_rk3328_timings(dev, (uint32_t *)ddr_psci_param); 761 762 flush_cache((unsigned long)ddr_psci_param, 763 (DIV_ROUND_UP(size, 4096) + 1) * 0x1000); 764 765 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0, 766 ROCKCHIP_SIP_CONFIG_DRAM_INIT); 767 if (res.a0) { 768 printf("rockchip_sip_config_dram_init error:%lx\n", 769 res.a0); 770 return -ENOMEM; 771 } 772 773 return 0; 774 } 775 776 static __maybe_unused int px30_devfreq_init(struct udevice *dev) 777 { 778 struct arm_smccc_res res; 779 u32 size; 780 781 res = sip_smc_dram(0, 0, 782 ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION); 783 printf("current ATF version 0x%lx!\n", res.a1); 784 if (res.a0 || res.a1 < 0x103) { 785 printf("trusted firmware need to update or is invalid!\n"); 786 return -ENXIO; 787 } 788 789 printf("read tf version 0x%lx!\n", res.a1); 790 791 /* 792 * first 4KB is used for interface parameters 793 * after 4KB * N is dts parameters 794 */ 795 size = sizeof(struct px30_ddr_dts_config_timing); 796 res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1, 797 SHARE_PAGE_TYPE_DDR); 798 if (res.a0 != 0) { 799 printf("no ATF memory for init\n"); 800 return -ENOMEM; 801 } 802 803 ddr_psci_param = (struct share_params *)res.a1; 804 of_get_px30_timings(dev, (uint32_t *)ddr_psci_param); 805 806 flush_cache((unsigned long)ddr_psci_param, 807 (DIV_ROUND_UP(size, 4096) + 1) * 0x1000); 808 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0, 809 ROCKCHIP_SIP_CONFIG_DRAM_INIT); 810 if (res.a0) { 811 printf("rockchip_sip_config_dram_init error:%lx\n", 812 res.a0); 813 return -ENOMEM; 814 } 815 816 return 0; 817 } 818 819 int rockchip_ddrclk_sip_set_rate_v2(unsigned long drate) 820 { 821 struct share_params *p; 822 struct arm_smccc_res res; 823 824 p = ddr_psci_param; 825 826 p->hz = drate; 827 p->lcdc_type = 0; 828 p->wait_flag1 = 0; 829 p->wait_flag0 = 0; 830 p->complt_hwirq = 105; 831 832 flush_cache((unsigned long)ddr_psci_param, sizeof(struct share_params)); 833 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0, 834 ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE); 835 836 return res.a0; 837 } 838 839 unsigned long rockchip_ddrclk_sip_recalc_rate_v2(void) 840 { 841 struct arm_smccc_res res; 842 843 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0, 844 ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE); 845 if (!res.a0) 846 return res.a1; 847 else 848 return 0; 849 } 850 851 unsigned long rockchip_ddrclk_sip_round_rate_v2(unsigned long rate) 852 { 853 struct share_params *p; 854 struct arm_smccc_res res; 855 856 p = ddr_psci_param; 857 858 p->hz = rate; 859 860 flush_cache((unsigned long)ddr_psci_param, sizeof(struct share_params)); 861 862 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0, 863 ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE); 864 if (!res.a0) 865 return res.a1; 866 else 867 return 0; 868 } 869 870 int set_ddr_freq(unsigned long freq) 871 { 872 if (freq < MHZ) 873 freq *= MHZ; 874 if (freq) { 875 freq = rockchip_ddrclk_sip_round_rate_v2(freq); 876 rockchip_ddrclk_sip_set_rate_v2(freq); 877 } 878 freq = rockchip_ddrclk_sip_recalc_rate_v2(); 879 printf("current ddr freq:%lu Hz\n", freq); 880 881 return freq; 882 } 883 884 int rockchip_dmcfreq_probe(struct udevice *dev) 885 { 886 int ret; 887 888 #if defined(CONFIG_ROCKCHIP_PX30) 889 ret = px30_devfreq_init(dev); 890 #elif defined(CONFIG_ROCKCHIP_RK3328) 891 ret = rk3328_devfreq_init(dev); 892 #else 893 ret = -1; 894 printf("Unsupported chip type\n"); 895 #endif 896 if (ret) 897 return ret; 898 899 printf("dram freq:%ld Hz\n", rockchip_ddrclk_sip_recalc_rate_v2()); 900 901 return 0; 902 } 903