1 /* 2 * Copyright (C) 2005 Freescale Semiconductor, Inc. 3 * 4 * Author: Shlomi Gridish 5 * 6 * Description: UCC GETH Driver -- PHY handling 7 * Driver for UEC on QE 8 * Based on 8260_io/fcc_enet.c 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #include "common.h" 18 #include "net.h" 19 #include "malloc.h" 20 #include "asm/errno.h" 21 #include "asm/immap_qe.h" 22 #include "asm/io.h" 23 #include "qe.h" 24 #include "uccf.h" 25 #include "uec.h" 26 #include "uec_phy.h" 27 #include "miiphy.h" 28 29 #define ugphy_printk(format, arg...) \ 30 printf(format "\n", ## arg) 31 32 #define ugphy_dbg(format, arg...) \ 33 ugphy_printk(format , ## arg) 34 #define ugphy_err(format, arg...) \ 35 ugphy_printk(format , ## arg) 36 #define ugphy_info(format, arg...) \ 37 ugphy_printk(format , ## arg) 38 #define ugphy_warn(format, arg...) \ 39 ugphy_printk(format , ## arg) 40 41 #ifdef UEC_VERBOSE_DEBUG 42 #define ugphy_vdbg ugphy_dbg 43 #else 44 #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0) 45 #endif /* UEC_VERBOSE_DEBUG */ 46 47 /*--------------------------------------------------------------------+ 48 * Fixed PHY (PHY-less) support for Ethernet Ports. 49 * 50 * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c 51 *--------------------------------------------------------------------*/ 52 53 /* 54 * Some boards do not have a PHY for each ethernet port. These ports are known 55 * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate 56 * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address) 57 * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned 58 * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network 59 * speed and duplex should be for the port. 60 * 61 * Example board header configuration file: 62 * #define CONFIG_FIXED_PHY 0xFFFFFFFF 63 * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address) 64 * 65 * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR 66 * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02 67 * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR 68 * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04 69 * 70 * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \ 71 * {name, speed, duplex}, 72 * 73 * #define CONFIG_SYS_FIXED_PHY_PORTS \ 74 * CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \ 75 * CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF) 76 */ 77 78 #ifndef CONFIG_FIXED_PHY 79 #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */ 80 #endif 81 82 #ifndef CONFIG_SYS_FIXED_PHY_PORTS 83 #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */ 84 #endif 85 86 struct fixed_phy_port { 87 char name[NAMESIZE]; /* ethernet port name */ 88 unsigned int speed; /* specified speed 10,100 or 1000 */ 89 unsigned int duplex; /* specified duplex FULL or HALF */ 90 }; 91 92 static const struct fixed_phy_port fixed_phy_port[] = { 93 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ 94 }; 95 96 /*--------------------------------------------------------------------+ 97 * BitBang MII support for ethernet ports 98 * 99 * Based from MPC8560ADS implementation 100 *--------------------------------------------------------------------*/ 101 /* 102 * Example board header file to define bitbang ethernet ports: 103 * 104 * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name, 105 * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0") 106 */ 107 #ifndef CONFIG_SYS_BITBANG_PHY_PORTS 108 #define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */ 109 #endif 110 111 #if defined(CONFIG_BITBANGMII) 112 static const char *bitbang_phy_port[] = { 113 CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */ 114 }; 115 #endif /* CONFIG_BITBANGMII */ 116 117 static void config_genmii_advert (struct uec_mii_info *mii_info); 118 static void genmii_setup_forced (struct uec_mii_info *mii_info); 119 static void genmii_restart_aneg (struct uec_mii_info *mii_info); 120 static int gbit_config_aneg (struct uec_mii_info *mii_info); 121 static int genmii_config_aneg (struct uec_mii_info *mii_info); 122 static int genmii_update_link (struct uec_mii_info *mii_info); 123 static int genmii_read_status (struct uec_mii_info *mii_info); 124 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum); 125 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val); 126 127 /* Write value to the PHY for this device to the register at regnum, */ 128 /* waiting until the write is done before it returns. All PHY */ 129 /* configuration has to be done through the TSEC1 MIIM regs */ 130 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) 131 { 132 uec_private_t *ugeth = (uec_private_t *) dev->priv; 133 uec_mii_t *ug_regs; 134 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; 135 u32 tmp_reg; 136 137 138 #if defined(CONFIG_BITBANGMII) 139 u32 i = 0; 140 141 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) { 142 if (strncmp(dev->name, bitbang_phy_port[i], 143 sizeof(dev->name)) == 0) { 144 (void)bb_miiphy_write(NULL, mii_id, regnum, value); 145 return; 146 } 147 } 148 #endif /* CONFIG_BITBANGMII */ 149 150 ug_regs = ugeth->uec_mii_regs; 151 152 /* Stop the MII management read cycle */ 153 out_be32 (&ug_regs->miimcom, 0); 154 /* Setting up the MII Mangement Address Register */ 155 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; 156 out_be32 (&ug_regs->miimadd, tmp_reg); 157 158 /* Setting up the MII Mangement Control Register with the value */ 159 out_be32 (&ug_regs->miimcon, (u32) value); 160 sync(); 161 162 /* Wait till MII management write is complete */ 163 while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY); 164 } 165 166 /* Reads from register regnum in the PHY for device dev, */ 167 /* returning the value. Clears miimcom first. All PHY */ 168 /* configuration has to be done through the TSEC1 MIIM regs */ 169 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum) 170 { 171 uec_private_t *ugeth = (uec_private_t *) dev->priv; 172 uec_mii_t *ug_regs; 173 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; 174 u32 tmp_reg; 175 u16 value; 176 177 178 #if defined(CONFIG_BITBANGMII) 179 u32 i = 0; 180 181 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) { 182 if (strncmp(dev->name, bitbang_phy_port[i], 183 sizeof(dev->name)) == 0) { 184 (void)bb_miiphy_read(NULL, mii_id, regnum, &value); 185 return (value); 186 } 187 } 188 #endif /* CONFIG_BITBANGMII */ 189 190 ug_regs = ugeth->uec_mii_regs; 191 192 /* Setting up the MII Mangement Address Register */ 193 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; 194 out_be32 (&ug_regs->miimadd, tmp_reg); 195 196 /* clear MII management command cycle */ 197 out_be32 (&ug_regs->miimcom, 0); 198 sync(); 199 200 /* Perform an MII management read cycle */ 201 out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE); 202 203 /* Wait till MII management write is complete */ 204 while ((in_be32 (&ug_regs->miimind)) & 205 (MIIMIND_NOT_VALID | MIIMIND_BUSY)); 206 207 /* Read MII management status */ 208 value = (u16) in_be32 (&ug_regs->miimstat); 209 if (value == 0xffff) 210 ugphy_vdbg 211 ("read wrong value : mii_id %d,mii_reg %d, base %08x", 212 mii_id, mii_reg, (u32) & (ug_regs->miimcfg)); 213 214 return (value); 215 } 216 217 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info) 218 { 219 if (mii_info->phyinfo->ack_interrupt) 220 mii_info->phyinfo->ack_interrupt (mii_info); 221 } 222 223 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, 224 u32 interrupts) 225 { 226 mii_info->interrupts = interrupts; 227 if (mii_info->phyinfo->config_intr) 228 mii_info->phyinfo->config_intr (mii_info); 229 } 230 231 /* Writes MII_ADVERTISE with the appropriate values, after 232 * sanitizing advertise to make sure only supported features 233 * are advertised 234 */ 235 static void config_genmii_advert (struct uec_mii_info *mii_info) 236 { 237 u32 advertise; 238 u16 adv; 239 240 /* Only allow advertising what this PHY supports */ 241 mii_info->advertising &= mii_info->phyinfo->features; 242 advertise = mii_info->advertising; 243 244 /* Setup standard advertisement */ 245 adv = phy_read (mii_info, PHY_ANAR); 246 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); 247 if (advertise & ADVERTISED_10baseT_Half) 248 adv |= ADVERTISE_10HALF; 249 if (advertise & ADVERTISED_10baseT_Full) 250 adv |= ADVERTISE_10FULL; 251 if (advertise & ADVERTISED_100baseT_Half) 252 adv |= ADVERTISE_100HALF; 253 if (advertise & ADVERTISED_100baseT_Full) 254 adv |= ADVERTISE_100FULL; 255 phy_write (mii_info, PHY_ANAR, adv); 256 } 257 258 static void genmii_setup_forced (struct uec_mii_info *mii_info) 259 { 260 u16 ctrl; 261 u32 features = mii_info->phyinfo->features; 262 263 ctrl = phy_read (mii_info, PHY_BMCR); 264 265 ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS | 266 PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON); 267 ctrl |= PHY_BMCR_RESET; 268 269 switch (mii_info->speed) { 270 case SPEED_1000: 271 if (features & (SUPPORTED_1000baseT_Half 272 | SUPPORTED_1000baseT_Full)) { 273 ctrl |= PHY_BMCR_1000_MBPS; 274 break; 275 } 276 mii_info->speed = SPEED_100; 277 case SPEED_100: 278 if (features & (SUPPORTED_100baseT_Half 279 | SUPPORTED_100baseT_Full)) { 280 ctrl |= PHY_BMCR_100_MBPS; 281 break; 282 } 283 mii_info->speed = SPEED_10; 284 case SPEED_10: 285 if (features & (SUPPORTED_10baseT_Half 286 | SUPPORTED_10baseT_Full)) 287 break; 288 default: /* Unsupported speed! */ 289 ugphy_err ("%s: Bad speed!", mii_info->dev->name); 290 break; 291 } 292 293 phy_write (mii_info, PHY_BMCR, ctrl); 294 } 295 296 /* Enable and Restart Autonegotiation */ 297 static void genmii_restart_aneg (struct uec_mii_info *mii_info) 298 { 299 u16 ctl; 300 301 ctl = phy_read (mii_info, PHY_BMCR); 302 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); 303 phy_write (mii_info, PHY_BMCR, ctl); 304 } 305 306 static int gbit_config_aneg (struct uec_mii_info *mii_info) 307 { 308 u16 adv; 309 u32 advertise; 310 311 if (mii_info->autoneg) { 312 /* Configure the ADVERTISE register */ 313 config_genmii_advert (mii_info); 314 advertise = mii_info->advertising; 315 316 adv = phy_read (mii_info, MII_1000BASETCONTROL); 317 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | 318 MII_1000BASETCONTROL_HALFDUPLEXCAP); 319 if (advertise & SUPPORTED_1000baseT_Half) 320 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP; 321 if (advertise & SUPPORTED_1000baseT_Full) 322 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP; 323 phy_write (mii_info, MII_1000BASETCONTROL, adv); 324 325 /* Start/Restart aneg */ 326 genmii_restart_aneg (mii_info); 327 } else 328 genmii_setup_forced (mii_info); 329 330 return 0; 331 } 332 333 static int marvell_config_aneg (struct uec_mii_info *mii_info) 334 { 335 /* The Marvell PHY has an errata which requires 336 * that certain registers get written in order 337 * to restart autonegotiation */ 338 phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET); 339 340 phy_write (mii_info, 0x1d, 0x1f); 341 phy_write (mii_info, 0x1e, 0x200c); 342 phy_write (mii_info, 0x1d, 0x5); 343 phy_write (mii_info, 0x1e, 0); 344 phy_write (mii_info, 0x1e, 0x100); 345 346 gbit_config_aneg (mii_info); 347 348 return 0; 349 } 350 351 static int genmii_config_aneg (struct uec_mii_info *mii_info) 352 { 353 if (mii_info->autoneg) { 354 config_genmii_advert (mii_info); 355 genmii_restart_aneg (mii_info); 356 } else 357 genmii_setup_forced (mii_info); 358 359 return 0; 360 } 361 362 static int genmii_update_link (struct uec_mii_info *mii_info) 363 { 364 u16 status; 365 366 /* Status is read once to clear old link state */ 367 phy_read (mii_info, PHY_BMSR); 368 369 /* 370 * Wait if the link is up, and autonegotiation is in progress 371 * (ie - we're capable and it's not done) 372 */ 373 status = phy_read(mii_info, PHY_BMSR); 374 if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE) 375 && !(status & PHY_BMSR_AUTN_COMP)) { 376 int i = 0; 377 378 while (!(status & PHY_BMSR_AUTN_COMP)) { 379 /* 380 * Timeout reached ? 381 */ 382 if (i > UGETH_AN_TIMEOUT) { 383 mii_info->link = 0; 384 return 0; 385 } 386 387 i++; 388 udelay(1000); /* 1 ms */ 389 status = phy_read(mii_info, PHY_BMSR); 390 } 391 mii_info->link = 1; 392 } else { 393 if (status & PHY_BMSR_LS) 394 mii_info->link = 1; 395 else 396 mii_info->link = 0; 397 } 398 399 return 0; 400 } 401 402 static int genmii_read_status (struct uec_mii_info *mii_info) 403 { 404 u16 status; 405 int err; 406 407 /* Update the link, but return if there 408 * was an error */ 409 err = genmii_update_link (mii_info); 410 if (err) 411 return err; 412 413 if (mii_info->autoneg) { 414 status = phy_read(mii_info, MII_1000BASETSTATUS); 415 416 if (status & (LPA_1000FULL | LPA_1000HALF)) { 417 mii_info->speed = SPEED_1000; 418 if (status & LPA_1000FULL) 419 mii_info->duplex = DUPLEX_FULL; 420 else 421 mii_info->duplex = DUPLEX_HALF; 422 } else { 423 status = phy_read(mii_info, PHY_ANLPAR); 424 425 if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) 426 mii_info->duplex = DUPLEX_FULL; 427 else 428 mii_info->duplex = DUPLEX_HALF; 429 if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) 430 mii_info->speed = SPEED_100; 431 else 432 mii_info->speed = SPEED_10; 433 } 434 mii_info->pause = 0; 435 } 436 /* On non-aneg, we assume what we put in BMCR is the speed, 437 * though magic-aneg shouldn't prevent this case from occurring 438 */ 439 440 return 0; 441 } 442 443 static int bcm_init(struct uec_mii_info *mii_info) 444 { 445 struct eth_device *edev = mii_info->dev; 446 uec_private_t *uec = edev->priv; 447 448 gbit_config_aneg(mii_info); 449 450 if ((uec->uec_info->enet_interface_type == RGMII_RXID) && 451 (uec->uec_info->speed == 1000)) { 452 u16 val; 453 int cnt = 50; 454 455 /* Wait for aneg to complete. */ 456 do 457 val = phy_read(mii_info, PHY_BMSR); 458 while (--cnt && !(val & PHY_BMSR_AUTN_COMP)); 459 460 /* Set RDX clk delay. */ 461 phy_write(mii_info, 0x18, 0x7 | (7 << 12)); 462 463 val = phy_read(mii_info, 0x18); 464 /* Set RDX-RXC skew. */ 465 val |= (1 << 8); 466 val |= (7 | (7 << 12)); 467 /* Write bits 14:0. */ 468 val |= (1 << 15); 469 phy_write(mii_info, 0x18, val); 470 } 471 472 return 0; 473 } 474 475 static int marvell_init(struct uec_mii_info *mii_info) 476 { 477 struct eth_device *edev = mii_info->dev; 478 uec_private_t *uec = edev->priv; 479 enum enet_interface_type iface = uec->uec_info->enet_interface_type; 480 int speed = uec->uec_info->speed; 481 482 if ((speed == 1000) && 483 (iface == RGMII_ID || 484 iface == RGMII_RXID || 485 iface == RGMII_TXID)) { 486 int temp; 487 488 temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR); 489 if (iface == RGMII_ID) { 490 temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY; 491 } else if (iface == RGMII_RXID) { 492 temp &= ~MII_M1111_TX_DELAY; 493 temp |= MII_M1111_RX_DELAY; 494 } else if (iface == RGMII_TXID) { 495 temp &= ~MII_M1111_RX_DELAY; 496 temp |= MII_M1111_TX_DELAY; 497 } 498 phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp); 499 500 temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR); 501 temp &= ~MII_M1111_HWCFG_MODE_MASK; 502 temp |= MII_M1111_HWCFG_MODE_RGMII; 503 phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp); 504 505 phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET); 506 } 507 508 return 0; 509 } 510 511 static int marvell_read_status (struct uec_mii_info *mii_info) 512 { 513 u16 status; 514 int err; 515 516 /* Update the link, but return if there 517 * was an error */ 518 err = genmii_update_link (mii_info); 519 if (err) 520 return err; 521 522 /* If the link is up, read the speed and duplex */ 523 /* If we aren't autonegotiating, assume speeds 524 * are as set */ 525 if (mii_info->autoneg && mii_info->link) { 526 int speed; 527 528 status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS); 529 530 /* Get the duplexity */ 531 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX) 532 mii_info->duplex = DUPLEX_FULL; 533 else 534 mii_info->duplex = DUPLEX_HALF; 535 536 /* Get the speed */ 537 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK; 538 switch (speed) { 539 case MII_M1011_PHY_SPEC_STATUS_1000: 540 mii_info->speed = SPEED_1000; 541 break; 542 case MII_M1011_PHY_SPEC_STATUS_100: 543 mii_info->speed = SPEED_100; 544 break; 545 default: 546 mii_info->speed = SPEED_10; 547 break; 548 } 549 mii_info->pause = 0; 550 } 551 552 return 0; 553 } 554 555 static int marvell_ack_interrupt (struct uec_mii_info *mii_info) 556 { 557 /* Clear the interrupts by reading the reg */ 558 phy_read (mii_info, MII_M1011_IEVENT); 559 560 return 0; 561 } 562 563 static int marvell_config_intr (struct uec_mii_info *mii_info) 564 { 565 if (mii_info->interrupts == MII_INTERRUPT_ENABLED) 566 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); 567 else 568 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); 569 570 return 0; 571 } 572 573 static int dm9161_init (struct uec_mii_info *mii_info) 574 { 575 /* Reset the PHY */ 576 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) | 577 PHY_BMCR_RESET); 578 /* PHY and MAC connect */ 579 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) & 580 ~PHY_BMCR_ISO); 581 582 phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT); 583 584 config_genmii_advert (mii_info); 585 /* Start/restart aneg */ 586 genmii_config_aneg (mii_info); 587 588 return 0; 589 } 590 591 static int dm9161_config_aneg (struct uec_mii_info *mii_info) 592 { 593 return 0; 594 } 595 596 static int dm9161_read_status (struct uec_mii_info *mii_info) 597 { 598 u16 status; 599 int err; 600 601 /* Update the link, but return if there was an error */ 602 err = genmii_update_link (mii_info); 603 if (err) 604 return err; 605 /* If the link is up, read the speed and duplex 606 If we aren't autonegotiating assume speeds are as set */ 607 if (mii_info->autoneg && mii_info->link) { 608 status = phy_read (mii_info, MII_DM9161_SCSR); 609 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H)) 610 mii_info->speed = SPEED_100; 611 else 612 mii_info->speed = SPEED_10; 613 614 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F)) 615 mii_info->duplex = DUPLEX_FULL; 616 else 617 mii_info->duplex = DUPLEX_HALF; 618 } 619 620 return 0; 621 } 622 623 static int dm9161_ack_interrupt (struct uec_mii_info *mii_info) 624 { 625 /* Clear the interrupt by reading the reg */ 626 phy_read (mii_info, MII_DM9161_INTR); 627 628 return 0; 629 } 630 631 static int dm9161_config_intr (struct uec_mii_info *mii_info) 632 { 633 if (mii_info->interrupts == MII_INTERRUPT_ENABLED) 634 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); 635 else 636 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); 637 638 return 0; 639 } 640 641 static void dm9161_close (struct uec_mii_info *mii_info) 642 { 643 } 644 645 static int fixed_phy_aneg (struct uec_mii_info *mii_info) 646 { 647 mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */ 648 return 0; 649 } 650 651 static int fixed_phy_read_status (struct uec_mii_info *mii_info) 652 { 653 int i = 0; 654 655 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) { 656 if (strncmp(mii_info->dev->name, fixed_phy_port[i].name, 657 strlen(mii_info->dev->name)) == 0) { 658 mii_info->speed = fixed_phy_port[i].speed; 659 mii_info->duplex = fixed_phy_port[i].duplex; 660 mii_info->link = 1; /* Link is always UP */ 661 mii_info->pause = 0; 662 break; 663 } 664 } 665 return 0; 666 } 667 668 static int smsc_config_aneg (struct uec_mii_info *mii_info) 669 { 670 return 0; 671 } 672 673 static int smsc_read_status (struct uec_mii_info *mii_info) 674 { 675 u16 status; 676 int err; 677 678 /* Update the link, but return if there 679 * was an error */ 680 err = genmii_update_link (mii_info); 681 if (err) 682 return err; 683 684 /* If the link is up, read the speed and duplex */ 685 /* If we aren't autonegotiating, assume speeds 686 * are as set */ 687 if (mii_info->autoneg && mii_info->link) { 688 int val; 689 690 status = phy_read (mii_info, 0x1f); 691 val = (status & 0x1c) >> 2; 692 693 switch (val) { 694 case 1: 695 mii_info->duplex = DUPLEX_HALF; 696 mii_info->speed = SPEED_10; 697 break; 698 case 5: 699 mii_info->duplex = DUPLEX_FULL; 700 mii_info->speed = SPEED_10; 701 break; 702 case 2: 703 mii_info->duplex = DUPLEX_HALF; 704 mii_info->speed = SPEED_100; 705 break; 706 case 6: 707 mii_info->duplex = DUPLEX_FULL; 708 mii_info->speed = SPEED_100; 709 break; 710 } 711 mii_info->pause = 0; 712 } 713 714 return 0; 715 } 716 717 static struct phy_info phy_info_dm9161 = { 718 .phy_id = 0x0181b880, 719 .phy_id_mask = 0x0ffffff0, 720 .name = "Davicom DM9161E", 721 .init = dm9161_init, 722 .config_aneg = dm9161_config_aneg, 723 .read_status = dm9161_read_status, 724 .close = dm9161_close, 725 }; 726 727 static struct phy_info phy_info_dm9161a = { 728 .phy_id = 0x0181b8a0, 729 .phy_id_mask = 0x0ffffff0, 730 .name = "Davicom DM9161A", 731 .features = MII_BASIC_FEATURES, 732 .init = dm9161_init, 733 .config_aneg = dm9161_config_aneg, 734 .read_status = dm9161_read_status, 735 .ack_interrupt = dm9161_ack_interrupt, 736 .config_intr = dm9161_config_intr, 737 .close = dm9161_close, 738 }; 739 740 static struct phy_info phy_info_marvell = { 741 .phy_id = 0x01410c00, 742 .phy_id_mask = 0xffffff00, 743 .name = "Marvell 88E11x1", 744 .features = MII_GBIT_FEATURES, 745 .init = &marvell_init, 746 .config_aneg = &marvell_config_aneg, 747 .read_status = &marvell_read_status, 748 .ack_interrupt = &marvell_ack_interrupt, 749 .config_intr = &marvell_config_intr, 750 }; 751 752 static struct phy_info phy_info_bcm5481 = { 753 .phy_id = 0x0143bca0, 754 .phy_id_mask = 0xffffff0, 755 .name = "Broadcom 5481", 756 .features = MII_GBIT_FEATURES, 757 .read_status = genmii_read_status, 758 .init = bcm_init, 759 }; 760 761 static struct phy_info phy_info_fixedphy = { 762 .phy_id = CONFIG_FIXED_PHY, 763 .phy_id_mask = CONFIG_FIXED_PHY, 764 .name = "Fixed PHY", 765 .config_aneg = fixed_phy_aneg, 766 .read_status = fixed_phy_read_status, 767 }; 768 769 static struct phy_info phy_info_smsclan8700 = { 770 .phy_id = 0x0007c0c0, 771 .phy_id_mask = 0xfffffff0, 772 .name = "SMSC LAN8700", 773 .features = MII_BASIC_FEATURES, 774 .config_aneg = smsc_config_aneg, 775 .read_status = smsc_read_status, 776 }; 777 778 static struct phy_info phy_info_genmii = { 779 .phy_id = 0x00000000, 780 .phy_id_mask = 0x00000000, 781 .name = "Generic MII", 782 .features = MII_BASIC_FEATURES, 783 .config_aneg = genmii_config_aneg, 784 .read_status = genmii_read_status, 785 }; 786 787 static struct phy_info *phy_info[] = { 788 &phy_info_dm9161, 789 &phy_info_dm9161a, 790 &phy_info_marvell, 791 &phy_info_bcm5481, 792 &phy_info_smsclan8700, 793 &phy_info_fixedphy, 794 &phy_info_genmii, 795 NULL 796 }; 797 798 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum) 799 { 800 return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum); 801 } 802 803 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val) 804 { 805 mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val); 806 } 807 808 /* Use the PHY ID registers to determine what type of PHY is attached 809 * to device dev. return a struct phy_info structure describing that PHY 810 */ 811 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info) 812 { 813 u16 phy_reg; 814 u32 phy_ID; 815 int i; 816 struct phy_info *theInfo = NULL; 817 818 /* Grab the bits from PHYIR1, and put them in the upper half */ 819 phy_reg = phy_read (mii_info, PHY_PHYIDR1); 820 phy_ID = (phy_reg & 0xffff) << 16; 821 822 /* Grab the bits from PHYIR2, and put them in the lower half */ 823 phy_reg = phy_read (mii_info, PHY_PHYIDR2); 824 phy_ID |= (phy_reg & 0xffff); 825 826 /* loop through all the known PHY types, and find one that */ 827 /* matches the ID we read from the PHY. */ 828 for (i = 0; phy_info[i]; i++) 829 if (phy_info[i]->phy_id == 830 (phy_ID & phy_info[i]->phy_id_mask)) { 831 theInfo = phy_info[i]; 832 break; 833 } 834 835 /* This shouldn't happen, as we have generic PHY support */ 836 if (theInfo == NULL) { 837 ugphy_info ("UEC: PHY id %x is not supported!", phy_ID); 838 return NULL; 839 } else { 840 ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID); 841 } 842 843 return theInfo; 844 } 845 846 void marvell_phy_interface_mode (struct eth_device *dev, 847 enet_interface_type_e type, 848 int speed 849 ) 850 { 851 uec_private_t *uec = (uec_private_t *) dev->priv; 852 struct uec_mii_info *mii_info; 853 u16 status; 854 855 if (!uec->mii_info) { 856 printf ("%s: the PHY not initialized\n", __FUNCTION__); 857 return; 858 } 859 mii_info = uec->mii_info; 860 861 if (type == RGMII) { 862 if (speed == 100) { 863 phy_write (mii_info, 0x00, 0x9140); 864 phy_write (mii_info, 0x1d, 0x001f); 865 phy_write (mii_info, 0x1e, 0x200c); 866 phy_write (mii_info, 0x1d, 0x0005); 867 phy_write (mii_info, 0x1e, 0x0000); 868 phy_write (mii_info, 0x1e, 0x0100); 869 phy_write (mii_info, 0x09, 0x0e00); 870 phy_write (mii_info, 0x04, 0x01e1); 871 phy_write (mii_info, 0x00, 0x9140); 872 phy_write (mii_info, 0x00, 0x1000); 873 udelay (100000); 874 phy_write (mii_info, 0x00, 0x2900); 875 phy_write (mii_info, 0x14, 0x0cd2); 876 phy_write (mii_info, 0x00, 0xa100); 877 phy_write (mii_info, 0x09, 0x0000); 878 phy_write (mii_info, 0x1b, 0x800b); 879 phy_write (mii_info, 0x04, 0x05e1); 880 phy_write (mii_info, 0x00, 0xa100); 881 phy_write (mii_info, 0x00, 0x2100); 882 udelay (1000000); 883 } else if (speed == 10) { 884 phy_write (mii_info, 0x14, 0x8e40); 885 phy_write (mii_info, 0x1b, 0x800b); 886 phy_write (mii_info, 0x14, 0x0c82); 887 phy_write (mii_info, 0x00, 0x8100); 888 udelay (1000000); 889 } 890 } 891 892 /* handle 88e1111 rev.B2 erratum 5.6 */ 893 if (mii_info->autoneg) { 894 status = phy_read (mii_info, PHY_BMCR); 895 phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON); 896 } 897 /* now the B2 will correctly report autoneg completion status */ 898 } 899 900 void change_phy_interface_mode (struct eth_device *dev, 901 enet_interface_type_e type, int speed) 902 { 903 #ifdef CONFIG_PHY_MODE_NEED_CHANGE 904 marvell_phy_interface_mode (dev, type, speed); 905 #endif 906 } 907