1 /* 2 * Copyright (C) 2005 Freescale Semiconductor, Inc. 3 * 4 * Author: Shlomi Gridish 5 * 6 * Description: UCC GETH Driver -- PHY handling 7 * Driver for UEC on QE 8 * Based on 8260_io/fcc_enet.c 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #include "common.h" 18 #include "net.h" 19 #include "malloc.h" 20 #include "asm/errno.h" 21 #include "asm/immap_qe.h" 22 #include "asm/io.h" 23 #include "qe.h" 24 #include "uccf.h" 25 #include "uec.h" 26 #include "uec_phy.h" 27 #include "miiphy.h" 28 29 #if defined(CONFIG_QE) 30 31 #define UEC_VERBOSE_DEBUG 32 #define ugphy_printk(format, arg...) \ 33 printf(format "\n", ## arg) 34 35 #define ugphy_dbg(format, arg...) \ 36 ugphy_printk(format , ## arg) 37 #define ugphy_err(format, arg...) \ 38 ugphy_printk(format , ## arg) 39 #define ugphy_info(format, arg...) \ 40 ugphy_printk(format , ## arg) 41 #define ugphy_warn(format, arg...) \ 42 ugphy_printk(format , ## arg) 43 44 #ifdef UEC_VERBOSE_DEBUG 45 #define ugphy_vdbg ugphy_dbg 46 #else 47 #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0) 48 #endif /* UEC_VERBOSE_DEBUG */ 49 50 static void config_genmii_advert(struct uec_mii_info *mii_info); 51 static void genmii_setup_forced(struct uec_mii_info *mii_info); 52 static void genmii_restart_aneg(struct uec_mii_info *mii_info); 53 static int gbit_config_aneg(struct uec_mii_info *mii_info); 54 static int genmii_config_aneg(struct uec_mii_info *mii_info); 55 static int genmii_update_link(struct uec_mii_info *mii_info); 56 static int genmii_read_status(struct uec_mii_info *mii_info); 57 u16 phy_read(struct uec_mii_info *mii_info, u16 regnum); 58 void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val); 59 60 /* Write value to the PHY for this device to the register at regnum, */ 61 /* waiting until the write is done before it returns. All PHY */ 62 /* configuration has to be done through the TSEC1 MIIM regs */ 63 void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value) 64 { 65 uec_private_t *ugeth = (uec_private_t *)dev->priv; 66 uec_t *ug_regs; 67 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum; 68 u32 tmp_reg; 69 70 ug_regs = ugeth->uec_regs; 71 72 /* Stop the MII management read cycle */ 73 out_be32(&ug_regs->miimcom, 0); 74 /* Setting up the MII Mangement Address Register */ 75 tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; 76 out_be32(&ug_regs->miimadd, tmp_reg); 77 78 /* Setting up the MII Mangement Control Register with the value */ 79 out_be32(&ug_regs->miimcon, (u32)value); 80 81 /* Wait till MII management write is complete */ 82 while((in_be32(&ug_regs->miimind)) & MIIMIND_BUSY); 83 84 udelay(100000); 85 } 86 87 /* Reads from register regnum in the PHY for device dev, */ 88 /* returning the value. Clears miimcom first. All PHY */ 89 /* configuration has to be done through the TSEC1 MIIM regs */ 90 int read_phy_reg(struct eth_device *dev, int mii_id, int regnum) 91 { 92 uec_private_t *ugeth = (uec_private_t *)dev->priv; 93 uec_t *ug_regs; 94 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum; 95 u32 tmp_reg; 96 u16 value; 97 98 ug_regs = ugeth->uec_regs; 99 100 /* Setting up the MII Mangement Address Register */ 101 tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg ; 102 out_be32(&ug_regs->miimadd, tmp_reg); 103 104 /* Perform an MII management read cycle */ 105 out_be32(&ug_regs->miimcom, 0); 106 out_be32(&ug_regs->miimcom, MIIMCOM_READ_CYCLE); 107 108 /* Wait till MII management write is complete */ 109 while((in_be32(&ug_regs->miimind)) & (MIIMIND_NOT_VALID | MIIMIND_BUSY)); 110 111 udelay(100000); 112 113 /* Read MII management status */ 114 value = (u16)in_be32(&ug_regs->miimstat); 115 if(value == 0xffff) 116 ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x", 117 mii_id, mii_reg, (u32) &(ug_regs->miimcfg)); 118 119 return (value); 120 } 121 122 void mii_clear_phy_interrupt(struct uec_mii_info *mii_info) 123 { 124 if(mii_info->phyinfo->ack_interrupt) 125 mii_info->phyinfo->ack_interrupt(mii_info); 126 } 127 128 void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts) 129 { 130 mii_info->interrupts = interrupts; 131 if(mii_info->phyinfo->config_intr) 132 mii_info->phyinfo->config_intr(mii_info); 133 } 134 135 /* Writes MII_ADVERTISE with the appropriate values, after 136 * sanitizing advertise to make sure only supported features 137 * are advertised 138 */ 139 static void config_genmii_advert(struct uec_mii_info *mii_info) 140 { 141 u32 advertise; 142 u16 adv; 143 144 /* Only allow advertising what this PHY supports */ 145 mii_info->advertising &= mii_info->phyinfo->features; 146 advertise = mii_info->advertising; 147 148 /* Setup standard advertisement */ 149 adv = phy_read(mii_info, PHY_ANAR); 150 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); 151 if (advertise & ADVERTISED_10baseT_Half) 152 adv |= ADVERTISE_10HALF; 153 if (advertise & ADVERTISED_10baseT_Full) 154 adv |= ADVERTISE_10FULL; 155 if (advertise & ADVERTISED_100baseT_Half) 156 adv |= ADVERTISE_100HALF; 157 if (advertise & ADVERTISED_100baseT_Full) 158 adv |= ADVERTISE_100FULL; 159 phy_write(mii_info, PHY_ANAR, adv); 160 } 161 162 static void genmii_setup_forced(struct uec_mii_info *mii_info) 163 { 164 u16 ctrl; 165 u32 features = mii_info->phyinfo->features; 166 167 ctrl = phy_read(mii_info, PHY_BMCR); 168 169 ctrl &= ~(PHY_BMCR_DPLX|PHY_BMCR_100_MBPS| 170 PHY_BMCR_1000_MBPS|PHY_BMCR_AUTON); 171 ctrl |= PHY_BMCR_RESET; 172 173 switch(mii_info->speed) { 174 case SPEED_1000: 175 if(features & (SUPPORTED_1000baseT_Half 176 | SUPPORTED_1000baseT_Full)) { 177 ctrl |= PHY_BMCR_1000_MBPS; 178 break; 179 } 180 mii_info->speed = SPEED_100; 181 case SPEED_100: 182 if (features & (SUPPORTED_100baseT_Half 183 | SUPPORTED_100baseT_Full)) { 184 ctrl |= PHY_BMCR_100_MBPS; 185 break; 186 } 187 mii_info->speed = SPEED_10; 188 case SPEED_10: 189 if (features & (SUPPORTED_10baseT_Half 190 | SUPPORTED_10baseT_Full)) 191 break; 192 default: /* Unsupported speed! */ 193 ugphy_err("%s: Bad speed!", mii_info->dev->name); 194 break; 195 } 196 197 phy_write(mii_info, PHY_BMCR, ctrl); 198 } 199 200 /* Enable and Restart Autonegotiation */ 201 static void genmii_restart_aneg(struct uec_mii_info *mii_info) 202 { 203 u16 ctl; 204 205 ctl = phy_read(mii_info, PHY_BMCR); 206 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); 207 phy_write(mii_info, PHY_BMCR, ctl); 208 } 209 210 static int gbit_config_aneg(struct uec_mii_info *mii_info) 211 { 212 u16 adv; 213 u32 advertise; 214 215 if(mii_info->autoneg) { 216 /* Configure the ADVERTISE register */ 217 config_genmii_advert(mii_info); 218 advertise = mii_info->advertising; 219 220 adv = phy_read(mii_info, MII_1000BASETCONTROL); 221 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | 222 MII_1000BASETCONTROL_HALFDUPLEXCAP); 223 if (advertise & SUPPORTED_1000baseT_Half) 224 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP; 225 if (advertise & SUPPORTED_1000baseT_Full) 226 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP; 227 phy_write(mii_info, MII_1000BASETCONTROL, adv); 228 229 /* Start/Restart aneg */ 230 genmii_restart_aneg(mii_info); 231 } else 232 genmii_setup_forced(mii_info); 233 234 return 0; 235 } 236 237 static int marvell_config_aneg(struct uec_mii_info *mii_info) 238 { 239 /* The Marvell PHY has an errata which requires 240 * that certain registers get written in order 241 * to restart autonegotiation */ 242 phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET); 243 244 phy_write(mii_info, 0x1d, 0x1f); 245 phy_write(mii_info, 0x1e, 0x200c); 246 phy_write(mii_info, 0x1d, 0x5); 247 phy_write(mii_info, 0x1e, 0); 248 phy_write(mii_info, 0x1e, 0x100); 249 250 gbit_config_aneg(mii_info); 251 252 return 0; 253 } 254 255 static int genmii_config_aneg(struct uec_mii_info *mii_info) 256 { 257 if (mii_info->autoneg) { 258 config_genmii_advert(mii_info); 259 genmii_restart_aneg(mii_info); 260 } else 261 genmii_setup_forced(mii_info); 262 263 return 0; 264 } 265 266 static int genmii_update_link(struct uec_mii_info *mii_info) 267 { 268 u16 status; 269 270 /* Do a fake read */ 271 phy_read(mii_info, PHY_BMSR); 272 273 /* Read link and autonegotiation status */ 274 status = phy_read(mii_info, PHY_BMSR); 275 if ((status & PHY_BMSR_LS) == 0) 276 mii_info->link = 0; 277 else 278 mii_info->link = 1; 279 280 /* If we are autonegotiating, and not done, 281 * return an error */ 282 if (mii_info->autoneg && !(status & PHY_BMSR_AUTN_COMP)) 283 return -EAGAIN; 284 285 return 0; 286 } 287 288 static int genmii_read_status(struct uec_mii_info *mii_info) 289 { 290 u16 status; 291 int err; 292 293 /* Update the link, but return if there 294 * was an error */ 295 err = genmii_update_link(mii_info); 296 if (err) 297 return err; 298 299 if (mii_info->autoneg) { 300 status = phy_read(mii_info, PHY_ANLPAR); 301 302 if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) 303 mii_info->duplex = DUPLEX_FULL; 304 else 305 mii_info->duplex = DUPLEX_HALF; 306 if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) 307 mii_info->speed = SPEED_100; 308 else 309 mii_info->speed = SPEED_10; 310 mii_info->pause = 0; 311 } 312 /* On non-aneg, we assume what we put in BMCR is the speed, 313 * though magic-aneg shouldn't prevent this case from occurring 314 */ 315 316 return 0; 317 } 318 319 static int marvell_read_status(struct uec_mii_info *mii_info) 320 { 321 u16 status; 322 int err; 323 324 /* Update the link, but return if there 325 * was an error */ 326 err = genmii_update_link(mii_info); 327 if (err) 328 return err; 329 330 /* If the link is up, read the speed and duplex */ 331 /* If we aren't autonegotiating, assume speeds 332 * are as set */ 333 if (mii_info->autoneg && mii_info->link) { 334 int speed; 335 status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS); 336 337 /* Get the duplexity */ 338 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX) 339 mii_info->duplex = DUPLEX_FULL; 340 else 341 mii_info->duplex = DUPLEX_HALF; 342 343 /* Get the speed */ 344 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK; 345 switch(speed) { 346 case MII_M1011_PHY_SPEC_STATUS_1000: 347 mii_info->speed = SPEED_1000; 348 break; 349 case MII_M1011_PHY_SPEC_STATUS_100: 350 mii_info->speed = SPEED_100; 351 break; 352 default: 353 mii_info->speed = SPEED_10; 354 break; 355 } 356 mii_info->pause = 0; 357 } 358 359 return 0; 360 } 361 362 static int marvell_ack_interrupt(struct uec_mii_info *mii_info) 363 { 364 /* Clear the interrupts by reading the reg */ 365 phy_read(mii_info, MII_M1011_IEVENT); 366 367 return 0; 368 } 369 370 static int marvell_config_intr(struct uec_mii_info *mii_info) 371 { 372 if(mii_info->interrupts == MII_INTERRUPT_ENABLED) 373 phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); 374 else 375 phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); 376 377 return 0; 378 } 379 380 static int dm9161_init(struct uec_mii_info *mii_info) 381 { 382 /* Reset the PHY */ 383 phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) | 384 PHY_BMCR_RESET); 385 /* PHY and MAC connect*/ 386 phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) & 387 ~PHY_BMCR_ISO); 388 #ifdef CONFIG_RMII_MODE 389 phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT); 390 #else 391 phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT); 392 #endif 393 config_genmii_advert(mii_info); 394 /* Start/restart aneg */ 395 genmii_config_aneg(mii_info); 396 /* Delay to wait the aneg compeleted */ 397 udelay(3000000); 398 399 return 0; 400 } 401 402 static int dm9161_config_aneg(struct uec_mii_info *mii_info) 403 { 404 return 0; 405 } 406 407 static int dm9161_read_status(struct uec_mii_info *mii_info) 408 { 409 u16 status; 410 int err; 411 412 /* Update the link, but return if there was an error*/ 413 err = genmii_update_link(mii_info); 414 if (err) 415 return err; 416 /* If the link is up, read the speed and duplex 417 If we aren't autonegotiating assume speeds are as set */ 418 if (mii_info->autoneg && mii_info->link) { 419 status = phy_read(mii_info, MII_DM9161_SCSR); 420 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H)) 421 mii_info->speed = SPEED_100; 422 else 423 mii_info->speed = SPEED_10; 424 425 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F)) 426 mii_info->duplex = DUPLEX_FULL; 427 else 428 mii_info->duplex = DUPLEX_HALF; 429 } 430 431 return 0; 432 } 433 434 static int dm9161_ack_interrupt(struct uec_mii_info *mii_info) 435 { 436 /* Clear the interrupt by reading the reg */ 437 phy_read(mii_info, MII_DM9161_INTR); 438 439 return 0; 440 } 441 442 static int dm9161_config_intr(struct uec_mii_info *mii_info) 443 { 444 if (mii_info->interrupts == MII_INTERRUPT_ENABLED) 445 phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); 446 else 447 phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); 448 449 return 0; 450 } 451 452 static void dm9161_close(struct uec_mii_info *mii_info) 453 { 454 } 455 456 static struct phy_info phy_info_dm9161 = { 457 .phy_id = 0x0181b880, 458 .phy_id_mask = 0x0ffffff0, 459 .name = "Davicom DM9161E", 460 .init = dm9161_init, 461 .config_aneg = dm9161_config_aneg, 462 .read_status = dm9161_read_status, 463 .close = dm9161_close, 464 }; 465 466 static struct phy_info phy_info_dm9161a = { 467 .phy_id = 0x0181b8a0, 468 .phy_id_mask = 0x0ffffff0, 469 .name = "Davicom DM9161A", 470 .features = MII_BASIC_FEATURES, 471 .init = dm9161_init, 472 .config_aneg = dm9161_config_aneg, 473 .read_status = dm9161_read_status, 474 .ack_interrupt = dm9161_ack_interrupt, 475 .config_intr = dm9161_config_intr, 476 .close = dm9161_close, 477 }; 478 479 static struct phy_info phy_info_marvell = { 480 .phy_id = 0x01410c00, 481 .phy_id_mask = 0xffffff00, 482 .name = "Marvell 88E11x1", 483 .features = MII_GBIT_FEATURES, 484 .config_aneg = &marvell_config_aneg, 485 .read_status = &marvell_read_status, 486 .ack_interrupt = &marvell_ack_interrupt, 487 .config_intr = &marvell_config_intr, 488 }; 489 490 static struct phy_info phy_info_genmii= { 491 .phy_id = 0x00000000, 492 .phy_id_mask = 0x00000000, 493 .name = "Generic MII", 494 .features = MII_BASIC_FEATURES, 495 .config_aneg = genmii_config_aneg, 496 .read_status = genmii_read_status, 497 }; 498 499 static struct phy_info *phy_info[] = { 500 &phy_info_dm9161, 501 &phy_info_dm9161a, 502 &phy_info_marvell, 503 &phy_info_genmii, 504 NULL 505 }; 506 507 u16 phy_read(struct uec_mii_info *mii_info, u16 regnum) 508 { 509 return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum); 510 } 511 512 void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val) 513 { 514 mii_info->mdio_write(mii_info->dev, 515 mii_info->mii_id, 516 regnum, val); 517 } 518 519 /* Use the PHY ID registers to determine what type of PHY is attached 520 * to device dev. return a struct phy_info structure describing that PHY 521 */ 522 struct phy_info * get_phy_info(struct uec_mii_info *mii_info) 523 { 524 u16 phy_reg; 525 u32 phy_ID; 526 int i; 527 struct phy_info *theInfo = NULL; 528 529 /* Grab the bits from PHYIR1, and put them in the upper half */ 530 phy_reg = phy_read(mii_info, PHY_PHYIDR1); 531 phy_ID = (phy_reg & 0xffff) << 16; 532 533 /* Grab the bits from PHYIR2, and put them in the lower half */ 534 phy_reg = phy_read(mii_info, PHY_PHYIDR2); 535 phy_ID |= (phy_reg & 0xffff); 536 537 /* loop through all the known PHY types, and find one that */ 538 /* matches the ID we read from the PHY. */ 539 for (i = 0; phy_info[i]; i++) 540 if (phy_info[i]->phy_id == 541 (phy_ID & phy_info[i]->phy_id_mask)) { 542 theInfo = phy_info[i]; 543 break; 544 } 545 546 /* This shouldn't happen, as we have generic PHY support */ 547 if (theInfo == NULL) { 548 ugphy_info("UEC: PHY id %x is not supported!", phy_ID); 549 return NULL; 550 } else { 551 ugphy_info("UEC: PHY is %s (%x)", theInfo->name, phy_ID); 552 } 553 554 return theInfo; 555 } 556 557 void marvell_phy_interface_mode(struct eth_device *dev, enet_interface_e mode) 558 { 559 uec_private_t *uec = (uec_private_t *)dev->priv; 560 struct uec_mii_info *mii_info; 561 562 if (!uec->mii_info) { 563 printf("%s: the PHY not intialized\n", __FUNCTION__); 564 return; 565 } 566 mii_info = uec->mii_info; 567 568 if (mode == ENET_100_RGMII) { 569 phy_write(mii_info, 0x00, 0x9140); 570 phy_write(mii_info, 0x1d, 0x001f); 571 phy_write(mii_info, 0x1e, 0x200c); 572 phy_write(mii_info, 0x1d, 0x0005); 573 phy_write(mii_info, 0x1e, 0x0000); 574 phy_write(mii_info, 0x1e, 0x0100); 575 phy_write(mii_info, 0x09, 0x0e00); 576 phy_write(mii_info, 0x04, 0x01e1); 577 phy_write(mii_info, 0x00, 0x9140); 578 phy_write(mii_info, 0x00, 0x1000); 579 udelay(100000); 580 phy_write(mii_info, 0x00, 0x2900); 581 phy_write(mii_info, 0x14, 0x0cd2); 582 phy_write(mii_info, 0x00, 0xa100); 583 phy_write(mii_info, 0x09, 0x0000); 584 phy_write(mii_info, 0x1b, 0x800b); 585 phy_write(mii_info, 0x04, 0x05e1); 586 phy_write(mii_info, 0x00, 0xa100); 587 phy_write(mii_info, 0x00, 0x2100); 588 udelay(1000000); 589 } else if (mode == ENET_10_RGMII) { 590 phy_write(mii_info, 0x14, 0x8e40); 591 phy_write(mii_info, 0x1b, 0x800b); 592 phy_write(mii_info, 0x14, 0x0c82); 593 phy_write(mii_info, 0x00, 0x8100); 594 udelay(1000000); 595 } 596 } 597 598 void change_phy_interface_mode(struct eth_device *dev, enet_interface_e mode) 599 { 600 #ifdef CONFIG_PHY_MODE_NEED_CHANGE 601 marvell_phy_interface_mode(dev, mode); 602 #endif 603 } 604 #endif /* CONFIG_QE */ 605