1 /* 2 * Copyright (C) 2006-2011 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #include "common.h" 23 #include "net.h" 24 #include "malloc.h" 25 #include "asm/errno.h" 26 #include "asm/io.h" 27 #include "asm/immap_qe.h" 28 #include "qe.h" 29 #include "uccf.h" 30 #include "uec.h" 31 #include "uec_phy.h" 32 #include "miiphy.h" 33 34 /* Default UTBIPAR SMI address */ 35 #ifndef CONFIG_UTBIPAR_INIT_TBIPA 36 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F 37 #endif 38 39 static uec_info_t uec_info[] = { 40 #ifdef CONFIG_UEC_ETH1 41 STD_UEC_INFO(1), /* UEC1 */ 42 #endif 43 #ifdef CONFIG_UEC_ETH2 44 STD_UEC_INFO(2), /* UEC2 */ 45 #endif 46 #ifdef CONFIG_UEC_ETH3 47 STD_UEC_INFO(3), /* UEC3 */ 48 #endif 49 #ifdef CONFIG_UEC_ETH4 50 STD_UEC_INFO(4), /* UEC4 */ 51 #endif 52 #ifdef CONFIG_UEC_ETH5 53 STD_UEC_INFO(5), /* UEC5 */ 54 #endif 55 #ifdef CONFIG_UEC_ETH6 56 STD_UEC_INFO(6), /* UEC6 */ 57 #endif 58 #ifdef CONFIG_UEC_ETH7 59 STD_UEC_INFO(7), /* UEC7 */ 60 #endif 61 #ifdef CONFIG_UEC_ETH8 62 STD_UEC_INFO(8), /* UEC8 */ 63 #endif 64 }; 65 66 #define MAXCONTROLLERS (8) 67 68 static struct eth_device *devlist[MAXCONTROLLERS]; 69 70 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode) 71 { 72 uec_t *uec_regs; 73 u32 maccfg1; 74 75 if (!uec) { 76 printf("%s: uec not initial\n", __FUNCTION__); 77 return -EINVAL; 78 } 79 uec_regs = uec->uec_regs; 80 81 maccfg1 = in_be32(&uec_regs->maccfg1); 82 83 if (mode & COMM_DIR_TX) { 84 maccfg1 |= MACCFG1_ENABLE_TX; 85 out_be32(&uec_regs->maccfg1, maccfg1); 86 uec->mac_tx_enabled = 1; 87 } 88 89 if (mode & COMM_DIR_RX) { 90 maccfg1 |= MACCFG1_ENABLE_RX; 91 out_be32(&uec_regs->maccfg1, maccfg1); 92 uec->mac_rx_enabled = 1; 93 } 94 95 return 0; 96 } 97 98 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode) 99 { 100 uec_t *uec_regs; 101 u32 maccfg1; 102 103 if (!uec) { 104 printf("%s: uec not initial\n", __FUNCTION__); 105 return -EINVAL; 106 } 107 uec_regs = uec->uec_regs; 108 109 maccfg1 = in_be32(&uec_regs->maccfg1); 110 111 if (mode & COMM_DIR_TX) { 112 maccfg1 &= ~MACCFG1_ENABLE_TX; 113 out_be32(&uec_regs->maccfg1, maccfg1); 114 uec->mac_tx_enabled = 0; 115 } 116 117 if (mode & COMM_DIR_RX) { 118 maccfg1 &= ~MACCFG1_ENABLE_RX; 119 out_be32(&uec_regs->maccfg1, maccfg1); 120 uec->mac_rx_enabled = 0; 121 } 122 123 return 0; 124 } 125 126 static int uec_graceful_stop_tx(uec_private_t *uec) 127 { 128 ucc_fast_t *uf_regs; 129 u32 cecr_subblock; 130 u32 ucce; 131 132 if (!uec || !uec->uccf) { 133 printf("%s: No handle passed.\n", __FUNCTION__); 134 return -EINVAL; 135 } 136 137 uf_regs = uec->uccf->uf_regs; 138 139 /* Clear the grace stop event */ 140 out_be32(&uf_regs->ucce, UCCE_GRA); 141 142 /* Issue host command */ 143 cecr_subblock = 144 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); 145 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, 146 (u8)QE_CR_PROTOCOL_ETHERNET, 0); 147 148 /* Wait for command to complete */ 149 do { 150 ucce = in_be32(&uf_regs->ucce); 151 } while (! (ucce & UCCE_GRA)); 152 153 uec->grace_stopped_tx = 1; 154 155 return 0; 156 } 157 158 static int uec_graceful_stop_rx(uec_private_t *uec) 159 { 160 u32 cecr_subblock; 161 u8 ack; 162 163 if (!uec) { 164 printf("%s: No handle passed.\n", __FUNCTION__); 165 return -EINVAL; 166 } 167 168 if (!uec->p_rx_glbl_pram) { 169 printf("%s: No init rx global parameter\n", __FUNCTION__); 170 return -EINVAL; 171 } 172 173 /* Clear acknowledge bit */ 174 ack = uec->p_rx_glbl_pram->rxgstpack; 175 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; 176 uec->p_rx_glbl_pram->rxgstpack = ack; 177 178 /* Keep issuing cmd and checking ack bit until it is asserted */ 179 do { 180 /* Issue host command */ 181 cecr_subblock = 182 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); 183 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, 184 (u8)QE_CR_PROTOCOL_ETHERNET, 0); 185 ack = uec->p_rx_glbl_pram->rxgstpack; 186 } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX )); 187 188 uec->grace_stopped_rx = 1; 189 190 return 0; 191 } 192 193 static int uec_restart_tx(uec_private_t *uec) 194 { 195 u32 cecr_subblock; 196 197 if (!uec || !uec->uec_info) { 198 printf("%s: No handle passed.\n", __FUNCTION__); 199 return -EINVAL; 200 } 201 202 cecr_subblock = 203 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); 204 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, 205 (u8)QE_CR_PROTOCOL_ETHERNET, 0); 206 207 uec->grace_stopped_tx = 0; 208 209 return 0; 210 } 211 212 static int uec_restart_rx(uec_private_t *uec) 213 { 214 u32 cecr_subblock; 215 216 if (!uec || !uec->uec_info) { 217 printf("%s: No handle passed.\n", __FUNCTION__); 218 return -EINVAL; 219 } 220 221 cecr_subblock = 222 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); 223 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, 224 (u8)QE_CR_PROTOCOL_ETHERNET, 0); 225 226 uec->grace_stopped_rx = 0; 227 228 return 0; 229 } 230 231 static int uec_open(uec_private_t *uec, comm_dir_e mode) 232 { 233 ucc_fast_private_t *uccf; 234 235 if (!uec || !uec->uccf) { 236 printf("%s: No handle passed.\n", __FUNCTION__); 237 return -EINVAL; 238 } 239 uccf = uec->uccf; 240 241 /* check if the UCC number is in range. */ 242 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { 243 printf("%s: ucc_num out of range.\n", __FUNCTION__); 244 return -EINVAL; 245 } 246 247 /* Enable MAC */ 248 uec_mac_enable(uec, mode); 249 250 /* Enable UCC fast */ 251 ucc_fast_enable(uccf, mode); 252 253 /* RISC microcode start */ 254 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) { 255 uec_restart_tx(uec); 256 } 257 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) { 258 uec_restart_rx(uec); 259 } 260 261 return 0; 262 } 263 264 static int uec_stop(uec_private_t *uec, comm_dir_e mode) 265 { 266 ucc_fast_private_t *uccf; 267 268 if (!uec || !uec->uccf) { 269 printf("%s: No handle passed.\n", __FUNCTION__); 270 return -EINVAL; 271 } 272 uccf = uec->uccf; 273 274 /* check if the UCC number is in range. */ 275 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { 276 printf("%s: ucc_num out of range.\n", __FUNCTION__); 277 return -EINVAL; 278 } 279 /* Stop any transmissions */ 280 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) { 281 uec_graceful_stop_tx(uec); 282 } 283 /* Stop any receptions */ 284 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) { 285 uec_graceful_stop_rx(uec); 286 } 287 288 /* Disable the UCC fast */ 289 ucc_fast_disable(uec->uccf, mode); 290 291 /* Disable the MAC */ 292 uec_mac_disable(uec, mode); 293 294 return 0; 295 } 296 297 static int uec_set_mac_duplex(uec_private_t *uec, int duplex) 298 { 299 uec_t *uec_regs; 300 u32 maccfg2; 301 302 if (!uec) { 303 printf("%s: uec not initial\n", __FUNCTION__); 304 return -EINVAL; 305 } 306 uec_regs = uec->uec_regs; 307 308 if (duplex == DUPLEX_HALF) { 309 maccfg2 = in_be32(&uec_regs->maccfg2); 310 maccfg2 &= ~MACCFG2_FDX; 311 out_be32(&uec_regs->maccfg2, maccfg2); 312 } 313 314 if (duplex == DUPLEX_FULL) { 315 maccfg2 = in_be32(&uec_regs->maccfg2); 316 maccfg2 |= MACCFG2_FDX; 317 out_be32(&uec_regs->maccfg2, maccfg2); 318 } 319 320 return 0; 321 } 322 323 static int uec_set_mac_if_mode(uec_private_t *uec, 324 enum fsl_phy_enet_if if_mode, int speed) 325 { 326 enum fsl_phy_enet_if enet_if_mode; 327 uec_info_t *uec_info; 328 uec_t *uec_regs; 329 u32 upsmr; 330 u32 maccfg2; 331 332 if (!uec) { 333 printf("%s: uec not initial\n", __FUNCTION__); 334 return -EINVAL; 335 } 336 337 uec_info = uec->uec_info; 338 uec_regs = uec->uec_regs; 339 enet_if_mode = if_mode; 340 341 maccfg2 = in_be32(&uec_regs->maccfg2); 342 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; 343 344 upsmr = in_be32(&uec->uccf->uf_regs->upsmr); 345 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM); 346 347 switch (speed) { 348 case 10: 349 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; 350 switch (enet_if_mode) { 351 case MII: 352 break; 353 case RGMII: 354 upsmr |= (UPSMR_RPM | UPSMR_R10M); 355 break; 356 case RMII: 357 upsmr |= (UPSMR_R10M | UPSMR_RMM); 358 break; 359 default: 360 return -EINVAL; 361 break; 362 } 363 break; 364 case 100: 365 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; 366 switch (enet_if_mode) { 367 case MII: 368 break; 369 case RGMII: 370 upsmr |= UPSMR_RPM; 371 break; 372 case RMII: 373 upsmr |= UPSMR_RMM; 374 break; 375 default: 376 return -EINVAL; 377 break; 378 } 379 break; 380 case 1000: 381 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; 382 switch (enet_if_mode) { 383 case GMII: 384 break; 385 case TBI: 386 upsmr |= UPSMR_TBIM; 387 break; 388 case RTBI: 389 upsmr |= (UPSMR_RPM | UPSMR_TBIM); 390 break; 391 case RGMII_RXID: 392 case RGMII_ID: 393 case RGMII: 394 upsmr |= UPSMR_RPM; 395 break; 396 case SGMII: 397 upsmr |= UPSMR_SGMM; 398 break; 399 default: 400 return -EINVAL; 401 break; 402 } 403 break; 404 default: 405 return -EINVAL; 406 break; 407 } 408 409 out_be32(&uec_regs->maccfg2, maccfg2); 410 out_be32(&uec->uccf->uf_regs->upsmr, upsmr); 411 412 return 0; 413 } 414 415 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs) 416 { 417 uint timeout = 0x1000; 418 u32 miimcfg = 0; 419 420 miimcfg = in_be32(&uec_mii_regs->miimcfg); 421 miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE; 422 out_be32(&uec_mii_regs->miimcfg, miimcfg); 423 424 /* Wait until the bus is free */ 425 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--); 426 if (timeout <= 0) { 427 printf("%s: The MII Bus is stuck!", __FUNCTION__); 428 return -ETIMEDOUT; 429 } 430 431 return 0; 432 } 433 434 static int init_phy(struct eth_device *dev) 435 { 436 uec_private_t *uec; 437 uec_mii_t *umii_regs; 438 struct uec_mii_info *mii_info; 439 struct phy_info *curphy; 440 int err; 441 442 uec = (uec_private_t *)dev->priv; 443 umii_regs = uec->uec_mii_regs; 444 445 uec->oldlink = 0; 446 uec->oldspeed = 0; 447 uec->oldduplex = -1; 448 449 mii_info = malloc(sizeof(*mii_info)); 450 if (!mii_info) { 451 printf("%s: Could not allocate mii_info", dev->name); 452 return -ENOMEM; 453 } 454 memset(mii_info, 0, sizeof(*mii_info)); 455 456 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { 457 mii_info->speed = SPEED_1000; 458 } else { 459 mii_info->speed = SPEED_100; 460 } 461 462 mii_info->duplex = DUPLEX_FULL; 463 mii_info->pause = 0; 464 mii_info->link = 1; 465 466 mii_info->advertising = (ADVERTISED_10baseT_Half | 467 ADVERTISED_10baseT_Full | 468 ADVERTISED_100baseT_Half | 469 ADVERTISED_100baseT_Full | 470 ADVERTISED_1000baseT_Full); 471 mii_info->autoneg = 1; 472 mii_info->mii_id = uec->uec_info->phy_address; 473 mii_info->dev = dev; 474 475 mii_info->mdio_read = &uec_read_phy_reg; 476 mii_info->mdio_write = &uec_write_phy_reg; 477 478 uec->mii_info = mii_info; 479 480 qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num); 481 482 if (init_mii_management_configuration(umii_regs)) { 483 printf("%s: The MII Bus is stuck!", dev->name); 484 err = -1; 485 goto bus_fail; 486 } 487 488 /* get info for this PHY */ 489 curphy = uec_get_phy_info(uec->mii_info); 490 if (!curphy) { 491 printf("%s: No PHY found", dev->name); 492 err = -1; 493 goto no_phy; 494 } 495 496 mii_info->phyinfo = curphy; 497 498 /* Run the commands which initialize the PHY */ 499 if (curphy->init) { 500 err = curphy->init(uec->mii_info); 501 if (err) 502 goto phy_init_fail; 503 } 504 505 return 0; 506 507 phy_init_fail: 508 no_phy: 509 bus_fail: 510 free(mii_info); 511 return err; 512 } 513 514 static void adjust_link(struct eth_device *dev) 515 { 516 uec_private_t *uec = (uec_private_t *)dev->priv; 517 uec_t *uec_regs; 518 struct uec_mii_info *mii_info = uec->mii_info; 519 520 extern void change_phy_interface_mode(struct eth_device *dev, 521 enum fsl_phy_enet_if mode, int speed); 522 uec_regs = uec->uec_regs; 523 524 if (mii_info->link) { 525 /* Now we make sure that we can be in full duplex mode. 526 * If not, we operate in half-duplex mode. */ 527 if (mii_info->duplex != uec->oldduplex) { 528 if (!(mii_info->duplex)) { 529 uec_set_mac_duplex(uec, DUPLEX_HALF); 530 printf("%s: Half Duplex\n", dev->name); 531 } else { 532 uec_set_mac_duplex(uec, DUPLEX_FULL); 533 printf("%s: Full Duplex\n", dev->name); 534 } 535 uec->oldduplex = mii_info->duplex; 536 } 537 538 if (mii_info->speed != uec->oldspeed) { 539 enum fsl_phy_enet_if mode = \ 540 uec->uec_info->enet_interface_type; 541 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { 542 switch (mii_info->speed) { 543 case 1000: 544 break; 545 case 100: 546 printf ("switching to rgmii 100\n"); 547 mode = RGMII; 548 break; 549 case 10: 550 printf ("switching to rgmii 10\n"); 551 mode = RGMII; 552 break; 553 default: 554 printf("%s: Ack,Speed(%d)is illegal\n", 555 dev->name, mii_info->speed); 556 break; 557 } 558 } 559 560 /* change phy */ 561 change_phy_interface_mode(dev, mode, mii_info->speed); 562 /* change the MAC interface mode */ 563 uec_set_mac_if_mode(uec, mode, mii_info->speed); 564 565 printf("%s: Speed %dBT\n", dev->name, mii_info->speed); 566 uec->oldspeed = mii_info->speed; 567 } 568 569 if (!uec->oldlink) { 570 printf("%s: Link is up\n", dev->name); 571 uec->oldlink = 1; 572 } 573 574 } else { /* if (mii_info->link) */ 575 if (uec->oldlink) { 576 printf("%s: Link is down\n", dev->name); 577 uec->oldlink = 0; 578 uec->oldspeed = 0; 579 uec->oldduplex = -1; 580 } 581 } 582 } 583 584 static void phy_change(struct eth_device *dev) 585 { 586 uec_private_t *uec = (uec_private_t *)dev->priv; 587 588 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ 589 defined(CONFIG_P1021) || defined(CONFIG_P1025) 590 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 591 592 /* QE9 and QE12 need to be set for enabling QE MII managment signals */ 593 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); 594 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); 595 #endif 596 597 /* Update the link, speed, duplex */ 598 uec->mii_info->phyinfo->read_status(uec->mii_info); 599 600 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ 601 defined(CONFIG_P1021) || defined(CONFIG_P1025) 602 /* 603 * QE12 is muxed with LBCTL, it needs to be released for enabling 604 * LBCTL signal for LBC usage. 605 */ 606 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); 607 #endif 608 609 /* Adjust the interface according to speed */ 610 adjust_link(dev); 611 } 612 613 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 614 615 /* 616 * Find a device index from the devlist by name 617 * 618 * Returns: 619 * The index where the device is located, -1 on error 620 */ 621 static int uec_miiphy_find_dev_by_name(const char *devname) 622 { 623 int i; 624 625 for (i = 0; i < MAXCONTROLLERS; i++) { 626 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) { 627 break; 628 } 629 } 630 631 /* If device cannot be found, returns -1 */ 632 if (i == MAXCONTROLLERS) { 633 debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname); 634 i = -1; 635 } 636 637 return i; 638 } 639 640 /* 641 * Read a MII PHY register. 642 * 643 * Returns: 644 * 0 on success 645 */ 646 static int uec_miiphy_read(const char *devname, unsigned char addr, 647 unsigned char reg, unsigned short *value) 648 { 649 int devindex = 0; 650 651 if (devname == NULL || value == NULL) { 652 debug("%s: NULL pointer given\n", __FUNCTION__); 653 } else { 654 devindex = uec_miiphy_find_dev_by_name(devname); 655 if (devindex >= 0) { 656 *value = uec_read_phy_reg(devlist[devindex], addr, reg); 657 } 658 } 659 return 0; 660 } 661 662 /* 663 * Write a MII PHY register. 664 * 665 * Returns: 666 * 0 on success 667 */ 668 static int uec_miiphy_write(const char *devname, unsigned char addr, 669 unsigned char reg, unsigned short value) 670 { 671 int devindex = 0; 672 673 if (devname == NULL) { 674 debug("%s: NULL pointer given\n", __FUNCTION__); 675 } else { 676 devindex = uec_miiphy_find_dev_by_name(devname); 677 if (devindex >= 0) { 678 uec_write_phy_reg(devlist[devindex], addr, reg, value); 679 } 680 } 681 return 0; 682 } 683 #endif 684 685 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr) 686 { 687 uec_t *uec_regs; 688 u32 mac_addr1; 689 u32 mac_addr2; 690 691 if (!uec) { 692 printf("%s: uec not initial\n", __FUNCTION__); 693 return -EINVAL; 694 } 695 696 uec_regs = uec->uec_regs; 697 698 /* if a station address of 0x12345678ABCD, perform a write to 699 MACSTNADDR1 of 0xCDAB7856, 700 MACSTNADDR2 of 0x34120000 */ 701 702 mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \ 703 (mac_addr[3] << 8) | (mac_addr[2]); 704 out_be32(&uec_regs->macstnaddr1, mac_addr1); 705 706 mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000; 707 out_be32(&uec_regs->macstnaddr2, mac_addr2); 708 709 return 0; 710 } 711 712 static int uec_convert_threads_num(uec_num_of_threads_e threads_num, 713 int *threads_num_ret) 714 { 715 int num_threads_numerica; 716 717 switch (threads_num) { 718 case UEC_NUM_OF_THREADS_1: 719 num_threads_numerica = 1; 720 break; 721 case UEC_NUM_OF_THREADS_2: 722 num_threads_numerica = 2; 723 break; 724 case UEC_NUM_OF_THREADS_4: 725 num_threads_numerica = 4; 726 break; 727 case UEC_NUM_OF_THREADS_6: 728 num_threads_numerica = 6; 729 break; 730 case UEC_NUM_OF_THREADS_8: 731 num_threads_numerica = 8; 732 break; 733 default: 734 printf("%s: Bad number of threads value.", 735 __FUNCTION__); 736 return -EINVAL; 737 } 738 739 *threads_num_ret = num_threads_numerica; 740 741 return 0; 742 } 743 744 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx) 745 { 746 uec_info_t *uec_info; 747 u32 end_bd; 748 u8 bmrx = 0; 749 int i; 750 751 uec_info = uec->uec_info; 752 753 /* Alloc global Tx parameter RAM page */ 754 uec->tx_glbl_pram_offset = qe_muram_alloc( 755 sizeof(uec_tx_global_pram_t), 756 UEC_TX_GLOBAL_PRAM_ALIGNMENT); 757 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *) 758 qe_muram_addr(uec->tx_glbl_pram_offset); 759 760 /* Zero the global Tx prameter RAM */ 761 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t)); 762 763 /* Init global Tx parameter RAM */ 764 765 /* TEMODER, RMON statistics disable, one Tx queue */ 766 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE); 767 768 /* SQPTR */ 769 uec->send_q_mem_reg_offset = qe_muram_alloc( 770 sizeof(uec_send_queue_qd_t), 771 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); 772 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *) 773 qe_muram_addr(uec->send_q_mem_reg_offset); 774 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset); 775 776 /* Setup the table with TxBDs ring */ 777 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1) 778 * SIZEOFBD; 779 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base, 780 (u32)(uec->p_tx_bd_ring)); 781 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address, 782 end_bd); 783 784 /* Scheduler Base Pointer, we have only one Tx queue, no need it */ 785 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0); 786 787 /* TxRMON Base Pointer, TxRMON disable, we don't need it */ 788 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0); 789 790 /* TSTATE, global snooping, big endian, the CSB bus selected */ 791 bmrx = BMR_INIT_VALUE; 792 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT)); 793 794 /* IPH_Offset */ 795 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) { 796 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0); 797 } 798 799 /* VTAG table */ 800 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) { 801 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0); 802 } 803 804 /* TQPTR */ 805 uec->thread_dat_tx_offset = qe_muram_alloc( 806 num_threads_tx * sizeof(uec_thread_data_tx_t) + 807 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT); 808 809 uec->p_thread_data_tx = (uec_thread_data_tx_t *) 810 qe_muram_addr(uec->thread_dat_tx_offset); 811 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset); 812 } 813 814 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx) 815 { 816 u8 bmrx = 0; 817 int i; 818 uec_82xx_address_filtering_pram_t *p_af_pram; 819 820 /* Allocate global Rx parameter RAM page */ 821 uec->rx_glbl_pram_offset = qe_muram_alloc( 822 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT); 823 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *) 824 qe_muram_addr(uec->rx_glbl_pram_offset); 825 826 /* Zero Global Rx parameter RAM */ 827 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t)); 828 829 /* Init global Rx parameter RAM */ 830 /* REMODER, Extended feature mode disable, VLAN disable, 831 LossLess flow control disable, Receive firmware statisic disable, 832 Extended address parsing mode disable, One Rx queues, 833 Dynamic maximum/minimum frame length disable, IP checksum check 834 disable, IP address alignment disable 835 */ 836 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE); 837 838 /* RQPTR */ 839 uec->thread_dat_rx_offset = qe_muram_alloc( 840 num_threads_rx * sizeof(uec_thread_data_rx_t), 841 UEC_THREAD_DATA_ALIGNMENT); 842 uec->p_thread_data_rx = (uec_thread_data_rx_t *) 843 qe_muram_addr(uec->thread_dat_rx_offset); 844 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset); 845 846 /* Type_or_Len */ 847 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072); 848 849 /* RxRMON base pointer, we don't need it */ 850 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0); 851 852 /* IntCoalescingPTR, we don't need it, no interrupt */ 853 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0); 854 855 /* RSTATE, global snooping, big endian, the CSB bus selected */ 856 bmrx = BMR_INIT_VALUE; 857 out_8(&uec->p_rx_glbl_pram->rstate, bmrx); 858 859 /* MRBLR */ 860 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN); 861 862 /* RBDQPTR */ 863 uec->rx_bd_qs_tbl_offset = qe_muram_alloc( 864 sizeof(uec_rx_bd_queues_entry_t) + \ 865 sizeof(uec_rx_prefetched_bds_t), 866 UEC_RX_BD_QUEUES_ALIGNMENT); 867 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *) 868 qe_muram_addr(uec->rx_bd_qs_tbl_offset); 869 870 /* Zero it */ 871 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \ 872 sizeof(uec_rx_prefetched_bds_t)); 873 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset); 874 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr, 875 (u32)uec->p_rx_bd_ring); 876 877 /* MFLR */ 878 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN); 879 /* MINFLR */ 880 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN); 881 /* MAXD1 */ 882 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN); 883 /* MAXD2 */ 884 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN); 885 /* ECAM_PTR */ 886 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0); 887 /* L2QT */ 888 out_be32(&uec->p_rx_glbl_pram->l2qt, 0); 889 /* L3QT */ 890 for (i = 0; i < 8; i++) { 891 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0); 892 } 893 894 /* VLAN_TYPE */ 895 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100); 896 /* TCI */ 897 out_be16(&uec->p_rx_glbl_pram->vlantci, 0); 898 899 /* Clear PQ2 style address filtering hash table */ 900 p_af_pram = (uec_82xx_address_filtering_pram_t *) \ 901 uec->p_rx_glbl_pram->addressfiltering; 902 903 p_af_pram->iaddr_h = 0; 904 p_af_pram->iaddr_l = 0; 905 p_af_pram->gaddr_h = 0; 906 p_af_pram->gaddr_l = 0; 907 } 908 909 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec, 910 int thread_tx, int thread_rx) 911 { 912 uec_init_cmd_pram_t *p_init_enet_param; 913 u32 init_enet_param_offset; 914 uec_info_t *uec_info; 915 int i; 916 int snum; 917 u32 init_enet_offset; 918 u32 entry_val; 919 u32 command; 920 u32 cecr_subblock; 921 922 uec_info = uec->uec_info; 923 924 /* Allocate init enet command parameter */ 925 uec->init_enet_param_offset = qe_muram_alloc( 926 sizeof(uec_init_cmd_pram_t), 4); 927 init_enet_param_offset = uec->init_enet_param_offset; 928 uec->p_init_enet_param = (uec_init_cmd_pram_t *) 929 qe_muram_addr(uec->init_enet_param_offset); 930 931 /* Zero init enet command struct */ 932 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t)); 933 934 /* Init the command struct */ 935 p_init_enet_param = uec->p_init_enet_param; 936 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0; 937 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1; 938 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2; 939 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3; 940 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4; 941 p_init_enet_param->largestexternallookupkeysize = 0; 942 943 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx) 944 << ENET_INIT_PARAM_RGF_SHIFT; 945 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx) 946 << ENET_INIT_PARAM_TGF_SHIFT; 947 948 /* Init Rx global parameter pointer */ 949 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset | 950 (u32)uec_info->risc_rx; 951 952 /* Init Rx threads */ 953 for (i = 0; i < (thread_rx + 1); i++) { 954 if ((snum = qe_get_snum()) < 0) { 955 printf("%s can not get snum\n", __FUNCTION__); 956 return -ENOMEM; 957 } 958 959 if (i==0) { 960 init_enet_offset = 0; 961 } else { 962 init_enet_offset = qe_muram_alloc( 963 sizeof(uec_thread_rx_pram_t), 964 UEC_THREAD_RX_PRAM_ALIGNMENT); 965 } 966 967 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | 968 init_enet_offset | (u32)uec_info->risc_rx; 969 p_init_enet_param->rxthread[i] = entry_val; 970 } 971 972 /* Init Tx global parameter pointer */ 973 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset | 974 (u32)uec_info->risc_tx; 975 976 /* Init Tx threads */ 977 for (i = 0; i < thread_tx; i++) { 978 if ((snum = qe_get_snum()) < 0) { 979 printf("%s can not get snum\n", __FUNCTION__); 980 return -ENOMEM; 981 } 982 983 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t), 984 UEC_THREAD_TX_PRAM_ALIGNMENT); 985 986 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | 987 init_enet_offset | (u32)uec_info->risc_tx; 988 p_init_enet_param->txthread[i] = entry_val; 989 } 990 991 __asm__ __volatile__("sync"); 992 993 /* Issue QE command */ 994 command = QE_INIT_TX_RX; 995 cecr_subblock = ucc_fast_get_qe_cr_subblock( 996 uec->uec_info->uf_info.ucc_num); 997 qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET, 998 init_enet_param_offset); 999 1000 return 0; 1001 } 1002 1003 static int uec_startup(uec_private_t *uec) 1004 { 1005 uec_info_t *uec_info; 1006 ucc_fast_info_t *uf_info; 1007 ucc_fast_private_t *uccf; 1008 ucc_fast_t *uf_regs; 1009 uec_t *uec_regs; 1010 int num_threads_tx; 1011 int num_threads_rx; 1012 u32 utbipar; 1013 u32 length; 1014 u32 align; 1015 qe_bd_t *bd; 1016 u8 *buf; 1017 int i; 1018 1019 if (!uec || !uec->uec_info) { 1020 printf("%s: uec or uec_info not initial\n", __FUNCTION__); 1021 return -EINVAL; 1022 } 1023 1024 uec_info = uec->uec_info; 1025 uf_info = &(uec_info->uf_info); 1026 1027 /* Check if Rx BD ring len is illegal */ 1028 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \ 1029 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) { 1030 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n", 1031 __FUNCTION__); 1032 return -EINVAL; 1033 } 1034 1035 /* Check if Tx BD ring len is illegal */ 1036 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) { 1037 printf("%s: Tx BD ring length must not be smaller than 2.\n", 1038 __FUNCTION__); 1039 return -EINVAL; 1040 } 1041 1042 /* Check if MRBLR is illegal */ 1043 if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) { 1044 printf("%s: max rx buffer length must be mutliple of 128.\n", 1045 __FUNCTION__); 1046 return -EINVAL; 1047 } 1048 1049 /* Both Rx and Tx are stopped */ 1050 uec->grace_stopped_rx = 1; 1051 uec->grace_stopped_tx = 1; 1052 1053 /* Init UCC fast */ 1054 if (ucc_fast_init(uf_info, &uccf)) { 1055 printf("%s: failed to init ucc fast\n", __FUNCTION__); 1056 return -ENOMEM; 1057 } 1058 1059 /* Save uccf */ 1060 uec->uccf = uccf; 1061 1062 /* Convert the Tx threads number */ 1063 if (uec_convert_threads_num(uec_info->num_threads_tx, 1064 &num_threads_tx)) { 1065 return -EINVAL; 1066 } 1067 1068 /* Convert the Rx threads number */ 1069 if (uec_convert_threads_num(uec_info->num_threads_rx, 1070 &num_threads_rx)) { 1071 return -EINVAL; 1072 } 1073 1074 uf_regs = uccf->uf_regs; 1075 1076 /* UEC register is following UCC fast registers */ 1077 uec_regs = (uec_t *)(&uf_regs->ucc_eth); 1078 1079 /* Save the UEC register pointer to UEC private struct */ 1080 uec->uec_regs = uec_regs; 1081 1082 /* Init UPSMR, enable hardware statistics (UCC) */ 1083 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE); 1084 1085 /* Init MACCFG1, flow control disable, disable Tx and Rx */ 1086 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE); 1087 1088 /* Init MACCFG2, length check, MAC PAD and CRC enable */ 1089 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE); 1090 1091 /* Setup MAC interface mode */ 1092 uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed); 1093 1094 /* Setup MII management base */ 1095 #ifndef CONFIG_eTSEC_MDIO_BUS 1096 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg); 1097 #else 1098 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS; 1099 #endif 1100 1101 /* Setup MII master clock source */ 1102 qe_set_mii_clk_src(uec_info->uf_info.ucc_num); 1103 1104 /* Setup UTBIPAR */ 1105 utbipar = in_be32(&uec_regs->utbipar); 1106 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK; 1107 1108 /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC. 1109 * This frees up the remaining SMI addresses for use. 1110 */ 1111 utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT; 1112 out_be32(&uec_regs->utbipar, utbipar); 1113 1114 /* Configure the TBI for SGMII operation */ 1115 if ((uec->uec_info->enet_interface_type == SGMII) && 1116 (uec->uec_info->speed == 1000)) { 1117 uec_write_phy_reg(uec->dev, uec_regs->utbipar, 1118 ENET_TBI_MII_ANA, TBIANA_SETTINGS); 1119 1120 uec_write_phy_reg(uec->dev, uec_regs->utbipar, 1121 ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); 1122 1123 uec_write_phy_reg(uec->dev, uec_regs->utbipar, 1124 ENET_TBI_MII_CR, TBICR_SETTINGS); 1125 } 1126 1127 /* Allocate Tx BDs */ 1128 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) / 1129 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) * 1130 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 1131 if ((uec_info->tx_bd_ring_len * SIZEOFBD) % 1132 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) { 1133 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 1134 } 1135 1136 align = UEC_TX_BD_RING_ALIGNMENT; 1137 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align)); 1138 if (uec->tx_bd_ring_offset != 0) { 1139 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align) 1140 & ~(align - 1)); 1141 } 1142 1143 /* Zero all of Tx BDs */ 1144 memset((void *)(uec->tx_bd_ring_offset), 0, length + align); 1145 1146 /* Allocate Rx BDs */ 1147 length = uec_info->rx_bd_ring_len * SIZEOFBD; 1148 align = UEC_RX_BD_RING_ALIGNMENT; 1149 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align))); 1150 if (uec->rx_bd_ring_offset != 0) { 1151 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align) 1152 & ~(align - 1)); 1153 } 1154 1155 /* Zero all of Rx BDs */ 1156 memset((void *)(uec->rx_bd_ring_offset), 0, length + align); 1157 1158 /* Allocate Rx buffer */ 1159 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN; 1160 align = UEC_RX_DATA_BUF_ALIGNMENT; 1161 uec->rx_buf_offset = (u32)malloc(length + align); 1162 if (uec->rx_buf_offset != 0) { 1163 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align) 1164 & ~(align - 1)); 1165 } 1166 1167 /* Zero all of the Rx buffer */ 1168 memset((void *)(uec->rx_buf_offset), 0, length + align); 1169 1170 /* Init TxBD ring */ 1171 bd = (qe_bd_t *)uec->p_tx_bd_ring; 1172 uec->txBd = bd; 1173 1174 for (i = 0; i < uec_info->tx_bd_ring_len; i++) { 1175 BD_DATA_CLEAR(bd); 1176 BD_STATUS_SET(bd, 0); 1177 BD_LENGTH_SET(bd, 0); 1178 bd ++; 1179 } 1180 BD_STATUS_SET((--bd), TxBD_WRAP); 1181 1182 /* Init RxBD ring */ 1183 bd = (qe_bd_t *)uec->p_rx_bd_ring; 1184 uec->rxBd = bd; 1185 buf = uec->p_rx_buf; 1186 for (i = 0; i < uec_info->rx_bd_ring_len; i++) { 1187 BD_DATA_SET(bd, buf); 1188 BD_LENGTH_SET(bd, 0); 1189 BD_STATUS_SET(bd, RxBD_EMPTY); 1190 buf += MAX_RXBUF_LEN; 1191 bd ++; 1192 } 1193 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY); 1194 1195 /* Init global Tx parameter RAM */ 1196 uec_init_tx_parameter(uec, num_threads_tx); 1197 1198 /* Init global Rx parameter RAM */ 1199 uec_init_rx_parameter(uec, num_threads_rx); 1200 1201 /* Init ethernet Tx and Rx parameter command */ 1202 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx, 1203 num_threads_rx)) { 1204 printf("%s issue init enet cmd failed\n", __FUNCTION__); 1205 return -ENOMEM; 1206 } 1207 1208 return 0; 1209 } 1210 1211 static int uec_init(struct eth_device* dev, bd_t *bd) 1212 { 1213 uec_private_t *uec; 1214 int err, i; 1215 struct phy_info *curphy; 1216 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ 1217 defined(CONFIG_P1021) || defined(CONFIG_P1025) 1218 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 1219 #endif 1220 1221 uec = (uec_private_t *)dev->priv; 1222 1223 if (uec->the_first_run == 0) { 1224 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ 1225 defined(CONFIG_P1021) || defined(CONFIG_P1025) 1226 /* QE9 and QE12 need to be set for enabling QE MII managment signals */ 1227 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); 1228 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); 1229 #endif 1230 1231 err = init_phy(dev); 1232 if (err) { 1233 printf("%s: Cannot initialize PHY, aborting.\n", 1234 dev->name); 1235 return err; 1236 } 1237 1238 curphy = uec->mii_info->phyinfo; 1239 1240 if (curphy->config_aneg) { 1241 err = curphy->config_aneg(uec->mii_info); 1242 if (err) { 1243 printf("%s: Can't negotiate PHY\n", dev->name); 1244 return err; 1245 } 1246 } 1247 1248 /* Give PHYs up to 5 sec to report a link */ 1249 i = 50; 1250 do { 1251 err = curphy->read_status(uec->mii_info); 1252 if (!(((i-- > 0) && !uec->mii_info->link) || err)) 1253 break; 1254 udelay(100000); 1255 } while (1); 1256 1257 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ 1258 defined(CONFIG_P1021) || defined(CONFIG_P1025) 1259 /* QE12 needs to be released for enabling LBCTL signal*/ 1260 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); 1261 #endif 1262 1263 if (err || i <= 0) 1264 printf("warning: %s: timeout on PHY link\n", dev->name); 1265 1266 adjust_link(dev); 1267 uec->the_first_run = 1; 1268 } 1269 1270 /* Set up the MAC address */ 1271 if (dev->enetaddr[0] & 0x01) { 1272 printf("%s: MacAddress is multcast address\n", 1273 __FUNCTION__); 1274 return -1; 1275 } 1276 uec_set_mac_address(uec, dev->enetaddr); 1277 1278 1279 err = uec_open(uec, COMM_DIR_RX_AND_TX); 1280 if (err) { 1281 printf("%s: cannot enable UEC device\n", dev->name); 1282 return -1; 1283 } 1284 1285 phy_change(dev); 1286 1287 return (uec->mii_info->link ? 0 : -1); 1288 } 1289 1290 static void uec_halt(struct eth_device* dev) 1291 { 1292 uec_private_t *uec = (uec_private_t *)dev->priv; 1293 uec_stop(uec, COMM_DIR_RX_AND_TX); 1294 } 1295 1296 static int uec_send(struct eth_device* dev, volatile void *buf, int len) 1297 { 1298 uec_private_t *uec; 1299 ucc_fast_private_t *uccf; 1300 volatile qe_bd_t *bd; 1301 u16 status; 1302 int i; 1303 int result = 0; 1304 1305 uec = (uec_private_t *)dev->priv; 1306 uccf = uec->uccf; 1307 bd = uec->txBd; 1308 1309 /* Find an empty TxBD */ 1310 for (i = 0; bd->status & TxBD_READY; i++) { 1311 if (i > 0x100000) { 1312 printf("%s: tx buffer not ready\n", dev->name); 1313 return result; 1314 } 1315 } 1316 1317 /* Init TxBD */ 1318 BD_DATA_SET(bd, buf); 1319 BD_LENGTH_SET(bd, len); 1320 status = bd->status; 1321 status &= BD_WRAP; 1322 status |= (TxBD_READY | TxBD_LAST); 1323 BD_STATUS_SET(bd, status); 1324 1325 /* Tell UCC to transmit the buffer */ 1326 ucc_fast_transmit_on_demand(uccf); 1327 1328 /* Wait for buffer to be transmitted */ 1329 for (i = 0; bd->status & TxBD_READY; i++) { 1330 if (i > 0x100000) { 1331 printf("%s: tx error\n", dev->name); 1332 return result; 1333 } 1334 } 1335 1336 /* Ok, the buffer be transimitted */ 1337 BD_ADVANCE(bd, status, uec->p_tx_bd_ring); 1338 uec->txBd = bd; 1339 result = 1; 1340 1341 return result; 1342 } 1343 1344 static int uec_recv(struct eth_device* dev) 1345 { 1346 uec_private_t *uec = dev->priv; 1347 volatile qe_bd_t *bd; 1348 u16 status; 1349 u16 len; 1350 u8 *data; 1351 1352 bd = uec->rxBd; 1353 status = bd->status; 1354 1355 while (!(status & RxBD_EMPTY)) { 1356 if (!(status & RxBD_ERROR)) { 1357 data = BD_DATA(bd); 1358 len = BD_LENGTH(bd); 1359 NetReceive(data, len); 1360 } else { 1361 printf("%s: Rx error\n", dev->name); 1362 } 1363 status &= BD_CLEAN; 1364 BD_LENGTH_SET(bd, 0); 1365 BD_STATUS_SET(bd, status | RxBD_EMPTY); 1366 BD_ADVANCE(bd, status, uec->p_rx_bd_ring); 1367 status = bd->status; 1368 } 1369 uec->rxBd = bd; 1370 1371 return 1; 1372 } 1373 1374 int uec_initialize(bd_t *bis, uec_info_t *uec_info) 1375 { 1376 struct eth_device *dev; 1377 int i; 1378 uec_private_t *uec; 1379 int err; 1380 1381 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 1382 if (!dev) 1383 return 0; 1384 memset(dev, 0, sizeof(struct eth_device)); 1385 1386 /* Allocate the UEC private struct */ 1387 uec = (uec_private_t *)malloc(sizeof(uec_private_t)); 1388 if (!uec) { 1389 return -ENOMEM; 1390 } 1391 memset(uec, 0, sizeof(uec_private_t)); 1392 1393 /* Adjust uec_info */ 1394 #if (MAX_QE_RISC == 4) 1395 uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS; 1396 uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS; 1397 #endif 1398 1399 devlist[uec_info->uf_info.ucc_num] = dev; 1400 1401 uec->uec_info = uec_info; 1402 uec->dev = dev; 1403 1404 sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num); 1405 dev->iobase = 0; 1406 dev->priv = (void *)uec; 1407 dev->init = uec_init; 1408 dev->halt = uec_halt; 1409 dev->send = uec_send; 1410 dev->recv = uec_recv; 1411 1412 /* Clear the ethnet address */ 1413 for (i = 0; i < 6; i++) 1414 dev->enetaddr[i] = 0; 1415 1416 eth_register(dev); 1417 1418 err = uec_startup(uec); 1419 if (err) { 1420 printf("%s: Cannot configure net device, aborting.",dev->name); 1421 return err; 1422 } 1423 1424 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 1425 miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write); 1426 #endif 1427 1428 return 1; 1429 } 1430 1431 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num) 1432 { 1433 int i; 1434 1435 for (i = 0; i < num; i++) 1436 uec_initialize(bis, &uecs[i]); 1437 1438 return 0; 1439 } 1440 1441 int uec_standard_init(bd_t *bis) 1442 { 1443 return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info)); 1444 } 1445