1 /* 2 * Copyright (c) 2016 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <div64.h> 11 #include <dm.h> 12 #include <pwm.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/pwm.h> 17 #include <power/regulator.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 struct rk_pwm_priv { 22 struct rk3288_pwm *regs; 23 ulong freq; 24 uint enable_conf; 25 }; 26 27 static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity) 28 { 29 struct rk_pwm_priv *priv = dev_get_priv(dev); 30 31 debug("%s: polarity=%u\n", __func__, polarity); 32 priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK); 33 if (polarity) 34 priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE; 35 else 36 priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE; 37 38 return 0; 39 } 40 41 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns, 42 uint duty_ns) 43 { 44 struct rk_pwm_priv *priv = dev_get_priv(dev); 45 struct rk3288_pwm *regs = priv->regs; 46 unsigned long period, duty; 47 uint32_t ctrl; 48 49 debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns); 50 51 ctrl = readl(®s->ctrl); 52 /* Ignore bit0: RK_PWM_ENABLE */ 53 ctrl &= ~0xfffe; 54 ctrl |= PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | 55 PWM_CONTINUOUS | priv->enable_conf; 56 writel(ctrl, ®s->ctrl); 57 58 period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000); 59 duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000); 60 61 writel(period, ®s->period_hpr); 62 writel(duty, ®s->duty_lpr); 63 debug("%s: period=%lu, duty=%lu\n", __func__, period, duty); 64 65 return 0; 66 } 67 68 static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable) 69 { 70 struct rk_pwm_priv *priv = dev_get_priv(dev); 71 struct rk3288_pwm *regs = priv->regs; 72 73 debug("%s: Enable '%s'\n", __func__, dev->name); 74 clrsetbits_le32(®s->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0); 75 76 return 0; 77 } 78 79 static int rk_pwm_ofdata_to_platdata(struct udevice *dev) 80 { 81 struct rk_pwm_priv *priv = dev_get_priv(dev); 82 83 priv->regs = (struct rk3288_pwm *)dev_read_addr(dev); 84 85 return 0; 86 } 87 88 static int rk_pwm_probe(struct udevice *dev) 89 { 90 struct rk_pwm_priv *priv = dev_get_priv(dev); 91 struct clk clk; 92 int ret = 0; 93 94 ret = clk_get_by_index(dev, 0, &clk); 95 if (ret < 0) { 96 debug("%s get clock fail!\n", __func__); 97 return -EINVAL; 98 } 99 priv->freq = clk_get_rate(&clk); 100 priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE; 101 102 return 0; 103 } 104 105 static const struct pwm_ops rk_pwm_ops = { 106 .set_invert = rk_pwm_set_invert, 107 .set_config = rk_pwm_set_config, 108 .set_enable = rk_pwm_set_enable, 109 }; 110 111 static const struct udevice_id rk_pwm_ids[] = { 112 { .compatible = "rockchip,rk3288-pwm" }, 113 { .compatible = "rockchip,rk3328-pwm" }, 114 { } 115 }; 116 117 U_BOOT_DRIVER(rk_pwm) = { 118 .name = "rk_pwm", 119 .id = UCLASS_PWM, 120 .of_match = rk_pwm_ids, 121 .ops = &rk_pwm_ops, 122 .ofdata_to_platdata = rk_pwm_ofdata_to_platdata, 123 .probe = rk_pwm_probe, 124 .priv_auto_alloc_size = sizeof(struct rk_pwm_priv), 125 }; 126