1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * Based on Rockchip's drivers/power/pmic/pmic_rk808.c: 6 * Copyright (C) 2012 rockchips 7 * zyw <zyw@rock-chips.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <power/rk8xx_pmic.h> 16 #include <power/pmic.h> 17 #include <power/regulator.h> 18 19 #ifndef CONFIG_SPL_BUILD 20 #define ENABLE_DRIVER 21 #endif 22 23 /* Not used or exisit register and configure */ 24 #define NA -1 25 26 /* Field Definitions */ 27 #define RK808_BUCK_VSEL_MASK 0x3f 28 #define RK808_BUCK4_VSEL_MASK 0xf 29 #define RK808_LDO_VSEL_MASK 0x1f 30 31 #define RK818_BUCK_VSEL_MASK 0x3f 32 #define RK818_BUCK4_VSEL_MASK 0x1f 33 #define RK818_LDO_VSEL_MASK 0x1f 34 #define RK818_LDO3_ON_VSEL_MASK 0xf 35 #define RK818_BOOST_ON_VSEL_MASK 0xe0 36 #define RK818_USB_ILIM_SEL_MASK 0x0f 37 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 38 39 /* RK809 BUCK5 */ 40 #define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1) 41 #define RK809_BUCK5_VSEL_MASK 0x07 42 43 /* RK817 BUCK */ 44 #define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * (n - 1)) 45 #define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * (n - 1)) 46 #define RK817_BUCK_VSEL_MASK 0x7f 47 #define RK817_BUCK_CONFIG(i) (0xba + (i) * 3) 48 49 /* RK817 LDO */ 50 #define RK817_LDO_ON_VSEL(n) (0xcc + 2 * (n - 1)) 51 #define RK817_LDO_SLP_VSEL(n) (0xcd + 2 * (n - 1)) 52 #define RK817_LDO_VSEL_MASK 0x7f 53 54 /* RK817 ENABLE */ 55 #define RK817_POWER_EN(n) (0xb1 + (n)) 56 #define RK817_POWER_SLP_EN(n) (0xb5 + (n)) 57 58 /* 59 * Ramp delay 60 */ 61 #define RK805_RAMP_RATE_OFFSET 3 62 #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET) 63 #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET) 64 #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET) 65 #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET) 66 #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET) 67 68 #define RK808_RAMP_RATE_OFFSET 3 69 #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET) 70 #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET) 71 #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET) 72 #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET) 73 #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET) 74 75 #define RK817_RAMP_RATE_OFFSET 6 76 #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET) 77 #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET) 78 #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET) 79 #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET) 80 #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET) 81 82 struct rk8xx_reg_info { 83 uint min_uv; 84 uint step_uv; 85 u8 vsel_reg; 86 u8 vsel_sleep_reg; 87 u8 config_reg; 88 u8 vsel_mask; 89 u8 min_sel; 90 }; 91 92 static const struct rk8xx_reg_info rk808_buck[] = { 93 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, }, 94 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, }, 95 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK808_BUCK_VSEL_MASK, }, 96 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, }, 97 }; 98 99 static const struct rk8xx_reg_info rk816_buck[] = { 100 /* buck 1 */ 101 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, }, 102 { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, }, 103 { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, }, 104 /* buck 2 */ 105 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, }, 106 { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, }, 107 { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, }, 108 /* buck 3 */ 109 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, }, 110 /* buck 4 */ 111 { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, }, 112 }; 113 114 static const struct rk8xx_reg_info rk809_buck5[] = { 115 /* buck 5 */ 116 { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, }, 117 { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, }, 118 { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, }, 119 { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, }, 120 }; 121 122 static const struct rk8xx_reg_info rk817_buck[] = { 123 /* buck 1 */ 124 { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, }, 125 { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, }, 126 { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, }, 127 /* buck 2 */ 128 { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, }, 129 { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, }, 130 { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, }, 131 /* buck 3 */ 132 { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, }, 133 { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, }, 134 { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, }, 135 /* buck 4 */ 136 { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, }, 137 { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, }, 138 { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, }, 139 }; 140 141 static const struct rk8xx_reg_info rk818_buck[] = { 142 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, }, 143 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, }, 144 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, }, 145 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, }, 146 }; 147 148 #ifdef ENABLE_DRIVER 149 static const struct rk8xx_reg_info rk808_ldo[] = { 150 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 151 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 152 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK808_BUCK4_VSEL_MASK, }, 153 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 154 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 155 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 156 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 157 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 158 }; 159 160 static const struct rk8xx_reg_info rk816_ldo[] = { 161 { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 162 { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 163 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 164 { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 165 { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 166 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 167 }; 168 169 static const struct rk8xx_reg_info rk817_ldo[] = { 170 /* ldo1 */ 171 { 600000, 25000, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x00, }, 172 { 3400000, 0, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x70, }, 173 /* ldo2 */ 174 { 600000, 25000, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x00, }, 175 { 3400000, 0, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x70, }, 176 /* ldo3 */ 177 { 600000, 25000, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x00, }, 178 { 3400000, 0, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x70, }, 179 /* ldo4 */ 180 { 600000, 25000, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x00, }, 181 { 3400000, 0, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x70, }, 182 /* ldo5 */ 183 { 600000, 25000, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x00, }, 184 { 3400000, 0, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x70, }, 185 /* ldo6 */ 186 { 600000, 25000, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x00, }, 187 { 3400000, 0, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x70, }, 188 /* ldo7 */ 189 { 600000, 25000, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x00, }, 190 { 3400000, 0, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x70, }, 191 /* ldo8 */ 192 { 600000, 25000, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x00, }, 193 { 3400000, 0, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x70, }, 194 /* ldo9 */ 195 { 600000, 25000, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x00, }, 196 { 3400000, 0, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x70, }, 197 }; 198 199 static const struct rk8xx_reg_info rk818_ldo[] = { 200 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 201 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 202 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO3_ON_VSEL_MASK, }, 203 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 204 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 205 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 206 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 207 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 208 }; 209 #endif 210 211 static const u16 rk818_chrg_cur_input_array[] = { 212 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 213 }; 214 215 static const uint rk818_chrg_shutdown_vsel_array[] = { 216 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000 217 }; 218 219 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, 220 int num, int uvolt) 221 { 222 struct rk8xx_priv *priv = dev_get_priv(pmic); 223 224 switch (priv->variant) { 225 case RK805_ID: 226 case RK816_ID: 227 switch (num) { 228 case 0: 229 case 1: 230 if (uvolt <= 1450000) 231 return &rk816_buck[num * 3 + 0]; 232 else if (uvolt <= 2200000) 233 return &rk816_buck[num * 3 + 1]; 234 else 235 return &rk816_buck[num * 3 + 2]; 236 default: 237 return &rk816_buck[num + 4]; 238 } 239 240 case RK809_ID: 241 case RK817_ID: 242 switch (num) { 243 case 0 ... 2: 244 if (uvolt < 1500000) 245 return &rk817_buck[num * 3 + 0]; 246 else if (uvolt < 2400000) 247 return &rk817_buck[num * 3 + 1]; 248 else 249 return &rk817_buck[num * 3 + 2]; 250 case 3: 251 if (uvolt < 1500000) 252 return &rk817_buck[num * 3 + 0]; 253 else if (uvolt < 3400000) 254 return &rk817_buck[num * 3 + 1]; 255 else 256 return &rk817_buck[num * 3 + 2]; 257 /* BUCK5 for RK809 */ 258 default: 259 if (uvolt < 1800000) 260 return &rk809_buck5[0]; 261 else if (uvolt < 2800000) 262 return &rk809_buck5[1]; 263 else if (uvolt < 3300000) 264 return &rk809_buck5[2]; 265 else 266 return &rk809_buck5[3]; 267 } 268 case RK818_ID: 269 return &rk818_buck[num]; 270 default: 271 return &rk808_buck[num]; 272 } 273 } 274 275 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt) 276 { 277 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 278 int mask = info->vsel_mask; 279 int val; 280 281 if (info->vsel_reg == NA) 282 return -ENOSYS; 283 284 if (info->step_uv == 0) /* Fixed voltage */ 285 val = info->min_sel; 286 else 287 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 288 289 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 290 __func__, uvolt, buck+1, info->vsel_reg, mask, val); 291 292 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); 293 } 294 295 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) 296 { 297 uint mask, value, en_reg; 298 int ret; 299 struct rk8xx_priv *priv = dev_get_priv(pmic); 300 301 switch (priv->variant) { 302 case RK805_ID: 303 case RK816_ID: 304 if (buck >= 4) { 305 buck -= 4; 306 en_reg = RK816_REG_DCDC_EN2; 307 } else { 308 en_reg = RK816_REG_DCDC_EN1; 309 } 310 if (enable) 311 value = ((1 << buck) | (1 << (buck + 4))); 312 else 313 value = ((0 << buck) | (1 << (buck + 4))); 314 ret = pmic_reg_write(pmic, en_reg, value); 315 break; 316 317 case RK808_ID: 318 case RK818_ID: 319 mask = 1 << buck; 320 if (enable) { 321 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 322 0, 3 << (buck * 2)); 323 if (ret) 324 return ret; 325 ret = pmic_clrsetbits(pmic, REG_DCDC_UV_ACT, 326 1 << buck, 0); 327 if (ret) 328 return ret; 329 } 330 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask, 331 enable ? mask : 0); 332 break; 333 case RK809_ID: 334 case RK817_ID: 335 if (buck < 4) { 336 if (enable) 337 value = ((1 << buck) | (1 << (buck + 4))); 338 else 339 value = ((0 << buck) | (1 << (buck + 4))); 340 ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value); 341 /* BUCK5 for RK809 */ 342 } else { 343 if (enable) 344 value = ((1 << 1) | (1 << 5)); 345 else 346 value = ((0 << 1) | (1 << 5)); 347 ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value); 348 } 349 break; 350 default: 351 ret = -EINVAL; 352 } 353 354 return ret; 355 } 356 357 #ifdef ENABLE_DRIVER 358 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt) 359 { 360 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 361 int mask = info->vsel_mask; 362 int val; 363 364 if (info->vsel_sleep_reg == NA) 365 return -ENOSYS; 366 367 if (info->step_uv == 0) 368 val = info->min_sel; 369 else 370 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 371 372 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 373 __func__, uvolt, buck+1, info->vsel_sleep_reg, mask, val); 374 375 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); 376 } 377 378 static int _buck_get_enable(struct udevice *pmic, int buck) 379 { 380 struct rk8xx_priv *priv = dev_get_priv(pmic); 381 uint mask = 0; 382 int ret = 0; 383 384 switch (priv->variant) { 385 case RK805_ID: 386 case RK816_ID: 387 if (buck >= 4) { 388 mask = 1 << (buck - 4); 389 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2); 390 } else { 391 mask = 1 << buck; 392 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1); 393 } 394 break; 395 case RK808_ID: 396 case RK818_ID: 397 mask = 1 << buck; 398 ret = pmic_reg_read(pmic, REG_DCDC_EN); 399 if (ret < 0) 400 return ret; 401 break; 402 case RK809_ID: 403 case RK817_ID: 404 if (buck < 4) { 405 mask = 1 << buck; 406 ret = pmic_reg_read(pmic, RK817_POWER_EN(0)); 407 /* BUCK5 for RK809 */ 408 } else { 409 mask = 1 << 1; 410 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 411 } 412 break; 413 } 414 415 if (ret < 0) 416 return ret; 417 418 return ret & mask ? true : false; 419 } 420 421 static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay) 422 { 423 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0); 424 struct rk8xx_priv *priv = dev_get_priv(pmic); 425 u32 ramp_value, ramp_mask; 426 427 if (info->config_reg == NA) 428 return -ENOSYS; 429 430 switch (priv->variant) { 431 case RK805_ID: 432 ramp_mask = RK805_RAMP_RATE_MASK; 433 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 434 switch (ramp_delay) { 435 case 0 ... 3000: 436 ramp_value = RK805_RAMP_RATE_3MV_PER_US; 437 break; 438 case 3001 ... 6000: 439 ramp_value = RK805_RAMP_RATE_6MV_PER_US; 440 break; 441 case 6001 ... 12500: 442 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 443 break; 444 case 12501 ... 25000: 445 ramp_value = RK805_RAMP_RATE_25MV_PER_US; 446 break; 447 default: 448 printf("buck%d ramp_delay: %d not supported\n", 449 buck, ramp_delay); 450 } 451 break; 452 case RK808_ID: 453 case RK816_ID: 454 case RK818_ID: 455 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 456 ramp_mask = RK808_RAMP_RATE_MASK; 457 switch (ramp_delay) { 458 case 1 ... 2000: 459 ramp_value = RK808_RAMP_RATE_2MV_PER_US; 460 break; 461 case 2001 ... 4000: 462 ramp_value = RK808_RAMP_RATE_4MV_PER_US; 463 break; 464 case 4001 ... 6000: 465 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 466 break; 467 case 6001 ... 10000: 468 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 469 break; 470 default: 471 printf("buck%d ramp_delay: %d not supported\n", 472 buck, ramp_delay); 473 } 474 break; 475 case RK809_ID: 476 case RK817_ID: 477 ramp_mask = RK817_RAMP_RATE_MASK; 478 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 479 switch (ramp_delay) { 480 case 0 ... 3000: 481 ramp_value = RK817_RAMP_RATE_3MV_PER_US; 482 break; 483 case 3001 ... 6300: 484 ramp_value = RK817_RAMP_RATE_6_3MV_PER_US; 485 break; 486 case 6301 ... 12500: 487 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 488 break; 489 case 12501 ... 25000: 490 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 491 break; 492 default: 493 printf("buck%d ramp_delay: %d not supported\n", 494 buck, ramp_delay); 495 } 496 break; 497 default: 498 return -EINVAL; 499 } 500 501 return pmic_clrsetbits(pmic, info->config_reg, ramp_mask, ramp_value); 502 } 503 504 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) 505 { 506 uint mask; 507 int ret; 508 struct rk8xx_priv *priv = dev_get_priv(pmic); 509 510 switch (priv->variant) { 511 case RK805_ID: 512 case RK816_ID: 513 mask = 1 << buck; 514 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask, 515 enable ? mask : 0); 516 break; 517 case RK808_ID: 518 case RK818_ID: 519 mask = 1 << buck; 520 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask, 521 enable ? 0 : mask); 522 break; 523 case RK809_ID: 524 case RK817_ID: 525 if (buck < 4) 526 mask = 1 << buck; 527 else 528 mask = 1 << 5; /* BUCK5 for RK809 */ 529 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 530 enable ? mask : 0); 531 break; 532 default: 533 ret = -EINVAL; 534 } 535 536 return ret; 537 } 538 539 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, 540 int num, int uvolt) 541 { 542 struct rk8xx_priv *priv = dev_get_priv(pmic); 543 544 switch (priv->variant) { 545 case RK805_ID: 546 case RK816_ID: 547 return &rk816_ldo[num]; 548 case RK809_ID: 549 case RK817_ID: 550 if (uvolt < 3400000) 551 return &rk817_ldo[num * 2 + 0]; 552 else 553 return &rk817_ldo[num * 2 + 1]; 554 case RK818_ID: 555 return &rk818_ldo[num]; 556 default: 557 return &rk808_ldo[num]; 558 } 559 } 560 561 static int _ldo_get_enable(struct udevice *pmic, int ldo) 562 { 563 struct rk8xx_priv *priv = dev_get_priv(pmic); 564 uint mask = 0; 565 int ret = 0; 566 567 switch (priv->variant) { 568 case RK805_ID: 569 case RK816_ID: 570 if (ldo >= 4) { 571 mask = 1 << (ldo - 4); 572 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2); 573 } else { 574 mask = 1 << ldo; 575 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1); 576 } 577 break; 578 case RK808_ID: 579 case RK818_ID: 580 mask = 1 << ldo; 581 ret = pmic_reg_read(pmic, REG_LDO_EN); 582 if (ret < 0) 583 return ret; 584 break; 585 case RK809_ID: 586 case RK817_ID: 587 if (ldo < 4) { 588 mask = 1 << ldo; 589 ret = pmic_reg_read(pmic, RK817_POWER_EN(1)); 590 } else if (ldo < 8) { 591 mask = 1 << (ldo - 4); 592 ret = pmic_reg_read(pmic, RK817_POWER_EN(2)); 593 } else if (ldo == 8) { 594 mask = 1 << 0; 595 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 596 } else { 597 return false; 598 } 599 break; 600 } 601 602 if (ret < 0) 603 return ret; 604 605 return ret & mask ? true : false; 606 } 607 608 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable) 609 { 610 struct rk8xx_priv *priv = dev_get_priv(pmic); 611 uint mask, value, en_reg; 612 int ret = 0; 613 614 switch (priv->variant) { 615 case RK805_ID: 616 case RK816_ID: 617 if (ldo >= 4) { 618 ldo -= 4; 619 en_reg = RK816_REG_LDO_EN2; 620 } else { 621 en_reg = RK816_REG_LDO_EN1; 622 } 623 if (enable) 624 value = ((1 << ldo) | (1 << (ldo + 4))); 625 else 626 value = ((0 << ldo) | (1 << (ldo + 4))); 627 628 ret = pmic_reg_write(pmic, en_reg, value); 629 break; 630 case RK808_ID: 631 case RK818_ID: 632 mask = 1 << ldo; 633 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask, 634 enable ? mask : 0); 635 break; 636 case RK809_ID: 637 case RK817_ID: 638 if (ldo < 4) { 639 en_reg = RK817_POWER_EN(1); 640 } else if (ldo < 8) { 641 ldo -= 4; 642 en_reg = RK817_POWER_EN(2); 643 } else if (ldo == 8) { 644 ldo = 0; /* BIT 0 */ 645 en_reg = RK817_POWER_EN(3); 646 } else { 647 return -EINVAL; 648 } 649 if (enable) 650 value = ((1 << ldo) | (1 << (ldo + 4))); 651 else 652 value = ((0 << ldo) | (1 << (ldo + 4))); 653 ret = pmic_reg_write(pmic, en_reg, value); 654 break; 655 } 656 657 return ret; 658 } 659 660 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable) 661 { 662 struct rk8xx_priv *priv = dev_get_priv(pmic); 663 uint mask; 664 int ret = 0; 665 666 switch (priv->variant) { 667 case RK805_ID: 668 case RK816_ID: 669 mask = 1 << ldo; 670 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask, 671 enable ? mask : 0); 672 break; 673 case RK808_ID: 674 case RK818_ID: 675 mask = 1 << ldo; 676 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask, 677 enable ? 0 : mask); 678 break; 679 case RK809_ID: 680 case RK817_ID: 681 if (ldo == 8) { 682 mask = 1 << 4; /* LDO9 */ 683 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 684 enable ? mask : 0); 685 } else { 686 mask = 1 << ldo; 687 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask, 688 enable ? mask : 0); 689 } 690 break; 691 } 692 693 return ret; 694 } 695 696 static int buck_get_value(struct udevice *dev) 697 { 698 int buck = dev->driver_data - 1; 699 /* We assume level-1 voltage is enough for usage in U-Boot */ 700 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 701 int mask = info->vsel_mask; 702 int ret, val; 703 704 if (info->vsel_reg == NA) 705 return -ENOSYS; 706 707 ret = pmic_reg_read(dev->parent, info->vsel_reg); 708 if (ret < 0) 709 return ret; 710 val = ret & mask; 711 712 return info->min_uv + val * info->step_uv; 713 } 714 715 static int buck_set_value(struct udevice *dev, int uvolt) 716 { 717 int buck = dev->driver_data - 1; 718 719 return _buck_set_value(dev->parent, buck, uvolt); 720 } 721 722 static int buck_set_suspend_value(struct udevice *dev, int uvolt) 723 { 724 int buck = dev->driver_data - 1; 725 726 return _buck_set_suspend_value(dev->parent, buck, uvolt); 727 } 728 729 static int buck_set_enable(struct udevice *dev, bool enable) 730 { 731 int buck = dev->driver_data - 1; 732 733 return _buck_set_enable(dev->parent, buck, enable); 734 } 735 736 static int buck_set_suspend_enable(struct udevice *dev, bool enable) 737 { 738 int buck = dev->driver_data - 1; 739 740 return _buck_set_suspend_enable(dev->parent, buck, enable); 741 } 742 743 static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay) 744 { 745 int buck = dev->driver_data - 1; 746 747 return _buck_set_ramp_delay(dev->parent, buck, ramp_delay); 748 } 749 750 static int buck_get_enable(struct udevice *dev) 751 { 752 int buck = dev->driver_data - 1; 753 754 return _buck_get_enable(dev->parent, buck); 755 } 756 757 static int ldo_get_value(struct udevice *dev) 758 { 759 int ldo = dev->driver_data - 1; 760 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); 761 int mask = info->vsel_mask; 762 int ret, val; 763 764 if (info->vsel_reg == NA) 765 return -ENOSYS; 766 ret = pmic_reg_read(dev->parent, info->vsel_reg); 767 if (ret < 0) 768 return ret; 769 val = ret & mask; 770 771 return info->min_uv + val * info->step_uv; 772 } 773 774 static int ldo_set_value(struct udevice *dev, int uvolt) 775 { 776 int ldo = dev->driver_data - 1; 777 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 778 int mask = info->vsel_mask; 779 int val; 780 781 if (info->vsel_reg == NA) 782 return -ENOSYS; 783 784 if (info->step_uv == 0) 785 val = info->min_sel; 786 else 787 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 788 789 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 790 __func__, uvolt, ldo+1, info->vsel_reg, mask, val); 791 792 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); 793 } 794 795 static int ldo_set_suspend_value(struct udevice *dev, int uvolt) 796 { 797 int ldo = dev->driver_data - 1; 798 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 799 int mask = info->vsel_mask; 800 int val; 801 802 if (info->vsel_sleep_reg == NA) 803 return -ENOSYS; 804 805 if (info->step_uv == 0) 806 val = info->min_sel; 807 else 808 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 809 810 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 811 __func__, uvolt, ldo+1, info->vsel_sleep_reg, mask, val); 812 813 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); 814 } 815 816 static int ldo_set_enable(struct udevice *dev, bool enable) 817 { 818 int ldo = dev->driver_data - 1; 819 820 return _ldo_set_enable(dev->parent, ldo, enable); 821 } 822 823 static int ldo_set_suspend_enable(struct udevice *dev, bool enable) 824 { 825 int ldo = dev->driver_data - 1; 826 827 return _ldo_set_suspend_enable(dev->parent, ldo, enable); 828 } 829 830 static int ldo_get_enable(struct udevice *dev) 831 { 832 int ldo = dev->driver_data - 1; 833 834 return _ldo_get_enable(dev->parent, ldo); 835 } 836 837 static int switch_set_enable(struct udevice *dev, bool enable) 838 { 839 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 840 int ret = 0, sw = dev->driver_data - 1; 841 uint mask = 0; 842 843 switch (priv->variant) { 844 case RK808_ID: 845 mask = 1 << (sw + 5); 846 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 847 enable ? mask : 0); 848 break; 849 case RK809_ID: 850 mask = (1 << (sw + 2)) | (1 << (sw + 6)); 851 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask, 852 enable ? mask : 0); 853 break; 854 case RK818_ID: 855 mask = 1 << 6; 856 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 857 enable ? mask : 0); 858 break; 859 } 860 861 debug("%s: switch%d, enable=%d, mask=0x%x\n", 862 __func__, sw + 1, enable, mask); 863 864 return ret; 865 } 866 867 static int switch_get_enable(struct udevice *dev) 868 { 869 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 870 int ret = 0, sw = dev->driver_data - 1; 871 uint mask = 0; 872 873 switch (priv->variant) { 874 case RK808_ID: 875 mask = 1 << (sw + 5); 876 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 877 break; 878 case RK809_ID: 879 mask = 1 << (sw + 2); 880 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3)); 881 break; 882 case RK818_ID: 883 mask = 1 << 6; 884 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 885 break; 886 } 887 888 if (ret < 0) 889 return ret; 890 891 return ret & mask ? true : false; 892 } 893 894 static int switch_set_suspend_value(struct udevice *dev, int uvolt) 895 { 896 return 0; 897 } 898 899 static int switch_set_suspend_enable(struct udevice *dev, bool enable) 900 { 901 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 902 int ret = 0, sw = dev->driver_data - 1; 903 uint mask = 0; 904 905 switch (priv->variant) { 906 case RK808_ID: 907 mask = 1 << (sw + 5); 908 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 909 enable ? 0 : mask); 910 break; 911 case RK809_ID: 912 mask = 1 << (sw + 6); 913 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask, 914 enable ? mask : 0); 915 break; 916 case RK818_ID: 917 mask = 1 << 6; 918 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 919 enable ? 0 : mask); 920 break; 921 } 922 923 debug("%s: switch%d, enable=%d, mask=0x%x\n", 924 __func__, sw + 1, enable, mask); 925 926 return ret; 927 } 928 929 static int rk8xx_buck_probe(struct udevice *dev) 930 { 931 struct dm_regulator_uclass_platdata *uc_pdata; 932 933 uc_pdata = dev_get_uclass_platdata(dev); 934 935 uc_pdata->type = REGULATOR_TYPE_BUCK; 936 uc_pdata->mode_count = 0; 937 938 return 0; 939 } 940 941 static int rk8xx_ldo_probe(struct udevice *dev) 942 { 943 struct dm_regulator_uclass_platdata *uc_pdata; 944 945 uc_pdata = dev_get_uclass_platdata(dev); 946 947 uc_pdata->type = REGULATOR_TYPE_LDO; 948 uc_pdata->mode_count = 0; 949 950 return 0; 951 } 952 953 static int rk8xx_switch_probe(struct udevice *dev) 954 { 955 struct dm_regulator_uclass_platdata *uc_pdata; 956 957 uc_pdata = dev_get_uclass_platdata(dev); 958 959 uc_pdata->type = REGULATOR_TYPE_FIXED; 960 uc_pdata->mode_count = 0; 961 962 return 0; 963 } 964 965 static const struct dm_regulator_ops rk8xx_buck_ops = { 966 .get_value = buck_get_value, 967 .set_value = buck_set_value, 968 .set_suspend_value = buck_set_suspend_value, 969 .get_enable = buck_get_enable, 970 .set_enable = buck_set_enable, 971 .set_suspend_enable = buck_set_suspend_enable, 972 .set_ramp_delay = buck_set_ramp_delay, 973 }; 974 975 static const struct dm_regulator_ops rk8xx_ldo_ops = { 976 .get_value = ldo_get_value, 977 .set_value = ldo_set_value, 978 .set_suspend_value = ldo_set_suspend_value, 979 .get_enable = ldo_get_enable, 980 .set_enable = ldo_set_enable, 981 .set_suspend_enable = ldo_set_suspend_enable, 982 }; 983 984 static const struct dm_regulator_ops rk8xx_switch_ops = { 985 .get_enable = switch_get_enable, 986 .set_enable = switch_set_enable, 987 .set_suspend_enable = switch_set_suspend_enable, 988 .set_suspend_value = switch_set_suspend_value, 989 }; 990 991 U_BOOT_DRIVER(rk8xx_buck) = { 992 .name = "rk8xx_buck", 993 .id = UCLASS_REGULATOR, 994 .ops = &rk8xx_buck_ops, 995 .probe = rk8xx_buck_probe, 996 }; 997 998 U_BOOT_DRIVER(rk8xx_ldo) = { 999 .name = "rk8xx_ldo", 1000 .id = UCLASS_REGULATOR, 1001 .ops = &rk8xx_ldo_ops, 1002 .probe = rk8xx_ldo_probe, 1003 }; 1004 1005 U_BOOT_DRIVER(rk8xx_switch) = { 1006 .name = "rk8xx_switch", 1007 .id = UCLASS_REGULATOR, 1008 .ops = &rk8xx_switch_ops, 1009 .probe = rk8xx_switch_probe, 1010 }; 1011 #endif 1012 1013 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt) 1014 { 1015 int ret; 1016 1017 ret = _buck_set_value(pmic, buck, uvolt); 1018 if (ret) 1019 return ret; 1020 1021 return _buck_set_enable(pmic, buck, true); 1022 } 1023 1024 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma) 1025 { 1026 uint i; 1027 1028 for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++) 1029 if (current_ma <= rk818_chrg_cur_input_array[i]) 1030 break; 1031 1032 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); 1033 } 1034 1035 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt) 1036 { 1037 uint i; 1038 1039 for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++) 1040 if (uvolt <= rk818_chrg_shutdown_vsel_array[i]) 1041 break; 1042 1043 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, 1044 i); 1045 } 1046