1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * Based on Rockchip's drivers/power/pmic/pmic_rk808.c: 6 * Copyright (C) 2012 rockchips 7 * zyw <zyw@rock-chips.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <log.h> 16 #include <linux/delay.h> 17 #include <power/rk8xx_pmic.h> 18 #include <power/pmic.h> 19 #include <power/regulator.h> 20 21 #ifndef CONFIG_SPL_BUILD 22 #define ENABLE_DRIVER 23 #endif 24 25 /* Not used or exisit register and configure */ 26 #define NA -1 27 28 /* Field Definitions */ 29 #define RK808_BUCK_VSEL_MASK 0x3f 30 #define RK808_BUCK4_VSEL_MASK 0xf 31 #define RK808_LDO_VSEL_MASK 0x1f 32 33 #define RK818_BUCK_VSEL_MASK 0x3f 34 #define RK818_BUCK4_VSEL_MASK 0x1f 35 #define RK818_LDO_VSEL_MASK 0x1f 36 #define RK818_LDO3_ON_VSEL_MASK 0xf 37 #define RK818_BOOST_ON_VSEL_MASK 0xe0 38 #define RK818_USB_ILIM_SEL_MASK 0x0f 39 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 40 41 /* RK809 BUCK5 */ 42 #define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1) 43 #define RK809_BUCK5_VSEL_MASK 0x07 44 45 /* RK817 BUCK */ 46 #define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * (n - 1)) 47 #define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * (n - 1)) 48 #define RK817_BUCK_VSEL_MASK 0x7f 49 #define RK817_BUCK_CONFIG(i) (0xba + (i) * 3) 50 51 /* RK817 LDO */ 52 #define RK817_LDO_ON_VSEL(n) (0xcc + 2 * (n - 1)) 53 #define RK817_LDO_SLP_VSEL(n) (0xcd + 2 * (n - 1)) 54 #define RK817_LDO_VSEL_MASK 0x7f 55 56 /* RK817 ENABLE */ 57 #define RK817_POWER_EN(n) (0xb1 + (n)) 58 #define RK817_POWER_SLP_EN(n) (0xb5 + (n)) 59 60 /* 61 * Ramp delay 62 */ 63 #define RK805_RAMP_RATE_OFFSET 3 64 #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET) 65 #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET) 66 #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET) 67 #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET) 68 #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET) 69 70 #define RK808_RAMP_RATE_OFFSET 3 71 #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET) 72 #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET) 73 #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET) 74 #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET) 75 #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET) 76 77 #define RK817_RAMP_RATE_OFFSET 6 78 #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET) 79 #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET) 80 #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET) 81 #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET) 82 #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET) 83 84 struct rk8xx_reg_info { 85 uint min_uv; 86 uint step_uv; 87 u8 vsel_reg; 88 u8 vsel_sleep_reg; 89 u8 config_reg; 90 u8 vsel_mask; 91 u8 min_sel; 92 /* only for buck now */ 93 u8 max_sel; 94 u8 range_num; 95 }; 96 97 static const struct rk8xx_reg_info rk808_buck[] = { 98 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f, 1}, 99 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f, 1}, 100 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1}, 101 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK,0x00, 0x0f, 1}, 102 }; 103 104 static const struct rk8xx_reg_info rk816_buck[] = { 105 /* buck 1 */ 106 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b, 3}, 107 { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e, 3}, 108 { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f, 3}, 109 /* buck 2 */ 110 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b, 3}, 111 { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e, 3}, 112 { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f, 3}, 113 /* buck 3 */ 114 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1}, 115 /* buck 4 */ 116 { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK,0x00, 0x1b, 1}, 117 }; 118 119 static const struct rk8xx_reg_info rk809_buck5[] = { 120 /* buck 5 */ 121 { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, 0x00, 4}, 122 { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, 0x03, 4}, 123 { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, 0x05, 4}, 124 { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, 0x07, 4}, 125 }; 126 127 static const struct rk8xx_reg_info rk817_buck[] = { 128 /* buck 1 */ 129 { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3}, 130 { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3}, 131 { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3}, 132 /* buck 2 */ 133 { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3}, 134 { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3}, 135 { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3}, 136 /* buck 3 */ 137 { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3}, 138 { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3}, 139 { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3}, 140 /* buck 4 */ 141 { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3}, 142 { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, 0x62, 3}, 143 { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, 0x63, 3}, 144 }; 145 146 static const struct rk8xx_reg_info rk818_buck[] = { 147 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f, 1}, 148 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f, 1}, 149 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1}, 150 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK,0x00, 0x10, 1}, 151 }; 152 153 #ifdef ENABLE_DRIVER 154 static const struct rk8xx_reg_info rk808_ldo[] = { 155 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 156 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 157 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK808_BUCK4_VSEL_MASK, }, 158 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 159 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 160 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 161 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 162 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 163 }; 164 165 static const struct rk8xx_reg_info rk816_ldo[] = { 166 { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 167 { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 168 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 169 { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 170 { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 171 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 172 }; 173 174 static const struct rk8xx_reg_info rk817_ldo[] = { 175 /* ldo1 */ 176 { 600000, 25000, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x00, }, 177 { 3400000, 0, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x70, }, 178 /* ldo2 */ 179 { 600000, 25000, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x00, }, 180 { 3400000, 0, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x70, }, 181 /* ldo3 */ 182 { 600000, 25000, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x00, }, 183 { 3400000, 0, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x70, }, 184 /* ldo4 */ 185 { 600000, 25000, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x00, }, 186 { 3400000, 0, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x70, }, 187 /* ldo5 */ 188 { 600000, 25000, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x00, }, 189 { 3400000, 0, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x70, }, 190 /* ldo6 */ 191 { 600000, 25000, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x00, }, 192 { 3400000, 0, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x70, }, 193 /* ldo7 */ 194 { 600000, 25000, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x00, }, 195 { 3400000, 0, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x70, }, 196 /* ldo8 */ 197 { 600000, 25000, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x00, }, 198 { 3400000, 0, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x70, }, 199 /* ldo9 */ 200 { 600000, 25000, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x00, }, 201 { 3400000, 0, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x70, }, 202 }; 203 204 static const struct rk8xx_reg_info rk818_ldo[] = { 205 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 206 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 207 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO3_ON_VSEL_MASK, }, 208 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 209 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 210 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 211 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 212 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 213 }; 214 #endif 215 216 static const u16 rk818_chrg_cur_input_array[] = { 217 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 218 }; 219 220 static const uint rk818_chrg_shutdown_vsel_array[] = { 221 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000 222 }; 223 224 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, 225 int num, int uvolt) 226 { 227 struct rk8xx_priv *priv = dev_get_priv(pmic); 228 229 switch (priv->variant) { 230 case RK805_ID: 231 case RK816_ID: 232 switch (num) { 233 case 0: 234 case 1: 235 if (uvolt <= 1450000) 236 return &rk816_buck[num * 3 + 0]; 237 else if (uvolt <= 2200000) 238 return &rk816_buck[num * 3 + 1]; 239 else 240 return &rk816_buck[num * 3 + 2]; 241 default: 242 return &rk816_buck[num + 4]; 243 } 244 245 case RK809_ID: 246 case RK817_ID: 247 switch (num) { 248 case 0 ... 2: 249 if (uvolt < 1500000) 250 return &rk817_buck[num * 3 + 0]; 251 else if (uvolt < 2400000) 252 return &rk817_buck[num * 3 + 1]; 253 else 254 return &rk817_buck[num * 3 + 2]; 255 case 3: 256 if (uvolt < 1500000) 257 return &rk817_buck[num * 3 + 0]; 258 else if (uvolt < 3400000) 259 return &rk817_buck[num * 3 + 1]; 260 else 261 return &rk817_buck[num * 3 + 2]; 262 /* BUCK5 for RK809 */ 263 default: 264 if (uvolt < 1800000) 265 return &rk809_buck5[0]; 266 else if (uvolt < 2800000) 267 return &rk809_buck5[1]; 268 else if (uvolt < 3300000) 269 return &rk809_buck5[2]; 270 else 271 return &rk809_buck5[3]; 272 } 273 case RK818_ID: 274 return &rk818_buck[num]; 275 default: 276 return &rk808_buck[num]; 277 } 278 } 279 280 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt) 281 { 282 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 283 struct rk8xx_priv *priv = dev_get_priv(pmic); 284 int mask = info->vsel_mask; 285 int val; 286 287 if (info->vsel_reg == NA) 288 return -ENOSYS; 289 290 if (info->step_uv == 0) /* Fixed voltage */ 291 val = info->min_sel; 292 else 293 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 294 295 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 296 __func__, uvolt, buck+1, info->vsel_reg, mask, val); 297 298 if (priv->variant == RK816_ID) { 299 pmic_clrsetbits(pmic, info->vsel_reg, mask, val); 300 return pmic_clrsetbits(pmic, RK816_REG_DCDC_EN2, 1 << 7, 1 << 7); 301 } else { 302 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); 303 } 304 } 305 306 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) 307 { 308 uint mask, value, en_reg; 309 int ret; 310 struct rk8xx_priv *priv = dev_get_priv(pmic); 311 312 switch (priv->variant) { 313 case RK805_ID: 314 case RK816_ID: 315 if (buck >= 4) { 316 buck -= 4; 317 en_reg = RK816_REG_DCDC_EN2; 318 } else { 319 en_reg = RK816_REG_DCDC_EN1; 320 } 321 if (enable) 322 value = ((1 << buck) | (1 << (buck + 4))); 323 else 324 value = ((0 << buck) | (1 << (buck + 4))); 325 ret = pmic_reg_write(pmic, en_reg, value); 326 break; 327 328 case RK808_ID: 329 case RK818_ID: 330 mask = 1 << buck; 331 if (enable) { 332 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 333 0, 3 << (buck * 2)); 334 if (ret) 335 return ret; 336 } 337 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask, 338 enable ? mask : 0); 339 break; 340 case RK809_ID: 341 case RK817_ID: 342 if (buck < 4) { 343 if (enable) 344 value = ((1 << buck) | (1 << (buck + 4))); 345 else 346 value = ((0 << buck) | (1 << (buck + 4))); 347 ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value); 348 /* BUCK5 for RK809 */ 349 } else { 350 if (enable) 351 value = ((1 << 1) | (1 << 5)); 352 else 353 value = ((0 << 1) | (1 << 5)); 354 ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value); 355 } 356 break; 357 default: 358 ret = -EINVAL; 359 } 360 361 return ret; 362 } 363 364 #ifdef ENABLE_DRIVER 365 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt) 366 { 367 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 368 int mask = info->vsel_mask; 369 int val; 370 371 if (info->vsel_sleep_reg == NA) 372 return -ENOSYS; 373 374 if (info->step_uv == 0) 375 val = info->min_sel; 376 else 377 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 378 379 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 380 __func__, uvolt, buck+1, info->vsel_sleep_reg, mask, val); 381 382 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); 383 } 384 385 static int _buck_get_enable(struct udevice *pmic, int buck) 386 { 387 struct rk8xx_priv *priv = dev_get_priv(pmic); 388 uint mask = 0; 389 int ret = 0; 390 391 switch (priv->variant) { 392 case RK805_ID: 393 case RK816_ID: 394 if (buck >= 4) { 395 mask = 1 << (buck - 4); 396 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2); 397 } else { 398 mask = 1 << buck; 399 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1); 400 } 401 break; 402 case RK808_ID: 403 case RK818_ID: 404 mask = 1 << buck; 405 ret = pmic_reg_read(pmic, REG_DCDC_EN); 406 if (ret < 0) 407 return ret; 408 break; 409 case RK809_ID: 410 case RK817_ID: 411 if (buck < 4) { 412 mask = 1 << buck; 413 ret = pmic_reg_read(pmic, RK817_POWER_EN(0)); 414 /* BUCK5 for RK809 */ 415 } else { 416 mask = 1 << 1; 417 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 418 } 419 break; 420 } 421 422 if (ret < 0) 423 return ret; 424 425 return ret & mask ? true : false; 426 } 427 428 static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay) 429 { 430 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0); 431 struct rk8xx_priv *priv = dev_get_priv(pmic); 432 u32 ramp_value, ramp_mask; 433 434 if (info->config_reg == NA) 435 return -ENOSYS; 436 437 switch (priv->variant) { 438 case RK805_ID: 439 ramp_mask = RK805_RAMP_RATE_MASK; 440 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 441 switch (ramp_delay) { 442 case 0 ... 3000: 443 ramp_value = RK805_RAMP_RATE_3MV_PER_US; 444 break; 445 case 3001 ... 6000: 446 ramp_value = RK805_RAMP_RATE_6MV_PER_US; 447 break; 448 case 6001 ... 12500: 449 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 450 break; 451 case 12501 ... 25000: 452 ramp_value = RK805_RAMP_RATE_25MV_PER_US; 453 break; 454 default: 455 printf("buck%d ramp_delay: %d not supported\n", 456 buck, ramp_delay); 457 } 458 break; 459 case RK808_ID: 460 case RK816_ID: 461 case RK818_ID: 462 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 463 ramp_mask = RK808_RAMP_RATE_MASK; 464 switch (ramp_delay) { 465 case 1 ... 2000: 466 ramp_value = RK808_RAMP_RATE_2MV_PER_US; 467 break; 468 case 2001 ... 4000: 469 ramp_value = RK808_RAMP_RATE_4MV_PER_US; 470 break; 471 case 4001 ... 6000: 472 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 473 break; 474 case 6001 ... 10000: 475 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 476 break; 477 default: 478 printf("buck%d ramp_delay: %d not supported\n", 479 buck, ramp_delay); 480 } 481 break; 482 case RK809_ID: 483 case RK817_ID: 484 ramp_mask = RK817_RAMP_RATE_MASK; 485 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 486 switch (ramp_delay) { 487 case 0 ... 3000: 488 ramp_value = RK817_RAMP_RATE_3MV_PER_US; 489 break; 490 case 3001 ... 6300: 491 ramp_value = RK817_RAMP_RATE_6_3MV_PER_US; 492 break; 493 case 6301 ... 12500: 494 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 495 break; 496 case 12501 ... 25000: 497 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 498 break; 499 default: 500 printf("buck%d ramp_delay: %d not supported\n", 501 buck, ramp_delay); 502 } 503 break; 504 default: 505 return -EINVAL; 506 } 507 508 return pmic_clrsetbits(pmic, info->config_reg, ramp_mask, ramp_value); 509 } 510 511 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) 512 { 513 uint mask; 514 int ret; 515 struct rk8xx_priv *priv = dev_get_priv(pmic); 516 517 switch (priv->variant) { 518 case RK805_ID: 519 case RK816_ID: 520 mask = 1 << buck; 521 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask, 522 enable ? mask : 0); 523 break; 524 case RK808_ID: 525 case RK818_ID: 526 mask = 1 << buck; 527 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask, 528 enable ? 0 : mask); 529 break; 530 case RK809_ID: 531 case RK817_ID: 532 if (buck < 4) 533 mask = 1 << buck; 534 else 535 mask = 1 << 5; /* BUCK5 for RK809 */ 536 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 537 enable ? mask : 0); 538 break; 539 default: 540 ret = -EINVAL; 541 } 542 543 return ret; 544 } 545 546 static int _buck_get_suspend_enable(struct udevice *pmic, int buck) 547 { 548 struct rk8xx_priv *priv = dev_get_priv(pmic); 549 int ret, val; 550 uint mask; 551 552 switch (priv->variant) { 553 case RK805_ID: 554 case RK816_ID: 555 mask = 1 << buck; 556 val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN); 557 if (val < 0) 558 return val; 559 ret = val & mask ? 1 : 0; 560 break; 561 case RK808_ID: 562 case RK818_ID: 563 mask = 1 << buck; 564 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1); 565 if (val < 0) 566 return val; 567 ret = val & mask ? 0 : 1; 568 break; 569 case RK809_ID: 570 case RK817_ID: 571 if (buck < 4) 572 mask = 1 << buck; 573 else 574 mask = 1 << 5; /* BUCK5 for RK809 */ 575 576 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); 577 if (val < 0) 578 return val; 579 ret = val & mask ? 1 : 0; 580 break; 581 default: 582 ret = -EINVAL; 583 } 584 585 return ret; 586 } 587 588 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, 589 int num, int uvolt) 590 { 591 struct rk8xx_priv *priv = dev_get_priv(pmic); 592 593 switch (priv->variant) { 594 case RK805_ID: 595 case RK816_ID: 596 return &rk816_ldo[num]; 597 case RK809_ID: 598 case RK817_ID: 599 if (uvolt < 3400000) 600 return &rk817_ldo[num * 2 + 0]; 601 else 602 return &rk817_ldo[num * 2 + 1]; 603 case RK818_ID: 604 return &rk818_ldo[num]; 605 default: 606 return &rk808_ldo[num]; 607 } 608 } 609 610 static int _ldo_get_enable(struct udevice *pmic, int ldo) 611 { 612 struct rk8xx_priv *priv = dev_get_priv(pmic); 613 uint mask = 0; 614 int ret = 0; 615 616 switch (priv->variant) { 617 case RK805_ID: 618 case RK816_ID: 619 if (ldo >= 4) { 620 mask = 1 << (ldo - 4); 621 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2); 622 } else { 623 mask = 1 << ldo; 624 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1); 625 } 626 break; 627 case RK808_ID: 628 case RK818_ID: 629 mask = 1 << ldo; 630 ret = pmic_reg_read(pmic, REG_LDO_EN); 631 if (ret < 0) 632 return ret; 633 break; 634 case RK809_ID: 635 case RK817_ID: 636 if (ldo < 4) { 637 mask = 1 << ldo; 638 ret = pmic_reg_read(pmic, RK817_POWER_EN(1)); 639 } else if (ldo < 8) { 640 mask = 1 << (ldo - 4); 641 ret = pmic_reg_read(pmic, RK817_POWER_EN(2)); 642 } else if (ldo == 8) { 643 mask = 1 << 0; 644 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 645 } else { 646 return false; 647 } 648 break; 649 } 650 651 if (ret < 0) 652 return ret; 653 654 return ret & mask ? true : false; 655 } 656 657 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable) 658 { 659 struct rk8xx_priv *priv = dev_get_priv(pmic); 660 uint mask, value, en_reg; 661 int ret = 0; 662 663 switch (priv->variant) { 664 case RK805_ID: 665 case RK816_ID: 666 if (ldo >= 4) { 667 ldo -= 4; 668 en_reg = RK816_REG_LDO_EN2; 669 } else { 670 en_reg = RK816_REG_LDO_EN1; 671 } 672 if (enable) 673 value = ((1 << ldo) | (1 << (ldo + 4))); 674 else 675 value = ((0 << ldo) | (1 << (ldo + 4))); 676 677 ret = pmic_reg_write(pmic, en_reg, value); 678 break; 679 case RK808_ID: 680 case RK818_ID: 681 mask = 1 << ldo; 682 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask, 683 enable ? mask : 0); 684 break; 685 case RK809_ID: 686 case RK817_ID: 687 if (ldo < 4) { 688 en_reg = RK817_POWER_EN(1); 689 } else if (ldo < 8) { 690 ldo -= 4; 691 en_reg = RK817_POWER_EN(2); 692 } else if (ldo == 8) { 693 ldo = 0; /* BIT 0 */ 694 en_reg = RK817_POWER_EN(3); 695 } else { 696 return -EINVAL; 697 } 698 if (enable) 699 value = ((1 << ldo) | (1 << (ldo + 4))); 700 else 701 value = ((0 << ldo) | (1 << (ldo + 4))); 702 ret = pmic_reg_write(pmic, en_reg, value); 703 break; 704 } 705 706 if (enable) 707 udelay(500); 708 709 return ret; 710 } 711 712 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable) 713 { 714 struct rk8xx_priv *priv = dev_get_priv(pmic); 715 uint mask; 716 int ret = 0; 717 718 switch (priv->variant) { 719 case RK805_ID: 720 case RK816_ID: 721 mask = 1 << ldo; 722 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask, 723 enable ? mask : 0); 724 break; 725 case RK808_ID: 726 case RK818_ID: 727 mask = 1 << ldo; 728 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask, 729 enable ? 0 : mask); 730 break; 731 case RK809_ID: 732 case RK817_ID: 733 if (ldo == 8) { 734 mask = 1 << 4; /* LDO9 */ 735 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 736 enable ? mask : 0); 737 } else { 738 mask = 1 << ldo; 739 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask, 740 enable ? mask : 0); 741 } 742 break; 743 } 744 745 return ret; 746 } 747 748 static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) 749 { 750 struct rk8xx_priv *priv = dev_get_priv(pmic); 751 int val, ret = 0; 752 uint mask; 753 754 switch (priv->variant) { 755 case RK805_ID: 756 case RK816_ID: 757 mask = 1 << ldo; 758 val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN); 759 if (val < 0) 760 return val; 761 ret = val & mask ? 1 : 0; 762 break; 763 case RK808_ID: 764 case RK818_ID: 765 mask = 1 << ldo; 766 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2); 767 if (val < 0) 768 return val; 769 ret = val & mask ? 0 : 1; 770 break; 771 case RK809_ID: 772 case RK817_ID: 773 if (ldo == 8) { 774 mask = 1 << 4; /* LDO9 */ 775 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); 776 if (val < 0) 777 return val; 778 ret = val & mask ? 1 : 0; 779 } else { 780 mask = 1 << ldo; 781 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1)); 782 if (val < 0) 783 return val; 784 ret = val & mask ? 1 : 0; 785 } 786 break; 787 } 788 789 return ret; 790 } 791 792 static int buck_get_value(struct udevice *dev) 793 { 794 int buck = dev->driver_data - 1; 795 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 796 int mask = info->vsel_mask; 797 int i, ret, val; 798 799 if (info->vsel_reg == NA) 800 return -ENOSYS; 801 802 ret = pmic_reg_read(dev->parent, info->vsel_reg); 803 if (ret < 0) 804 return ret; 805 806 val = ret & mask; 807 if (val >= info->min_sel && val <= info->max_sel) 808 goto finish; 809 810 /* unlucky to try */ 811 for (i = 1; i < info->range_num; i++) { 812 info++; 813 if (val <= info->max_sel && val >= info->min_sel) 814 break; 815 } 816 817 finish: 818 return info->min_uv + (val - info->min_sel) * info->step_uv; 819 } 820 821 static int buck_set_value(struct udevice *dev, int uvolt) 822 { 823 int buck = dev->driver_data - 1; 824 825 return _buck_set_value(dev->parent, buck, uvolt); 826 } 827 828 static int buck_get_suspend_value(struct udevice *dev) 829 { 830 int buck = dev->driver_data - 1; 831 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 832 int mask = info->vsel_mask; 833 int i, ret, val; 834 835 if (info->vsel_sleep_reg == NA) 836 return -ENOSYS; 837 838 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg); 839 if (ret < 0) 840 return ret; 841 842 val = ret & mask; 843 if (val <= info->max_sel && val >= info->min_sel) 844 goto finish; 845 846 /* unlucky to try */ 847 for (i = 1; i < info->range_num; i++) { 848 info++; 849 if (val <= info->max_sel && val >= info->min_sel) 850 break; 851 } 852 853 finish: 854 return info->min_uv + (val - info->min_sel) * info->step_uv; 855 } 856 857 static int buck_set_suspend_value(struct udevice *dev, int uvolt) 858 { 859 int buck = dev->driver_data - 1; 860 861 return _buck_set_suspend_value(dev->parent, buck, uvolt); 862 } 863 864 static int buck_set_enable(struct udevice *dev, bool enable) 865 { 866 int buck = dev->driver_data - 1; 867 868 return _buck_set_enable(dev->parent, buck, enable); 869 } 870 871 static int buck_set_suspend_enable(struct udevice *dev, bool enable) 872 { 873 int buck = dev->driver_data - 1; 874 875 return _buck_set_suspend_enable(dev->parent, buck, enable); 876 } 877 878 static int buck_get_suspend_enable(struct udevice *dev) 879 { 880 int buck = dev->driver_data - 1; 881 882 return _buck_get_suspend_enable(dev->parent, buck); 883 } 884 885 static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay) 886 { 887 int buck = dev->driver_data - 1; 888 889 return _buck_set_ramp_delay(dev->parent, buck, ramp_delay); 890 } 891 892 static int buck_get_enable(struct udevice *dev) 893 { 894 int buck = dev->driver_data - 1; 895 896 return _buck_get_enable(dev->parent, buck); 897 } 898 899 static int ldo_get_value(struct udevice *dev) 900 { 901 int ldo = dev->driver_data - 1; 902 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); 903 int mask = info->vsel_mask; 904 int ret, val; 905 906 if (info->vsel_reg == NA) 907 return -ENOSYS; 908 ret = pmic_reg_read(dev->parent, info->vsel_reg); 909 if (ret < 0) 910 return ret; 911 val = ret & mask; 912 913 return info->min_uv + val * info->step_uv; 914 } 915 916 static int ldo_set_value(struct udevice *dev, int uvolt) 917 { 918 int ldo = dev->driver_data - 1; 919 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 920 int mask = info->vsel_mask; 921 int val; 922 923 if (info->vsel_reg == NA) 924 return -ENOSYS; 925 926 if (info->step_uv == 0) 927 val = info->min_sel; 928 else 929 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 930 931 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 932 __func__, uvolt, ldo+1, info->vsel_reg, mask, val); 933 934 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); 935 } 936 937 static int ldo_set_suspend_value(struct udevice *dev, int uvolt) 938 { 939 int ldo = dev->driver_data - 1; 940 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 941 int mask = info->vsel_mask; 942 int val; 943 944 if (info->vsel_sleep_reg == NA) 945 return -ENOSYS; 946 947 if (info->step_uv == 0) 948 val = info->min_sel; 949 else 950 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 951 952 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 953 __func__, uvolt, ldo+1, info->vsel_sleep_reg, mask, val); 954 955 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); 956 } 957 958 static int ldo_get_suspend_value(struct udevice *dev) 959 { 960 int ldo = dev->driver_data - 1; 961 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); 962 int mask = info->vsel_mask; 963 int val, ret; 964 965 if (info->vsel_sleep_reg == NA) 966 return -ENOSYS; 967 968 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg); 969 if (ret < 0) 970 return ret; 971 972 val = ret & mask; 973 974 return info->min_uv + val * info->step_uv; 975 } 976 977 static int ldo_set_enable(struct udevice *dev, bool enable) 978 { 979 int ldo = dev->driver_data - 1; 980 981 return _ldo_set_enable(dev->parent, ldo, enable); 982 } 983 984 static int ldo_set_suspend_enable(struct udevice *dev, bool enable) 985 { 986 int ldo = dev->driver_data - 1; 987 988 return _ldo_set_suspend_enable(dev->parent, ldo, enable); 989 } 990 991 static int ldo_get_suspend_enable(struct udevice *dev) 992 { 993 int ldo = dev->driver_data - 1; 994 995 return _ldo_get_suspend_enable(dev->parent, ldo); 996 } 997 998 static int ldo_get_enable(struct udevice *dev) 999 { 1000 int ldo = dev->driver_data - 1; 1001 1002 return _ldo_get_enable(dev->parent, ldo); 1003 } 1004 1005 static int switch_set_enable(struct udevice *dev, bool enable) 1006 { 1007 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1008 int ret = 0, sw = dev->driver_data - 1; 1009 uint mask = 0; 1010 1011 switch (priv->variant) { 1012 case RK808_ID: 1013 mask = 1 << (sw + 5); 1014 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 1015 enable ? mask : 0); 1016 break; 1017 case RK809_ID: 1018 mask = (1 << (sw + 2)) | (1 << (sw + 6)); 1019 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask, 1020 enable ? mask : (1 << (sw + 6))); 1021 break; 1022 case RK818_ID: 1023 mask = 1 << 6; 1024 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 1025 enable ? mask : 0); 1026 break; 1027 } 1028 1029 debug("%s: switch%d, enable=%d, mask=0x%x\n", 1030 __func__, sw + 1, enable, mask); 1031 1032 return ret; 1033 } 1034 1035 static int switch_get_enable(struct udevice *dev) 1036 { 1037 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1038 int ret = 0, sw = dev->driver_data - 1; 1039 uint mask = 0; 1040 1041 switch (priv->variant) { 1042 case RK808_ID: 1043 mask = 1 << (sw + 5); 1044 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 1045 break; 1046 case RK809_ID: 1047 mask = 1 << (sw + 2); 1048 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3)); 1049 break; 1050 case RK818_ID: 1051 mask = 1 << 6; 1052 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 1053 break; 1054 } 1055 1056 if (ret < 0) 1057 return ret; 1058 1059 return ret & mask ? true : false; 1060 } 1061 1062 static int switch_set_suspend_value(struct udevice *dev, int uvolt) 1063 { 1064 return 0; 1065 } 1066 1067 static int switch_get_suspend_value(struct udevice *dev) 1068 { 1069 return 0; 1070 } 1071 1072 static int switch_set_suspend_enable(struct udevice *dev, bool enable) 1073 { 1074 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1075 int ret = 0, sw = dev->driver_data - 1; 1076 uint mask = 0; 1077 1078 switch (priv->variant) { 1079 case RK808_ID: 1080 mask = 1 << (sw + 5); 1081 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 1082 enable ? 0 : mask); 1083 break; 1084 case RK809_ID: 1085 mask = 1 << (sw + 6); 1086 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask, 1087 enable ? mask : 0); 1088 break; 1089 case RK818_ID: 1090 mask = 1 << 6; 1091 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 1092 enable ? 0 : mask); 1093 break; 1094 } 1095 1096 debug("%s: switch%d, enable=%d, mask=0x%x\n", 1097 __func__, sw + 1, enable, mask); 1098 1099 return ret; 1100 } 1101 1102 static int switch_get_suspend_enable(struct udevice *dev) 1103 { 1104 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1105 int val, ret = 0, sw = dev->driver_data - 1; 1106 uint mask = 0; 1107 1108 switch (priv->variant) { 1109 case RK808_ID: 1110 mask = 1 << (sw + 5); 1111 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); 1112 if (val < 0) 1113 return val; 1114 ret = val & mask ? 0 : 1; 1115 break; 1116 case RK809_ID: 1117 mask = 1 << (sw + 6); 1118 val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0)); 1119 if (val < 0) 1120 return val; 1121 ret = val & mask ? 1 : 0; 1122 break; 1123 case RK818_ID: 1124 mask = 1 << 6; 1125 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); 1126 if (val < 0) 1127 return val; 1128 ret = val & mask ? 0 : 1; 1129 break; 1130 } 1131 1132 return ret; 1133 } 1134 1135 /* 1136 * RK8xx switch does not need to set the voltage, 1137 * but if dts set regulator-min-microvolt/regulator-max-microvolt, 1138 * will cause regulator set value fail and not to enable this switch. 1139 * So add an empty function to return success. 1140 */ 1141 static int switch_get_value(struct udevice *dev) 1142 { 1143 const char *supply_name[] = { "vcc9-supply", "vcc8-supply", }; 1144 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1145 struct udevice *supply; 1146 int id = dev->driver_data - 1; 1147 1148 if (!switch_get_enable(dev)) 1149 return 0; 1150 1151 /* note: rk817 only contains switch0 */ 1152 if ((priv->variant == RK809_ID) || (priv->variant == RK817_ID)) { 1153 if (!uclass_get_device_by_phandle(UCLASS_REGULATOR, 1154 dev_get_parent(dev), 1155 supply_name[id], 1156 &supply)) 1157 return regulator_get_value(supply); 1158 } 1159 1160 return 0; 1161 } 1162 1163 static int switch_set_value(struct udevice *dev, int uvolt) 1164 { 1165 return 0; 1166 } 1167 1168 static int rk8xx_buck_probe(struct udevice *dev) 1169 { 1170 struct dm_regulator_uclass_platdata *uc_pdata; 1171 1172 uc_pdata = dev_get_uclass_platdata(dev); 1173 1174 uc_pdata->type = REGULATOR_TYPE_BUCK; 1175 uc_pdata->mode_count = 0; 1176 1177 return 0; 1178 } 1179 1180 static int rk8xx_ldo_probe(struct udevice *dev) 1181 { 1182 struct dm_regulator_uclass_platdata *uc_pdata; 1183 1184 uc_pdata = dev_get_uclass_platdata(dev); 1185 1186 uc_pdata->type = REGULATOR_TYPE_LDO; 1187 uc_pdata->mode_count = 0; 1188 1189 return 0; 1190 } 1191 1192 static int rk8xx_switch_probe(struct udevice *dev) 1193 { 1194 struct dm_regulator_uclass_platdata *uc_pdata; 1195 1196 uc_pdata = dev_get_uclass_platdata(dev); 1197 1198 uc_pdata->type = REGULATOR_TYPE_FIXED; 1199 uc_pdata->mode_count = 0; 1200 1201 return 0; 1202 } 1203 1204 static const struct dm_regulator_ops rk8xx_buck_ops = { 1205 .get_value = buck_get_value, 1206 .set_value = buck_set_value, 1207 .set_suspend_value = buck_set_suspend_value, 1208 .get_suspend_value = buck_get_suspend_value, 1209 .get_enable = buck_get_enable, 1210 .set_enable = buck_set_enable, 1211 .set_suspend_enable = buck_set_suspend_enable, 1212 .get_suspend_enable = buck_get_suspend_enable, 1213 .set_ramp_delay = buck_set_ramp_delay, 1214 }; 1215 1216 static const struct dm_regulator_ops rk8xx_ldo_ops = { 1217 .get_value = ldo_get_value, 1218 .set_value = ldo_set_value, 1219 .set_suspend_value = ldo_set_suspend_value, 1220 .get_suspend_value = ldo_get_suspend_value, 1221 .get_enable = ldo_get_enable, 1222 .set_enable = ldo_set_enable, 1223 .set_suspend_enable = ldo_set_suspend_enable, 1224 .get_suspend_enable = ldo_get_suspend_enable, 1225 }; 1226 1227 static const struct dm_regulator_ops rk8xx_switch_ops = { 1228 .get_value = switch_get_value, 1229 .set_value = switch_set_value, 1230 .get_enable = switch_get_enable, 1231 .set_enable = switch_set_enable, 1232 .set_suspend_enable = switch_set_suspend_enable, 1233 .get_suspend_enable = switch_get_suspend_enable, 1234 .set_suspend_value = switch_set_suspend_value, 1235 .get_suspend_value = switch_get_suspend_value, 1236 }; 1237 1238 U_BOOT_DRIVER(rk8xx_buck) = { 1239 .name = "rk8xx_buck", 1240 .id = UCLASS_REGULATOR, 1241 .ops = &rk8xx_buck_ops, 1242 .probe = rk8xx_buck_probe, 1243 }; 1244 1245 U_BOOT_DRIVER(rk8xx_ldo) = { 1246 .name = "rk8xx_ldo", 1247 .id = UCLASS_REGULATOR, 1248 .ops = &rk8xx_ldo_ops, 1249 .probe = rk8xx_ldo_probe, 1250 }; 1251 1252 U_BOOT_DRIVER(rk8xx_switch) = { 1253 .name = "rk8xx_switch", 1254 .id = UCLASS_REGULATOR, 1255 .ops = &rk8xx_switch_ops, 1256 .probe = rk8xx_switch_probe, 1257 }; 1258 #endif 1259 1260 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt) 1261 { 1262 int ret; 1263 1264 ret = _buck_set_value(pmic, buck, uvolt); 1265 if (ret) 1266 return ret; 1267 1268 return _buck_set_enable(pmic, buck, true); 1269 } 1270 1271 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma) 1272 { 1273 uint i; 1274 1275 for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++) 1276 if (current_ma <= rk818_chrg_cur_input_array[i]) 1277 break; 1278 1279 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); 1280 } 1281 1282 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt) 1283 { 1284 uint i; 1285 1286 for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++) 1287 if (uvolt <= rk818_chrg_shutdown_vsel_array[i]) 1288 break; 1289 1290 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, 1291 i); 1292 } 1293