1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * Based on Rockchip's drivers/power/pmic/pmic_rk808.c: 6 * Copyright (C) 2012 rockchips 7 * zyw <zyw@rock-chips.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <power/rk8xx_pmic.h> 16 #include <power/pmic.h> 17 #include <power/regulator.h> 18 19 #ifndef CONFIG_SPL_BUILD 20 #define ENABLE_DRIVER 21 #endif 22 23 /* Not used or exisit register and configure */ 24 #define NA -1 25 26 /* Field Definitions */ 27 #define RK808_BUCK_VSEL_MASK 0x3f 28 #define RK808_BUCK4_VSEL_MASK 0xf 29 #define RK808_LDO_VSEL_MASK 0x1f 30 31 #define RK818_BUCK_VSEL_MASK 0x3f 32 #define RK818_BUCK4_VSEL_MASK 0x1f 33 #define RK818_LDO_VSEL_MASK 0x1f 34 #define RK818_LDO3_ON_VSEL_MASK 0xf 35 #define RK818_BOOST_ON_VSEL_MASK 0xe0 36 #define RK818_USB_ILIM_SEL_MASK 0x0f 37 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 38 39 /* RK809 BUCK5 */ 40 #define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1) 41 #define RK809_BUCK5_VSEL_MASK 0x07 42 43 /* RK817 BUCK */ 44 #define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * (n - 1)) 45 #define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * (n - 1)) 46 #define RK817_BUCK_VSEL_MASK 0x7f 47 #define RK817_BUCK_CONFIG(i) (0xba + (i) * 3) 48 49 /* RK817 LDO */ 50 #define RK817_LDO_ON_VSEL(n) (0xcc + 2 * (n - 1)) 51 #define RK817_LDO_SLP_VSEL(n) (0xcd + 2 * (n - 1)) 52 #define RK817_LDO_VSEL_MASK 0x7f 53 54 /* RK817 ENABLE */ 55 #define RK817_POWER_EN(n) (0xb1 + (n)) 56 #define RK817_POWER_SLP_EN(n) (0xb5 + (n)) 57 58 /* 59 * Ramp delay 60 */ 61 #define RK805_RAMP_RATE_OFFSET 3 62 #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET) 63 #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET) 64 #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET) 65 #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET) 66 #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET) 67 68 #define RK808_RAMP_RATE_OFFSET 3 69 #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET) 70 #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET) 71 #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET) 72 #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET) 73 #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET) 74 75 #define RK817_RAMP_RATE_OFFSET 6 76 #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET) 77 #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET) 78 #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET) 79 #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET) 80 #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET) 81 82 struct rk8xx_reg_info { 83 uint min_uv; 84 uint step_uv; 85 u8 vsel_reg; 86 u8 vsel_sleep_reg; 87 u8 config_reg; 88 u8 vsel_mask; 89 u8 min_sel; 90 }; 91 92 static const struct rk8xx_reg_info rk808_buck[] = { 93 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, }, 94 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, }, 95 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK808_BUCK_VSEL_MASK, }, 96 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, }, 97 }; 98 99 static const struct rk8xx_reg_info rk816_buck[] = { 100 /* buck 1 */ 101 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, }, 102 { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, }, 103 { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, }, 104 /* buck 2 */ 105 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, }, 106 { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, }, 107 { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, }, 108 /* buck 3 */ 109 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, }, 110 /* buck 4 */ 111 { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, }, 112 }; 113 114 static const struct rk8xx_reg_info rk809_buck5[] = { 115 /* buck 5 */ 116 { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, }, 117 { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, }, 118 { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, }, 119 { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, }, 120 }; 121 122 static const struct rk8xx_reg_info rk817_buck[] = { 123 /* buck 1 */ 124 { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, }, 125 { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, }, 126 { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, }, 127 /* buck 2 */ 128 { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, }, 129 { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, }, 130 { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, }, 131 /* buck 3 */ 132 { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, }, 133 { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, }, 134 { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, }, 135 /* buck 4 */ 136 { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, }, 137 { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, }, 138 { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, }, 139 }; 140 141 static const struct rk8xx_reg_info rk818_buck[] = { 142 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, }, 143 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, }, 144 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, }, 145 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, }, 146 }; 147 148 #ifdef ENABLE_DRIVER 149 static const struct rk8xx_reg_info rk808_ldo[] = { 150 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 151 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 152 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK808_BUCK4_VSEL_MASK, }, 153 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 154 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 155 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 156 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 157 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 158 }; 159 160 static const struct rk8xx_reg_info rk816_ldo[] = { 161 { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 162 { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 163 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 164 { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 165 { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 166 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 167 }; 168 169 static const struct rk8xx_reg_info rk817_ldo[] = { 170 /* ldo1 */ 171 { 600000, 25000, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x00, }, 172 { 3400000, 0, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x70, }, 173 /* ldo2 */ 174 { 600000, 25000, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x00, }, 175 { 3400000, 0, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x70, }, 176 /* ldo3 */ 177 { 600000, 25000, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x00, }, 178 { 3400000, 0, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x70, }, 179 /* ldo4 */ 180 { 600000, 25000, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x00, }, 181 { 3400000, 0, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x70, }, 182 /* ldo5 */ 183 { 600000, 25000, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x00, }, 184 { 3400000, 0, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x70, }, 185 /* ldo6 */ 186 { 600000, 25000, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x00, }, 187 { 3400000, 0, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x70, }, 188 /* ldo7 */ 189 { 600000, 25000, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x00, }, 190 { 3400000, 0, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x70, }, 191 /* ldo8 */ 192 { 600000, 25000, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x00, }, 193 { 3400000, 0, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x70, }, 194 /* ldo9 */ 195 { 600000, 25000, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x00, }, 196 { 3400000, 0, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x70, }, 197 }; 198 199 static const struct rk8xx_reg_info rk818_ldo[] = { 200 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 201 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 202 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO3_ON_VSEL_MASK, }, 203 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 204 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 205 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 206 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 207 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 208 }; 209 #endif 210 211 static const u16 rk818_chrg_cur_input_array[] = { 212 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 213 }; 214 215 static const uint rk818_chrg_shutdown_vsel_array[] = { 216 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000 217 }; 218 219 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, 220 int num, int uvolt) 221 { 222 struct rk8xx_priv *priv = dev_get_priv(pmic); 223 224 switch (priv->variant) { 225 case RK805_ID: 226 case RK816_ID: 227 switch (num) { 228 case 0: 229 case 1: 230 if (uvolt <= 1450000) 231 return &rk816_buck[num * 3 + 0]; 232 else if (uvolt <= 2200000) 233 return &rk816_buck[num * 3 + 1]; 234 else 235 return &rk816_buck[num * 3 + 2]; 236 default: 237 return &rk816_buck[num + 4]; 238 } 239 240 case RK809_ID: 241 case RK817_ID: 242 switch (num) { 243 case 0 ... 2: 244 if (uvolt < 1500000) 245 return &rk817_buck[num * 3 + 0]; 246 else if (uvolt < 2400000) 247 return &rk817_buck[num * 3 + 1]; 248 else 249 return &rk817_buck[num * 3 + 2]; 250 case 3: 251 if (uvolt < 1500000) 252 return &rk817_buck[num * 3 + 0]; 253 else if (uvolt < 3400000) 254 return &rk817_buck[num * 3 + 1]; 255 else 256 return &rk817_buck[num * 3 + 2]; 257 /* BUCK5 for RK809 */ 258 default: 259 if (uvolt < 1800000) 260 return &rk809_buck5[0]; 261 else if (uvolt < 2800000) 262 return &rk809_buck5[1]; 263 else if (uvolt < 3300000) 264 return &rk809_buck5[2]; 265 else 266 return &rk809_buck5[3]; 267 } 268 case RK818_ID: 269 return &rk818_buck[num]; 270 default: 271 return &rk808_buck[num]; 272 } 273 } 274 275 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt) 276 { 277 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 278 int mask = info->vsel_mask; 279 int val; 280 281 if (info->vsel_reg == NA) 282 return -ENOSYS; 283 284 if (info->step_uv == 0) /* Fixed voltage */ 285 val = info->min_sel; 286 else 287 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 288 289 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 290 __func__, uvolt, buck+1, info->vsel_reg, mask, val); 291 292 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); 293 } 294 295 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) 296 { 297 uint mask, value, en_reg; 298 int ret; 299 struct rk8xx_priv *priv = dev_get_priv(pmic); 300 301 switch (priv->variant) { 302 case RK805_ID: 303 case RK816_ID: 304 if (buck >= 4) { 305 buck -= 4; 306 en_reg = RK816_REG_DCDC_EN2; 307 } else { 308 en_reg = RK816_REG_DCDC_EN1; 309 } 310 if (enable) 311 value = ((1 << buck) | (1 << (buck + 4))); 312 else 313 value = ((0 << buck) | (1 << (buck + 4))); 314 ret = pmic_reg_write(pmic, en_reg, value); 315 break; 316 317 case RK808_ID: 318 case RK818_ID: 319 mask = 1 << buck; 320 if (enable) { 321 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 322 0, 3 << (buck * 2)); 323 if (ret) 324 return ret; 325 } 326 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask, 327 enable ? mask : 0); 328 break; 329 case RK809_ID: 330 case RK817_ID: 331 if (buck < 4) { 332 if (enable) 333 value = ((1 << buck) | (1 << (buck + 4))); 334 else 335 value = ((0 << buck) | (1 << (buck + 4))); 336 ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value); 337 /* BUCK5 for RK809 */ 338 } else { 339 if (enable) 340 value = ((1 << 1) | (1 << 5)); 341 else 342 value = ((0 << 1) | (1 << 5)); 343 ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value); 344 } 345 break; 346 default: 347 ret = -EINVAL; 348 } 349 350 return ret; 351 } 352 353 #ifdef ENABLE_DRIVER 354 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt) 355 { 356 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 357 int mask = info->vsel_mask; 358 int val; 359 360 if (info->vsel_sleep_reg == NA) 361 return -ENOSYS; 362 363 if (info->step_uv == 0) 364 val = info->min_sel; 365 else 366 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 367 368 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 369 __func__, uvolt, buck+1, info->vsel_sleep_reg, mask, val); 370 371 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); 372 } 373 374 static int _buck_get_enable(struct udevice *pmic, int buck) 375 { 376 struct rk8xx_priv *priv = dev_get_priv(pmic); 377 uint mask = 0; 378 int ret = 0; 379 380 switch (priv->variant) { 381 case RK805_ID: 382 case RK816_ID: 383 if (buck >= 4) { 384 mask = 1 << (buck - 4); 385 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2); 386 } else { 387 mask = 1 << buck; 388 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1); 389 } 390 break; 391 case RK808_ID: 392 case RK818_ID: 393 mask = 1 << buck; 394 ret = pmic_reg_read(pmic, REG_DCDC_EN); 395 if (ret < 0) 396 return ret; 397 break; 398 case RK809_ID: 399 case RK817_ID: 400 if (buck < 4) { 401 mask = 1 << buck; 402 ret = pmic_reg_read(pmic, RK817_POWER_EN(0)); 403 /* BUCK5 for RK809 */ 404 } else { 405 mask = 1 << 1; 406 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 407 } 408 break; 409 } 410 411 if (ret < 0) 412 return ret; 413 414 return ret & mask ? true : false; 415 } 416 417 static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay) 418 { 419 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0); 420 struct rk8xx_priv *priv = dev_get_priv(pmic); 421 u32 ramp_value, ramp_mask; 422 423 if (info->config_reg == NA) 424 return -ENOSYS; 425 426 switch (priv->variant) { 427 case RK805_ID: 428 ramp_mask = RK805_RAMP_RATE_MASK; 429 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 430 switch (ramp_delay) { 431 case 0 ... 3000: 432 ramp_value = RK805_RAMP_RATE_3MV_PER_US; 433 break; 434 case 3001 ... 6000: 435 ramp_value = RK805_RAMP_RATE_6MV_PER_US; 436 break; 437 case 6001 ... 12500: 438 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 439 break; 440 case 12501 ... 25000: 441 ramp_value = RK805_RAMP_RATE_25MV_PER_US; 442 break; 443 default: 444 printf("buck%d ramp_delay: %d not supported\n", 445 buck, ramp_delay); 446 } 447 break; 448 case RK808_ID: 449 case RK816_ID: 450 case RK818_ID: 451 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 452 ramp_mask = RK808_RAMP_RATE_MASK; 453 switch (ramp_delay) { 454 case 1 ... 2000: 455 ramp_value = RK808_RAMP_RATE_2MV_PER_US; 456 break; 457 case 2001 ... 4000: 458 ramp_value = RK808_RAMP_RATE_4MV_PER_US; 459 break; 460 case 4001 ... 6000: 461 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 462 break; 463 case 6001 ... 10000: 464 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 465 break; 466 default: 467 printf("buck%d ramp_delay: %d not supported\n", 468 buck, ramp_delay); 469 } 470 break; 471 case RK809_ID: 472 case RK817_ID: 473 ramp_mask = RK817_RAMP_RATE_MASK; 474 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 475 switch (ramp_delay) { 476 case 0 ... 3000: 477 ramp_value = RK817_RAMP_RATE_3MV_PER_US; 478 break; 479 case 3001 ... 6300: 480 ramp_value = RK817_RAMP_RATE_6_3MV_PER_US; 481 break; 482 case 6301 ... 12500: 483 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 484 break; 485 case 12501 ... 25000: 486 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 487 break; 488 default: 489 printf("buck%d ramp_delay: %d not supported\n", 490 buck, ramp_delay); 491 } 492 break; 493 default: 494 return -EINVAL; 495 } 496 497 return pmic_clrsetbits(pmic, info->config_reg, ramp_mask, ramp_value); 498 } 499 500 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) 501 { 502 uint mask; 503 int ret; 504 struct rk8xx_priv *priv = dev_get_priv(pmic); 505 506 switch (priv->variant) { 507 case RK805_ID: 508 case RK816_ID: 509 mask = 1 << buck; 510 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask, 511 enable ? mask : 0); 512 break; 513 case RK808_ID: 514 case RK818_ID: 515 mask = 1 << buck; 516 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask, 517 enable ? 0 : mask); 518 break; 519 case RK809_ID: 520 case RK817_ID: 521 if (buck < 4) 522 mask = 1 << buck; 523 else 524 mask = 1 << 5; /* BUCK5 for RK809 */ 525 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 526 enable ? mask : 0); 527 break; 528 default: 529 ret = -EINVAL; 530 } 531 532 return ret; 533 } 534 535 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, 536 int num, int uvolt) 537 { 538 struct rk8xx_priv *priv = dev_get_priv(pmic); 539 540 switch (priv->variant) { 541 case RK805_ID: 542 case RK816_ID: 543 return &rk816_ldo[num]; 544 case RK809_ID: 545 case RK817_ID: 546 if (uvolt < 3400000) 547 return &rk817_ldo[num * 2 + 0]; 548 else 549 return &rk817_ldo[num * 2 + 1]; 550 case RK818_ID: 551 return &rk818_ldo[num]; 552 default: 553 return &rk808_ldo[num]; 554 } 555 } 556 557 static int _ldo_get_enable(struct udevice *pmic, int ldo) 558 { 559 struct rk8xx_priv *priv = dev_get_priv(pmic); 560 uint mask = 0; 561 int ret = 0; 562 563 switch (priv->variant) { 564 case RK805_ID: 565 case RK816_ID: 566 if (ldo >= 4) { 567 mask = 1 << (ldo - 4); 568 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2); 569 } else { 570 mask = 1 << ldo; 571 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1); 572 } 573 break; 574 case RK808_ID: 575 case RK818_ID: 576 mask = 1 << ldo; 577 ret = pmic_reg_read(pmic, REG_LDO_EN); 578 if (ret < 0) 579 return ret; 580 break; 581 case RK809_ID: 582 case RK817_ID: 583 if (ldo < 4) { 584 mask = 1 << ldo; 585 ret = pmic_reg_read(pmic, RK817_POWER_EN(1)); 586 } else if (ldo < 8) { 587 mask = 1 << (ldo - 4); 588 ret = pmic_reg_read(pmic, RK817_POWER_EN(2)); 589 } else if (ldo == 8) { 590 mask = 1 << 0; 591 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 592 } else { 593 return false; 594 } 595 break; 596 } 597 598 if (ret < 0) 599 return ret; 600 601 return ret & mask ? true : false; 602 } 603 604 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable) 605 { 606 struct rk8xx_priv *priv = dev_get_priv(pmic); 607 uint mask, value, en_reg; 608 int ret = 0; 609 610 switch (priv->variant) { 611 case RK805_ID: 612 case RK816_ID: 613 if (ldo >= 4) { 614 ldo -= 4; 615 en_reg = RK816_REG_LDO_EN2; 616 } else { 617 en_reg = RK816_REG_LDO_EN1; 618 } 619 if (enable) 620 value = ((1 << ldo) | (1 << (ldo + 4))); 621 else 622 value = ((0 << ldo) | (1 << (ldo + 4))); 623 624 ret = pmic_reg_write(pmic, en_reg, value); 625 break; 626 case RK808_ID: 627 case RK818_ID: 628 mask = 1 << ldo; 629 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask, 630 enable ? mask : 0); 631 break; 632 case RK809_ID: 633 case RK817_ID: 634 if (ldo < 4) { 635 en_reg = RK817_POWER_EN(1); 636 } else if (ldo < 8) { 637 ldo -= 4; 638 en_reg = RK817_POWER_EN(2); 639 } else if (ldo == 8) { 640 ldo = 0; /* BIT 0 */ 641 en_reg = RK817_POWER_EN(3); 642 } else { 643 return -EINVAL; 644 } 645 if (enable) 646 value = ((1 << ldo) | (1 << (ldo + 4))); 647 else 648 value = ((0 << ldo) | (1 << (ldo + 4))); 649 ret = pmic_reg_write(pmic, en_reg, value); 650 break; 651 } 652 653 return ret; 654 } 655 656 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable) 657 { 658 struct rk8xx_priv *priv = dev_get_priv(pmic); 659 uint mask; 660 int ret = 0; 661 662 switch (priv->variant) { 663 case RK805_ID: 664 case RK816_ID: 665 mask = 1 << ldo; 666 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask, 667 enable ? mask : 0); 668 break; 669 case RK808_ID: 670 case RK818_ID: 671 mask = 1 << ldo; 672 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask, 673 enable ? 0 : mask); 674 break; 675 case RK809_ID: 676 case RK817_ID: 677 if (ldo == 8) { 678 mask = 1 << 4; /* LDO9 */ 679 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 680 enable ? mask : 0); 681 } else { 682 mask = 1 << ldo; 683 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask, 684 enable ? mask : 0); 685 } 686 break; 687 } 688 689 return ret; 690 } 691 692 static int buck_get_value(struct udevice *dev) 693 { 694 int buck = dev->driver_data - 1; 695 /* We assume level-1 voltage is enough for usage in U-Boot */ 696 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 697 int mask = info->vsel_mask; 698 int ret, val; 699 700 if (info->vsel_reg == NA) 701 return -ENOSYS; 702 703 ret = pmic_reg_read(dev->parent, info->vsel_reg); 704 if (ret < 0) 705 return ret; 706 val = ret & mask; 707 708 return info->min_uv + val * info->step_uv; 709 } 710 711 static int buck_set_value(struct udevice *dev, int uvolt) 712 { 713 int buck = dev->driver_data - 1; 714 715 return _buck_set_value(dev->parent, buck, uvolt); 716 } 717 718 static int buck_set_suspend_value(struct udevice *dev, int uvolt) 719 { 720 int buck = dev->driver_data - 1; 721 722 return _buck_set_suspend_value(dev->parent, buck, uvolt); 723 } 724 725 static int buck_set_enable(struct udevice *dev, bool enable) 726 { 727 int buck = dev->driver_data - 1; 728 729 return _buck_set_enable(dev->parent, buck, enable); 730 } 731 732 static int buck_set_suspend_enable(struct udevice *dev, bool enable) 733 { 734 int buck = dev->driver_data - 1; 735 736 return _buck_set_suspend_enable(dev->parent, buck, enable); 737 } 738 739 static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay) 740 { 741 int buck = dev->driver_data - 1; 742 743 return _buck_set_ramp_delay(dev->parent, buck, ramp_delay); 744 } 745 746 static int buck_get_enable(struct udevice *dev) 747 { 748 int buck = dev->driver_data - 1; 749 750 return _buck_get_enable(dev->parent, buck); 751 } 752 753 static int ldo_get_value(struct udevice *dev) 754 { 755 int ldo = dev->driver_data - 1; 756 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); 757 int mask = info->vsel_mask; 758 int ret, val; 759 760 if (info->vsel_reg == NA) 761 return -ENOSYS; 762 ret = pmic_reg_read(dev->parent, info->vsel_reg); 763 if (ret < 0) 764 return ret; 765 val = ret & mask; 766 767 return info->min_uv + val * info->step_uv; 768 } 769 770 static int ldo_set_value(struct udevice *dev, int uvolt) 771 { 772 int ldo = dev->driver_data - 1; 773 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 774 int mask = info->vsel_mask; 775 int val; 776 777 if (info->vsel_reg == NA) 778 return -ENOSYS; 779 780 if (info->step_uv == 0) 781 val = info->min_sel; 782 else 783 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 784 785 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 786 __func__, uvolt, ldo+1, info->vsel_reg, mask, val); 787 788 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); 789 } 790 791 static int ldo_set_suspend_value(struct udevice *dev, int uvolt) 792 { 793 int ldo = dev->driver_data - 1; 794 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 795 int mask = info->vsel_mask; 796 int val; 797 798 if (info->vsel_sleep_reg == NA) 799 return -ENOSYS; 800 801 if (info->step_uv == 0) 802 val = info->min_sel; 803 else 804 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 805 806 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 807 __func__, uvolt, ldo+1, info->vsel_sleep_reg, mask, val); 808 809 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); 810 } 811 812 static int ldo_set_enable(struct udevice *dev, bool enable) 813 { 814 int ldo = dev->driver_data - 1; 815 816 return _ldo_set_enable(dev->parent, ldo, enable); 817 } 818 819 static int ldo_set_suspend_enable(struct udevice *dev, bool enable) 820 { 821 int ldo = dev->driver_data - 1; 822 823 return _ldo_set_suspend_enable(dev->parent, ldo, enable); 824 } 825 826 static int ldo_get_enable(struct udevice *dev) 827 { 828 int ldo = dev->driver_data - 1; 829 830 return _ldo_get_enable(dev->parent, ldo); 831 } 832 833 static int switch_set_enable(struct udevice *dev, bool enable) 834 { 835 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 836 int ret = 0, sw = dev->driver_data - 1; 837 uint mask = 0; 838 839 switch (priv->variant) { 840 case RK808_ID: 841 mask = 1 << (sw + 5); 842 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 843 enable ? mask : 0); 844 break; 845 case RK809_ID: 846 mask = (1 << (sw + 2)) | (1 << (sw + 6)); 847 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask, 848 enable ? mask : 0); 849 break; 850 case RK818_ID: 851 mask = 1 << 6; 852 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 853 enable ? mask : 0); 854 break; 855 } 856 857 debug("%s: switch%d, enable=%d, mask=0x%x\n", 858 __func__, sw + 1, enable, mask); 859 860 return ret; 861 } 862 863 static int switch_get_enable(struct udevice *dev) 864 { 865 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 866 int ret = 0, sw = dev->driver_data - 1; 867 uint mask = 0; 868 869 switch (priv->variant) { 870 case RK808_ID: 871 mask = 1 << (sw + 5); 872 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 873 break; 874 case RK809_ID: 875 mask = 1 << (sw + 2); 876 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3)); 877 break; 878 case RK818_ID: 879 mask = 1 << 6; 880 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 881 break; 882 } 883 884 if (ret < 0) 885 return ret; 886 887 return ret & mask ? true : false; 888 } 889 890 static int switch_set_suspend_value(struct udevice *dev, int uvolt) 891 { 892 return 0; 893 } 894 895 static int switch_set_suspend_enable(struct udevice *dev, bool enable) 896 { 897 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 898 int ret = 0, sw = dev->driver_data - 1; 899 uint mask = 0; 900 901 switch (priv->variant) { 902 case RK808_ID: 903 mask = 1 << (sw + 5); 904 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 905 enable ? 0 : mask); 906 break; 907 case RK809_ID: 908 mask = 1 << (sw + 6); 909 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask, 910 enable ? mask : 0); 911 break; 912 case RK818_ID: 913 mask = 1 << 6; 914 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 915 enable ? 0 : mask); 916 break; 917 } 918 919 debug("%s: switch%d, enable=%d, mask=0x%x\n", 920 __func__, sw + 1, enable, mask); 921 922 return ret; 923 } 924 925 static int rk8xx_buck_probe(struct udevice *dev) 926 { 927 struct dm_regulator_uclass_platdata *uc_pdata; 928 929 uc_pdata = dev_get_uclass_platdata(dev); 930 931 uc_pdata->type = REGULATOR_TYPE_BUCK; 932 uc_pdata->mode_count = 0; 933 934 return 0; 935 } 936 937 static int rk8xx_ldo_probe(struct udevice *dev) 938 { 939 struct dm_regulator_uclass_platdata *uc_pdata; 940 941 uc_pdata = dev_get_uclass_platdata(dev); 942 943 uc_pdata->type = REGULATOR_TYPE_LDO; 944 uc_pdata->mode_count = 0; 945 946 return 0; 947 } 948 949 static int rk8xx_switch_probe(struct udevice *dev) 950 { 951 struct dm_regulator_uclass_platdata *uc_pdata; 952 953 uc_pdata = dev_get_uclass_platdata(dev); 954 955 uc_pdata->type = REGULATOR_TYPE_FIXED; 956 uc_pdata->mode_count = 0; 957 958 return 0; 959 } 960 961 static const struct dm_regulator_ops rk8xx_buck_ops = { 962 .get_value = buck_get_value, 963 .set_value = buck_set_value, 964 .set_suspend_value = buck_set_suspend_value, 965 .get_enable = buck_get_enable, 966 .set_enable = buck_set_enable, 967 .set_suspend_enable = buck_set_suspend_enable, 968 .set_ramp_delay = buck_set_ramp_delay, 969 }; 970 971 static const struct dm_regulator_ops rk8xx_ldo_ops = { 972 .get_value = ldo_get_value, 973 .set_value = ldo_set_value, 974 .set_suspend_value = ldo_set_suspend_value, 975 .get_enable = ldo_get_enable, 976 .set_enable = ldo_set_enable, 977 .set_suspend_enable = ldo_set_suspend_enable, 978 }; 979 980 static const struct dm_regulator_ops rk8xx_switch_ops = { 981 .get_enable = switch_get_enable, 982 .set_enable = switch_set_enable, 983 .set_suspend_enable = switch_set_suspend_enable, 984 .set_suspend_value = switch_set_suspend_value, 985 }; 986 987 U_BOOT_DRIVER(rk8xx_buck) = { 988 .name = "rk8xx_buck", 989 .id = UCLASS_REGULATOR, 990 .ops = &rk8xx_buck_ops, 991 .probe = rk8xx_buck_probe, 992 }; 993 994 U_BOOT_DRIVER(rk8xx_ldo) = { 995 .name = "rk8xx_ldo", 996 .id = UCLASS_REGULATOR, 997 .ops = &rk8xx_ldo_ops, 998 .probe = rk8xx_ldo_probe, 999 }; 1000 1001 U_BOOT_DRIVER(rk8xx_switch) = { 1002 .name = "rk8xx_switch", 1003 .id = UCLASS_REGULATOR, 1004 .ops = &rk8xx_switch_ops, 1005 .probe = rk8xx_switch_probe, 1006 }; 1007 #endif 1008 1009 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt) 1010 { 1011 int ret; 1012 1013 ret = _buck_set_value(pmic, buck, uvolt); 1014 if (ret) 1015 return ret; 1016 1017 return _buck_set_enable(pmic, buck, true); 1018 } 1019 1020 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma) 1021 { 1022 uint i; 1023 1024 for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++) 1025 if (current_ma <= rk818_chrg_cur_input_array[i]) 1026 break; 1027 1028 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); 1029 } 1030 1031 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt) 1032 { 1033 uint i; 1034 1035 for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++) 1036 if (uvolt <= rk818_chrg_shutdown_vsel_array[i]) 1037 break; 1038 1039 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, 1040 i); 1041 } 1042