1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * Based on Rockchip's drivers/power/pmic/pmic_rk808.c: 6 * Copyright (C) 2012 rockchips 7 * zyw <zyw@rock-chips.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <power/rk8xx_pmic.h> 16 #include <power/pmic.h> 17 #include <power/regulator.h> 18 19 #ifndef CONFIG_SPL_BUILD 20 #define ENABLE_DRIVER 21 #endif 22 23 /* Not used or exisit register and configure */ 24 #define NA -1 25 26 /* Field Definitions */ 27 #define RK808_BUCK_VSEL_MASK 0x3f 28 #define RK808_BUCK4_VSEL_MASK 0xf 29 #define RK808_LDO_VSEL_MASK 0x1f 30 31 #define RK818_BUCK_VSEL_MASK 0x3f 32 #define RK818_BUCK4_VSEL_MASK 0x1f 33 #define RK818_LDO_VSEL_MASK 0x1f 34 #define RK818_LDO3_ON_VSEL_MASK 0xf 35 #define RK818_BOOST_ON_VSEL_MASK 0xe0 36 #define RK818_USB_ILIM_SEL_MASK 0x0f 37 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 38 39 /* RK809 BUCK5 */ 40 #define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1) 41 #define RK809_BUCK5_VSEL_MASK 0x07 42 43 /* RK817 BUCK */ 44 #define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * (n - 1)) 45 #define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * (n - 1)) 46 #define RK817_BUCK_VSEL_MASK 0x7f 47 #define RK817_BUCK_CONFIG(i) (0xba + (i) * 3) 48 49 /* RK817 LDO */ 50 #define RK817_LDO_ON_VSEL(n) (0xcc + 2 * (n - 1)) 51 #define RK817_LDO_SLP_VSEL(n) (0xcd + 2 * (n - 1)) 52 #define RK817_LDO_VSEL_MASK 0x7f 53 54 /* RK817 ENABLE */ 55 #define RK817_POWER_EN(n) (0xb1 + (n)) 56 #define RK817_POWER_SLP_EN(n) (0xb5 + (n)) 57 58 /* 59 * Ramp delay 60 */ 61 #define RK805_RAMP_RATE_OFFSET 3 62 #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET) 63 #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET) 64 #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET) 65 #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET) 66 #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET) 67 68 #define RK808_RAMP_RATE_OFFSET 3 69 #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET) 70 #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET) 71 #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET) 72 #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET) 73 #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET) 74 75 #define RK817_RAMP_RATE_OFFSET 6 76 #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET) 77 #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET) 78 #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET) 79 #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET) 80 #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET) 81 82 struct rk8xx_reg_info { 83 uint min_uv; 84 uint step_uv; 85 u8 vsel_reg; 86 u8 vsel_sleep_reg; 87 u8 config_reg; 88 u8 vsel_mask; 89 u8 min_sel; 90 }; 91 92 static const struct rk8xx_reg_info rk808_buck[] = { 93 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, }, 94 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, }, 95 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK808_BUCK_VSEL_MASK, }, 96 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, }, 97 }; 98 99 static const struct rk8xx_reg_info rk816_buck[] = { 100 /* buck 1 */ 101 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, }, 102 { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, }, 103 { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, }, 104 /* buck 2 */ 105 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, }, 106 { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, }, 107 { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, }, 108 /* buck 3 */ 109 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, }, 110 /* buck 4 */ 111 { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, }, 112 }; 113 114 static const struct rk8xx_reg_info rk809_buck5[] = { 115 /* buck 5 */ 116 { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, }, 117 { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, }, 118 { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, }, 119 { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, }, 120 }; 121 122 static const struct rk8xx_reg_info rk817_buck[] = { 123 /* buck 1 */ 124 { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, }, 125 { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, }, 126 { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, }, 127 /* buck 2 */ 128 { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, }, 129 { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, }, 130 { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, }, 131 /* buck 3 */ 132 { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, }, 133 { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, }, 134 { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, }, 135 /* buck 4 */ 136 { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, }, 137 { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, }, 138 { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, }, 139 }; 140 141 static const struct rk8xx_reg_info rk818_buck[] = { 142 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, }, 143 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, }, 144 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, }, 145 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, }, 146 }; 147 148 #ifdef ENABLE_DRIVER 149 static const struct rk8xx_reg_info rk808_ldo[] = { 150 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 151 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 152 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK808_BUCK4_VSEL_MASK, }, 153 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 154 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 155 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 156 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 157 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 158 }; 159 160 static const struct rk8xx_reg_info rk816_ldo[] = { 161 { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 162 { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 163 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 164 { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 165 { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 166 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 167 }; 168 169 static const struct rk8xx_reg_info rk817_ldo[] = { 170 /* ldo1 */ 171 { 600000, 25000, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x00, }, 172 { 3400000, 0, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x70, }, 173 /* ldo2 */ 174 { 600000, 25000, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x00, }, 175 { 3400000, 0, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x70, }, 176 /* ldo3 */ 177 { 600000, 25000, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x00, }, 178 { 3400000, 0, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x70, }, 179 /* ldo4 */ 180 { 600000, 25000, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x00, }, 181 { 3400000, 0, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x70, }, 182 /* ldo5 */ 183 { 600000, 25000, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x00, }, 184 { 3400000, 0, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x70, }, 185 /* ldo6 */ 186 { 600000, 25000, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x00, }, 187 { 3400000, 0, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x70, }, 188 /* ldo7 */ 189 { 600000, 25000, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x00, }, 190 { 3400000, 0, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x70, }, 191 /* ldo8 */ 192 { 600000, 25000, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x00, }, 193 { 3400000, 0, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x70, }, 194 /* ldo9 */ 195 { 600000, 25000, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x00, }, 196 { 3400000, 0, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x70, }, 197 }; 198 199 static const struct rk8xx_reg_info rk818_ldo[] = { 200 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 201 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 202 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO3_ON_VSEL_MASK, }, 203 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 204 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 205 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 206 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 207 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 208 }; 209 #endif 210 211 static const u16 rk818_chrg_cur_input_array[] = { 212 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 213 }; 214 215 static const uint rk818_chrg_shutdown_vsel_array[] = { 216 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000 217 }; 218 219 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, 220 int num, int uvolt) 221 { 222 struct rk8xx_priv *priv = dev_get_priv(pmic); 223 224 switch (priv->variant) { 225 case RK805_ID: 226 case RK816_ID: 227 switch (num) { 228 case 0: 229 case 1: 230 if (uvolt <= 1450000) 231 return &rk816_buck[num * 3 + 0]; 232 else if (uvolt <= 2200000) 233 return &rk816_buck[num * 3 + 1]; 234 else 235 return &rk816_buck[num * 3 + 2]; 236 default: 237 return &rk816_buck[num + 4]; 238 } 239 240 case RK809_ID: 241 case RK817_ID: 242 switch (num) { 243 case 0 ... 2: 244 if (uvolt < 1500000) 245 return &rk817_buck[num * 3 + 0]; 246 else if (uvolt < 2400000) 247 return &rk817_buck[num * 3 + 1]; 248 else 249 return &rk817_buck[num * 3 + 2]; 250 case 3: 251 if (uvolt < 1500000) 252 return &rk817_buck[num * 3 + 0]; 253 else if (uvolt < 3400000) 254 return &rk817_buck[num * 3 + 1]; 255 else 256 return &rk817_buck[num * 3 + 2]; 257 /* BUCK5 for RK809 */ 258 default: 259 if (uvolt < 1800000) 260 return &rk809_buck5[0]; 261 else if (uvolt < 2800000) 262 return &rk809_buck5[1]; 263 else if (uvolt < 3300000) 264 return &rk809_buck5[2]; 265 else 266 return &rk809_buck5[3]; 267 } 268 case RK818_ID: 269 return &rk818_buck[num]; 270 default: 271 return &rk808_buck[num]; 272 } 273 } 274 275 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt) 276 { 277 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 278 int mask = info->vsel_mask; 279 int val; 280 281 if (info->vsel_reg == NA) 282 return -ENOSYS; 283 284 if (info->step_uv == 0) /* Fixed voltage */ 285 val = info->min_sel; 286 else 287 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 288 289 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 290 __func__, uvolt, buck+1, info->vsel_reg, mask, val); 291 292 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); 293 } 294 295 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) 296 { 297 uint mask, value, en_reg; 298 int ret; 299 struct rk8xx_priv *priv = dev_get_priv(pmic); 300 301 switch (priv->variant) { 302 case RK805_ID: 303 case RK816_ID: 304 if (buck >= 4) { 305 buck -= 4; 306 en_reg = RK816_REG_DCDC_EN2; 307 } else { 308 en_reg = RK816_REG_DCDC_EN1; 309 } 310 if (enable) 311 value = ((1 << buck) | (1 << (buck + 4))); 312 else 313 value = ((0 << buck) | (1 << (buck + 4))); 314 ret = pmic_reg_write(pmic, en_reg, value); 315 break; 316 317 case RK808_ID: 318 case RK818_ID: 319 mask = 1 << buck; 320 if (enable) { 321 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 322 0, 3 << (buck * 2)); 323 if (ret) 324 return ret; 325 } 326 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask, 327 enable ? mask : 0); 328 break; 329 case RK809_ID: 330 case RK817_ID: 331 if (buck < 4) { 332 if (enable) 333 value = ((1 << buck) | (1 << (buck + 4))); 334 else 335 value = ((0 << buck) | (1 << (buck + 4))); 336 ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value); 337 /* BUCK5 for RK809 */ 338 } else { 339 if (enable) 340 value = ((1 << 1) | (1 << 5)); 341 else 342 value = ((0 << 1) | (1 << 5)); 343 ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value); 344 } 345 break; 346 default: 347 ret = -EINVAL; 348 } 349 350 return ret; 351 } 352 353 #ifdef ENABLE_DRIVER 354 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt) 355 { 356 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 357 int mask = info->vsel_mask; 358 int val; 359 360 if (info->vsel_sleep_reg == NA) 361 return -ENOSYS; 362 363 if (info->step_uv == 0) 364 val = info->min_sel; 365 else 366 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 367 368 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 369 __func__, uvolt, buck+1, info->vsel_sleep_reg, mask, val); 370 371 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); 372 } 373 374 static int _buck_get_enable(struct udevice *pmic, int buck) 375 { 376 struct rk8xx_priv *priv = dev_get_priv(pmic); 377 uint mask = 0; 378 int ret = 0; 379 380 switch (priv->variant) { 381 case RK805_ID: 382 case RK816_ID: 383 if (buck >= 4) { 384 mask = 1 << (buck - 4); 385 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2); 386 } else { 387 mask = 1 << buck; 388 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1); 389 } 390 break; 391 case RK808_ID: 392 case RK818_ID: 393 mask = 1 << buck; 394 ret = pmic_reg_read(pmic, REG_DCDC_EN); 395 if (ret < 0) 396 return ret; 397 break; 398 case RK809_ID: 399 case RK817_ID: 400 if (buck < 4) { 401 mask = 1 << buck; 402 ret = pmic_reg_read(pmic, RK817_POWER_EN(0)); 403 /* BUCK5 for RK809 */ 404 } else { 405 mask = 1 << 1; 406 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 407 } 408 break; 409 } 410 411 if (ret < 0) 412 return ret; 413 414 return ret & mask ? true : false; 415 } 416 417 static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay) 418 { 419 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0); 420 struct rk8xx_priv *priv = dev_get_priv(pmic); 421 u32 ramp_value, ramp_mask; 422 423 if (info->config_reg == NA) 424 return -ENOSYS; 425 426 switch (priv->variant) { 427 case RK805_ID: 428 ramp_mask = RK805_RAMP_RATE_MASK; 429 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 430 switch (ramp_delay) { 431 case 0 ... 3000: 432 ramp_value = RK805_RAMP_RATE_3MV_PER_US; 433 break; 434 case 3001 ... 6000: 435 ramp_value = RK805_RAMP_RATE_6MV_PER_US; 436 break; 437 case 6001 ... 12500: 438 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 439 break; 440 case 12501 ... 25000: 441 ramp_value = RK805_RAMP_RATE_25MV_PER_US; 442 break; 443 default: 444 printf("buck%d ramp_delay: %d not supported\n", 445 buck, ramp_delay); 446 } 447 break; 448 case RK808_ID: 449 case RK816_ID: 450 case RK818_ID: 451 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 452 ramp_mask = RK808_RAMP_RATE_MASK; 453 switch (ramp_delay) { 454 case 1 ... 2000: 455 ramp_value = RK808_RAMP_RATE_2MV_PER_US; 456 break; 457 case 2001 ... 4000: 458 ramp_value = RK808_RAMP_RATE_4MV_PER_US; 459 break; 460 case 4001 ... 6000: 461 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 462 break; 463 case 6001 ... 10000: 464 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 465 break; 466 default: 467 printf("buck%d ramp_delay: %d not supported\n", 468 buck, ramp_delay); 469 } 470 break; 471 case RK809_ID: 472 case RK817_ID: 473 ramp_mask = RK817_RAMP_RATE_MASK; 474 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 475 switch (ramp_delay) { 476 case 0 ... 3000: 477 ramp_value = RK817_RAMP_RATE_3MV_PER_US; 478 break; 479 case 3001 ... 6300: 480 ramp_value = RK817_RAMP_RATE_6_3MV_PER_US; 481 break; 482 case 6301 ... 12500: 483 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 484 break; 485 case 12501 ... 25000: 486 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 487 break; 488 default: 489 printf("buck%d ramp_delay: %d not supported\n", 490 buck, ramp_delay); 491 } 492 break; 493 default: 494 return -EINVAL; 495 } 496 497 return pmic_clrsetbits(pmic, info->config_reg, ramp_mask, ramp_value); 498 } 499 500 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) 501 { 502 uint mask; 503 int ret; 504 struct rk8xx_priv *priv = dev_get_priv(pmic); 505 506 switch (priv->variant) { 507 case RK805_ID: 508 case RK816_ID: 509 mask = 1 << buck; 510 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask, 511 enable ? mask : 0); 512 break; 513 case RK808_ID: 514 case RK818_ID: 515 mask = 1 << buck; 516 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask, 517 enable ? 0 : mask); 518 break; 519 case RK809_ID: 520 case RK817_ID: 521 if (buck < 4) 522 mask = 1 << buck; 523 else 524 mask = 1 << 5; /* BUCK5 for RK809 */ 525 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 526 enable ? mask : 0); 527 break; 528 default: 529 ret = -EINVAL; 530 } 531 532 return ret; 533 } 534 535 static int _buck_get_suspend_enable(struct udevice *pmic, int buck) 536 { 537 struct rk8xx_priv *priv = dev_get_priv(pmic); 538 int ret, val; 539 uint mask; 540 541 switch (priv->variant) { 542 case RK805_ID: 543 case RK816_ID: 544 mask = 1 << buck; 545 val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN); 546 if (val < 0) 547 return val; 548 ret = val & mask ? 1 : 0; 549 break; 550 case RK808_ID: 551 case RK818_ID: 552 mask = 1 << buck; 553 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1); 554 if (val < 0) 555 return val; 556 ret = val & mask ? 0 : 1; 557 break; 558 case RK809_ID: 559 case RK817_ID: 560 if (buck < 4) 561 mask = 1 << buck; 562 else 563 mask = 1 << 5; /* BUCK5 for RK809 */ 564 565 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); 566 if (val < 0) 567 return val; 568 ret = val & mask ? 1 : 0; 569 break; 570 default: 571 ret = -EINVAL; 572 } 573 574 return ret; 575 } 576 577 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, 578 int num, int uvolt) 579 { 580 struct rk8xx_priv *priv = dev_get_priv(pmic); 581 582 switch (priv->variant) { 583 case RK805_ID: 584 case RK816_ID: 585 return &rk816_ldo[num]; 586 case RK809_ID: 587 case RK817_ID: 588 if (uvolt < 3400000) 589 return &rk817_ldo[num * 2 + 0]; 590 else 591 return &rk817_ldo[num * 2 + 1]; 592 case RK818_ID: 593 return &rk818_ldo[num]; 594 default: 595 return &rk808_ldo[num]; 596 } 597 } 598 599 static int _ldo_get_enable(struct udevice *pmic, int ldo) 600 { 601 struct rk8xx_priv *priv = dev_get_priv(pmic); 602 uint mask = 0; 603 int ret = 0; 604 605 switch (priv->variant) { 606 case RK805_ID: 607 case RK816_ID: 608 if (ldo >= 4) { 609 mask = 1 << (ldo - 4); 610 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2); 611 } else { 612 mask = 1 << ldo; 613 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1); 614 } 615 break; 616 case RK808_ID: 617 case RK818_ID: 618 mask = 1 << ldo; 619 ret = pmic_reg_read(pmic, REG_LDO_EN); 620 if (ret < 0) 621 return ret; 622 break; 623 case RK809_ID: 624 case RK817_ID: 625 if (ldo < 4) { 626 mask = 1 << ldo; 627 ret = pmic_reg_read(pmic, RK817_POWER_EN(1)); 628 } else if (ldo < 8) { 629 mask = 1 << (ldo - 4); 630 ret = pmic_reg_read(pmic, RK817_POWER_EN(2)); 631 } else if (ldo == 8) { 632 mask = 1 << 0; 633 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 634 } else { 635 return false; 636 } 637 break; 638 } 639 640 if (ret < 0) 641 return ret; 642 643 return ret & mask ? true : false; 644 } 645 646 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable) 647 { 648 struct rk8xx_priv *priv = dev_get_priv(pmic); 649 uint mask, value, en_reg; 650 int ret = 0; 651 652 switch (priv->variant) { 653 case RK805_ID: 654 case RK816_ID: 655 if (ldo >= 4) { 656 ldo -= 4; 657 en_reg = RK816_REG_LDO_EN2; 658 } else { 659 en_reg = RK816_REG_LDO_EN1; 660 } 661 if (enable) 662 value = ((1 << ldo) | (1 << (ldo + 4))); 663 else 664 value = ((0 << ldo) | (1 << (ldo + 4))); 665 666 ret = pmic_reg_write(pmic, en_reg, value); 667 break; 668 case RK808_ID: 669 case RK818_ID: 670 mask = 1 << ldo; 671 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask, 672 enable ? mask : 0); 673 break; 674 case RK809_ID: 675 case RK817_ID: 676 if (ldo < 4) { 677 en_reg = RK817_POWER_EN(1); 678 } else if (ldo < 8) { 679 ldo -= 4; 680 en_reg = RK817_POWER_EN(2); 681 } else if (ldo == 8) { 682 ldo = 0; /* BIT 0 */ 683 en_reg = RK817_POWER_EN(3); 684 } else { 685 return -EINVAL; 686 } 687 if (enable) 688 value = ((1 << ldo) | (1 << (ldo + 4))); 689 else 690 value = ((0 << ldo) | (1 << (ldo + 4))); 691 ret = pmic_reg_write(pmic, en_reg, value); 692 break; 693 } 694 695 return ret; 696 } 697 698 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable) 699 { 700 struct rk8xx_priv *priv = dev_get_priv(pmic); 701 uint mask; 702 int ret = 0; 703 704 switch (priv->variant) { 705 case RK805_ID: 706 case RK816_ID: 707 mask = 1 << ldo; 708 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask, 709 enable ? mask : 0); 710 break; 711 case RK808_ID: 712 case RK818_ID: 713 mask = 1 << ldo; 714 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask, 715 enable ? 0 : mask); 716 break; 717 case RK809_ID: 718 case RK817_ID: 719 if (ldo == 8) { 720 mask = 1 << 4; /* LDO9 */ 721 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 722 enable ? mask : 0); 723 } else { 724 mask = 1 << ldo; 725 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask, 726 enable ? mask : 0); 727 } 728 break; 729 } 730 731 return ret; 732 } 733 734 static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) 735 { 736 struct rk8xx_priv *priv = dev_get_priv(pmic); 737 int val, ret = 0; 738 uint mask; 739 740 switch (priv->variant) { 741 case RK805_ID: 742 case RK816_ID: 743 mask = 1 << ldo; 744 val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN); 745 if (val < 0) 746 return val; 747 ret = val & mask ? 1 : 0; 748 break; 749 case RK808_ID: 750 case RK818_ID: 751 mask = 1 << ldo; 752 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2); 753 if (val < 0) 754 return val; 755 ret = val & mask ? 0 : 1; 756 break; 757 case RK809_ID: 758 case RK817_ID: 759 if (ldo == 8) { 760 mask = 1 << 4; /* LDO9 */ 761 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); 762 if (val < 0) 763 return val; 764 ret = val & mask ? 1 : 0; 765 } else { 766 mask = 1 << ldo; 767 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1)); 768 if (val < 0) 769 return val; 770 ret = val & mask ? 1 : 0; 771 } 772 break; 773 } 774 775 return ret; 776 } 777 778 static int buck_get_value(struct udevice *dev) 779 { 780 int buck = dev->driver_data - 1; 781 /* We assume level-1 voltage is enough for usage in U-Boot */ 782 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 783 int mask = info->vsel_mask; 784 int ret, val; 785 786 if (info->vsel_reg == NA) 787 return -ENOSYS; 788 789 ret = pmic_reg_read(dev->parent, info->vsel_reg); 790 if (ret < 0) 791 return ret; 792 val = ret & mask; 793 794 return info->min_uv + val * info->step_uv; 795 } 796 797 static int buck_set_value(struct udevice *dev, int uvolt) 798 { 799 int buck = dev->driver_data - 1; 800 801 return _buck_set_value(dev->parent, buck, uvolt); 802 } 803 804 static int buck_get_suspend_value(struct udevice *dev) 805 { 806 int buck = dev->driver_data - 1; 807 /* We assume level-1 voltage is enough for usage in U-Boot */ 808 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 809 int mask = info->vsel_mask; 810 int ret, val; 811 812 if (info->vsel_sleep_reg == NA) 813 return -ENOSYS; 814 815 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg); 816 if (ret < 0) 817 return ret; 818 819 val = ret & mask; 820 821 return info->min_uv + val * info->step_uv; 822 } 823 824 static int buck_set_suspend_value(struct udevice *dev, int uvolt) 825 { 826 int buck = dev->driver_data - 1; 827 828 return _buck_set_suspend_value(dev->parent, buck, uvolt); 829 } 830 831 static int buck_set_enable(struct udevice *dev, bool enable) 832 { 833 int buck = dev->driver_data - 1; 834 835 return _buck_set_enable(dev->parent, buck, enable); 836 } 837 838 static int buck_set_suspend_enable(struct udevice *dev, bool enable) 839 { 840 int buck = dev->driver_data - 1; 841 842 return _buck_set_suspend_enable(dev->parent, buck, enable); 843 } 844 845 static int buck_get_suspend_enable(struct udevice *dev) 846 { 847 int buck = dev->driver_data - 1; 848 849 return _buck_get_suspend_enable(dev->parent, buck); 850 } 851 852 static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay) 853 { 854 int buck = dev->driver_data - 1; 855 856 return _buck_set_ramp_delay(dev->parent, buck, ramp_delay); 857 } 858 859 static int buck_get_enable(struct udevice *dev) 860 { 861 int buck = dev->driver_data - 1; 862 863 return _buck_get_enable(dev->parent, buck); 864 } 865 866 static int ldo_get_value(struct udevice *dev) 867 { 868 int ldo = dev->driver_data - 1; 869 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); 870 int mask = info->vsel_mask; 871 int ret, val; 872 873 if (info->vsel_reg == NA) 874 return -ENOSYS; 875 ret = pmic_reg_read(dev->parent, info->vsel_reg); 876 if (ret < 0) 877 return ret; 878 val = ret & mask; 879 880 return info->min_uv + val * info->step_uv; 881 } 882 883 static int ldo_set_value(struct udevice *dev, int uvolt) 884 { 885 int ldo = dev->driver_data - 1; 886 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 887 int mask = info->vsel_mask; 888 int val; 889 890 if (info->vsel_reg == NA) 891 return -ENOSYS; 892 893 if (info->step_uv == 0) 894 val = info->min_sel; 895 else 896 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 897 898 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 899 __func__, uvolt, ldo+1, info->vsel_reg, mask, val); 900 901 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); 902 } 903 904 static int ldo_set_suspend_value(struct udevice *dev, int uvolt) 905 { 906 int ldo = dev->driver_data - 1; 907 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 908 int mask = info->vsel_mask; 909 int val; 910 911 if (info->vsel_sleep_reg == NA) 912 return -ENOSYS; 913 914 if (info->step_uv == 0) 915 val = info->min_sel; 916 else 917 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 918 919 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 920 __func__, uvolt, ldo+1, info->vsel_sleep_reg, mask, val); 921 922 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); 923 } 924 925 static int ldo_get_suspend_value(struct udevice *dev) 926 { 927 int ldo = dev->driver_data - 1; 928 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); 929 int mask = info->vsel_mask; 930 int val, ret; 931 932 if (info->vsel_sleep_reg == NA) 933 return -ENOSYS; 934 935 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg); 936 if (ret < 0) 937 return ret; 938 939 val = ret & mask; 940 941 return info->min_uv + val * info->step_uv; 942 } 943 944 static int ldo_set_enable(struct udevice *dev, bool enable) 945 { 946 int ldo = dev->driver_data - 1; 947 948 return _ldo_set_enable(dev->parent, ldo, enable); 949 } 950 951 static int ldo_set_suspend_enable(struct udevice *dev, bool enable) 952 { 953 int ldo = dev->driver_data - 1; 954 955 return _ldo_set_suspend_enable(dev->parent, ldo, enable); 956 } 957 958 static int ldo_get_suspend_enable(struct udevice *dev) 959 { 960 int ldo = dev->driver_data - 1; 961 962 return _ldo_get_suspend_enable(dev->parent, ldo); 963 } 964 965 static int ldo_get_enable(struct udevice *dev) 966 { 967 int ldo = dev->driver_data - 1; 968 969 return _ldo_get_enable(dev->parent, ldo); 970 } 971 972 static int switch_set_enable(struct udevice *dev, bool enable) 973 { 974 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 975 int ret = 0, sw = dev->driver_data - 1; 976 uint mask = 0; 977 978 switch (priv->variant) { 979 case RK808_ID: 980 mask = 1 << (sw + 5); 981 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 982 enable ? mask : 0); 983 break; 984 case RK809_ID: 985 mask = (1 << (sw + 2)) | (1 << (sw + 6)); 986 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask, 987 enable ? mask : 0); 988 break; 989 case RK818_ID: 990 mask = 1 << 6; 991 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 992 enable ? mask : 0); 993 break; 994 } 995 996 debug("%s: switch%d, enable=%d, mask=0x%x\n", 997 __func__, sw + 1, enable, mask); 998 999 return ret; 1000 } 1001 1002 static int switch_get_enable(struct udevice *dev) 1003 { 1004 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1005 int ret = 0, sw = dev->driver_data - 1; 1006 uint mask = 0; 1007 1008 switch (priv->variant) { 1009 case RK808_ID: 1010 mask = 1 << (sw + 5); 1011 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 1012 break; 1013 case RK809_ID: 1014 mask = 1 << (sw + 2); 1015 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3)); 1016 break; 1017 case RK818_ID: 1018 mask = 1 << 6; 1019 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 1020 break; 1021 } 1022 1023 if (ret < 0) 1024 return ret; 1025 1026 return ret & mask ? true : false; 1027 } 1028 1029 static int switch_set_suspend_value(struct udevice *dev, int uvolt) 1030 { 1031 return 0; 1032 } 1033 1034 static int switch_get_suspend_value(struct udevice *dev) 1035 { 1036 return 0; 1037 } 1038 1039 static int switch_set_suspend_enable(struct udevice *dev, bool enable) 1040 { 1041 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1042 int ret = 0, sw = dev->driver_data - 1; 1043 uint mask = 0; 1044 1045 switch (priv->variant) { 1046 case RK808_ID: 1047 mask = 1 << (sw + 5); 1048 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 1049 enable ? 0 : mask); 1050 break; 1051 case RK809_ID: 1052 mask = 1 << (sw + 6); 1053 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask, 1054 enable ? mask : 0); 1055 break; 1056 case RK818_ID: 1057 mask = 1 << 6; 1058 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 1059 enable ? 0 : mask); 1060 break; 1061 } 1062 1063 debug("%s: switch%d, enable=%d, mask=0x%x\n", 1064 __func__, sw + 1, enable, mask); 1065 1066 return ret; 1067 } 1068 1069 static int switch_get_suspend_enable(struct udevice *dev) 1070 { 1071 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1072 int val, ret = 0, sw = dev->driver_data - 1; 1073 uint mask = 0; 1074 1075 switch (priv->variant) { 1076 case RK808_ID: 1077 mask = 1 << (sw + 5); 1078 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); 1079 if (val < 0) 1080 return val; 1081 ret = val & mask ? 0 : 1; 1082 break; 1083 case RK809_ID: 1084 mask = 1 << (sw + 6); 1085 val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0)); 1086 if (val < 0) 1087 return val; 1088 ret = val & mask ? 1 : 0; 1089 break; 1090 case RK818_ID: 1091 mask = 1 << 6; 1092 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); 1093 if (val < 0) 1094 return val; 1095 ret = val & mask ? 0 : 1; 1096 break; 1097 } 1098 1099 return ret; 1100 } 1101 1102 static int rk8xx_buck_probe(struct udevice *dev) 1103 { 1104 struct dm_regulator_uclass_platdata *uc_pdata; 1105 1106 uc_pdata = dev_get_uclass_platdata(dev); 1107 1108 uc_pdata->type = REGULATOR_TYPE_BUCK; 1109 uc_pdata->mode_count = 0; 1110 1111 return 0; 1112 } 1113 1114 static int rk8xx_ldo_probe(struct udevice *dev) 1115 { 1116 struct dm_regulator_uclass_platdata *uc_pdata; 1117 1118 uc_pdata = dev_get_uclass_platdata(dev); 1119 1120 uc_pdata->type = REGULATOR_TYPE_LDO; 1121 uc_pdata->mode_count = 0; 1122 1123 return 0; 1124 } 1125 1126 static int rk8xx_switch_probe(struct udevice *dev) 1127 { 1128 struct dm_regulator_uclass_platdata *uc_pdata; 1129 1130 uc_pdata = dev_get_uclass_platdata(dev); 1131 1132 uc_pdata->type = REGULATOR_TYPE_FIXED; 1133 uc_pdata->mode_count = 0; 1134 1135 return 0; 1136 } 1137 1138 static const struct dm_regulator_ops rk8xx_buck_ops = { 1139 .get_value = buck_get_value, 1140 .set_value = buck_set_value, 1141 .set_suspend_value = buck_set_suspend_value, 1142 .get_suspend_value = buck_get_suspend_value, 1143 .get_enable = buck_get_enable, 1144 .set_enable = buck_set_enable, 1145 .set_suspend_enable = buck_set_suspend_enable, 1146 .get_suspend_enable = buck_get_suspend_enable, 1147 .set_ramp_delay = buck_set_ramp_delay, 1148 }; 1149 1150 static const struct dm_regulator_ops rk8xx_ldo_ops = { 1151 .get_value = ldo_get_value, 1152 .set_value = ldo_set_value, 1153 .set_suspend_value = ldo_set_suspend_value, 1154 .get_suspend_value = ldo_get_suspend_value, 1155 .get_enable = ldo_get_enable, 1156 .set_enable = ldo_set_enable, 1157 .set_suspend_enable = ldo_set_suspend_enable, 1158 .get_suspend_enable = ldo_get_suspend_enable, 1159 }; 1160 1161 static const struct dm_regulator_ops rk8xx_switch_ops = { 1162 .get_enable = switch_get_enable, 1163 .set_enable = switch_set_enable, 1164 .set_suspend_enable = switch_set_suspend_enable, 1165 .get_suspend_enable = switch_get_suspend_enable, 1166 .set_suspend_value = switch_set_suspend_value, 1167 .get_suspend_value = switch_get_suspend_value, 1168 }; 1169 1170 U_BOOT_DRIVER(rk8xx_buck) = { 1171 .name = "rk8xx_buck", 1172 .id = UCLASS_REGULATOR, 1173 .ops = &rk8xx_buck_ops, 1174 .probe = rk8xx_buck_probe, 1175 }; 1176 1177 U_BOOT_DRIVER(rk8xx_ldo) = { 1178 .name = "rk8xx_ldo", 1179 .id = UCLASS_REGULATOR, 1180 .ops = &rk8xx_ldo_ops, 1181 .probe = rk8xx_ldo_probe, 1182 }; 1183 1184 U_BOOT_DRIVER(rk8xx_switch) = { 1185 .name = "rk8xx_switch", 1186 .id = UCLASS_REGULATOR, 1187 .ops = &rk8xx_switch_ops, 1188 .probe = rk8xx_switch_probe, 1189 }; 1190 #endif 1191 1192 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt) 1193 { 1194 int ret; 1195 1196 ret = _buck_set_value(pmic, buck, uvolt); 1197 if (ret) 1198 return ret; 1199 1200 return _buck_set_enable(pmic, buck, true); 1201 } 1202 1203 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma) 1204 { 1205 uint i; 1206 1207 for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++) 1208 if (current_ma <= rk818_chrg_cur_input_array[i]) 1209 break; 1210 1211 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); 1212 } 1213 1214 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt) 1215 { 1216 uint i; 1217 1218 for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++) 1219 if (uvolt <= rk818_chrg_shutdown_vsel_array[i]) 1220 break; 1221 1222 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, 1223 i); 1224 } 1225