1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * Based on Rockchip's drivers/power/pmic/pmic_rk808.c: 6 * Copyright (C) 2012 rockchips 7 * zyw <zyw@rock-chips.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <power/rk8xx_pmic.h> 16 #include <power/pmic.h> 17 #include <power/regulator.h> 18 19 #ifndef CONFIG_SPL_BUILD 20 #define ENABLE_DRIVER 21 #endif 22 23 /* Field Definitions */ 24 #define RK808_BUCK_VSEL_MASK 0x3f 25 #define RK808_BUCK4_VSEL_MASK 0xf 26 #define RK808_LDO_VSEL_MASK 0x1f 27 28 #define RK818_BUCK_VSEL_MASK 0x3f 29 #define RK818_BUCK4_VSEL_MASK 0x1f 30 #define RK818_LDO_VSEL_MASK 0x1f 31 #define RK818_LDO3_ON_VSEL_MASK 0xf 32 #define RK818_BOOST_ON_VSEL_MASK 0xe0 33 #define RK818_USB_ILIM_SEL_MASK 0x0f 34 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 35 36 struct rk8xx_reg_info { 37 uint min_uv; 38 uint step_uv; 39 s8 vsel_reg; 40 s8 vsel_sleep_reg; 41 u8 vsel_mask; 42 }; 43 44 static const struct rk8xx_reg_info rk808_buck[] = { 45 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, RK808_BUCK_VSEL_MASK, }, 46 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, RK808_BUCK_VSEL_MASK, }, 47 { 712500, 12500, -1, -1, RK808_BUCK_VSEL_MASK, }, 48 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, RK808_BUCK4_VSEL_MASK, }, 49 }; 50 51 static const struct rk8xx_reg_info rk816_buck[] = { 52 /* buck 1 */ 53 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, RK818_BUCK_VSEL_MASK, }, 54 { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, RK818_BUCK_VSEL_MASK, }, 55 { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, RK818_BUCK_VSEL_MASK, }, 56 /* buck 2 */ 57 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, RK818_BUCK_VSEL_MASK, }, 58 { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, RK818_BUCK_VSEL_MASK, }, 59 { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, RK818_BUCK_VSEL_MASK, }, 60 /* buck 3 */ 61 { 712500, 12500, -1, -1, RK818_BUCK_VSEL_MASK, }, 62 /* buck 4 */ 63 { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, RK818_BUCK4_VSEL_MASK, }, 64 }; 65 66 static const struct rk8xx_reg_info rk818_buck[] = { 67 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, RK818_BUCK_VSEL_MASK, }, 68 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, RK818_BUCK_VSEL_MASK, }, 69 { 712500, 12500, -1, -1, RK818_BUCK_VSEL_MASK, }, 70 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, RK818_BUCK4_VSEL_MASK, }, 71 }; 72 73 #ifdef ENABLE_DRIVER 74 static const struct rk8xx_reg_info rk808_ldo[] = { 75 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 76 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 77 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, RK808_BUCK4_VSEL_MASK, }, 78 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 79 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 80 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 81 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 82 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 83 }; 84 85 static const struct rk8xx_reg_info rk816_ldo[] = { 86 { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 87 { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 88 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 89 { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 90 { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 91 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 92 }; 93 94 static const struct rk8xx_reg_info rk818_ldo[] = { 95 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 96 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 97 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, RK818_LDO3_ON_VSEL_MASK, }, 98 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 99 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 100 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 101 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 102 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 103 }; 104 #endif 105 106 static const u16 rk818_chrg_cur_input_array[] = { 107 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 108 }; 109 110 static const uint rk818_chrg_shutdown_vsel_array[] = { 111 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000 112 }; 113 114 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, 115 int num, int uvolt) 116 { 117 struct rk8xx_priv *priv = dev_get_priv(pmic); 118 119 switch (priv->variant) { 120 case RK805_ID: 121 case RK816_ID: 122 switch (num) { 123 case 0: 124 case 1: 125 if (uvolt <= 1450000) 126 return &rk816_buck[num * 3 + 0]; 127 else if (uvolt <= 2200000) 128 return &rk816_buck[num * 3 + 1]; 129 else 130 return &rk816_buck[num * 3 + 2]; 131 default: 132 return &rk816_buck[num + 4]; 133 } 134 case RK818_ID: 135 return &rk818_buck[num]; 136 default: 137 return &rk808_buck[num]; 138 } 139 } 140 141 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt) 142 { 143 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 144 int mask = info->vsel_mask; 145 int val; 146 147 if (info->vsel_reg == -1) 148 return -ENOSYS; 149 val = (uvolt - info->min_uv) / info->step_uv; 150 debug("%s: reg=%x, mask=%x, val=%x\n", __func__, info->vsel_reg, mask, 151 val); 152 153 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); 154 } 155 156 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) 157 { 158 uint mask, value, en_reg; 159 int ret; 160 struct rk8xx_priv *priv = dev_get_priv(pmic); 161 162 switch (priv->variant) { 163 case RK805_ID: 164 case RK816_ID: 165 if (buck >= 4) { 166 buck -= 4; 167 en_reg = RK816_REG_DCDC_EN2; 168 } else { 169 en_reg = RK816_REG_DCDC_EN1; 170 } 171 if (enable) 172 value = ((1 << buck) | (1 << (buck + 4))); 173 else 174 value = ((0 << buck) | (1 << (buck + 4))); 175 ret = pmic_reg_write(pmic, en_reg, value); 176 break; 177 178 case RK808_ID: 179 case RK818_ID: 180 mask = 1 << buck; 181 if (enable) { 182 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 183 0, 3 << (buck * 2)); 184 if (ret) 185 return ret; 186 ret = pmic_clrsetbits(pmic, REG_DCDC_UV_ACT, 187 1 << buck, 0); 188 if (ret) 189 return ret; 190 } 191 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask, 192 enable ? mask : 0); 193 break; 194 default: 195 ret = -EINVAL; 196 } 197 198 return ret; 199 } 200 201 #ifdef ENABLE_DRIVER 202 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt) 203 { 204 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 205 int mask = info->vsel_mask; 206 int val; 207 208 if (info->vsel_sleep_reg == -1) 209 return -ENOSYS; 210 val = (uvolt - info->min_uv) / info->step_uv; 211 debug("%s: reg=%x, mask=%x, val=%x\n", __func__, info->vsel_sleep_reg, mask, 212 val); 213 214 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); 215 } 216 217 static int _buck_get_enable(struct udevice *pmic, int buck) 218 { 219 struct rk8xx_priv *priv = dev_get_priv(pmic); 220 uint mask = 0; 221 int ret = 0; 222 223 switch (priv->variant) { 224 case RK805_ID: 225 case RK816_ID: 226 if (buck >= 4) { 227 mask = 1 << (buck - 4); 228 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2); 229 } else { 230 mask = 1 << buck; 231 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1); 232 } 233 break; 234 case RK808_ID: 235 case RK818_ID: 236 mask = 1 << buck; 237 ret = pmic_reg_read(pmic, REG_DCDC_EN); 238 if (ret < 0) 239 return ret; 240 break; 241 } 242 return ret & mask ? true : false; 243 } 244 245 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) 246 { 247 uint mask; 248 int ret; 249 struct rk8xx_priv *priv = dev_get_priv(pmic); 250 251 switch (priv->variant) { 252 case RK805_ID: 253 case RK816_ID: 254 mask = 1 << buck; 255 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask, 256 enable ? mask : 0); 257 break; 258 259 case RK808_ID: 260 case RK818_ID: 261 mask = 1 << buck; 262 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask, 263 enable ? 0 : mask); 264 break; 265 default: 266 ret = -EINVAL; 267 } 268 269 return ret; 270 } 271 272 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, 273 int num) 274 { 275 struct rk8xx_priv *priv = dev_get_priv(pmic); 276 277 switch (priv->variant) { 278 case RK805_ID: 279 case RK816_ID: 280 return &rk816_ldo[num]; 281 case RK818_ID: 282 return &rk818_ldo[num]; 283 default: 284 return &rk808_ldo[num]; 285 } 286 } 287 288 static int _ldo_get_enable(struct udevice *pmic, int ldo) 289 { 290 struct rk8xx_priv *priv = dev_get_priv(pmic); 291 uint mask = 0; 292 int ret = 0; 293 294 switch (priv->variant) { 295 case RK805_ID: 296 case RK816_ID: 297 if (ldo >= 4) { 298 mask = 1 << (ldo - 4); 299 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2); 300 } else { 301 mask = 1 << ldo; 302 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1); 303 } 304 break; 305 case RK808_ID: 306 case RK818_ID: 307 mask = 1 << ldo; 308 ret = pmic_reg_read(pmic, REG_LDO_EN); 309 if (ret < 0) 310 return ret; 311 break; 312 } 313 return ret & mask ? true : false; 314 } 315 316 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable) 317 { 318 struct rk8xx_priv *priv = dev_get_priv(pmic); 319 uint mask, value, en_reg; 320 int ret = 0; 321 322 switch (priv->variant) { 323 case RK805_ID: 324 case RK816_ID: 325 if (ldo >= 4) { 326 ldo -= 4; 327 en_reg = RK816_REG_LDO_EN2; 328 } else { 329 en_reg = RK816_REG_LDO_EN1; 330 } 331 if (enable) 332 value = ((1 << ldo) | (1 << (ldo + 4))); 333 else 334 value = ((0 << ldo) | (1 << (ldo + 4))); 335 336 ret = pmic_reg_write(pmic, en_reg, value); 337 break; 338 case RK808_ID: 339 case RK818_ID: 340 mask = 1 << ldo; 341 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask, 342 enable ? mask : 0); 343 break; 344 } 345 346 return ret; 347 } 348 349 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable) 350 { 351 struct rk8xx_priv *priv = dev_get_priv(pmic); 352 uint mask; 353 int ret = 0; 354 355 switch (priv->variant) { 356 case RK805_ID: 357 case RK816_ID: 358 mask = 1 << ldo; 359 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask, 360 enable ? mask : 0); 361 break; 362 case RK808_ID: 363 case RK818_ID: 364 mask = 1 << ldo; 365 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask, 366 enable ? 0 : mask); 367 break; 368 } 369 370 return ret; 371 } 372 373 static int buck_get_value(struct udevice *dev) 374 { 375 int buck = dev->driver_data - 1; 376 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 377 int mask = info->vsel_mask; 378 int ret, val; 379 380 if (info->vsel_reg == -1) 381 return -ENOSYS; 382 ret = pmic_reg_read(dev->parent, info->vsel_reg); 383 if (ret < 0) 384 return ret; 385 val = ret & mask; 386 387 return info->min_uv + val * info->step_uv; 388 } 389 390 static int buck_set_value(struct udevice *dev, int uvolt) 391 { 392 int buck = dev->driver_data - 1; 393 394 return _buck_set_value(dev->parent, buck, uvolt); 395 } 396 397 static int buck_set_suspend_value(struct udevice *dev, int uvolt) 398 { 399 int buck = dev->driver_data - 1; 400 401 return _buck_set_suspend_value(dev->parent, buck, uvolt); 402 } 403 404 static int buck_set_enable(struct udevice *dev, bool enable) 405 { 406 int buck = dev->driver_data - 1; 407 408 return _buck_set_enable(dev->parent, buck, enable); 409 } 410 411 static int buck_set_suspend_enable(struct udevice *dev, bool enable) 412 { 413 int buck = dev->driver_data - 1; 414 415 return _buck_set_suspend_enable(dev->parent, buck, enable); 416 } 417 418 static int buck_get_enable(struct udevice *dev) 419 { 420 int buck = dev->driver_data - 1; 421 422 return _buck_get_enable(dev->parent, buck); 423 } 424 425 static int ldo_get_value(struct udevice *dev) 426 { 427 int ldo = dev->driver_data - 1; 428 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo); 429 int mask = info->vsel_mask; 430 int ret, val; 431 432 if (info->vsel_reg == -1) 433 return -ENOSYS; 434 ret = pmic_reg_read(dev->parent, info->vsel_reg); 435 if (ret < 0) 436 return ret; 437 val = ret & mask; 438 439 return info->min_uv + val * info->step_uv; 440 } 441 442 static int ldo_set_value(struct udevice *dev, int uvolt) 443 { 444 int ldo = dev->driver_data - 1; 445 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo); 446 int mask = info->vsel_mask; 447 int val; 448 449 if (info->vsel_reg == -1) 450 return -ENOSYS; 451 val = (uvolt - info->min_uv) / info->step_uv; 452 debug("%s: reg=%x, mask=%x, val=%x\n", __func__, info->vsel_reg, mask, 453 val); 454 455 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); 456 } 457 458 static int ldo_set_suspend_value(struct udevice *dev, int uvolt) 459 { 460 int ldo = dev->driver_data - 1; 461 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo); 462 int mask = info->vsel_mask; 463 int val; 464 465 if (info->vsel_sleep_reg == -1) 466 return -ENOSYS; 467 val = (uvolt - info->min_uv) / info->step_uv; 468 debug("%s: reg=%x, mask=%x, val=%x\n", __func__, info->vsel_sleep_reg, mask, 469 val); 470 471 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); 472 } 473 474 static int ldo_set_enable(struct udevice *dev, bool enable) 475 { 476 int ldo = dev->driver_data - 1; 477 478 return _ldo_set_enable(dev->parent, ldo, enable); 479 } 480 481 static int ldo_set_suspend_enable(struct udevice *dev, bool enable) 482 { 483 int ldo = dev->driver_data - 1; 484 485 return _ldo_set_suspend_enable(dev->parent, ldo, enable); 486 } 487 488 static int ldo_get_enable(struct udevice *dev) 489 { 490 int ldo = dev->driver_data - 1; 491 492 return _ldo_get_enable(dev->parent, ldo); 493 } 494 495 static int switch_set_enable(struct udevice *dev, bool enable) 496 { 497 int sw = dev->driver_data - 1; 498 uint mask; 499 500 mask = 1 << (sw + 5); 501 502 return pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 503 enable ? mask : 0); 504 } 505 506 static int switch_get_enable(struct udevice *dev) 507 { 508 int sw = dev->driver_data - 1; 509 int ret; 510 uint mask; 511 512 mask = 1 << (sw + 5); 513 514 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 515 if (ret < 0) 516 return ret; 517 518 return ret & mask ? true : false; 519 } 520 521 static int rk8xx_buck_probe(struct udevice *dev) 522 { 523 struct dm_regulator_uclass_platdata *uc_pdata; 524 525 uc_pdata = dev_get_uclass_platdata(dev); 526 527 uc_pdata->type = REGULATOR_TYPE_BUCK; 528 uc_pdata->mode_count = 0; 529 530 return 0; 531 } 532 533 static int rk8xx_ldo_probe(struct udevice *dev) 534 { 535 struct dm_regulator_uclass_platdata *uc_pdata; 536 537 uc_pdata = dev_get_uclass_platdata(dev); 538 539 uc_pdata->type = REGULATOR_TYPE_LDO; 540 uc_pdata->mode_count = 0; 541 542 return 0; 543 } 544 545 static int rk8xx_switch_probe(struct udevice *dev) 546 { 547 struct dm_regulator_uclass_platdata *uc_pdata; 548 549 uc_pdata = dev_get_uclass_platdata(dev); 550 551 uc_pdata->type = REGULATOR_TYPE_FIXED; 552 uc_pdata->mode_count = 0; 553 554 return 0; 555 } 556 557 static const struct dm_regulator_ops rk8xx_buck_ops = { 558 .get_value = buck_get_value, 559 .set_value = buck_set_value, 560 .set_suspend_value = buck_set_suspend_value, 561 .get_enable = buck_get_enable, 562 .set_enable = buck_set_enable, 563 .set_suspend_enable = buck_set_suspend_enable, 564 }; 565 566 static const struct dm_regulator_ops rk8xx_ldo_ops = { 567 .get_value = ldo_get_value, 568 .set_value = ldo_set_value, 569 .set_suspend_value = ldo_set_suspend_value, 570 .get_enable = ldo_get_enable, 571 .set_enable = ldo_set_enable, 572 .set_suspend_enable = ldo_set_suspend_enable, 573 }; 574 575 static const struct dm_regulator_ops rk8xx_switch_ops = { 576 .get_enable = switch_get_enable, 577 .set_enable = switch_set_enable, 578 }; 579 580 U_BOOT_DRIVER(rk8xx_buck) = { 581 .name = "rk8xx_buck", 582 .id = UCLASS_REGULATOR, 583 .ops = &rk8xx_buck_ops, 584 .probe = rk8xx_buck_probe, 585 }; 586 587 U_BOOT_DRIVER(rk8xx_ldo) = { 588 .name = "rk8xx_ldo", 589 .id = UCLASS_REGULATOR, 590 .ops = &rk8xx_ldo_ops, 591 .probe = rk8xx_ldo_probe, 592 }; 593 594 U_BOOT_DRIVER(rk8xx_switch) = { 595 .name = "rk8xx_switch", 596 .id = UCLASS_REGULATOR, 597 .ops = &rk8xx_switch_ops, 598 .probe = rk8xx_switch_probe, 599 }; 600 #endif 601 602 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt) 603 { 604 int ret; 605 606 ret = _buck_set_value(pmic, buck, uvolt); 607 if (ret) 608 return ret; 609 610 return _buck_set_enable(pmic, buck, true); 611 } 612 613 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma) 614 { 615 uint i; 616 617 for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++) 618 if (current_ma <= rk818_chrg_cur_input_array[i]) 619 break; 620 621 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); 622 } 623 624 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt) 625 { 626 uint i; 627 628 for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++) 629 if (uvolt <= rk818_chrg_shutdown_vsel_array[i]) 630 break; 631 632 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, 633 i); 634 } 635