1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * Based on Rockchip's drivers/power/pmic/pmic_rk808.c: 6 * Copyright (C) 2012 rockchips 7 * zyw <zyw@rock-chips.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <power/rk8xx_pmic.h> 16 #include <power/pmic.h> 17 #include <power/regulator.h> 18 19 #ifndef CONFIG_SPL_BUILD 20 #define ENABLE_DRIVER 21 #endif 22 23 /* Field Definitions */ 24 #define RK808_BUCK_VSEL_MASK 0x3f 25 #define RK808_BUCK4_VSEL_MASK 0xf 26 #define RK808_LDO_VSEL_MASK 0x1f 27 28 #define RK818_BUCK_VSEL_MASK 0x3f 29 #define RK818_BUCK4_VSEL_MASK 0x1f 30 #define RK818_LDO_VSEL_MASK 0x1f 31 #define RK818_LDO3_ON_VSEL_MASK 0xf 32 #define RK818_BOOST_ON_VSEL_MASK 0xe0 33 #define RK818_USB_ILIM_SEL_MASK 0x0f 34 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 35 36 /* RK809 BUCK5 */ 37 #define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1) 38 #define RK809_BUCK5_VSEL_MASK 0x07 39 40 /* RK817 BUCK */ 41 #define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * (n - 1)) 42 #define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * (n - 1)) 43 #define RK817_BUCK_VSEL_MASK 0x7f 44 #define RK817_BUCK_CONFIG(i) (0xba + (i) * 3) 45 46 /* RK817 LDO */ 47 #define RK817_LDO_ON_VSEL(n) (0xcc + 2 * (n - 1)) 48 #define RK817_LDO_SLP_VSEL(n) (0xcd + 2 * (n - 1)) 49 #define RK817_LDO_VSEL_MASK 0x7f 50 51 /* RK817 ENABLE */ 52 #define RK817_POWER_EN(n) (0xb1 + (n)) 53 #define RK817_POWER_SLP_EN(n) (0xb5 + (n)) 54 55 /* 56 * Ramp delay 57 */ 58 #define RK805_RAMP_RATE_OFFSET 3 59 #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET) 60 #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET) 61 #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET) 62 #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET) 63 #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET) 64 65 #define RK808_RAMP_RATE_OFFSET 3 66 #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET) 67 #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET) 68 #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET) 69 #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET) 70 #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET) 71 72 #define RK817_RAMP_RATE_OFFSET 6 73 #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET) 74 #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET) 75 #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET) 76 #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET) 77 #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET) 78 79 struct rk8xx_reg_info { 80 uint min_uv; 81 uint step_uv; 82 u8 vsel_reg; 83 u8 vsel_sleep_reg; 84 u8 config_reg; 85 u8 vsel_mask; 86 u8 min_sel; 87 }; 88 89 static const struct rk8xx_reg_info rk808_buck[] = { 90 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, }, 91 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, }, 92 { 712500, 12500, -1, -1, REG_BUCK3_CONFIG, RK808_BUCK_VSEL_MASK, }, 93 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, }, 94 }; 95 96 static const struct rk8xx_reg_info rk816_buck[] = { 97 /* buck 1 */ 98 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, }, 99 { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, }, 100 { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, }, 101 /* buck 2 */ 102 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, }, 103 { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, }, 104 { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, }, 105 /* buck 3 */ 106 { 712500, 12500, -1, -1, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, }, 107 /* buck 4 */ 108 { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, }, 109 }; 110 111 static const struct rk8xx_reg_info rk809_buck5[] = { 112 /* buck 5 */ 113 { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), -1, RK809_BUCK5_VSEL_MASK, 0x00, }, 114 { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), -1, RK809_BUCK5_VSEL_MASK, 0x01, }, 115 { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), -1, RK809_BUCK5_VSEL_MASK, 0x04, }, 116 { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), -1, RK809_BUCK5_VSEL_MASK, 0x06, }, 117 }; 118 119 static const struct rk8xx_reg_info rk817_buck[] = { 120 /* buck 1 */ 121 { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, }, 122 { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, }, 123 { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, }, 124 /* buck 2 */ 125 { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, }, 126 { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, }, 127 { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, }, 128 /* buck 3 */ 129 { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, }, 130 { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, }, 131 { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, }, 132 /* buck 4 */ 133 { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, }, 134 { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, }, 135 { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, }, 136 }; 137 138 static const struct rk8xx_reg_info rk818_buck[] = { 139 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, }, 140 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, }, 141 { 712500, 12500, -1, -1, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, }, 142 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, }, 143 }; 144 145 #ifdef ENABLE_DRIVER 146 static const struct rk8xx_reg_info rk808_ldo[] = { 147 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 148 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 149 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, RK808_BUCK4_VSEL_MASK, }, 150 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 151 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 152 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 153 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 154 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, RK808_LDO_VSEL_MASK, }, 155 }; 156 157 static const struct rk8xx_reg_info rk816_ldo[] = { 158 { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 159 { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 160 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 161 { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 162 { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 163 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 164 }; 165 166 static const struct rk8xx_reg_info rk817_ldo[] = { 167 /* ldo1 */ 168 { 600000, 25000, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), RK817_LDO_VSEL_MASK, 0x00, }, 169 { 3400000, 0, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), RK817_LDO_VSEL_MASK, 0x70, }, 170 /* ldo2 */ 171 { 600000, 25000, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), RK817_LDO_VSEL_MASK, 0x00, }, 172 { 3400000, 0, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), RK817_LDO_VSEL_MASK, 0x70, }, 173 /* ldo3 */ 174 { 600000, 25000, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), RK817_LDO_VSEL_MASK, 0x00, }, 175 { 3400000, 0, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), RK817_LDO_VSEL_MASK, 0x70, }, 176 /* ldo4 */ 177 { 600000, 25000, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), RK817_LDO_VSEL_MASK, 0x00, }, 178 { 3400000, 0, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), RK817_LDO_VSEL_MASK, 0x70, }, 179 /* ldo5 */ 180 { 600000, 25000, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), RK817_LDO_VSEL_MASK, 0x00, }, 181 { 3400000, 0, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), RK817_LDO_VSEL_MASK, 0x70, }, 182 /* ldo6 */ 183 { 600000, 25000, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), RK817_LDO_VSEL_MASK, 0x00, }, 184 { 3400000, 0, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), RK817_LDO_VSEL_MASK, 0x70, }, 185 /* ldo7 */ 186 { 600000, 25000, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), RK817_LDO_VSEL_MASK, 0x00, }, 187 { 3400000, 0, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), RK817_LDO_VSEL_MASK, 0x70, }, 188 /* ldo8 */ 189 { 600000, 25000, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), RK817_LDO_VSEL_MASK, 0x00, }, 190 { 3400000, 0, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), RK817_LDO_VSEL_MASK, 0x70, }, 191 /* ldo9 */ 192 { 600000, 25000, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), RK817_LDO_VSEL_MASK, 0x00, }, 193 { 3400000, 0, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), RK817_LDO_VSEL_MASK, 0x70, }, 194 }; 195 196 static const struct rk8xx_reg_info rk818_ldo[] = { 197 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 198 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 199 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, RK818_LDO3_ON_VSEL_MASK, }, 200 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 201 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 202 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 203 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 204 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, RK818_LDO_VSEL_MASK, }, 205 }; 206 #endif 207 208 static const u16 rk818_chrg_cur_input_array[] = { 209 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 210 }; 211 212 static const uint rk818_chrg_shutdown_vsel_array[] = { 213 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000 214 }; 215 216 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, 217 int num, int uvolt) 218 { 219 struct rk8xx_priv *priv = dev_get_priv(pmic); 220 221 switch (priv->variant) { 222 case RK805_ID: 223 case RK816_ID: 224 switch (num) { 225 case 0: 226 case 1: 227 if (uvolt <= 1450000) 228 return &rk816_buck[num * 3 + 0]; 229 else if (uvolt <= 2200000) 230 return &rk816_buck[num * 3 + 1]; 231 else 232 return &rk816_buck[num * 3 + 2]; 233 default: 234 return &rk816_buck[num + 4]; 235 } 236 237 case RK809_ID: 238 case RK817_ID: 239 switch (num) { 240 case 0 ... 2: 241 if (uvolt < 1500000) 242 return &rk817_buck[num * 3 + 0]; 243 else if (uvolt < 2400000) 244 return &rk817_buck[num * 3 + 1]; 245 else 246 return &rk817_buck[num * 3 + 2]; 247 case 3: 248 if (uvolt < 1500000) 249 return &rk817_buck[num * 3 + 0]; 250 else if (uvolt < 3400000) 251 return &rk817_buck[num * 3 + 1]; 252 else 253 return &rk817_buck[num * 3 + 2]; 254 /* BUCK5 for RK809 */ 255 default: 256 if (uvolt < 1800000) 257 return &rk809_buck5[0]; 258 else if (uvolt < 2800000) 259 return &rk809_buck5[1]; 260 else if (uvolt < 3300000) 261 return &rk809_buck5[2]; 262 else 263 return &rk809_buck5[3]; 264 } 265 case RK818_ID: 266 return &rk818_buck[num]; 267 default: 268 return &rk808_buck[num]; 269 } 270 } 271 272 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt) 273 { 274 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 275 int mask = info->vsel_mask; 276 int val; 277 278 if (info->vsel_reg == -1) 279 return -ENOSYS; 280 281 if (info->step_uv == 0) /* Fixed voltage */ 282 val = info->min_sel; 283 else 284 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 285 286 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 287 __func__, uvolt, buck+1, info->vsel_reg, mask, val); 288 289 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); 290 } 291 292 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) 293 { 294 uint mask, value, en_reg; 295 int ret; 296 struct rk8xx_priv *priv = dev_get_priv(pmic); 297 298 switch (priv->variant) { 299 case RK805_ID: 300 case RK816_ID: 301 if (buck >= 4) { 302 buck -= 4; 303 en_reg = RK816_REG_DCDC_EN2; 304 } else { 305 en_reg = RK816_REG_DCDC_EN1; 306 } 307 if (enable) 308 value = ((1 << buck) | (1 << (buck + 4))); 309 else 310 value = ((0 << buck) | (1 << (buck + 4))); 311 ret = pmic_reg_write(pmic, en_reg, value); 312 break; 313 314 case RK808_ID: 315 case RK818_ID: 316 mask = 1 << buck; 317 if (enable) { 318 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 319 0, 3 << (buck * 2)); 320 if (ret) 321 return ret; 322 ret = pmic_clrsetbits(pmic, REG_DCDC_UV_ACT, 323 1 << buck, 0); 324 if (ret) 325 return ret; 326 } 327 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask, 328 enable ? mask : 0); 329 break; 330 case RK809_ID: 331 case RK817_ID: 332 if (buck < 4) { 333 if (enable) 334 value = ((1 << buck) | (1 << (buck + 4))); 335 else 336 value = ((0 << buck) | (1 << (buck + 4))); 337 ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value); 338 /* BUCK5 for RK809 */ 339 } else { 340 if (enable) 341 value = ((1 << 1) | (1 << 5)); 342 else 343 value = ((0 << 1) | (1 << 5)); 344 ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value); 345 } 346 break; 347 default: 348 ret = -EINVAL; 349 } 350 351 return ret; 352 } 353 354 #ifdef ENABLE_DRIVER 355 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt) 356 { 357 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 358 int mask = info->vsel_mask; 359 int val; 360 361 if (info->vsel_sleep_reg == -1) 362 return -ENOSYS; 363 364 if (info->step_uv == 0) 365 val = info->min_sel; 366 else 367 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 368 369 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 370 __func__, uvolt, buck+1, info->vsel_sleep_reg, mask, val); 371 372 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); 373 } 374 375 static int _buck_get_enable(struct udevice *pmic, int buck) 376 { 377 struct rk8xx_priv *priv = dev_get_priv(pmic); 378 uint mask = 0; 379 int ret = 0; 380 381 switch (priv->variant) { 382 case RK805_ID: 383 case RK816_ID: 384 if (buck >= 4) { 385 mask = 1 << (buck - 4); 386 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2); 387 } else { 388 mask = 1 << buck; 389 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1); 390 } 391 break; 392 case RK808_ID: 393 case RK818_ID: 394 mask = 1 << buck; 395 ret = pmic_reg_read(pmic, REG_DCDC_EN); 396 if (ret < 0) 397 return ret; 398 break; 399 case RK809_ID: 400 case RK817_ID: 401 if (buck < 4) { 402 mask = 1 << buck; 403 ret = pmic_reg_read(pmic, RK817_POWER_EN(0)); 404 /* BUCK5 for RK809 */ 405 } else { 406 mask = 1 << 1; 407 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 408 } 409 break; 410 } 411 412 if (ret < 0) 413 return ret; 414 415 return ret & mask ? true : false; 416 } 417 418 static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay) 419 { 420 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0); 421 struct rk8xx_priv *priv = dev_get_priv(pmic); 422 u32 ramp_value, ramp_mask; 423 424 if (info->config_reg == -1) 425 return -ENOSYS; 426 427 switch (priv->variant) { 428 case RK805_ID: 429 ramp_mask = RK805_RAMP_RATE_MASK; 430 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 431 switch (ramp_delay) { 432 case 0 ... 3000: 433 ramp_value = RK805_RAMP_RATE_3MV_PER_US; 434 break; 435 case 3001 ... 6000: 436 ramp_value = RK805_RAMP_RATE_6MV_PER_US; 437 break; 438 case 6001 ... 12500: 439 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 440 break; 441 case 12501 ... 25000: 442 ramp_value = RK805_RAMP_RATE_25MV_PER_US; 443 break; 444 default: 445 printf("buck%d ramp_delay: %d not supported\n", 446 buck, ramp_delay); 447 } 448 break; 449 case RK808_ID: 450 case RK816_ID: 451 case RK818_ID: 452 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 453 ramp_mask = RK808_RAMP_RATE_MASK; 454 switch (ramp_delay) { 455 case 1 ... 2000: 456 ramp_value = RK808_RAMP_RATE_2MV_PER_US; 457 break; 458 case 2001 ... 4000: 459 ramp_value = RK808_RAMP_RATE_4MV_PER_US; 460 break; 461 case 4001 ... 6000: 462 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 463 break; 464 case 6001 ... 10000: 465 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 466 break; 467 default: 468 printf("buck%d ramp_delay: %d not supported\n", 469 buck, ramp_delay); 470 } 471 break; 472 case RK809_ID: 473 case RK817_ID: 474 ramp_mask = RK817_RAMP_RATE_MASK; 475 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 476 switch (ramp_delay) { 477 case 0 ... 3000: 478 ramp_value = RK817_RAMP_RATE_3MV_PER_US; 479 break; 480 case 3001 ... 6300: 481 ramp_value = RK817_RAMP_RATE_6_3MV_PER_US; 482 break; 483 case 6301 ... 12500: 484 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 485 break; 486 case 12501 ... 25000: 487 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 488 break; 489 default: 490 printf("buck%d ramp_delay: %d not supported\n", 491 buck, ramp_delay); 492 } 493 break; 494 default: 495 return -EINVAL; 496 } 497 498 return pmic_clrsetbits(pmic, info->config_reg, ramp_mask, ramp_value); 499 } 500 501 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) 502 { 503 uint mask; 504 int ret; 505 struct rk8xx_priv *priv = dev_get_priv(pmic); 506 507 switch (priv->variant) { 508 case RK805_ID: 509 case RK816_ID: 510 mask = 1 << buck; 511 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask, 512 enable ? mask : 0); 513 break; 514 case RK808_ID: 515 case RK818_ID: 516 mask = 1 << buck; 517 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask, 518 enable ? 0 : mask); 519 break; 520 case RK809_ID: 521 case RK817_ID: 522 if (buck < 4) 523 mask = 1 << buck; 524 else 525 mask = 1 << 5; /* BUCK5 for RK809 */ 526 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 527 enable ? mask : 0); 528 break; 529 default: 530 ret = -EINVAL; 531 } 532 533 return ret; 534 } 535 536 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, 537 int num, int uvolt) 538 { 539 struct rk8xx_priv *priv = dev_get_priv(pmic); 540 541 switch (priv->variant) { 542 case RK805_ID: 543 case RK816_ID: 544 return &rk816_ldo[num]; 545 case RK809_ID: 546 case RK817_ID: 547 if (uvolt < 3400000) 548 return &rk817_ldo[num * 2 + 0]; 549 else 550 return &rk817_ldo[num * 2 + 1]; 551 case RK818_ID: 552 return &rk818_ldo[num]; 553 default: 554 return &rk808_ldo[num]; 555 } 556 } 557 558 static int _ldo_get_enable(struct udevice *pmic, int ldo) 559 { 560 struct rk8xx_priv *priv = dev_get_priv(pmic); 561 uint mask = 0; 562 int ret = 0; 563 564 switch (priv->variant) { 565 case RK805_ID: 566 case RK816_ID: 567 if (ldo >= 4) { 568 mask = 1 << (ldo - 4); 569 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2); 570 } else { 571 mask = 1 << ldo; 572 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1); 573 } 574 break; 575 case RK808_ID: 576 case RK818_ID: 577 mask = 1 << ldo; 578 ret = pmic_reg_read(pmic, REG_LDO_EN); 579 if (ret < 0) 580 return ret; 581 break; 582 case RK809_ID: 583 case RK817_ID: 584 if (ldo < 4) { 585 mask = 1 << ldo; 586 ret = pmic_reg_read(pmic, RK817_POWER_EN(1)); 587 } else if (ldo < 8) { 588 mask = 1 << (ldo - 4); 589 ret = pmic_reg_read(pmic, RK817_POWER_EN(2)); 590 } else if (ldo == 8) { 591 mask = 1 << 0; 592 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 593 } else { 594 return false; 595 } 596 break; 597 } 598 599 if (ret < 0) 600 return ret; 601 602 return ret & mask ? true : false; 603 } 604 605 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable) 606 { 607 struct rk8xx_priv *priv = dev_get_priv(pmic); 608 uint mask, value, en_reg; 609 int ret = 0; 610 611 switch (priv->variant) { 612 case RK805_ID: 613 case RK816_ID: 614 if (ldo >= 4) { 615 ldo -= 4; 616 en_reg = RK816_REG_LDO_EN2; 617 } else { 618 en_reg = RK816_REG_LDO_EN1; 619 } 620 if (enable) 621 value = ((1 << ldo) | (1 << (ldo + 4))); 622 else 623 value = ((0 << ldo) | (1 << (ldo + 4))); 624 625 ret = pmic_reg_write(pmic, en_reg, value); 626 break; 627 case RK808_ID: 628 case RK818_ID: 629 mask = 1 << ldo; 630 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask, 631 enable ? mask : 0); 632 break; 633 case RK809_ID: 634 case RK817_ID: 635 if (ldo < 4) { 636 en_reg = RK817_POWER_EN(1); 637 } else if (ldo < 8) { 638 ldo -= 4; 639 en_reg = RK817_POWER_EN(2); 640 } else if (ldo == 8) { 641 ldo = 0; /* BIT 0 */ 642 en_reg = RK817_POWER_EN(3); 643 } else { 644 return -EINVAL; 645 } 646 if (enable) 647 value = ((1 << ldo) | (1 << (ldo + 4))); 648 else 649 value = ((0 << ldo) | (1 << (ldo + 4))); 650 ret = pmic_reg_write(pmic, en_reg, value); 651 break; 652 } 653 654 return ret; 655 } 656 657 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable) 658 { 659 struct rk8xx_priv *priv = dev_get_priv(pmic); 660 uint mask; 661 int ret = 0; 662 663 switch (priv->variant) { 664 case RK805_ID: 665 case RK816_ID: 666 mask = 1 << ldo; 667 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask, 668 enable ? mask : 0); 669 break; 670 case RK808_ID: 671 case RK818_ID: 672 mask = 1 << ldo; 673 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask, 674 enable ? 0 : mask); 675 break; 676 case RK809_ID: 677 case RK817_ID: 678 if (ldo == 8) { 679 mask = 1 << 4; /* LDO9 */ 680 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 681 enable ? mask : 0); 682 } else { 683 mask = 1 << ldo; 684 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask, 685 enable ? mask : 0); 686 } 687 break; 688 } 689 690 return ret; 691 } 692 693 static int buck_get_value(struct udevice *dev) 694 { 695 int buck = dev->driver_data - 1; 696 /* We assume level-1 voltage is enough for usage in U-Boot */ 697 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 698 int mask = info->vsel_mask; 699 int ret, val; 700 701 if (info->vsel_reg == -1) 702 return -ENOSYS; 703 704 ret = pmic_reg_read(dev->parent, info->vsel_reg); 705 if (ret < 0) 706 return ret; 707 val = ret & mask; 708 709 return info->min_uv + val * info->step_uv; 710 } 711 712 static int buck_set_value(struct udevice *dev, int uvolt) 713 { 714 int buck = dev->driver_data - 1; 715 716 return _buck_set_value(dev->parent, buck, uvolt); 717 } 718 719 static int buck_set_suspend_value(struct udevice *dev, int uvolt) 720 { 721 int buck = dev->driver_data - 1; 722 723 return _buck_set_suspend_value(dev->parent, buck, uvolt); 724 } 725 726 static int buck_set_enable(struct udevice *dev, bool enable) 727 { 728 int buck = dev->driver_data - 1; 729 730 return _buck_set_enable(dev->parent, buck, enable); 731 } 732 733 static int buck_set_suspend_enable(struct udevice *dev, bool enable) 734 { 735 int buck = dev->driver_data - 1; 736 737 return _buck_set_suspend_enable(dev->parent, buck, enable); 738 } 739 740 static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay) 741 { 742 int buck = dev->driver_data - 1; 743 744 return _buck_set_ramp_delay(dev->parent, buck, ramp_delay); 745 } 746 747 static int buck_get_enable(struct udevice *dev) 748 { 749 int buck = dev->driver_data - 1; 750 751 return _buck_get_enable(dev->parent, buck); 752 } 753 754 static int ldo_get_value(struct udevice *dev) 755 { 756 int ldo = dev->driver_data - 1; 757 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); 758 int mask = info->vsel_mask; 759 int ret, val; 760 761 if (info->vsel_reg == -1) 762 return -ENOSYS; 763 ret = pmic_reg_read(dev->parent, info->vsel_reg); 764 if (ret < 0) 765 return ret; 766 val = ret & mask; 767 768 return info->min_uv + val * info->step_uv; 769 } 770 771 static int ldo_set_value(struct udevice *dev, int uvolt) 772 { 773 int ldo = dev->driver_data - 1; 774 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 775 int mask = info->vsel_mask; 776 int val; 777 778 if (info->vsel_reg == -1) 779 return -ENOSYS; 780 781 if (info->step_uv == 0) 782 val = info->min_sel; 783 else 784 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 785 786 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 787 __func__, uvolt, ldo+1, info->vsel_reg, mask, val); 788 789 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); 790 } 791 792 static int ldo_set_suspend_value(struct udevice *dev, int uvolt) 793 { 794 int ldo = dev->driver_data - 1; 795 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 796 int mask = info->vsel_mask; 797 int val; 798 799 if (info->vsel_sleep_reg == -1) 800 return -ENOSYS; 801 802 if (info->step_uv == 0) 803 val = info->min_sel; 804 else 805 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 806 807 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 808 __func__, uvolt, ldo+1, info->vsel_sleep_reg, mask, val); 809 810 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); 811 } 812 813 static int ldo_set_enable(struct udevice *dev, bool enable) 814 { 815 int ldo = dev->driver_data - 1; 816 817 return _ldo_set_enable(dev->parent, ldo, enable); 818 } 819 820 static int ldo_set_suspend_enable(struct udevice *dev, bool enable) 821 { 822 int ldo = dev->driver_data - 1; 823 824 return _ldo_set_suspend_enable(dev->parent, ldo, enable); 825 } 826 827 static int ldo_get_enable(struct udevice *dev) 828 { 829 int ldo = dev->driver_data - 1; 830 831 return _ldo_get_enable(dev->parent, ldo); 832 } 833 834 static int switch_set_enable(struct udevice *dev, bool enable) 835 { 836 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 837 int ret = 0, sw = dev->driver_data - 1; 838 uint mask = 0; 839 840 switch (priv->variant) { 841 case RK808_ID: 842 mask = 1 << (sw + 5); 843 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 844 enable ? mask : 0); 845 break; 846 case RK809_ID: 847 mask = (1 << (sw + 2)) | (1 << (sw + 6)); 848 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask, 849 enable ? mask : 0); 850 break; 851 case RK818_ID: 852 mask = 1 << 6; 853 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 854 enable ? mask : 0); 855 break; 856 } 857 858 debug("%s: switch%d, enable=%d, mask=0x%x\n", 859 __func__, sw + 1, enable, mask); 860 861 return ret; 862 } 863 864 static int switch_get_enable(struct udevice *dev) 865 { 866 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 867 int ret = 0, sw = dev->driver_data - 1; 868 uint mask = 0; 869 870 switch (priv->variant) { 871 case RK808_ID: 872 mask = 1 << (sw + 5); 873 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 874 break; 875 case RK809_ID: 876 mask = 1 << (sw + 2); 877 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3)); 878 break; 879 case RK818_ID: 880 mask = 1 << 6; 881 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 882 break; 883 } 884 885 if (ret < 0) 886 return ret; 887 888 return ret & mask ? true : false; 889 } 890 891 static int switch_set_suspend_value(struct udevice *dev, int uvolt) 892 { 893 return 0; 894 } 895 896 static int switch_set_suspend_enable(struct udevice *dev, bool enable) 897 { 898 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 899 int ret = 0, sw = dev->driver_data - 1; 900 uint mask = 0; 901 902 switch (priv->variant) { 903 case RK808_ID: 904 mask = 1 << (sw + 5); 905 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 906 enable ? 0 : mask); 907 break; 908 case RK809_ID: 909 mask = 1 << (sw + 6); 910 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask, 911 enable ? mask : 0); 912 break; 913 case RK818_ID: 914 mask = 1 << 6; 915 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 916 enable ? 0 : mask); 917 break; 918 } 919 920 debug("%s: switch%d, enable=%d, mask=0x%x\n", 921 __func__, sw + 1, enable, mask); 922 923 return ret; 924 } 925 926 static int rk8xx_buck_probe(struct udevice *dev) 927 { 928 struct dm_regulator_uclass_platdata *uc_pdata; 929 930 uc_pdata = dev_get_uclass_platdata(dev); 931 932 uc_pdata->type = REGULATOR_TYPE_BUCK; 933 uc_pdata->mode_count = 0; 934 935 return 0; 936 } 937 938 static int rk8xx_ldo_probe(struct udevice *dev) 939 { 940 struct dm_regulator_uclass_platdata *uc_pdata; 941 942 uc_pdata = dev_get_uclass_platdata(dev); 943 944 uc_pdata->type = REGULATOR_TYPE_LDO; 945 uc_pdata->mode_count = 0; 946 947 return 0; 948 } 949 950 static int rk8xx_switch_probe(struct udevice *dev) 951 { 952 struct dm_regulator_uclass_platdata *uc_pdata; 953 954 uc_pdata = dev_get_uclass_platdata(dev); 955 956 uc_pdata->type = REGULATOR_TYPE_FIXED; 957 uc_pdata->mode_count = 0; 958 959 return 0; 960 } 961 962 static const struct dm_regulator_ops rk8xx_buck_ops = { 963 .get_value = buck_get_value, 964 .set_value = buck_set_value, 965 .set_suspend_value = buck_set_suspend_value, 966 .get_enable = buck_get_enable, 967 .set_enable = buck_set_enable, 968 .set_suspend_enable = buck_set_suspend_enable, 969 .set_ramp_delay = buck_set_ramp_delay, 970 }; 971 972 static const struct dm_regulator_ops rk8xx_ldo_ops = { 973 .get_value = ldo_get_value, 974 .set_value = ldo_set_value, 975 .set_suspend_value = ldo_set_suspend_value, 976 .get_enable = ldo_get_enable, 977 .set_enable = ldo_set_enable, 978 .set_suspend_enable = ldo_set_suspend_enable, 979 }; 980 981 static const struct dm_regulator_ops rk8xx_switch_ops = { 982 .get_enable = switch_get_enable, 983 .set_enable = switch_set_enable, 984 .set_suspend_enable = switch_set_suspend_enable, 985 .set_suspend_value = switch_set_suspend_value, 986 }; 987 988 U_BOOT_DRIVER(rk8xx_buck) = { 989 .name = "rk8xx_buck", 990 .id = UCLASS_REGULATOR, 991 .ops = &rk8xx_buck_ops, 992 .probe = rk8xx_buck_probe, 993 }; 994 995 U_BOOT_DRIVER(rk8xx_ldo) = { 996 .name = "rk8xx_ldo", 997 .id = UCLASS_REGULATOR, 998 .ops = &rk8xx_ldo_ops, 999 .probe = rk8xx_ldo_probe, 1000 }; 1001 1002 U_BOOT_DRIVER(rk8xx_switch) = { 1003 .name = "rk8xx_switch", 1004 .id = UCLASS_REGULATOR, 1005 .ops = &rk8xx_switch_ops, 1006 .probe = rk8xx_switch_probe, 1007 }; 1008 #endif 1009 1010 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt) 1011 { 1012 int ret; 1013 1014 ret = _buck_set_value(pmic, buck, uvolt); 1015 if (ret) 1016 return ret; 1017 1018 return _buck_set_enable(pmic, buck, true); 1019 } 1020 1021 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma) 1022 { 1023 uint i; 1024 1025 for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++) 1026 if (current_ma <= rk818_chrg_cur_input_array[i]) 1027 break; 1028 1029 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); 1030 } 1031 1032 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt) 1033 { 1034 uint i; 1035 1036 for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++) 1037 if (uvolt <= rk818_chrg_shutdown_vsel_array[i]) 1038 break; 1039 1040 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, 1041 i); 1042 } 1043