1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * Based on Rockchip's drivers/power/pmic/pmic_rk808.c: 6 * Copyright (C) 2012 rockchips 7 * zyw <zyw@rock-chips.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <power/rk8xx_pmic.h> 16 #include <power/pmic.h> 17 #include <power/regulator.h> 18 19 #ifndef CONFIG_SPL_BUILD 20 #define ENABLE_DRIVER 21 #endif 22 23 /* Not used or exisit register and configure */ 24 #define NA -1 25 26 /* Field Definitions */ 27 #define RK808_BUCK_VSEL_MASK 0x3f 28 #define RK808_BUCK4_VSEL_MASK 0xf 29 #define RK808_LDO_VSEL_MASK 0x1f 30 31 #define RK818_BUCK_VSEL_MASK 0x3f 32 #define RK818_BUCK4_VSEL_MASK 0x1f 33 #define RK818_LDO_VSEL_MASK 0x1f 34 #define RK818_LDO3_ON_VSEL_MASK 0xf 35 #define RK818_BOOST_ON_VSEL_MASK 0xe0 36 #define RK818_USB_ILIM_SEL_MASK 0x0f 37 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 38 39 /* RK809 BUCK5 */ 40 #define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1) 41 #define RK809_BUCK5_VSEL_MASK 0x07 42 43 /* RK817 BUCK */ 44 #define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * (n - 1)) 45 #define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * (n - 1)) 46 #define RK817_BUCK_VSEL_MASK 0x7f 47 #define RK817_BUCK_CONFIG(i) (0xba + (i) * 3) 48 49 /* RK817 LDO */ 50 #define RK817_LDO_ON_VSEL(n) (0xcc + 2 * (n - 1)) 51 #define RK817_LDO_SLP_VSEL(n) (0xcd + 2 * (n - 1)) 52 #define RK817_LDO_VSEL_MASK 0x7f 53 54 /* RK817 ENABLE */ 55 #define RK817_POWER_EN(n) (0xb1 + (n)) 56 #define RK817_POWER_SLP_EN(n) (0xb5 + (n)) 57 58 /* 59 * Ramp delay 60 */ 61 #define RK805_RAMP_RATE_OFFSET 3 62 #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET) 63 #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET) 64 #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET) 65 #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET) 66 #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET) 67 68 #define RK808_RAMP_RATE_OFFSET 3 69 #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET) 70 #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET) 71 #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET) 72 #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET) 73 #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET) 74 75 #define RK817_RAMP_RATE_OFFSET 6 76 #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET) 77 #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET) 78 #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET) 79 #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET) 80 #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET) 81 82 struct rk8xx_reg_info { 83 uint min_uv; 84 uint step_uv; 85 u8 vsel_reg; 86 u8 vsel_sleep_reg; 87 u8 config_reg; 88 u8 vsel_mask; 89 u8 min_sel; 90 }; 91 92 static const struct rk8xx_reg_info rk808_buck[] = { 93 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, }, 94 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, }, 95 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK808_BUCK_VSEL_MASK, }, 96 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, }, 97 }; 98 99 static const struct rk8xx_reg_info rk816_buck[] = { 100 /* buck 1 */ 101 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, }, 102 { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, }, 103 { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, }, 104 /* buck 2 */ 105 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, }, 106 { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, }, 107 { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, }, 108 /* buck 3 */ 109 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, }, 110 /* buck 4 */ 111 { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, }, 112 }; 113 114 static const struct rk8xx_reg_info rk809_buck5[] = { 115 /* buck 5 */ 116 { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, }, 117 { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, }, 118 { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, }, 119 { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, }, 120 }; 121 122 static const struct rk8xx_reg_info rk817_buck[] = { 123 /* buck 1 */ 124 { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, }, 125 { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, }, 126 { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, }, 127 /* buck 2 */ 128 { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, }, 129 { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, }, 130 { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, }, 131 /* buck 3 */ 132 { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, }, 133 { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, }, 134 { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, }, 135 /* buck 4 */ 136 { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, }, 137 { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, }, 138 { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, }, 139 }; 140 141 static const struct rk8xx_reg_info rk818_buck[] = { 142 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, }, 143 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, }, 144 { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, }, 145 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, }, 146 }; 147 148 #ifdef ENABLE_DRIVER 149 static const struct rk8xx_reg_info rk808_ldo[] = { 150 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 151 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 152 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK808_BUCK4_VSEL_MASK, }, 153 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 154 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 155 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 156 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 157 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 158 }; 159 160 static const struct rk8xx_reg_info rk816_ldo[] = { 161 { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 162 { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 163 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 164 { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 165 { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 166 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 167 }; 168 169 static const struct rk8xx_reg_info rk817_ldo[] = { 170 /* ldo1 */ 171 { 600000, 25000, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x00, }, 172 { 3400000, 0, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x70, }, 173 /* ldo2 */ 174 { 600000, 25000, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x00, }, 175 { 3400000, 0, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x70, }, 176 /* ldo3 */ 177 { 600000, 25000, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x00, }, 178 { 3400000, 0, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x70, }, 179 /* ldo4 */ 180 { 600000, 25000, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x00, }, 181 { 3400000, 0, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x70, }, 182 /* ldo5 */ 183 { 600000, 25000, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x00, }, 184 { 3400000, 0, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x70, }, 185 /* ldo6 */ 186 { 600000, 25000, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x00, }, 187 { 3400000, 0, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x70, }, 188 /* ldo7 */ 189 { 600000, 25000, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x00, }, 190 { 3400000, 0, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x70, }, 191 /* ldo8 */ 192 { 600000, 25000, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x00, }, 193 { 3400000, 0, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x70, }, 194 /* ldo9 */ 195 { 600000, 25000, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x00, }, 196 { 3400000, 0, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x70, }, 197 }; 198 199 static const struct rk8xx_reg_info rk818_ldo[] = { 200 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 201 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 202 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO3_ON_VSEL_MASK, }, 203 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 204 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 205 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 206 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 207 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 208 }; 209 #endif 210 211 static const u16 rk818_chrg_cur_input_array[] = { 212 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 213 }; 214 215 static const uint rk818_chrg_shutdown_vsel_array[] = { 216 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000 217 }; 218 219 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, 220 int num, int uvolt) 221 { 222 struct rk8xx_priv *priv = dev_get_priv(pmic); 223 224 switch (priv->variant) { 225 case RK805_ID: 226 case RK816_ID: 227 switch (num) { 228 case 0: 229 case 1: 230 if (uvolt <= 1450000) 231 return &rk816_buck[num * 3 + 0]; 232 else if (uvolt <= 2200000) 233 return &rk816_buck[num * 3 + 1]; 234 else 235 return &rk816_buck[num * 3 + 2]; 236 default: 237 return &rk816_buck[num + 4]; 238 } 239 240 case RK809_ID: 241 case RK817_ID: 242 switch (num) { 243 case 0 ... 2: 244 if (uvolt < 1500000) 245 return &rk817_buck[num * 3 + 0]; 246 else if (uvolt < 2400000) 247 return &rk817_buck[num * 3 + 1]; 248 else 249 return &rk817_buck[num * 3 + 2]; 250 case 3: 251 if (uvolt < 1500000) 252 return &rk817_buck[num * 3 + 0]; 253 else if (uvolt < 3400000) 254 return &rk817_buck[num * 3 + 1]; 255 else 256 return &rk817_buck[num * 3 + 2]; 257 /* BUCK5 for RK809 */ 258 default: 259 if (uvolt < 1800000) 260 return &rk809_buck5[0]; 261 else if (uvolt < 2800000) 262 return &rk809_buck5[1]; 263 else if (uvolt < 3300000) 264 return &rk809_buck5[2]; 265 else 266 return &rk809_buck5[3]; 267 } 268 case RK818_ID: 269 return &rk818_buck[num]; 270 default: 271 return &rk808_buck[num]; 272 } 273 } 274 275 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt) 276 { 277 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 278 struct rk8xx_priv *priv = dev_get_priv(pmic); 279 int mask = info->vsel_mask; 280 int val; 281 282 if (info->vsel_reg == NA) 283 return -ENOSYS; 284 285 if (info->step_uv == 0) /* Fixed voltage */ 286 val = info->min_sel; 287 else 288 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 289 290 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 291 __func__, uvolt, buck+1, info->vsel_reg, mask, val); 292 293 if (priv->variant == RK816_ID) { 294 pmic_clrsetbits(pmic, info->vsel_reg, mask, val); 295 return pmic_clrsetbits(pmic, RK816_REG_DCDC_EN2, 1 << 7, 1 << 7); 296 } else { 297 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); 298 } 299 } 300 301 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) 302 { 303 uint mask, value, en_reg; 304 int ret; 305 struct rk8xx_priv *priv = dev_get_priv(pmic); 306 307 switch (priv->variant) { 308 case RK805_ID: 309 case RK816_ID: 310 if (buck >= 4) { 311 buck -= 4; 312 en_reg = RK816_REG_DCDC_EN2; 313 } else { 314 en_reg = RK816_REG_DCDC_EN1; 315 } 316 if (enable) 317 value = ((1 << buck) | (1 << (buck + 4))); 318 else 319 value = ((0 << buck) | (1 << (buck + 4))); 320 ret = pmic_reg_write(pmic, en_reg, value); 321 break; 322 323 case RK808_ID: 324 case RK818_ID: 325 mask = 1 << buck; 326 if (enable) { 327 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 328 0, 3 << (buck * 2)); 329 if (ret) 330 return ret; 331 } 332 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask, 333 enable ? mask : 0); 334 break; 335 case RK809_ID: 336 case RK817_ID: 337 if (buck < 4) { 338 if (enable) 339 value = ((1 << buck) | (1 << (buck + 4))); 340 else 341 value = ((0 << buck) | (1 << (buck + 4))); 342 ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value); 343 /* BUCK5 for RK809 */ 344 } else { 345 if (enable) 346 value = ((1 << 1) | (1 << 5)); 347 else 348 value = ((0 << 1) | (1 << 5)); 349 ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value); 350 } 351 break; 352 default: 353 ret = -EINVAL; 354 } 355 356 return ret; 357 } 358 359 #ifdef ENABLE_DRIVER 360 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt) 361 { 362 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 363 int mask = info->vsel_mask; 364 int val; 365 366 if (info->vsel_sleep_reg == NA) 367 return -ENOSYS; 368 369 if (info->step_uv == 0) 370 val = info->min_sel; 371 else 372 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 373 374 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 375 __func__, uvolt, buck+1, info->vsel_sleep_reg, mask, val); 376 377 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); 378 } 379 380 static int _buck_get_enable(struct udevice *pmic, int buck) 381 { 382 struct rk8xx_priv *priv = dev_get_priv(pmic); 383 uint mask = 0; 384 int ret = 0; 385 386 switch (priv->variant) { 387 case RK805_ID: 388 case RK816_ID: 389 if (buck >= 4) { 390 mask = 1 << (buck - 4); 391 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2); 392 } else { 393 mask = 1 << buck; 394 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1); 395 } 396 break; 397 case RK808_ID: 398 case RK818_ID: 399 mask = 1 << buck; 400 ret = pmic_reg_read(pmic, REG_DCDC_EN); 401 if (ret < 0) 402 return ret; 403 break; 404 case RK809_ID: 405 case RK817_ID: 406 if (buck < 4) { 407 mask = 1 << buck; 408 ret = pmic_reg_read(pmic, RK817_POWER_EN(0)); 409 /* BUCK5 for RK809 */ 410 } else { 411 mask = 1 << 1; 412 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 413 } 414 break; 415 } 416 417 if (ret < 0) 418 return ret; 419 420 return ret & mask ? true : false; 421 } 422 423 static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay) 424 { 425 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0); 426 struct rk8xx_priv *priv = dev_get_priv(pmic); 427 u32 ramp_value, ramp_mask; 428 429 if (info->config_reg == NA) 430 return -ENOSYS; 431 432 switch (priv->variant) { 433 case RK805_ID: 434 ramp_mask = RK805_RAMP_RATE_MASK; 435 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 436 switch (ramp_delay) { 437 case 0 ... 3000: 438 ramp_value = RK805_RAMP_RATE_3MV_PER_US; 439 break; 440 case 3001 ... 6000: 441 ramp_value = RK805_RAMP_RATE_6MV_PER_US; 442 break; 443 case 6001 ... 12500: 444 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 445 break; 446 case 12501 ... 25000: 447 ramp_value = RK805_RAMP_RATE_25MV_PER_US; 448 break; 449 default: 450 printf("buck%d ramp_delay: %d not supported\n", 451 buck, ramp_delay); 452 } 453 break; 454 case RK808_ID: 455 case RK816_ID: 456 case RK818_ID: 457 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 458 ramp_mask = RK808_RAMP_RATE_MASK; 459 switch (ramp_delay) { 460 case 1 ... 2000: 461 ramp_value = RK808_RAMP_RATE_2MV_PER_US; 462 break; 463 case 2001 ... 4000: 464 ramp_value = RK808_RAMP_RATE_4MV_PER_US; 465 break; 466 case 4001 ... 6000: 467 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 468 break; 469 case 6001 ... 10000: 470 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 471 break; 472 default: 473 printf("buck%d ramp_delay: %d not supported\n", 474 buck, ramp_delay); 475 } 476 break; 477 case RK809_ID: 478 case RK817_ID: 479 ramp_mask = RK817_RAMP_RATE_MASK; 480 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 481 switch (ramp_delay) { 482 case 0 ... 3000: 483 ramp_value = RK817_RAMP_RATE_3MV_PER_US; 484 break; 485 case 3001 ... 6300: 486 ramp_value = RK817_RAMP_RATE_6_3MV_PER_US; 487 break; 488 case 6301 ... 12500: 489 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 490 break; 491 case 12501 ... 25000: 492 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 493 break; 494 default: 495 printf("buck%d ramp_delay: %d not supported\n", 496 buck, ramp_delay); 497 } 498 break; 499 default: 500 return -EINVAL; 501 } 502 503 return pmic_clrsetbits(pmic, info->config_reg, ramp_mask, ramp_value); 504 } 505 506 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) 507 { 508 uint mask; 509 int ret; 510 struct rk8xx_priv *priv = dev_get_priv(pmic); 511 512 switch (priv->variant) { 513 case RK805_ID: 514 case RK816_ID: 515 mask = 1 << buck; 516 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask, 517 enable ? mask : 0); 518 break; 519 case RK808_ID: 520 case RK818_ID: 521 mask = 1 << buck; 522 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask, 523 enable ? 0 : mask); 524 break; 525 case RK809_ID: 526 case RK817_ID: 527 if (buck < 4) 528 mask = 1 << buck; 529 else 530 mask = 1 << 5; /* BUCK5 for RK809 */ 531 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 532 enable ? mask : 0); 533 break; 534 default: 535 ret = -EINVAL; 536 } 537 538 return ret; 539 } 540 541 static int _buck_get_suspend_enable(struct udevice *pmic, int buck) 542 { 543 struct rk8xx_priv *priv = dev_get_priv(pmic); 544 int ret, val; 545 uint mask; 546 547 switch (priv->variant) { 548 case RK805_ID: 549 case RK816_ID: 550 mask = 1 << buck; 551 val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN); 552 if (val < 0) 553 return val; 554 ret = val & mask ? 1 : 0; 555 break; 556 case RK808_ID: 557 case RK818_ID: 558 mask = 1 << buck; 559 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1); 560 if (val < 0) 561 return val; 562 ret = val & mask ? 0 : 1; 563 break; 564 case RK809_ID: 565 case RK817_ID: 566 if (buck < 4) 567 mask = 1 << buck; 568 else 569 mask = 1 << 5; /* BUCK5 for RK809 */ 570 571 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); 572 if (val < 0) 573 return val; 574 ret = val & mask ? 1 : 0; 575 break; 576 default: 577 ret = -EINVAL; 578 } 579 580 return ret; 581 } 582 583 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, 584 int num, int uvolt) 585 { 586 struct rk8xx_priv *priv = dev_get_priv(pmic); 587 588 switch (priv->variant) { 589 case RK805_ID: 590 case RK816_ID: 591 return &rk816_ldo[num]; 592 case RK809_ID: 593 case RK817_ID: 594 if (uvolt < 3400000) 595 return &rk817_ldo[num * 2 + 0]; 596 else 597 return &rk817_ldo[num * 2 + 1]; 598 case RK818_ID: 599 return &rk818_ldo[num]; 600 default: 601 return &rk808_ldo[num]; 602 } 603 } 604 605 static int _ldo_get_enable(struct udevice *pmic, int ldo) 606 { 607 struct rk8xx_priv *priv = dev_get_priv(pmic); 608 uint mask = 0; 609 int ret = 0; 610 611 switch (priv->variant) { 612 case RK805_ID: 613 case RK816_ID: 614 if (ldo >= 4) { 615 mask = 1 << (ldo - 4); 616 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2); 617 } else { 618 mask = 1 << ldo; 619 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1); 620 } 621 break; 622 case RK808_ID: 623 case RK818_ID: 624 mask = 1 << ldo; 625 ret = pmic_reg_read(pmic, REG_LDO_EN); 626 if (ret < 0) 627 return ret; 628 break; 629 case RK809_ID: 630 case RK817_ID: 631 if (ldo < 4) { 632 mask = 1 << ldo; 633 ret = pmic_reg_read(pmic, RK817_POWER_EN(1)); 634 } else if (ldo < 8) { 635 mask = 1 << (ldo - 4); 636 ret = pmic_reg_read(pmic, RK817_POWER_EN(2)); 637 } else if (ldo == 8) { 638 mask = 1 << 0; 639 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 640 } else { 641 return false; 642 } 643 break; 644 } 645 646 if (ret < 0) 647 return ret; 648 649 return ret & mask ? true : false; 650 } 651 652 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable) 653 { 654 struct rk8xx_priv *priv = dev_get_priv(pmic); 655 uint mask, value, en_reg; 656 int ret = 0; 657 658 switch (priv->variant) { 659 case RK805_ID: 660 case RK816_ID: 661 if (ldo >= 4) { 662 ldo -= 4; 663 en_reg = RK816_REG_LDO_EN2; 664 } else { 665 en_reg = RK816_REG_LDO_EN1; 666 } 667 if (enable) 668 value = ((1 << ldo) | (1 << (ldo + 4))); 669 else 670 value = ((0 << ldo) | (1 << (ldo + 4))); 671 672 ret = pmic_reg_write(pmic, en_reg, value); 673 break; 674 case RK808_ID: 675 case RK818_ID: 676 mask = 1 << ldo; 677 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask, 678 enable ? mask : 0); 679 break; 680 case RK809_ID: 681 case RK817_ID: 682 if (ldo < 4) { 683 en_reg = RK817_POWER_EN(1); 684 } else if (ldo < 8) { 685 ldo -= 4; 686 en_reg = RK817_POWER_EN(2); 687 } else if (ldo == 8) { 688 ldo = 0; /* BIT 0 */ 689 en_reg = RK817_POWER_EN(3); 690 } else { 691 return -EINVAL; 692 } 693 if (enable) 694 value = ((1 << ldo) | (1 << (ldo + 4))); 695 else 696 value = ((0 << ldo) | (1 << (ldo + 4))); 697 ret = pmic_reg_write(pmic, en_reg, value); 698 break; 699 } 700 701 return ret; 702 } 703 704 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable) 705 { 706 struct rk8xx_priv *priv = dev_get_priv(pmic); 707 uint mask; 708 int ret = 0; 709 710 switch (priv->variant) { 711 case RK805_ID: 712 case RK816_ID: 713 mask = 1 << ldo; 714 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask, 715 enable ? mask : 0); 716 break; 717 case RK808_ID: 718 case RK818_ID: 719 mask = 1 << ldo; 720 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask, 721 enable ? 0 : mask); 722 break; 723 case RK809_ID: 724 case RK817_ID: 725 if (ldo == 8) { 726 mask = 1 << 4; /* LDO9 */ 727 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 728 enable ? mask : 0); 729 } else { 730 mask = 1 << ldo; 731 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask, 732 enable ? mask : 0); 733 } 734 break; 735 } 736 737 return ret; 738 } 739 740 static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) 741 { 742 struct rk8xx_priv *priv = dev_get_priv(pmic); 743 int val, ret = 0; 744 uint mask; 745 746 switch (priv->variant) { 747 case RK805_ID: 748 case RK816_ID: 749 mask = 1 << ldo; 750 val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN); 751 if (val < 0) 752 return val; 753 ret = val & mask ? 1 : 0; 754 break; 755 case RK808_ID: 756 case RK818_ID: 757 mask = 1 << ldo; 758 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2); 759 if (val < 0) 760 return val; 761 ret = val & mask ? 0 : 1; 762 break; 763 case RK809_ID: 764 case RK817_ID: 765 if (ldo == 8) { 766 mask = 1 << 4; /* LDO9 */ 767 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); 768 if (val < 0) 769 return val; 770 ret = val & mask ? 1 : 0; 771 } else { 772 mask = 1 << ldo; 773 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1)); 774 if (val < 0) 775 return val; 776 ret = val & mask ? 1 : 0; 777 } 778 break; 779 } 780 781 return ret; 782 } 783 784 static int buck_get_value(struct udevice *dev) 785 { 786 int buck = dev->driver_data - 1; 787 /* We assume level-1 voltage is enough for usage in U-Boot */ 788 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 789 int mask = info->vsel_mask; 790 int ret, val; 791 792 if (info->vsel_reg == NA) 793 return -ENOSYS; 794 795 ret = pmic_reg_read(dev->parent, info->vsel_reg); 796 if (ret < 0) 797 return ret; 798 val = ret & mask; 799 800 return info->min_uv + val * info->step_uv; 801 } 802 803 static int buck_set_value(struct udevice *dev, int uvolt) 804 { 805 int buck = dev->driver_data - 1; 806 807 return _buck_set_value(dev->parent, buck, uvolt); 808 } 809 810 static int buck_get_suspend_value(struct udevice *dev) 811 { 812 int buck = dev->driver_data - 1; 813 /* We assume level-1 voltage is enough for usage in U-Boot */ 814 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 815 int mask = info->vsel_mask; 816 int ret, val; 817 818 if (info->vsel_sleep_reg == NA) 819 return -ENOSYS; 820 821 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg); 822 if (ret < 0) 823 return ret; 824 825 val = ret & mask; 826 827 return info->min_uv + val * info->step_uv; 828 } 829 830 static int buck_set_suspend_value(struct udevice *dev, int uvolt) 831 { 832 int buck = dev->driver_data - 1; 833 834 return _buck_set_suspend_value(dev->parent, buck, uvolt); 835 } 836 837 static int buck_set_enable(struct udevice *dev, bool enable) 838 { 839 int buck = dev->driver_data - 1; 840 841 return _buck_set_enable(dev->parent, buck, enable); 842 } 843 844 static int buck_set_suspend_enable(struct udevice *dev, bool enable) 845 { 846 int buck = dev->driver_data - 1; 847 848 return _buck_set_suspend_enable(dev->parent, buck, enable); 849 } 850 851 static int buck_get_suspend_enable(struct udevice *dev) 852 { 853 int buck = dev->driver_data - 1; 854 855 return _buck_get_suspend_enable(dev->parent, buck); 856 } 857 858 static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay) 859 { 860 int buck = dev->driver_data - 1; 861 862 return _buck_set_ramp_delay(dev->parent, buck, ramp_delay); 863 } 864 865 static int buck_get_enable(struct udevice *dev) 866 { 867 int buck = dev->driver_data - 1; 868 869 return _buck_get_enable(dev->parent, buck); 870 } 871 872 static int ldo_get_value(struct udevice *dev) 873 { 874 int ldo = dev->driver_data - 1; 875 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); 876 int mask = info->vsel_mask; 877 int ret, val; 878 879 if (info->vsel_reg == NA) 880 return -ENOSYS; 881 ret = pmic_reg_read(dev->parent, info->vsel_reg); 882 if (ret < 0) 883 return ret; 884 val = ret & mask; 885 886 return info->min_uv + val * info->step_uv; 887 } 888 889 static int ldo_set_value(struct udevice *dev, int uvolt) 890 { 891 int ldo = dev->driver_data - 1; 892 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 893 int mask = info->vsel_mask; 894 int val; 895 896 if (info->vsel_reg == NA) 897 return -ENOSYS; 898 899 if (info->step_uv == 0) 900 val = info->min_sel; 901 else 902 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 903 904 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 905 __func__, uvolt, ldo+1, info->vsel_reg, mask, val); 906 907 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); 908 } 909 910 static int ldo_set_suspend_value(struct udevice *dev, int uvolt) 911 { 912 int ldo = dev->driver_data - 1; 913 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 914 int mask = info->vsel_mask; 915 int val; 916 917 if (info->vsel_sleep_reg == NA) 918 return -ENOSYS; 919 920 if (info->step_uv == 0) 921 val = info->min_sel; 922 else 923 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 924 925 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 926 __func__, uvolt, ldo+1, info->vsel_sleep_reg, mask, val); 927 928 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); 929 } 930 931 static int ldo_get_suspend_value(struct udevice *dev) 932 { 933 int ldo = dev->driver_data - 1; 934 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); 935 int mask = info->vsel_mask; 936 int val, ret; 937 938 if (info->vsel_sleep_reg == NA) 939 return -ENOSYS; 940 941 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg); 942 if (ret < 0) 943 return ret; 944 945 val = ret & mask; 946 947 return info->min_uv + val * info->step_uv; 948 } 949 950 static int ldo_set_enable(struct udevice *dev, bool enable) 951 { 952 int ldo = dev->driver_data - 1; 953 954 return _ldo_set_enable(dev->parent, ldo, enable); 955 } 956 957 static int ldo_set_suspend_enable(struct udevice *dev, bool enable) 958 { 959 int ldo = dev->driver_data - 1; 960 961 return _ldo_set_suspend_enable(dev->parent, ldo, enable); 962 } 963 964 static int ldo_get_suspend_enable(struct udevice *dev) 965 { 966 int ldo = dev->driver_data - 1; 967 968 return _ldo_get_suspend_enable(dev->parent, ldo); 969 } 970 971 static int ldo_get_enable(struct udevice *dev) 972 { 973 int ldo = dev->driver_data - 1; 974 975 return _ldo_get_enable(dev->parent, ldo); 976 } 977 978 static int switch_set_enable(struct udevice *dev, bool enable) 979 { 980 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 981 int ret = 0, sw = dev->driver_data - 1; 982 uint mask = 0; 983 984 switch (priv->variant) { 985 case RK808_ID: 986 mask = 1 << (sw + 5); 987 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 988 enable ? mask : 0); 989 break; 990 case RK809_ID: 991 mask = (1 << (sw + 2)) | (1 << (sw + 6)); 992 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask, 993 enable ? mask : 0); 994 break; 995 case RK818_ID: 996 mask = 1 << 6; 997 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 998 enable ? mask : 0); 999 break; 1000 } 1001 1002 debug("%s: switch%d, enable=%d, mask=0x%x\n", 1003 __func__, sw + 1, enable, mask); 1004 1005 return ret; 1006 } 1007 1008 static int switch_get_enable(struct udevice *dev) 1009 { 1010 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1011 int ret = 0, sw = dev->driver_data - 1; 1012 uint mask = 0; 1013 1014 switch (priv->variant) { 1015 case RK808_ID: 1016 mask = 1 << (sw + 5); 1017 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 1018 break; 1019 case RK809_ID: 1020 mask = 1 << (sw + 2); 1021 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3)); 1022 break; 1023 case RK818_ID: 1024 mask = 1 << 6; 1025 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 1026 break; 1027 } 1028 1029 if (ret < 0) 1030 return ret; 1031 1032 return ret & mask ? true : false; 1033 } 1034 1035 static int switch_set_suspend_value(struct udevice *dev, int uvolt) 1036 { 1037 return 0; 1038 } 1039 1040 static int switch_get_suspend_value(struct udevice *dev) 1041 { 1042 return 0; 1043 } 1044 1045 static int switch_set_suspend_enable(struct udevice *dev, bool enable) 1046 { 1047 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1048 int ret = 0, sw = dev->driver_data - 1; 1049 uint mask = 0; 1050 1051 switch (priv->variant) { 1052 case RK808_ID: 1053 mask = 1 << (sw + 5); 1054 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 1055 enable ? 0 : mask); 1056 break; 1057 case RK809_ID: 1058 mask = 1 << (sw + 6); 1059 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask, 1060 enable ? mask : 0); 1061 break; 1062 case RK818_ID: 1063 mask = 1 << 6; 1064 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 1065 enable ? 0 : mask); 1066 break; 1067 } 1068 1069 debug("%s: switch%d, enable=%d, mask=0x%x\n", 1070 __func__, sw + 1, enable, mask); 1071 1072 return ret; 1073 } 1074 1075 static int switch_get_suspend_enable(struct udevice *dev) 1076 { 1077 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1078 int val, ret = 0, sw = dev->driver_data - 1; 1079 uint mask = 0; 1080 1081 switch (priv->variant) { 1082 case RK808_ID: 1083 mask = 1 << (sw + 5); 1084 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); 1085 if (val < 0) 1086 return val; 1087 ret = val & mask ? 0 : 1; 1088 break; 1089 case RK809_ID: 1090 mask = 1 << (sw + 6); 1091 val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0)); 1092 if (val < 0) 1093 return val; 1094 ret = val & mask ? 1 : 0; 1095 break; 1096 case RK818_ID: 1097 mask = 1 << 6; 1098 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); 1099 if (val < 0) 1100 return val; 1101 ret = val & mask ? 0 : 1; 1102 break; 1103 } 1104 1105 return ret; 1106 } 1107 1108 /* 1109 * RK8xx switch does not need to set the voltage, 1110 * but if dts set regulator-min-microvolt/regulator-max-microvolt, 1111 * will cause regulator set value fail and not to enable this switch. 1112 * So add an empty function to return success. 1113 */ 1114 static int switch_get_value(struct udevice *dev) 1115 { 1116 return 0; 1117 } 1118 1119 static int switch_set_value(struct udevice *dev, int uvolt) 1120 { 1121 return 0; 1122 } 1123 1124 static int rk8xx_buck_probe(struct udevice *dev) 1125 { 1126 struct dm_regulator_uclass_platdata *uc_pdata; 1127 1128 uc_pdata = dev_get_uclass_platdata(dev); 1129 1130 uc_pdata->type = REGULATOR_TYPE_BUCK; 1131 uc_pdata->mode_count = 0; 1132 1133 return 0; 1134 } 1135 1136 static int rk8xx_ldo_probe(struct udevice *dev) 1137 { 1138 struct dm_regulator_uclass_platdata *uc_pdata; 1139 1140 uc_pdata = dev_get_uclass_platdata(dev); 1141 1142 uc_pdata->type = REGULATOR_TYPE_LDO; 1143 uc_pdata->mode_count = 0; 1144 1145 return 0; 1146 } 1147 1148 static int rk8xx_switch_probe(struct udevice *dev) 1149 { 1150 struct dm_regulator_uclass_platdata *uc_pdata; 1151 1152 uc_pdata = dev_get_uclass_platdata(dev); 1153 1154 uc_pdata->type = REGULATOR_TYPE_FIXED; 1155 uc_pdata->mode_count = 0; 1156 1157 return 0; 1158 } 1159 1160 static const struct dm_regulator_ops rk8xx_buck_ops = { 1161 .get_value = buck_get_value, 1162 .set_value = buck_set_value, 1163 .set_suspend_value = buck_set_suspend_value, 1164 .get_suspend_value = buck_get_suspend_value, 1165 .get_enable = buck_get_enable, 1166 .set_enable = buck_set_enable, 1167 .set_suspend_enable = buck_set_suspend_enable, 1168 .get_suspend_enable = buck_get_suspend_enable, 1169 .set_ramp_delay = buck_set_ramp_delay, 1170 }; 1171 1172 static const struct dm_regulator_ops rk8xx_ldo_ops = { 1173 .get_value = ldo_get_value, 1174 .set_value = ldo_set_value, 1175 .set_suspend_value = ldo_set_suspend_value, 1176 .get_suspend_value = ldo_get_suspend_value, 1177 .get_enable = ldo_get_enable, 1178 .set_enable = ldo_set_enable, 1179 .set_suspend_enable = ldo_set_suspend_enable, 1180 .get_suspend_enable = ldo_get_suspend_enable, 1181 }; 1182 1183 static const struct dm_regulator_ops rk8xx_switch_ops = { 1184 .get_value = switch_get_value, 1185 .set_value = switch_set_value, 1186 .get_enable = switch_get_enable, 1187 .set_enable = switch_set_enable, 1188 .set_suspend_enable = switch_set_suspend_enable, 1189 .get_suspend_enable = switch_get_suspend_enable, 1190 .set_suspend_value = switch_set_suspend_value, 1191 .get_suspend_value = switch_get_suspend_value, 1192 }; 1193 1194 U_BOOT_DRIVER(rk8xx_buck) = { 1195 .name = "rk8xx_buck", 1196 .id = UCLASS_REGULATOR, 1197 .ops = &rk8xx_buck_ops, 1198 .probe = rk8xx_buck_probe, 1199 }; 1200 1201 U_BOOT_DRIVER(rk8xx_ldo) = { 1202 .name = "rk8xx_ldo", 1203 .id = UCLASS_REGULATOR, 1204 .ops = &rk8xx_ldo_ops, 1205 .probe = rk8xx_ldo_probe, 1206 }; 1207 1208 U_BOOT_DRIVER(rk8xx_switch) = { 1209 .name = "rk8xx_switch", 1210 .id = UCLASS_REGULATOR, 1211 .ops = &rk8xx_switch_ops, 1212 .probe = rk8xx_switch_probe, 1213 }; 1214 #endif 1215 1216 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt) 1217 { 1218 int ret; 1219 1220 ret = _buck_set_value(pmic, buck, uvolt); 1221 if (ret) 1222 return ret; 1223 1224 return _buck_set_enable(pmic, buck, true); 1225 } 1226 1227 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma) 1228 { 1229 uint i; 1230 1231 for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++) 1232 if (current_ma <= rk818_chrg_cur_input_array[i]) 1233 break; 1234 1235 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); 1236 } 1237 1238 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt) 1239 { 1240 uint i; 1241 1242 for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++) 1243 if (uvolt <= rk818_chrg_shutdown_vsel_array[i]) 1244 break; 1245 1246 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, 1247 i); 1248 } 1249