1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * Based on Rockchip's drivers/power/pmic/pmic_rk808.c: 6 * Copyright (C) 2012 rockchips 7 * zyw <zyw@rock-chips.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <log.h> 16 #include <linux/delay.h> 17 #include <power/rk8xx_pmic.h> 18 #include <power/pmic.h> 19 #include <power/regulator.h> 20 21 #ifndef CONFIG_SPL_BUILD 22 #define ENABLE_DRIVER 23 #endif 24 25 /* Not used or exisit register and configure */ 26 #define NA -1 27 28 /* Field Definitions */ 29 #define RK808_BUCK_VSEL_MASK 0x3f 30 #define RK808_BUCK4_VSEL_MASK 0xf 31 #define RK808_LDO_VSEL_MASK 0x1f 32 33 #define RK818_BUCK_VSEL_MASK 0x3f 34 #define RK818_BUCK4_VSEL_MASK 0x1f 35 #define RK818_LDO_VSEL_MASK 0x1f 36 #define RK818_LDO3_ON_VSEL_MASK 0xf 37 #define RK818_BOOST_ON_VSEL_MASK 0xe0 38 #define RK818_USB_ILIM_SEL_MASK 0x0f 39 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 40 41 /* RK809 BUCK5 */ 42 #define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1) 43 #define RK809_BUCK5_VSEL_MASK 0x07 44 45 /* RK817 BUCK */ 46 #define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * (n - 1)) 47 #define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * (n - 1)) 48 #define RK817_BUCK_VSEL_MASK 0x7f 49 #define RK817_BUCK_CONFIG(i) (0xba + (i) * 3) 50 51 /* RK817 LDO */ 52 #define RK817_LDO_ON_VSEL(n) (0xcc + 2 * (n - 1)) 53 #define RK817_LDO_SLP_VSEL(n) (0xcd + 2 * (n - 1)) 54 #define RK817_LDO_VSEL_MASK 0x7f 55 56 /* RK817 ENABLE */ 57 #define RK817_POWER_EN(n) (0xb1 + (n)) 58 #define RK817_POWER_SLP_EN(n) (0xb5 + (n)) 59 60 /* 61 * Ramp delay 62 */ 63 #define RK805_RAMP_RATE_OFFSET 3 64 #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET) 65 #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET) 66 #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET) 67 #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET) 68 #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET) 69 70 #define RK808_RAMP_RATE_OFFSET 3 71 #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET) 72 #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET) 73 #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET) 74 #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET) 75 #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET) 76 77 #define RK817_RAMP_RATE_OFFSET 6 78 #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET) 79 #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET) 80 #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET) 81 #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET) 82 #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET) 83 84 struct rk8xx_reg_info { 85 uint min_uv; 86 uint step_uv; 87 u8 vsel_reg; 88 u8 vsel_sleep_reg; 89 u8 config_reg; 90 u8 vsel_mask; 91 u8 min_sel; 92 /* only for buck now */ 93 u8 max_sel; 94 u8 range_num; 95 }; 96 97 static const struct rk8xx_reg_info rk806_buck[] = { 98 /* buck 1 */ 99 { 500000, 6250, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3}, 100 { 1500000, 25000, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xa0, 0xec, 3}, 101 { 3400000, 0, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3}, 102 /* buck 2 */ 103 { 500000, 6250, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3}, 104 { 1500000, 25000, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3}, 105 { 3400000, 0, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3}, 106 /* buck 3 */ 107 { 500000, 6250, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3}, 108 { 1500000, 25000, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3}, 109 { 3400000, 0, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3}, 110 /* buck 4 */ 111 { 500000, 6250, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3}, 112 { 1500000, 25000, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3}, 113 { 3400000, 0, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3}, 114 /* buck 5 */ 115 { 500000, 6250, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3}, 116 { 1500000, 25000, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3}, 117 { 3400000, 0, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3}, 118 /* buck 6 */ 119 { 500000, 6250, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3}, 120 { 1500000, 25000, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3}, 121 { 3400000, 0, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3}, 122 /* buck 7 */ 123 { 500000, 6250, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3}, 124 { 1500000, 25000, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3}, 125 { 3400000, 0, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3}, 126 /* buck 8 */ 127 { 500000, 6250, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3}, 128 { 1500000, 25000, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3}, 129 { 3400000, 0, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3}, 130 /* buck 9 */ 131 { 500000, 6250, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3}, 132 { 1500000, 25000, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3}, 133 { 3400000, 0, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3}, 134 /* buck 10 */ 135 { 500000, 6250, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0x00, 0x9f, 3}, 136 { 1500000, 25000, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xa0, 0xed, 3}, 137 { 3400000, 0, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xed, 0xff, 3}, 138 }; 139 140 static const struct rk8xx_reg_info rk806_nldo[] = { 141 /* nldo1 */ 142 { 500000, 12500, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0x00, }, 143 { 3400000, 0, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0xE8, }, 144 /* nldo2 */ 145 { 500000, 12500, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0x00, }, 146 { 3400000, 0, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0xE8, }, 147 /* nldo3 */ 148 { 500000, 12500, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0x00, }, 149 { 3400000, 0, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0xE8, }, 150 /* nldo4 */ 151 { 500000, 12500, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0x00, }, 152 { 3400000, 0, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0xE8, }, 153 /* nldo5 */ 154 { 500000, 12500, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0x00, }, 155 { 3400000, 0, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0xE8, }, 156 }; 157 158 static const struct rk8xx_reg_info rk806_pldo[] = { 159 /* pldo1 */ 160 { 500000, 12500, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0x00, }, 161 { 3400000, 0, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, 162 /* pldo2 */ 163 { 500000, 12500, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0x00, }, 164 { 3400000, 0, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, 165 /* pldo3 */ 166 { 500000, 12500, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0x00, }, 167 { 3400000, 0, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, 168 /* pldo4 */ 169 { 500000, 12500, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0x00, }, 170 { 3400000, 0, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, 171 /* pldo5 */ 172 { 500000, 12500, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0x00, }, 173 { 3400000, 0, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, 174 /* pldo6 */ 175 { 500000, 12500, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0x00, }, 176 { 3400000, 0, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, 177 }; 178 179 static const struct rk8xx_reg_info rk808_buck[] = { 180 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f, 1}, 181 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f, 1}, 182 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1}, 183 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK,0x00, 0x0f, 1}, 184 }; 185 186 static const struct rk8xx_reg_info rk816_buck[] = { 187 /* buck 1 */ 188 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b, 3}, 189 { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e, 3}, 190 { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f, 3}, 191 /* buck 2 */ 192 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b, 3}, 193 { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e, 3}, 194 { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f, 3}, 195 /* buck 3 */ 196 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1}, 197 /* buck 4 */ 198 { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK,0x00, 0x1b, 1}, 199 }; 200 201 static const struct rk8xx_reg_info rk809_buck5[] = { 202 /* buck 5 */ 203 { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, 0x00, 4}, 204 { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, 0x03, 4}, 205 { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, 0x05, 4}, 206 { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, 0x07, 4}, 207 }; 208 209 static const struct rk8xx_reg_info rk817_buck[] = { 210 /* buck 1 */ 211 { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3}, 212 { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3}, 213 { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3}, 214 /* buck 2 */ 215 { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3}, 216 { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3}, 217 { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3}, 218 /* buck 3 */ 219 { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3}, 220 { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, 0x58, 3}, 221 { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, 0x59, 3}, 222 /* buck 4 */ 223 { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, 0x4f, 3}, 224 { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, 0x62, 3}, 225 { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, 0x63, 3}, 226 }; 227 228 static const struct rk8xx_reg_info rk818_buck[] = { 229 { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f, 1}, 230 { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f, 1}, 231 { NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA, 1}, 232 { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK,0x00, 0x10, 1}, 233 }; 234 235 #ifdef ENABLE_DRIVER 236 static const struct rk8xx_reg_info rk808_ldo[] = { 237 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 238 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 239 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK808_BUCK4_VSEL_MASK, }, 240 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 241 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 242 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 243 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 244 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, }, 245 }; 246 247 static const struct rk8xx_reg_info rk816_ldo[] = { 248 { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 249 { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 250 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 251 { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 252 { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 253 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 254 }; 255 256 static const struct rk8xx_reg_info rk817_ldo[] = { 257 /* ldo1 */ 258 { 600000, 25000, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x00, }, 259 { 3400000, 0, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x70, }, 260 /* ldo2 */ 261 { 600000, 25000, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x00, }, 262 { 3400000, 0, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x70, }, 263 /* ldo3 */ 264 { 600000, 25000, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x00, }, 265 { 3400000, 0, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x70, }, 266 /* ldo4 */ 267 { 600000, 25000, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x00, }, 268 { 3400000, 0, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x70, }, 269 /* ldo5 */ 270 { 600000, 25000, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x00, }, 271 { 3400000, 0, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x70, }, 272 /* ldo6 */ 273 { 600000, 25000, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x00, }, 274 { 3400000, 0, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x70, }, 275 /* ldo7 */ 276 { 600000, 25000, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x00, }, 277 { 3400000, 0, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x70, }, 278 /* ldo8 */ 279 { 600000, 25000, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x00, }, 280 { 3400000, 0, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x70, }, 281 /* ldo9 */ 282 { 600000, 25000, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x00, }, 283 { 3400000, 0, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x70, }, 284 }; 285 286 static const struct rk8xx_reg_info rk818_ldo[] = { 287 { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 288 { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 289 { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO3_ON_VSEL_MASK, }, 290 { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 291 { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 292 { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 293 { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 294 { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, }, 295 }; 296 #endif 297 298 static const u16 rk818_chrg_cur_input_array[] = { 299 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 300 }; 301 302 static const uint rk818_chrg_shutdown_vsel_array[] = { 303 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000 304 }; 305 306 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, 307 int num, int uvolt) 308 { 309 struct rk8xx_priv *priv = dev_get_priv(pmic); 310 311 switch (priv->variant) { 312 case RK806_ID: 313 switch (num) { 314 case 0 ... 9: 315 if (uvolt < 1500000) 316 return &rk806_buck[num * 3 + 0]; 317 else if (uvolt < 3400000) 318 return &rk806_buck[num * 3 + 1]; 319 else 320 return &rk806_buck[num * 3 + 2]; 321 } 322 case RK805_ID: 323 case RK816_ID: 324 switch (num) { 325 case 0: 326 case 1: 327 if (uvolt <= 1450000) 328 return &rk816_buck[num * 3 + 0]; 329 else if (uvolt <= 2200000) 330 return &rk816_buck[num * 3 + 1]; 331 else 332 return &rk816_buck[num * 3 + 2]; 333 default: 334 return &rk816_buck[num + 4]; 335 } 336 337 case RK809_ID: 338 case RK817_ID: 339 switch (num) { 340 case 0 ... 2: 341 if (uvolt < 1500000) 342 return &rk817_buck[num * 3 + 0]; 343 else if (uvolt < 2400000) 344 return &rk817_buck[num * 3 + 1]; 345 else 346 return &rk817_buck[num * 3 + 2]; 347 case 3: 348 if (uvolt < 1500000) 349 return &rk817_buck[num * 3 + 0]; 350 else if (uvolt < 3400000) 351 return &rk817_buck[num * 3 + 1]; 352 else 353 return &rk817_buck[num * 3 + 2]; 354 /* BUCK5 for RK809 */ 355 default: 356 if (uvolt < 1800000) 357 return &rk809_buck5[0]; 358 else if (uvolt < 2800000) 359 return &rk809_buck5[1]; 360 else if (uvolt < 3300000) 361 return &rk809_buck5[2]; 362 else 363 return &rk809_buck5[3]; 364 } 365 case RK818_ID: 366 return &rk818_buck[num]; 367 default: 368 return &rk808_buck[num]; 369 } 370 } 371 372 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt) 373 { 374 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 375 struct rk8xx_priv *priv = dev_get_priv(pmic); 376 int mask = info->vsel_mask; 377 int val; 378 379 if (info->vsel_reg == NA) 380 return -ENOSYS; 381 382 if (info->step_uv == 0) /* Fixed voltage */ 383 val = info->min_sel; 384 else 385 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 386 387 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 388 __func__, uvolt, buck + 1, info->vsel_reg, mask, val); 389 390 if (priv->variant == RK816_ID) { 391 pmic_clrsetbits(pmic, info->vsel_reg, mask, val); 392 return pmic_clrsetbits(pmic, RK816_REG_DCDC_EN2, 1 << 7, 1 << 7); 393 } else { 394 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); 395 } 396 } 397 398 static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) 399 { 400 uint mask, value, en_reg; 401 int ret; 402 struct rk8xx_priv *priv = dev_get_priv(pmic); 403 404 switch (priv->variant) { 405 case RK806_ID: 406 en_reg = RK806_POWER_EN(buck / 4); 407 if (enable) 408 value = ((1 << buck % 4) | (1 << (buck % 4 + 4))); 409 else 410 value = ((0 << buck % 4) | (1 << (buck % 4 + 4))); 411 412 ret = pmic_reg_write(pmic, en_reg, value); 413 break; 414 case RK805_ID: 415 case RK816_ID: 416 if (buck >= 4) { 417 buck -= 4; 418 en_reg = RK816_REG_DCDC_EN2; 419 } else { 420 en_reg = RK816_REG_DCDC_EN1; 421 } 422 if (enable) 423 value = ((1 << buck) | (1 << (buck + 4))); 424 else 425 value = ((0 << buck) | (1 << (buck + 4))); 426 ret = pmic_reg_write(pmic, en_reg, value); 427 break; 428 429 case RK808_ID: 430 case RK818_ID: 431 mask = 1 << buck; 432 if (enable) { 433 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 434 0, 3 << (buck * 2)); 435 if (ret) 436 return ret; 437 } 438 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask, 439 enable ? mask : 0); 440 break; 441 case RK809_ID: 442 case RK817_ID: 443 if (buck < 4) { 444 if (enable) 445 value = ((1 << buck) | (1 << (buck + 4))); 446 else 447 value = ((0 << buck) | (1 << (buck + 4))); 448 ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value); 449 /* BUCK5 for RK809 */ 450 } else { 451 if (enable) 452 value = ((1 << 1) | (1 << 5)); 453 else 454 value = ((0 << 1) | (1 << 5)); 455 ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value); 456 } 457 break; 458 default: 459 ret = -EINVAL; 460 } 461 462 return ret; 463 } 464 465 #ifdef ENABLE_DRIVER 466 static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt) 467 { 468 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt); 469 int mask = info->vsel_mask; 470 int val; 471 472 if (info->vsel_sleep_reg == NA) 473 return -ENOSYS; 474 475 if (info->step_uv == 0) 476 val = info->min_sel; 477 else 478 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 479 480 debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 481 __func__, uvolt, buck + 1, info->vsel_sleep_reg, mask, val); 482 483 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); 484 } 485 486 static int _buck_get_enable(struct udevice *pmic, int buck) 487 { 488 struct rk8xx_priv *priv = dev_get_priv(pmic); 489 uint mask = 0; 490 int ret = 0; 491 492 switch (priv->variant) { 493 case RK806_ID: 494 mask = 1 << buck % 4; 495 ret = pmic_reg_read(pmic, RK806_POWER_EN(buck / 4)); 496 break; 497 case RK805_ID: 498 case RK816_ID: 499 if (buck >= 4) { 500 mask = 1 << (buck - 4); 501 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2); 502 } else { 503 mask = 1 << buck; 504 ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1); 505 } 506 break; 507 case RK808_ID: 508 case RK818_ID: 509 mask = 1 << buck; 510 ret = pmic_reg_read(pmic, REG_DCDC_EN); 511 if (ret < 0) 512 return ret; 513 break; 514 case RK809_ID: 515 case RK817_ID: 516 if (buck < 4) { 517 mask = 1 << buck; 518 ret = pmic_reg_read(pmic, RK817_POWER_EN(0)); 519 /* BUCK5 for RK809 */ 520 } else { 521 mask = 1 << 1; 522 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 523 } 524 break; 525 } 526 527 if (ret < 0) 528 return ret; 529 530 return ret & mask ? true : false; 531 } 532 533 static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay) 534 { 535 const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0); 536 struct rk8xx_priv *priv = dev_get_priv(pmic); 537 u32 ramp_value, ramp_mask; 538 int reg_value, ramp_reg1, ramp_reg2; 539 540 if (info->config_reg == NA) 541 return -ENOSYS; 542 543 switch (priv->variant) { 544 case RK805_ID: 545 ramp_mask = RK805_RAMP_RATE_MASK; 546 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 547 switch (ramp_delay) { 548 case 0 ... 3000: 549 ramp_value = RK805_RAMP_RATE_3MV_PER_US; 550 break; 551 case 3001 ... 6000: 552 ramp_value = RK805_RAMP_RATE_6MV_PER_US; 553 break; 554 case 6001 ... 12500: 555 ramp_value = RK805_RAMP_RATE_12_5MV_PER_US; 556 break; 557 case 12501 ... 25000: 558 ramp_value = RK805_RAMP_RATE_25MV_PER_US; 559 break; 560 default: 561 printf("buck%d ramp_delay: %d not supported\n", 562 buck, ramp_delay); 563 } 564 break; 565 case RK806_ID: 566 switch (ramp_delay) { 567 case 1 ... 390: 568 ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK; 569 break; 570 case 391 ... 961: 571 ramp_value = RK806_RAMP_RATE_1LSB_PER_13CLK; 572 break; 573 case 962 ... 1560: 574 ramp_value = RK806_RAMP_RATE_1LSB_PER_8CLK; 575 break; 576 case 1561 ... 3125: 577 ramp_value = RK806_RAMP_RATE_1LSB_PER_4CLK; 578 break; 579 case 3126 ... 6250: 580 ramp_value = RK806_RAMP_RATE_1LSB_PER_2CLK; 581 break; 582 case 6251 ... 12500: 583 ramp_value = RK806_RAMP_RATE_1LSB_PER_1CLK; 584 break; 585 case 12501 ... 25000: 586 ramp_value = RK806_RAMP_RATE_2LSB_PER_1CLK; 587 break; 588 case 25001 ... 50000: /* 50mV/us */ 589 ramp_value = RK806_RAMP_RATE_4LSB_PER_1CLK; 590 break; 591 default: 592 ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK; 593 printf("buck%d ramp_delay: %d not supported\n", 594 buck, ramp_delay); 595 return -EINVAL; 596 } 597 ramp_reg1 = RK806_RAMP_RATE_REG1(buck); 598 if (buck < 8) 599 ramp_reg2 = RK806_RAMP_RATE_REG1_8; 600 else 601 ramp_reg2 = RK806_RAMP_RATE_REG9_10; 602 603 reg_value = pmic_reg_read(pmic, ramp_reg1); 604 if (reg_value < 0) { 605 printf("buck%d read ramp reg(0x%x) error: %d", buck, ramp_reg1, reg_value); 606 return reg_value; 607 } 608 reg_value &= 0x3f; 609 610 pmic_reg_write(pmic, 611 ramp_reg1, 612 reg_value | (ramp_value & 0x03) << 0x06); 613 614 reg_value = pmic_reg_read(pmic, ramp_reg2); 615 if (reg_value < 0) { 616 printf("buck%d read ramp reg(0x%x) error: %d", buck, ramp_reg2, reg_value); 617 return reg_value; 618 } 619 620 return pmic_reg_write(pmic, 621 ramp_reg2, 622 reg_value | (ramp_value & 0x04) << (buck % 8)); 623 case RK808_ID: 624 case RK816_ID: 625 case RK818_ID: 626 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 627 ramp_mask = RK808_RAMP_RATE_MASK; 628 switch (ramp_delay) { 629 case 1 ... 2000: 630 ramp_value = RK808_RAMP_RATE_2MV_PER_US; 631 break; 632 case 2001 ... 4000: 633 ramp_value = RK808_RAMP_RATE_4MV_PER_US; 634 break; 635 case 4001 ... 6000: 636 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 637 break; 638 case 6001 ... 10000: 639 ramp_value = RK808_RAMP_RATE_6MV_PER_US; 640 break; 641 default: 642 printf("buck%d ramp_delay: %d not supported\n", 643 buck, ramp_delay); 644 } 645 break; 646 case RK809_ID: 647 case RK817_ID: 648 ramp_mask = RK817_RAMP_RATE_MASK; 649 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 650 switch (ramp_delay) { 651 case 0 ... 3000: 652 ramp_value = RK817_RAMP_RATE_3MV_PER_US; 653 break; 654 case 3001 ... 6300: 655 ramp_value = RK817_RAMP_RATE_6_3MV_PER_US; 656 break; 657 case 6301 ... 12500: 658 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 659 break; 660 case 12501 ... 25000: 661 ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 662 break; 663 default: 664 printf("buck%d ramp_delay: %d not supported\n", 665 buck, ramp_delay); 666 } 667 break; 668 default: 669 return -EINVAL; 670 } 671 672 return pmic_clrsetbits(pmic, info->config_reg, ramp_mask, ramp_value); 673 } 674 675 static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) 676 { 677 uint mask; 678 int ret; 679 struct rk8xx_priv *priv = dev_get_priv(pmic); 680 681 switch (priv->variant) { 682 case RK805_ID: 683 case RK816_ID: 684 mask = 1 << buck; 685 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask, 686 enable ? mask : 0); 687 break; 688 case RK806_ID: 689 if (buck <= 7) { 690 mask = 1 << buck; 691 ret = pmic_clrsetbits(pmic, RK806_BUCK_SUSPEND_EN, mask, 692 enable ? mask : 0); 693 } else { 694 if (buck == 8) 695 mask = 0x40; 696 else 697 mask = 0x80; 698 ret = pmic_clrsetbits(pmic, RK806_NLDO_SUSPEND_EN, mask, 699 enable ? mask : 0); 700 } 701 break; 702 case RK808_ID: 703 case RK818_ID: 704 mask = 1 << buck; 705 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask, 706 enable ? 0 : mask); 707 break; 708 case RK809_ID: 709 case RK817_ID: 710 if (buck < 4) 711 mask = 1 << buck; 712 else 713 mask = 1 << 5; /* BUCK5 for RK809 */ 714 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 715 enable ? mask : 0); 716 break; 717 default: 718 ret = -EINVAL; 719 } 720 721 return ret; 722 } 723 724 static int _buck_get_suspend_enable(struct udevice *pmic, int buck) 725 { 726 struct rk8xx_priv *priv = dev_get_priv(pmic); 727 int ret, val; 728 uint mask; 729 730 switch (priv->variant) { 731 case RK805_ID: 732 case RK816_ID: 733 mask = 1 << buck; 734 val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN); 735 if (val < 0) 736 return val; 737 ret = val & mask ? 1 : 0; 738 break; 739 case RK806_ID: 740 if (buck <= 7) { 741 mask = 1 << buck % 7; 742 val = pmic_reg_read(pmic, RK806_BUCK_SUSPEND_EN); 743 } else { 744 mask = 1 << ((buck - 7) + 6); 745 val = pmic_reg_read(pmic, RK806_NLDO_SUSPEND_EN); 746 } 747 748 if (val < 0) 749 return val; 750 ret = val & mask ? 1 : 0; 751 break; 752 case RK808_ID: 753 case RK818_ID: 754 mask = 1 << buck; 755 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1); 756 if (val < 0) 757 return val; 758 ret = val & mask ? 0 : 1; 759 break; 760 case RK809_ID: 761 case RK817_ID: 762 if (buck < 4) 763 mask = 1 << buck; 764 else 765 mask = 1 << 5; /* BUCK5 for RK809 */ 766 767 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); 768 if (val < 0) 769 return val; 770 ret = val & mask ? 1 : 0; 771 break; 772 default: 773 ret = -EINVAL; 774 } 775 776 return ret; 777 } 778 779 static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, 780 int num, int uvolt) 781 { 782 struct rk8xx_priv *priv = dev_get_priv(pmic); 783 784 switch (priv->variant) { 785 case RK805_ID: 786 case RK816_ID: 787 return &rk816_ldo[num]; 788 case RK806_ID: 789 if (uvolt < 3400000) 790 return &rk806_nldo[num * 2]; 791 else 792 return &rk806_nldo[num * 2 + 1]; 793 case RK809_ID: 794 case RK817_ID: 795 if (uvolt < 3400000) 796 return &rk817_ldo[num * 2 + 0]; 797 else 798 return &rk817_ldo[num * 2 + 1]; 799 case RK818_ID: 800 return &rk818_ldo[num]; 801 default: 802 return &rk808_ldo[num]; 803 } 804 } 805 806 static int _ldo_get_enable(struct udevice *pmic, int ldo) 807 { 808 struct rk8xx_priv *priv = dev_get_priv(pmic); 809 uint mask = 0; 810 int ret = 0; 811 812 switch (priv->variant) { 813 case RK805_ID: 814 case RK816_ID: 815 if (ldo >= 4) { 816 mask = 1 << (ldo - 4); 817 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2); 818 } else { 819 mask = 1 << ldo; 820 ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1); 821 } 822 break; 823 case RK806_ID: 824 if (ldo < 4) { 825 mask = 1 << ldo % 4; 826 ret = pmic_reg_read(pmic, RK806_NLDO_EN(ldo / 4)); 827 } else { 828 mask = 1 << 2; 829 ret = pmic_reg_read(pmic, RK806_NLDO_EN(2)); 830 } 831 break; 832 case RK808_ID: 833 case RK818_ID: 834 mask = 1 << ldo; 835 ret = pmic_reg_read(pmic, REG_LDO_EN); 836 if (ret < 0) 837 return ret; 838 break; 839 case RK809_ID: 840 case RK817_ID: 841 if (ldo < 4) { 842 mask = 1 << ldo; 843 ret = pmic_reg_read(pmic, RK817_POWER_EN(1)); 844 } else if (ldo < 8) { 845 mask = 1 << (ldo - 4); 846 ret = pmic_reg_read(pmic, RK817_POWER_EN(2)); 847 } else if (ldo == 8) { 848 mask = 1 << 0; 849 ret = pmic_reg_read(pmic, RK817_POWER_EN(3)); 850 } else { 851 return false; 852 } 853 break; 854 } 855 856 if (ret < 0) 857 return ret; 858 859 return ret & mask ? true : false; 860 } 861 862 static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable) 863 { 864 struct rk8xx_priv *priv = dev_get_priv(pmic); 865 uint mask, value, en_reg; 866 int ret = 0; 867 868 switch (priv->variant) { 869 case RK805_ID: 870 case RK816_ID: 871 if (ldo >= 4) { 872 ldo -= 4; 873 en_reg = RK816_REG_LDO_EN2; 874 } else { 875 en_reg = RK816_REG_LDO_EN1; 876 } 877 if (enable) 878 value = ((1 << ldo) | (1 << (ldo + 4))); 879 else 880 value = ((0 << ldo) | (1 << (ldo + 4))); 881 882 ret = pmic_reg_write(pmic, en_reg, value); 883 break; 884 case RK806_ID: 885 if (ldo < 4) { 886 en_reg = RK806_NLDO_EN(0); 887 if (enable) 888 value = ((1 << ldo % 4) | (1 << (ldo % 4 + 4))); 889 else 890 value = ((0 << ldo % 4) | (1 << (ldo % 4 + 4))); 891 ret = pmic_reg_write(pmic, en_reg, value); 892 } else { 893 en_reg = RK806_NLDO_EN(2); 894 if (enable) 895 value = 0x44; 896 else 897 value = 0x40; 898 ret = pmic_reg_write(pmic, en_reg, value); 899 } 900 break; 901 case RK808_ID: 902 case RK818_ID: 903 mask = 1 << ldo; 904 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask, 905 enable ? mask : 0); 906 break; 907 case RK809_ID: 908 case RK817_ID: 909 if (ldo < 4) { 910 en_reg = RK817_POWER_EN(1); 911 } else if (ldo < 8) { 912 ldo -= 4; 913 en_reg = RK817_POWER_EN(2); 914 } else if (ldo == 8) { 915 ldo = 0; /* BIT 0 */ 916 en_reg = RK817_POWER_EN(3); 917 } else { 918 return -EINVAL; 919 } 920 if (enable) 921 value = ((1 << ldo) | (1 << (ldo + 4))); 922 else 923 value = ((0 << ldo) | (1 << (ldo + 4))); 924 ret = pmic_reg_write(pmic, en_reg, value); 925 break; 926 } 927 928 if (enable) 929 udelay(500); 930 931 return ret; 932 } 933 934 static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable) 935 { 936 struct rk8xx_priv *priv = dev_get_priv(pmic); 937 uint mask; 938 int ret = 0; 939 940 switch (priv->variant) { 941 case RK805_ID: 942 case RK816_ID: 943 mask = 1 << ldo; 944 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask, 945 enable ? mask : 0); 946 break; 947 case RK806_ID: 948 mask = 1 << ldo; 949 ret = pmic_clrsetbits(pmic, RK806_NLDO_SUSPEND_EN, mask, 950 enable ? mask : 0); 951 break; 952 case RK808_ID: 953 case RK818_ID: 954 mask = 1 << ldo; 955 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask, 956 enable ? 0 : mask); 957 break; 958 case RK809_ID: 959 case RK817_ID: 960 if (ldo == 8) { 961 mask = 1 << 4; /* LDO9 */ 962 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, 963 enable ? mask : 0); 964 } else { 965 mask = 1 << ldo; 966 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask, 967 enable ? mask : 0); 968 } 969 break; 970 } 971 972 return ret; 973 } 974 975 static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) 976 { 977 struct rk8xx_priv *priv = dev_get_priv(pmic); 978 int val, ret = 0; 979 uint mask; 980 981 switch (priv->variant) { 982 case RK805_ID: 983 case RK816_ID: 984 mask = 1 << ldo; 985 val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN); 986 if (val < 0) 987 return val; 988 ret = val & mask ? 1 : 0; 989 break; 990 case RK806_ID: 991 mask = 1 << ldo; 992 val = pmic_reg_read(pmic, RK806_NLDO_SUSPEND_EN); 993 994 if (val < 0) 995 return val; 996 ret = val & mask ? 1 : 0; 997 break; 998 case RK808_ID: 999 case RK818_ID: 1000 mask = 1 << ldo; 1001 val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2); 1002 if (val < 0) 1003 return val; 1004 ret = val & mask ? 0 : 1; 1005 break; 1006 case RK809_ID: 1007 case RK817_ID: 1008 if (ldo == 8) { 1009 mask = 1 << 4; /* LDO9 */ 1010 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); 1011 if (val < 0) 1012 return val; 1013 ret = val & mask ? 1 : 0; 1014 } else { 1015 mask = 1 << ldo; 1016 val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1)); 1017 if (val < 0) 1018 return val; 1019 ret = val & mask ? 1 : 0; 1020 } 1021 break; 1022 } 1023 1024 return ret; 1025 } 1026 1027 static int buck_get_value(struct udevice *dev) 1028 { 1029 int buck = dev->driver_data - 1; 1030 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 1031 int mask = info->vsel_mask; 1032 int i, ret, val; 1033 1034 if (info->vsel_reg == NA) 1035 return -ENOSYS; 1036 1037 ret = pmic_reg_read(dev->parent, info->vsel_reg); 1038 if (ret < 0) 1039 return ret; 1040 1041 val = ret & mask; 1042 if (val >= info->min_sel && val <= info->max_sel) 1043 goto finish; 1044 1045 /* unlucky to try */ 1046 for (i = 1; i < info->range_num; i++) { 1047 info++; 1048 if (val <= info->max_sel && val >= info->min_sel) 1049 break; 1050 } 1051 1052 finish: 1053 return info->min_uv + (val - info->min_sel) * info->step_uv; 1054 } 1055 1056 static int buck_set_value(struct udevice *dev, int uvolt) 1057 { 1058 int buck = dev->driver_data - 1; 1059 1060 return _buck_set_value(dev->parent, buck, uvolt); 1061 } 1062 1063 static int buck_get_suspend_value(struct udevice *dev) 1064 { 1065 int buck = dev->driver_data - 1; 1066 const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0); 1067 int mask = info->vsel_mask; 1068 int i, ret, val; 1069 1070 if (info->vsel_sleep_reg == NA) 1071 return -ENOSYS; 1072 1073 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg); 1074 if (ret < 0) 1075 return ret; 1076 1077 val = ret & mask; 1078 if (val <= info->max_sel && val >= info->min_sel) 1079 goto finish; 1080 1081 /* unlucky to try */ 1082 for (i = 1; i < info->range_num; i++) { 1083 info++; 1084 if (val <= info->max_sel && val >= info->min_sel) 1085 break; 1086 } 1087 1088 finish: 1089 return info->min_uv + (val - info->min_sel) * info->step_uv; 1090 } 1091 1092 static int buck_set_suspend_value(struct udevice *dev, int uvolt) 1093 { 1094 int buck = dev->driver_data - 1; 1095 1096 return _buck_set_suspend_value(dev->parent, buck, uvolt); 1097 } 1098 1099 static int buck_set_enable(struct udevice *dev, bool enable) 1100 { 1101 int buck = dev->driver_data - 1; 1102 1103 return _buck_set_enable(dev->parent, buck, enable); 1104 } 1105 1106 static int buck_set_suspend_enable(struct udevice *dev, bool enable) 1107 { 1108 int buck = dev->driver_data - 1; 1109 1110 return _buck_set_suspend_enable(dev->parent, buck, enable); 1111 } 1112 1113 static int buck_get_suspend_enable(struct udevice *dev) 1114 { 1115 int buck = dev->driver_data - 1; 1116 1117 return _buck_get_suspend_enable(dev->parent, buck); 1118 } 1119 1120 static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay) 1121 { 1122 int buck = dev->driver_data - 1; 1123 1124 return _buck_set_ramp_delay(dev->parent, buck, ramp_delay); 1125 } 1126 1127 static int buck_get_enable(struct udevice *dev) 1128 { 1129 int buck = dev->driver_data - 1; 1130 1131 return _buck_get_enable(dev->parent, buck); 1132 } 1133 1134 static int ldo_get_value(struct udevice *dev) 1135 { 1136 int ldo = dev->driver_data - 1; 1137 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); 1138 int mask = info->vsel_mask; 1139 int ret, val; 1140 1141 if (info->vsel_reg == NA) 1142 return -ENOSYS; 1143 ret = pmic_reg_read(dev->parent, info->vsel_reg); 1144 if (ret < 0) 1145 return ret; 1146 val = ret & mask; 1147 1148 return info->min_uv + val * info->step_uv; 1149 } 1150 1151 static int ldo_set_value(struct udevice *dev, int uvolt) 1152 { 1153 int ldo = dev->driver_data - 1; 1154 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 1155 int mask = info->vsel_mask; 1156 int val; 1157 1158 if (info->vsel_reg == NA) 1159 return -ENOSYS; 1160 1161 if (info->step_uv == 0) 1162 val = info->min_sel; 1163 else 1164 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 1165 1166 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 1167 __func__, uvolt, ldo + 1, info->vsel_reg, mask, val); 1168 1169 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); 1170 } 1171 1172 static int ldo_set_suspend_value(struct udevice *dev, int uvolt) 1173 { 1174 int ldo = dev->driver_data - 1; 1175 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); 1176 int mask = info->vsel_mask; 1177 int val; 1178 1179 if (info->vsel_sleep_reg == NA) 1180 return -ENOSYS; 1181 1182 if (info->step_uv == 0) 1183 val = info->min_sel; 1184 else 1185 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 1186 1187 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 1188 __func__, uvolt, ldo + 1, info->vsel_sleep_reg, mask, val); 1189 1190 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); 1191 } 1192 1193 static int ldo_get_suspend_value(struct udevice *dev) 1194 { 1195 int ldo = dev->driver_data - 1; 1196 const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); 1197 int mask = info->vsel_mask; 1198 int val, ret; 1199 1200 if (info->vsel_sleep_reg == NA) 1201 return -ENOSYS; 1202 1203 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg); 1204 if (ret < 0) 1205 return ret; 1206 1207 val = ret & mask; 1208 1209 return info->min_uv + val * info->step_uv; 1210 } 1211 1212 static int ldo_set_enable(struct udevice *dev, bool enable) 1213 { 1214 int ldo = dev->driver_data - 1; 1215 1216 return _ldo_set_enable(dev->parent, ldo, enable); 1217 } 1218 1219 static int ldo_set_suspend_enable(struct udevice *dev, bool enable) 1220 { 1221 int ldo = dev->driver_data - 1; 1222 1223 return _ldo_set_suspend_enable(dev->parent, ldo, enable); 1224 } 1225 1226 static int ldo_get_suspend_enable(struct udevice *dev) 1227 { 1228 int ldo = dev->driver_data - 1; 1229 1230 return _ldo_get_suspend_enable(dev->parent, ldo); 1231 } 1232 1233 static int ldo_get_enable(struct udevice *dev) 1234 { 1235 int ldo = dev->driver_data - 1; 1236 1237 return _ldo_get_enable(dev->parent, ldo); 1238 } 1239 1240 static int switch_set_enable(struct udevice *dev, bool enable) 1241 { 1242 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1243 int ret = 0, sw = dev->driver_data - 1; 1244 uint mask = 0; 1245 1246 switch (priv->variant) { 1247 case RK808_ID: 1248 mask = 1 << (sw + 5); 1249 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 1250 enable ? mask : 0); 1251 break; 1252 case RK809_ID: 1253 mask = (1 << (sw + 2)) | (1 << (sw + 6)); 1254 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask, 1255 enable ? mask : (1 << (sw + 6))); 1256 break; 1257 case RK818_ID: 1258 mask = 1 << 6; 1259 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, 1260 enable ? mask : 0); 1261 break; 1262 } 1263 1264 debug("%s: switch%d, enable=%d, mask=0x%x\n", 1265 __func__, sw + 1, enable, mask); 1266 1267 return ret; 1268 } 1269 1270 static int switch_get_enable(struct udevice *dev) 1271 { 1272 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1273 int ret = 0, sw = dev->driver_data - 1; 1274 uint mask = 0; 1275 1276 switch (priv->variant) { 1277 case RK808_ID: 1278 mask = 1 << (sw + 5); 1279 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 1280 break; 1281 case RK809_ID: 1282 mask = 1 << (sw + 2); 1283 ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3)); 1284 break; 1285 case RK818_ID: 1286 mask = 1 << 6; 1287 ret = pmic_reg_read(dev->parent, REG_DCDC_EN); 1288 break; 1289 } 1290 1291 if (ret < 0) 1292 return ret; 1293 1294 return ret & mask ? true : false; 1295 } 1296 1297 static int switch_set_suspend_value(struct udevice *dev, int uvolt) 1298 { 1299 return 0; 1300 } 1301 1302 static int switch_get_suspend_value(struct udevice *dev) 1303 { 1304 return 0; 1305 } 1306 1307 static int switch_set_suspend_enable(struct udevice *dev, bool enable) 1308 { 1309 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1310 int ret = 0, sw = dev->driver_data - 1; 1311 uint mask = 0; 1312 1313 switch (priv->variant) { 1314 case RK808_ID: 1315 mask = 1 << (sw + 5); 1316 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 1317 enable ? 0 : mask); 1318 break; 1319 case RK809_ID: 1320 mask = 1 << (sw + 6); 1321 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask, 1322 enable ? mask : 0); 1323 break; 1324 case RK818_ID: 1325 mask = 1 << 6; 1326 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, 1327 enable ? 0 : mask); 1328 break; 1329 } 1330 1331 debug("%s: switch%d, enable=%d, mask=0x%x\n", 1332 __func__, sw + 1, enable, mask); 1333 1334 return ret; 1335 } 1336 1337 static int switch_get_suspend_enable(struct udevice *dev) 1338 { 1339 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1340 int val, ret = 0, sw = dev->driver_data - 1; 1341 uint mask = 0; 1342 1343 switch (priv->variant) { 1344 case RK808_ID: 1345 mask = 1 << (sw + 5); 1346 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); 1347 if (val < 0) 1348 return val; 1349 ret = val & mask ? 0 : 1; 1350 break; 1351 case RK809_ID: 1352 mask = 1 << (sw + 6); 1353 val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0)); 1354 if (val < 0) 1355 return val; 1356 ret = val & mask ? 1 : 0; 1357 break; 1358 case RK818_ID: 1359 mask = 1 << 6; 1360 val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); 1361 if (val < 0) 1362 return val; 1363 ret = val & mask ? 0 : 1; 1364 break; 1365 } 1366 1367 return ret; 1368 } 1369 1370 /* 1371 * RK8xx switch does not need to set the voltage, 1372 * but if dts set regulator-min-microvolt/regulator-max-microvolt, 1373 * will cause regulator set value fail and not to enable this switch. 1374 * So add an empty function to return success. 1375 */ 1376 static int switch_get_value(struct udevice *dev) 1377 { 1378 const char *supply_name[] = { "vcc9-supply", "vcc8-supply", }; 1379 struct rk8xx_priv *priv = dev_get_priv(dev->parent); 1380 struct udevice *supply; 1381 int id = dev->driver_data - 1; 1382 1383 if (!switch_get_enable(dev)) 1384 return 0; 1385 1386 /* note: rk817 only contains switch0 */ 1387 if ((priv->variant == RK809_ID) || (priv->variant == RK817_ID)) { 1388 if (!uclass_get_device_by_phandle(UCLASS_REGULATOR, 1389 dev_get_parent(dev), 1390 supply_name[id], 1391 &supply)) 1392 return regulator_get_value(supply); 1393 } 1394 1395 return 0; 1396 } 1397 1398 static int switch_set_value(struct udevice *dev, int uvolt) 1399 { 1400 return 0; 1401 } 1402 1403 static const struct rk8xx_reg_info *get_pldo_reg(struct udevice *pmic, 1404 int num, int uvolt) 1405 { 1406 struct rk8xx_priv *priv = dev_get_priv(pmic); 1407 1408 switch (priv->variant) { 1409 case RK806_ID: 1410 if (uvolt < 3400000) 1411 return &rk806_pldo[num * 2]; 1412 else 1413 return &rk806_pldo[num * 2 + 1]; 1414 default: 1415 return &rk806_pldo[num * 2]; 1416 } 1417 } 1418 1419 static int _pldo_get_enable(struct udevice *pmic, int pldo) 1420 { 1421 struct rk8xx_priv *priv = dev_get_priv(pmic); 1422 uint mask = 0, en_reg; 1423 int ret = 0; 1424 1425 switch (priv->variant) { 1426 case RK806_ID: 1427 if ((pldo < 3) || (pldo == 5)) { 1428 en_reg = RK806_PLDO_EN(0); 1429 mask = RK806_PLDO0_2_SET(pldo); 1430 if (pldo == 5) 1431 mask = (1 << 0); 1432 ret = pmic_reg_read(pmic, en_reg); 1433 } else if ((pldo == 3) || (pldo == 4)) { 1434 en_reg = RK806_PLDO_EN(1); 1435 if (pldo == 3) 1436 mask = (1 << 0); 1437 else 1438 mask = (1 << 1); 1439 ret = pmic_reg_read(pmic, en_reg); 1440 } 1441 break; 1442 1443 default: 1444 return -EINVAL; 1445 } 1446 1447 if (ret < 0) 1448 return ret; 1449 1450 return ret & mask ? true : false; 1451 } 1452 1453 static int _pldo_set_enable(struct udevice *pmic, int pldo, bool enable) 1454 { 1455 struct rk8xx_priv *priv = dev_get_priv(pmic); 1456 uint value, en_reg; 1457 int ret = 0; 1458 1459 switch (priv->variant) { 1460 case RK806_ID: 1461 if (pldo < 3) { 1462 en_reg = RK806_PLDO_EN(0); 1463 if (enable) 1464 value = RK806_PLDO0_2_SET(pldo); 1465 else 1466 value = RK806_PLDO0_2_CLR(pldo); 1467 ret = pmic_reg_write(pmic, en_reg, value); 1468 } else if (pldo == 3) { 1469 en_reg = RK806_PLDO_EN(1); 1470 if (enable) 1471 value = ((1 << 0) | (1 << 4)); 1472 else 1473 value = (1 << 4); 1474 ret = pmic_reg_write(pmic, en_reg, value); 1475 } else if (pldo == 4) { 1476 en_reg = RK806_PLDO_EN(1); 1477 if (enable) 1478 value = ((1 << 1) | (1 << 5)); 1479 else 1480 value = ((0 << 1) | (1 << 5)); 1481 ret = pmic_reg_write(pmic, en_reg, value); 1482 } else if (pldo == 5) { 1483 en_reg = RK806_PLDO_EN(0); 1484 if (enable) 1485 value = ((1 << 0) | (1 << 4)); 1486 else 1487 value = ((0 << 0) | (1 << 4)); 1488 ret = pmic_reg_write(pmic, en_reg, value); 1489 } 1490 1491 break; 1492 default: 1493 return -EINVAL; 1494 } 1495 1496 return ret; 1497 } 1498 1499 static int pldo_get_value(struct udevice *dev) 1500 { 1501 int ldo = dev->driver_data - 1; 1502 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, 0); 1503 int mask = info->vsel_mask; 1504 int ret, val; 1505 1506 if (info->vsel_reg == NA) 1507 return -EINVAL; 1508 1509 ret = pmic_reg_read(dev->parent, info->vsel_reg); 1510 if (ret < 0) 1511 return ret; 1512 val = ret & mask; 1513 1514 return info->min_uv + val * info->step_uv; 1515 } 1516 1517 static int pldo_set_value(struct udevice *dev, int uvolt) 1518 { 1519 int ldo = dev->driver_data - 1; 1520 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, uvolt); 1521 int mask = info->vsel_mask; 1522 int val; 1523 1524 if (info->vsel_reg == NA) 1525 return -EINVAL; 1526 1527 if (info->step_uv == 0) 1528 val = info->min_sel; 1529 else 1530 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 1531 1532 debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", 1533 __func__, uvolt, ldo + 1, info->vsel_reg, mask, val); 1534 1535 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); 1536 } 1537 1538 static int pldo_set_enable(struct udevice *dev, bool enable) 1539 { 1540 int ldo = dev->driver_data - 1; 1541 1542 return _pldo_set_enable(dev->parent, ldo, enable); 1543 } 1544 1545 static int pldo_get_enable(struct udevice *dev) 1546 { 1547 int ldo = dev->driver_data - 1; 1548 1549 return _pldo_get_enable(dev->parent, ldo); 1550 } 1551 1552 static int pldo_set_suspend_value(struct udevice *dev, int uvolt) 1553 { 1554 int ldo = dev->driver_data - 1; 1555 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, uvolt);; 1556 int mask = info->vsel_mask; 1557 int val; 1558 1559 if (info->vsel_sleep_reg == NA) 1560 return -EINVAL; 1561 1562 if (info->step_uv == 0) 1563 val = info->min_sel; 1564 else 1565 val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; 1566 1567 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); 1568 } 1569 1570 static int pldo_get_suspend_value(struct udevice *dev) 1571 { 1572 int ldo = dev->driver_data - 1; 1573 const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, ldo, 0); 1574 int mask = info->vsel_mask; 1575 int val, ret; 1576 1577 if (info->vsel_sleep_reg == NA) 1578 return -EINVAL; 1579 1580 ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg); 1581 if (ret < 0) 1582 return ret; 1583 1584 val = ret & mask; 1585 1586 return info->min_uv + val * info->step_uv; 1587 } 1588 1589 static int _pldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable) 1590 { 1591 uint mask; 1592 int ret; 1593 1594 if (ldo < 5) 1595 mask = 1 << (ldo + 1); 1596 else 1597 mask = 1; 1598 ret = pmic_clrsetbits(pmic, RK806_PLDO_SUSPEND_EN, mask, 1599 enable ? mask : 0); 1600 1601 return ret; 1602 } 1603 1604 static int _pldo_get_suspend_enable(struct udevice *pmic, int ldo) 1605 { 1606 uint mask, val; 1607 int ret; 1608 1609 if (ldo < 5) 1610 mask = 1 << (ldo + 1); 1611 else 1612 mask = 1; 1613 val = pmic_reg_read(pmic, RK806_PLDO_SUSPEND_EN); 1614 1615 if (val < 0) 1616 return val; 1617 ret = val & mask ? 1 : 0; 1618 1619 return ret; 1620 } 1621 static int pldo_set_suspend_enable(struct udevice *dev, bool enable) 1622 { 1623 int ldo = dev->driver_data - 1; 1624 1625 return _pldo_set_suspend_enable(dev->parent, ldo, enable); 1626 } 1627 1628 static int pldo_get_suspend_enable(struct udevice *dev) 1629 { 1630 int ldo = dev->driver_data - 1; 1631 1632 return _pldo_get_suspend_enable(dev->parent, ldo); 1633 } 1634 1635 static int rk8xx_buck_probe(struct udevice *dev) 1636 { 1637 struct dm_regulator_uclass_platdata *uc_pdata; 1638 1639 uc_pdata = dev_get_uclass_platdata(dev); 1640 1641 uc_pdata->type = REGULATOR_TYPE_BUCK; 1642 uc_pdata->mode_count = 0; 1643 1644 return 0; 1645 } 1646 1647 static int rk8xx_ldo_probe(struct udevice *dev) 1648 { 1649 struct dm_regulator_uclass_platdata *uc_pdata; 1650 1651 uc_pdata = dev_get_uclass_platdata(dev); 1652 1653 uc_pdata->type = REGULATOR_TYPE_LDO; 1654 uc_pdata->mode_count = 0; 1655 1656 return 0; 1657 } 1658 1659 static int rk8xx_switch_probe(struct udevice *dev) 1660 { 1661 struct dm_regulator_uclass_platdata *uc_pdata; 1662 1663 uc_pdata = dev_get_uclass_platdata(dev); 1664 1665 uc_pdata->type = REGULATOR_TYPE_FIXED; 1666 uc_pdata->mode_count = 0; 1667 1668 return 0; 1669 } 1670 1671 static int rk8xx_pldo_probe(struct udevice *dev) 1672 { 1673 struct dm_regulator_uclass_platdata *uc_pdata; 1674 1675 uc_pdata = dev_get_uclass_platdata(dev); 1676 uc_pdata->type = REGULATOR_TYPE_LDO; 1677 uc_pdata->mode_count = 0; 1678 1679 return 0; 1680 } 1681 1682 static const struct dm_regulator_ops rk8xx_buck_ops = { 1683 .get_value = buck_get_value, 1684 .set_value = buck_set_value, 1685 .set_suspend_value = buck_set_suspend_value, 1686 .get_suspend_value = buck_get_suspend_value, 1687 .get_enable = buck_get_enable, 1688 .set_enable = buck_set_enable, 1689 .set_suspend_enable = buck_set_suspend_enable, 1690 .get_suspend_enable = buck_get_suspend_enable, 1691 .set_ramp_delay = buck_set_ramp_delay, 1692 }; 1693 1694 static const struct dm_regulator_ops rk8xx_ldo_ops = { 1695 .get_value = ldo_get_value, 1696 .set_value = ldo_set_value, 1697 .set_suspend_value = ldo_set_suspend_value, 1698 .get_suspend_value = ldo_get_suspend_value, 1699 .get_enable = ldo_get_enable, 1700 .set_enable = ldo_set_enable, 1701 .set_suspend_enable = ldo_set_suspend_enable, 1702 .get_suspend_enable = ldo_get_suspend_enable, 1703 }; 1704 1705 static const struct dm_regulator_ops rk8xx_switch_ops = { 1706 .get_value = switch_get_value, 1707 .set_value = switch_set_value, 1708 .get_enable = switch_get_enable, 1709 .set_enable = switch_set_enable, 1710 .set_suspend_enable = switch_set_suspend_enable, 1711 .get_suspend_enable = switch_get_suspend_enable, 1712 .set_suspend_value = switch_set_suspend_value, 1713 .get_suspend_value = switch_get_suspend_value, 1714 }; 1715 1716 static const struct dm_regulator_ops rk8xx_pldo_ops = { 1717 .get_value = pldo_get_value, 1718 .set_value = pldo_set_value, 1719 .set_suspend_value = pldo_set_suspend_value, 1720 .get_suspend_value = pldo_get_suspend_value, 1721 .get_enable = pldo_get_enable, 1722 .set_enable = pldo_set_enable, 1723 .set_suspend_enable = pldo_set_suspend_enable, 1724 .get_suspend_enable = pldo_get_suspend_enable, 1725 }; 1726 1727 U_BOOT_DRIVER(rk8xx_buck) = { 1728 .name = "rk8xx_buck", 1729 .id = UCLASS_REGULATOR, 1730 .ops = &rk8xx_buck_ops, 1731 .probe = rk8xx_buck_probe, 1732 }; 1733 1734 U_BOOT_DRIVER(rk8xx_ldo) = { 1735 .name = "rk8xx_ldo", 1736 .id = UCLASS_REGULATOR, 1737 .ops = &rk8xx_ldo_ops, 1738 .probe = rk8xx_ldo_probe, 1739 }; 1740 1741 U_BOOT_DRIVER(rk8xx_switch) = { 1742 .name = "rk8xx_switch", 1743 .id = UCLASS_REGULATOR, 1744 .ops = &rk8xx_switch_ops, 1745 .probe = rk8xx_switch_probe, 1746 }; 1747 1748 U_BOOT_DRIVER(rk8xx_spi_pldo) = { 1749 .name = "rk8xx_pldo", 1750 .id = UCLASS_REGULATOR, 1751 .ops = &rk8xx_pldo_ops, 1752 .probe = rk8xx_pldo_probe, 1753 }; 1754 #endif 1755 1756 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt) 1757 { 1758 int ret; 1759 1760 ret = _buck_set_value(pmic, buck, uvolt); 1761 if (ret) 1762 return ret; 1763 1764 return _buck_set_enable(pmic, buck, true); 1765 } 1766 1767 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma) 1768 { 1769 uint i; 1770 1771 for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++) 1772 if (current_ma <= rk818_chrg_cur_input_array[i]) 1773 break; 1774 1775 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); 1776 } 1777 1778 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt) 1779 { 1780 uint i; 1781 1782 for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++) 1783 if (uvolt <= rk818_chrg_shutdown_vsel_array[i]) 1784 break; 1785 1786 return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, 1787 i); 1788 } 1789