xref: /rk3399_rockchip-uboot/drivers/power/power_delivery/tcpci.h (revision a2c816168781679673113f0036de72b906b415b6)
1*a2c81616SWang Jie /* SPDX-License-Identifier: GPL-2.0+ */
2*a2c81616SWang Jie /*
3*a2c81616SWang Jie  * Copyright 2015-2017 Google, Inc
4*a2c81616SWang Jie  *
5*a2c81616SWang Jie  * USB Type-C Port Controller Interface.
6*a2c81616SWang Jie  */
7*a2c81616SWang Jie 
8*a2c81616SWang Jie #ifndef __LINUX_USB_TCPCI_H
9*a2c81616SWang Jie #define __LINUX_USB_TCPCI_H
10*a2c81616SWang Jie 
11*a2c81616SWang Jie #define TCPC_VENDOR_ID			0x0
12*a2c81616SWang Jie #define TCPC_PRODUCT_ID			0x2
13*a2c81616SWang Jie #define TCPC_BCD_DEV			0x4
14*a2c81616SWang Jie #define TCPC_TC_REV			0x6
15*a2c81616SWang Jie #define TCPC_PD_REV			0x8
16*a2c81616SWang Jie #define TCPC_PD_INT_REV			0xa
17*a2c81616SWang Jie 
18*a2c81616SWang Jie #define TCPC_ALERT			0x10
19*a2c81616SWang Jie #define TCPC_ALERT_VBUS_DISCNCT		BIT(11)
20*a2c81616SWang Jie #define TCPC_ALERT_RX_BUF_OVF		BIT(10)
21*a2c81616SWang Jie #define TCPC_ALERT_FAULT		BIT(9)
22*a2c81616SWang Jie #define TCPC_ALERT_V_ALARM_LO		BIT(8)
23*a2c81616SWang Jie #define TCPC_ALERT_V_ALARM_HI		BIT(7)
24*a2c81616SWang Jie #define TCPC_ALERT_TX_SUCCESS		BIT(6)
25*a2c81616SWang Jie #define TCPC_ALERT_TX_DISCARDED		BIT(5)
26*a2c81616SWang Jie #define TCPC_ALERT_TX_FAILED		BIT(4)
27*a2c81616SWang Jie #define TCPC_ALERT_RX_HARD_RST		BIT(3)
28*a2c81616SWang Jie #define TCPC_ALERT_RX_STATUS		BIT(2)
29*a2c81616SWang Jie #define TCPC_ALERT_POWER_STATUS		BIT(1)
30*a2c81616SWang Jie #define TCPC_ALERT_CC_STATUS		BIT(0)
31*a2c81616SWang Jie 
32*a2c81616SWang Jie #define TCPC_ALERT_MASK			0x12
33*a2c81616SWang Jie #define TCPC_POWER_STATUS_MASK		0x14
34*a2c81616SWang Jie #define TCPC_FAULT_STATUS_MASK		0x15
35*a2c81616SWang Jie #define TCPC_CONFIG_STD_OUTPUT		0x18
36*a2c81616SWang Jie 
37*a2c81616SWang Jie #define TCPC_TCPC_CTRL			0x19
38*a2c81616SWang Jie #define TCPC_TCPC_CTRL_ORIENTATION	BIT(0)
39*a2c81616SWang Jie 
40*a2c81616SWang Jie #define TCPC_ROLE_CTRL			0x1a
41*a2c81616SWang Jie #define TCPC_ROLE_CTRL_DRP		BIT(6)
42*a2c81616SWang Jie #define TCPC_ROLE_CTRL_RP_VAL_SHIFT	4
43*a2c81616SWang Jie #define TCPC_ROLE_CTRL_RP_VAL_MASK	0x3
44*a2c81616SWang Jie #define TCPC_ROLE_CTRL_RP_VAL_DEF	0x0
45*a2c81616SWang Jie #define TCPC_ROLE_CTRL_RP_VAL_1_5	0x1
46*a2c81616SWang Jie #define TCPC_ROLE_CTRL_RP_VAL_3_0	0x2
47*a2c81616SWang Jie #define TCPC_ROLE_CTRL_CC2_SHIFT	2
48*a2c81616SWang Jie #define TCPC_ROLE_CTRL_CC2_MASK		0x3
49*a2c81616SWang Jie #define TCPC_ROLE_CTRL_CC1_SHIFT	0
50*a2c81616SWang Jie #define TCPC_ROLE_CTRL_CC1_MASK		0x3
51*a2c81616SWang Jie #define TCPC_ROLE_CTRL_CC_RA		0x0
52*a2c81616SWang Jie #define TCPC_ROLE_CTRL_CC_RP		0x1
53*a2c81616SWang Jie #define TCPC_ROLE_CTRL_CC_RD		0x2
54*a2c81616SWang Jie #define TCPC_ROLE_CTRL_CC_OPEN		0x3
55*a2c81616SWang Jie 
56*a2c81616SWang Jie #define TCPC_FAULT_CTRL			0x1b
57*a2c81616SWang Jie 
58*a2c81616SWang Jie #define TCPC_POWER_CTRL			0x1c
59*a2c81616SWang Jie #define TCPC_POWER_CTRL_VCONN_ENABLE	BIT(0)
60*a2c81616SWang Jie 
61*a2c81616SWang Jie #define TCPC_CC_STATUS			0x1d
62*a2c81616SWang Jie #define TCPC_CC_STATUS_TOGGLING		BIT(5)
63*a2c81616SWang Jie #define TCPC_CC_STATUS_TERM		BIT(4)
64*a2c81616SWang Jie #define TCPC_CC_STATUS_CC2_SHIFT	2
65*a2c81616SWang Jie #define TCPC_CC_STATUS_CC2_MASK		0x3
66*a2c81616SWang Jie #define TCPC_CC_STATUS_CC1_SHIFT	0
67*a2c81616SWang Jie #define TCPC_CC_STATUS_CC1_MASK		0x3
68*a2c81616SWang Jie 
69*a2c81616SWang Jie #define TCPC_POWER_STATUS		0x1e
70*a2c81616SWang Jie #define TCPC_POWER_STATUS_UNINIT	BIT(6)
71*a2c81616SWang Jie #define TCPC_POWER_STATUS_VBUS_DET	BIT(3)
72*a2c81616SWang Jie #define TCPC_POWER_STATUS_VBUS_PRES	BIT(2)
73*a2c81616SWang Jie 
74*a2c81616SWang Jie #define TCPC_FAULT_STATUS		0x1f
75*a2c81616SWang Jie 
76*a2c81616SWang Jie #define TCPC_COMMAND			0x23
77*a2c81616SWang Jie #define TCPC_CMD_WAKE_I2C		0x11
78*a2c81616SWang Jie #define TCPC_CMD_DISABLE_VBUS_DETECT	0x22
79*a2c81616SWang Jie #define TCPC_CMD_ENABLE_VBUS_DETECT	0x33
80*a2c81616SWang Jie #define TCPC_CMD_DISABLE_SINK_VBUS	0x44
81*a2c81616SWang Jie #define TCPC_CMD_SINK_VBUS		0x55
82*a2c81616SWang Jie #define TCPC_CMD_DISABLE_SRC_VBUS	0x66
83*a2c81616SWang Jie #define TCPC_CMD_SRC_VBUS_DEFAULT	0x77
84*a2c81616SWang Jie #define TCPC_CMD_SRC_VBUS_HIGH		0x88
85*a2c81616SWang Jie #define TCPC_CMD_LOOK4CONNECTION	0x99
86*a2c81616SWang Jie #define TCPC_CMD_RXONEMORE		0xAA
87*a2c81616SWang Jie #define TCPC_CMD_I2C_IDLE		0xFF
88*a2c81616SWang Jie 
89*a2c81616SWang Jie #define TCPC_DEV_CAP_1			0x24
90*a2c81616SWang Jie #define TCPC_DEV_CAP_2			0x26
91*a2c81616SWang Jie #define TCPC_STD_INPUT_CAP		0x28
92*a2c81616SWang Jie #define TCPC_STD_OUTPUT_CAP		0x29
93*a2c81616SWang Jie 
94*a2c81616SWang Jie #define TCPC_MSG_HDR_INFO		0x2e
95*a2c81616SWang Jie #define TCPC_MSG_HDR_INFO_DATA_ROLE	BIT(3)
96*a2c81616SWang Jie #define TCPC_MSG_HDR_INFO_PWR_ROLE	BIT(0)
97*a2c81616SWang Jie #define TCPC_MSG_HDR_INFO_REV_SHIFT	1
98*a2c81616SWang Jie #define TCPC_MSG_HDR_INFO_REV_MASK	0x3
99*a2c81616SWang Jie 
100*a2c81616SWang Jie #define TCPC_RX_DETECT			0x2f
101*a2c81616SWang Jie #define TCPC_RX_DETECT_HARD_RESET	BIT(5)
102*a2c81616SWang Jie #define TCPC_RX_DETECT_SOP		BIT(0)
103*a2c81616SWang Jie 
104*a2c81616SWang Jie #define TCPC_RX_BYTE_CNT		0x30
105*a2c81616SWang Jie #define TCPC_RX_BUF_FRAME_TYPE		0x31
106*a2c81616SWang Jie #define TCPC_RX_HDR			0x32
107*a2c81616SWang Jie #define TCPC_RX_DATA			0x34 /* through 0x4f */
108*a2c81616SWang Jie 
109*a2c81616SWang Jie #define TCPC_TRANSMIT			0x50
110*a2c81616SWang Jie #define TCPC_TRANSMIT_RETRY_SHIFT	4
111*a2c81616SWang Jie #define TCPC_TRANSMIT_RETRY_MASK	0x3
112*a2c81616SWang Jie #define TCPC_TRANSMIT_TYPE_SHIFT	0
113*a2c81616SWang Jie #define TCPC_TRANSMIT_TYPE_MASK		0x7
114*a2c81616SWang Jie 
115*a2c81616SWang Jie #define TCPC_TX_BYTE_CNT		0x51
116*a2c81616SWang Jie #define TCPC_TX_HDR			0x52
117*a2c81616SWang Jie #define TCPC_TX_DATA			0x54 /* through 0x6f */
118*a2c81616SWang Jie 
119*a2c81616SWang Jie #define TCPC_VBUS_VOLTAGE			0x70
120*a2c81616SWang Jie #define TCPC_VBUS_SINK_DISCONNECT_THRESH	0x72
121*a2c81616SWang Jie #define TCPC_VBUS_STOP_DISCHARGE_THRESH		0x74
122*a2c81616SWang Jie #define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG		0x76
123*a2c81616SWang Jie #define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG		0x78
124*a2c81616SWang Jie 
125*a2c81616SWang Jie #define TCPC_BMCIO_CTRL				0x90
126*a2c81616SWang Jie #define TCPC_BMCIO_VBUS_DETECT_MASK		BIT(1)
127*a2c81616SWang Jie #define TCPC_BMCIO_VBUS_DETECT_ENABLE		BIT(1)
128*a2c81616SWang Jie #define TCPC_BMCIO_VBUS_DETECT_DISABLE		0
129*a2c81616SWang Jie #define TCPC_BMCIO_24M_OSC_MASK                 BIT(0)
130*a2c81616SWang Jie #define TCPC_BMCIO_ENABLE_24M_OSC		BIT(0)
131*a2c81616SWang Jie #define TCPC_BMCIO_DISABLE_24M_OSC		0
132*a2c81616SWang Jie 
133*a2c81616SWang Jie struct tcpci;
134*a2c81616SWang Jie struct tcpci_data {
135*a2c81616SWang Jie 	struct regmap *regmap;
136*a2c81616SWang Jie 	int (*init)(struct tcpci *tcpci, struct tcpci_data *data);
137*a2c81616SWang Jie 	int (*set_vconn)(struct tcpci *tcpci, struct tcpci_data *data,
138*a2c81616SWang Jie 			 bool enable);
139*a2c81616SWang Jie 	int (*start_drp_toggling)(struct tcpci *tcpci, struct tcpci_data *data,
140*a2c81616SWang Jie 				  enum typec_cc_status cc);
141*a2c81616SWang Jie };
142*a2c81616SWang Jie 
143*a2c81616SWang Jie struct tcpci *tcpci_register_port(struct udevice *dev, struct tcpci_data *data);
144*a2c81616SWang Jie void tcpci_unregister_port(struct tcpci *tcpci);
145*a2c81616SWang Jie int tcpci_get_voltage_fun(struct tcpci *tcpci);
146*a2c81616SWang Jie int tcpci_get_current_fun(struct tcpci *tcpci);
147*a2c81616SWang Jie int tcpci_get_online_fun(struct tcpci *tcpci);
148*a2c81616SWang Jie irqreturn_t tcpci_irq(struct tcpci *tcpci);
149*a2c81616SWang Jie 
150*a2c81616SWang Jie #endif /* __LINUX_USB_TCPCI_H */
151