1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <irq-generic.h> 12 #include <power/rk8xx_pmic.h> 13 #include <power/pmic.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #if CONFIG_IS_ENABLED(IRQ) 18 /* RK805 */ 19 static const struct virq_reg rk805_irqs[] = { 20 [RK8XX_IRQ_PWRON_FALL] = { 21 .mask = RK805_IRQ_PWRON_FALL_MSK, 22 .reg_offset = 0, 23 }, 24 [RK8XX_IRQ_PWRON_RISE] = { 25 .mask = RK805_IRQ_PWRON_RISE_MSK, 26 .reg_offset = 0, 27 }, 28 }; 29 30 static struct virq_chip rk805_irq_chip = { 31 .status_base = RK805_INT_STS_REG, 32 .mask_base = RK805_INT_MSK_REG, 33 .num_regs = 1, 34 .read = pmic_reg_read, 35 .write = pmic_reg_write, 36 .irqs = rk805_irqs, 37 .num_irqs = ARRAY_SIZE(rk805_irqs), 38 }; 39 40 /* RK806 */ 41 static const struct virq_reg rk806_irqs[] = { 42 [RK8XX_IRQ_PWRON_FALL] = { 43 .mask = RK806_IRQ_PWRON_FALL_MSK, 44 .reg_offset = 0, 45 }, 46 [RK8XX_IRQ_PWRON_RISE] = { 47 .mask = RK806_IRQ_PWRON_RISE_MSK, 48 .reg_offset = 0, 49 }, 50 }; 51 52 static struct virq_chip rk806_irq_chip = { 53 .status_base = RK806_INT_STS0, 54 .mask_base = RK806_INT_MSK0, 55 .irq_reg_stride = 2, 56 .num_regs = 2, 57 .read = pmic_reg_read, 58 .write = pmic_reg_write, 59 .irqs = rk806_irqs, 60 .num_irqs = ARRAY_SIZE(rk806_irqs), 61 }; 62 63 /* RK808 */ 64 static const struct virq_reg rk808_irqs[] = { 65 [RK8XX_IRQ_PLUG_OUT] = { 66 .mask = RK808_IRQ_PLUG_OUT_MSK, 67 .reg_offset = 1, 68 }, 69 }; 70 71 static struct virq_chip rk808_irq_chip = { 72 .status_base = RK808_INT_STS_REG1, 73 .mask_base = RK808_INT_MSK_REG1, 74 .irq_reg_stride = 2, 75 .num_regs = 2, 76 .read = pmic_reg_read, 77 .write = pmic_reg_write, 78 .irqs = rk808_irqs, 79 .num_irqs = ARRAY_SIZE(rk808_irqs), 80 }; 81 82 /* RK816 */ 83 static const struct virq_reg rk816_irqs[] = { 84 [RK8XX_IRQ_PWRON_FALL] = { 85 .mask = RK816_IRQ_PWRON_FALL_MSK, 86 .reg_offset = 0, 87 }, 88 [RK8XX_IRQ_PWRON_RISE] = { 89 .mask = RK816_IRQ_PWRON_RISE_MSK, 90 .reg_offset = 0, 91 }, 92 [RK8XX_IRQ_PLUG_OUT] = { 93 .mask = RK816_IRQ_PLUG_OUT_MSK, 94 .reg_offset = 2, 95 }, 96 [RK8XX_IRQ_CHG_OK] = { 97 .mask = RK816_IRQ_CHR_OK_MSK, 98 .reg_offset = 2, 99 }, 100 }; 101 102 static struct virq_chip rk816_irq_chip = { 103 .status_base = RK816_INT_STS_REG1, 104 .mask_base = RK816_INT_MSK_REG1, 105 .irq_unalign_reg_idx = 1, /* idx <= 1, stride = 3 */ 106 .irq_unalign_reg_stride = 3, 107 .irq_reg_stride = 2, /* idx > 1, stride = 2 */ 108 .num_regs = 3, 109 .read = pmic_reg_read, 110 .write = pmic_reg_write, 111 .irqs = rk816_irqs, 112 .num_irqs = ARRAY_SIZE(rk816_irqs), 113 }; 114 115 /* RK818 */ 116 static const struct virq_reg rk818_irqs[] = { 117 [RK8XX_IRQ_PLUG_OUT] = { 118 .mask = RK818_IRQ_PLUG_OUT_MSK, 119 .reg_offset = 1, 120 }, 121 [RK8XX_IRQ_CHG_OK] = { 122 .mask = RK818_IRQ_CHR_OK_MSK, 123 .reg_offset = 1, 124 }, 125 }; 126 127 static struct virq_chip rk818_irq_chip = { 128 .status_base = RK818_INT_STS_REG1, 129 .mask_base = RK818_INT_MSK_REG1, 130 .irq_reg_stride = 2, 131 .num_regs = 2, 132 .read = pmic_reg_read, 133 .write = pmic_reg_write, 134 .irqs = rk818_irqs, 135 .num_irqs = ARRAY_SIZE(rk818_irqs), 136 }; 137 138 /* RK817/RK809 */ 139 static const struct virq_reg rk817_irqs[] = { 140 [RK8XX_IRQ_PWRON_FALL] = { 141 .mask = RK817_IRQ_PWRON_FALL_MSK, 142 .reg_offset = 0, 143 }, 144 [RK8XX_IRQ_PWRON_RISE] = { 145 .mask = RK817_IRQ_PWRON_RISE_MSK, 146 .reg_offset = 0, 147 }, 148 [RK8XX_IRQ_PLUG_OUT] = { 149 .mask = RK817_IRQ_PLUG_OUT_MSK, 150 .reg_offset = 1, 151 }, 152 [RK8XX_IRQ_PLUG_IN] = { 153 .mask = RK817_IRQ_PLUG_IN_MSK, 154 .reg_offset = 1, 155 }, 156 }; 157 158 static struct virq_chip rk817_irq_chip = { 159 .status_base = RK817_INT_STS_REG0, 160 .mask_base = RK817_INT_MSK_REG0, 161 .irq_reg_stride = 2, 162 .num_regs = 3, 163 .read = pmic_reg_read, 164 .write = pmic_reg_write, 165 .irqs = rk817_irqs, 166 .num_irqs = ARRAY_SIZE(rk817_irqs), 167 }; 168 #endif 169 170 static struct reg_data rk817_init_reg[] = { 171 /* enable the under-voltage protection, 172 * the under-voltage protection will shutdown the LDO3 and reset the PMIC 173 */ 174 { RK817_BUCK4_CMIN, 0x6b, 0x6e}, 175 { RK817_PMIC_SYS_CFG1, 0x20, 0x70}, 176 /* Set pmic_sleep as none function */ 177 { RK817_PMIC_SYS_CFG3, 0x00, 0x18 }, 178 /* GATE pin function: gate function */ 179 { RK817_GPIO_INT_CFG, 0x00, 0x20 }, 180 #ifdef CONFIG_DM_CHARGE_DISPLAY 181 /* Set pmic_int active low */ 182 { RK817_GPIO_INT_CFG, 0x00, 0x02 }, 183 #endif 184 }; 185 186 static struct reg_data rk818_init_current[] = { 187 { REG_USB_CTRL, 0x07, 0x0f}, /* 2A */ 188 }; 189 190 /* 191 * Order WARNING: Must put "LDO" after the "NLDO" and "PLDO" ! 192 * 193 * See: pmic_bind_children() 194 * if (!strstr(node_name, info->prefix)) { 195 * ...... 196 * } 197 * 198 * Without this order, the prefix "LDO" will be matched if a regulator 199 * dts node name contains "NLDO" or "PLDO". 200 */ 201 static const struct pmic_child_info pmic_children_info[] = { 202 { .prefix = "DCDC", .driver = "rk8xx_buck"}, 203 { .prefix = "NLDO", .driver = "rk8xx_ldo"}, 204 { .prefix = "PLDO", .driver = "rk8xx_pldo"}, 205 { .prefix = "LDO", .driver = "rk8xx_ldo"}, 206 { .prefix = "SWITCH", .driver = "rk8xx_switch"}, 207 { }, 208 }; 209 210 static const struct pmic_child_info power_key_info[] = { 211 { .prefix = "pwrkey", .driver = "rk8xx_pwrkey"}, 212 { }, 213 }; 214 215 static const struct pmic_child_info rtc_info[] = { 216 { .prefix = "rtc", .driver = "rk8xx_rtc"}, 217 { }, 218 }; 219 220 static const struct pmic_child_info fuel_gauge_info[] = { 221 { .addr = "1c", .prefix = "battery", .driver = "rk818_fg"}, 222 { .addr = "20", .prefix = "battery", .driver = "rk817_fg"}, 223 { .addr = "1a", .prefix = "battery", .driver = "rk816_fg"}, 224 { }, 225 }; 226 227 static const struct pmic_child_info rk817_codec_info[] = { 228 { .prefix = "codec", .driver = "rk817_codec"}, 229 { }, 230 }; 231 232 static int rk8xx_reg_count(struct udevice *dev) 233 { 234 struct rk8xx_priv *priv = dev_get_priv(dev); 235 236 switch (priv->variant) { 237 case RK809_ID: 238 case RK817_ID: 239 return RK817_NUM_OF_REGS; 240 default: 241 return RK808_NUM_OF_REGS; 242 } 243 } 244 245 static int rk8xx_write(struct udevice *dev, uint reg, const uint8_t *buff, 246 int len) 247 { 248 int ret; 249 250 ret = dm_i2c_write(dev, reg, buff, len); 251 if (ret) { 252 printf("%s: write reg 0x%02x failed, ret=%d\n", __func__, reg, ret); 253 return ret; 254 } 255 256 return 0; 257 } 258 259 static int rk8xx_read(struct udevice *dev, uint reg, uint8_t *buff, int len) 260 { 261 int ret; 262 263 ret = dm_i2c_read(dev, reg, buff, len); 264 if (ret) { 265 printf("%s: read reg 0x%02x failed, ret=%d\n", __func__, reg, ret); 266 return ret; 267 } 268 269 return 0; 270 } 271 272 static int rk8xx_suspend(struct udevice *dev) 273 { 274 struct rk8xx_priv *priv = dev_get_priv(dev); 275 int ret = 0; 276 u8 i, val; 277 278 switch (priv->variant) { 279 case RK806_ID: 280 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 281 if (ret) 282 return ret; 283 val &= RK806_PWRCTRL_FUN_MSK; 284 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 285 if (ret) 286 return ret; 287 288 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 289 if (ret) 290 return ret; 291 292 val &= RK806_PWRCTRL_FUN_MSK; 293 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 294 if (ret) 295 return ret; 296 297 for (i = RK806_VSEL_CTR_SEL0; i <= RK806_DVS_CTR_SEL4; i++) { 298 ret = rk8xx_read(dev, i, &val, 1); 299 if (ret) 300 return ret; 301 val &= RK806_VSEL_CTRL_MSK; 302 ret = rk8xx_write(dev, i, &val, 1); 303 if (ret) 304 return ret; 305 } 306 307 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 308 if (ret) 309 return ret; 310 val &= RK806_PWRCTRL_FUN_MSK; 311 val |= RK806_ENABLE_PWRCTRL; 312 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 313 if (ret) 314 return ret; 315 316 for (i = RK806_VSEL_CTR_SEL0; i <= RK806_DVS_CTR_SEL4; i++) { 317 ret = rk8xx_read(dev, i, &val, 1); 318 if (ret) 319 return ret; 320 val &= RK806_VSEL_CTRL_MSK; 321 val |= RK806_VSEL_PWRCTRL1; 322 ret = rk8xx_write(dev, i, &val, 1); 323 if (ret) 324 return ret; 325 } 326 break; 327 case RK809_ID: 328 case RK817_ID: 329 /* pmic_sleep active high */ 330 ret = rk8xx_read(dev, RK817_PMIC_SYS_CFG3, &val, 1); 331 if (ret) 332 return ret; 333 priv->sleep_pin = val; 334 val &= ~0x38; 335 val |= 0x28; 336 ret = rk8xx_write(dev, RK817_PMIC_SYS_CFG3, &val, 1); 337 break; 338 default: 339 return 0; 340 } 341 342 return ret; 343 } 344 345 static int rk8xx_resume(struct udevice *dev) 346 { 347 struct rk8xx_priv *priv = dev_get_priv(dev); 348 int ret = 0; 349 u8 i, val; 350 351 switch (priv->variant) { 352 case RK806_ID: 353 for (i = RK806_VSEL_CTR_SEL0; i <= RK806_DVS_CTR_SEL4; i++) { 354 ret = rk8xx_read(dev, i, &val, 1); 355 if (ret) 356 return ret; 357 val &= RK806_VSEL_CTRL_MSK; 358 ret = rk8xx_write(dev, i, &val, 1); 359 if (ret) 360 return ret; 361 } 362 363 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 364 if (ret) 365 return ret; 366 val &= RK806_PWRCTRL_FUN_MSK; 367 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 368 if (ret) 369 return ret; 370 371 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 372 if (ret) 373 return ret; 374 val &= RK806_PWRCTRL_FUN_MSK; 375 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 376 break; 377 case RK809_ID: 378 case RK817_ID: 379 ret = rk8xx_write(dev, RK817_PMIC_SYS_CFG3, &priv->sleep_pin, 1); 380 break; 381 default: 382 return 0; 383 } 384 385 return ret; 386 } 387 388 static int rk8xx_shutdown(struct udevice *dev) 389 { 390 struct rk8xx_priv *priv = dev_get_priv(dev); 391 u8 val, dev_off, devctrl_reg; 392 int ret = 0; 393 394 switch (priv->variant) { 395 case RK806_ID: 396 devctrl_reg = RK806_SYS_CFG3; 397 dev_off = RK806_DEV_OFF; 398 break; 399 case RK808_ID: 400 devctrl_reg = REG_DEVCTRL; 401 dev_off = BIT(3); 402 break; 403 case RK805_ID: 404 case RK816_ID: 405 case RK818_ID: 406 devctrl_reg = REG_DEVCTRL; 407 dev_off = BIT(0); 408 break; 409 case RK809_ID: 410 case RK817_ID: 411 devctrl_reg = RK817_REG_SYS_CFG3; 412 dev_off = BIT(0); 413 break; 414 default: 415 printf("Unknown PMIC: RK%x\n", priv->variant); 416 return -EINVAL; 417 } 418 419 ret = rk8xx_read(dev, devctrl_reg, &val, 1); 420 if (ret) 421 return ret; 422 423 val |= dev_off; 424 ret = rk8xx_write(dev, devctrl_reg, &val, 1); 425 if (ret) 426 return ret; 427 428 return 0; 429 } 430 431 #if CONFIG_IS_ENABLED(PMIC_CHILDREN) 432 static int rk8xx_bind(struct udevice *dev) 433 { 434 ofnode regulators_node; 435 int children; 436 437 regulators_node = dev_read_subnode(dev, "regulators"); 438 if (!ofnode_valid(regulators_node)) { 439 debug("%s: %s regulators subnode not found!\n", __func__, 440 dev->name); 441 return -ENXIO; 442 } 443 444 debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); 445 446 children = pmic_bind_children(dev, regulators_node, pmic_children_info); 447 if (!children) 448 debug("%s: %s - no child found\n", __func__, dev->name); 449 450 children = pmic_bind_children(dev, dev->node, power_key_info); 451 if (!children) 452 debug("%s: %s - no child found\n", __func__, dev->name); 453 454 children = pmic_bind_children(dev, dev->node, rtc_info); 455 if (!children) 456 debug("%s: %s - no child found\n", __func__, dev->name); 457 458 children = pmic_bind_children(dev, dev->node, fuel_gauge_info); 459 if (!children) 460 debug("%s: %s - no child found\n", __func__, dev->name); 461 462 children = pmic_bind_children(dev, dev->node, rk817_codec_info); 463 if (!children) 464 debug("%s: %s - no child found\n", __func__, dev->name); 465 466 /* Always return success for this device */ 467 return 0; 468 } 469 #endif 470 471 #if CONFIG_IS_ENABLED(IRQ) 472 /* 473 * When system suspend during U-Boot charge, make sure the plugout event 474 * be able to wakeup cpu in wfi/wfe state. 475 */ 476 #ifdef CONFIG_DM_CHARGE_DISPLAY 477 static void rk8xx_plug_out_handler(int irq, void *data) 478 { 479 printf("Plug out interrupt\n"); 480 } 481 #endif 482 483 static int rk8xx_irq_chip_init(struct udevice *dev) 484 { 485 struct rk8xx_priv *priv = dev_get_priv(dev); 486 struct virq_chip *irq_chip = NULL; 487 __maybe_unused int irq_plugout = 1; 488 uint8_t value; 489 int ret; 490 491 switch (priv->variant) { 492 case RK806_ID: 493 irq_chip = &rk806_irq_chip; 494 irq_plugout = 0; 495 ret = rk8xx_read(dev, RK806_GPIO_INT_CONFIG, &value, 1); 496 if (ret) 497 return ret; 498 /* set INT polarity active low */ 499 value &= (~RK806_INT_POL_HIGH); 500 ret = rk8xx_write(dev, RK806_GPIO_INT_CONFIG, &value, 1); 501 if (ret) 502 return ret; 503 break; 504 case RK808_ID: 505 irq_chip = &rk808_irq_chip; 506 break; 507 case RK805_ID: 508 irq_chip = &rk805_irq_chip; 509 irq_plugout = 0; 510 break; 511 case RK816_ID: 512 irq_chip = &rk816_irq_chip; 513 break; 514 case RK818_ID: 515 irq_chip = &rk818_irq_chip; 516 break; 517 case RK809_ID: 518 case RK817_ID: 519 irq_chip = &rk817_irq_chip; 520 break; 521 default: 522 return -EINVAL; 523 } 524 525 if (irq_chip) { 526 ret = virq_add_chip(dev, irq_chip, priv->irq); 527 if (ret) { 528 printf("Failed to add irqchip(irq=%d), ret=%d\n", 529 priv->irq, ret); 530 return ret; 531 } 532 533 priv->irq_chip = irq_chip; 534 535 #ifdef CONFIG_DM_CHARGE_DISPLAY 536 int irq; 537 538 if (irq_plugout) { 539 irq = virq_to_irq(irq_chip, RK8XX_IRQ_PLUG_OUT); 540 if (irq < 0) { 541 printf("Failed to register plugout irq, ret=%d\n", irq); 542 return irq; 543 } 544 irq_install_handler(irq, rk8xx_plug_out_handler, dev); 545 irq_handler_enable_suspend_only(irq); 546 } 547 #endif 548 } 549 550 return 0; 551 } 552 #else 553 static inline int rk8xx_irq_chip_init(struct udevice *dev) { return 0; } 554 #endif 555 556 static int rk8xx_ofdata_to_platdata(struct udevice *dev) 557 { 558 struct rk8xx_priv *rk8xx = dev_get_priv(dev); 559 u32 interrupt, phandle, val; 560 int ret; 561 562 phandle = dev_read_u32_default(dev, "interrupt-parent", -ENODATA); 563 if (phandle == -ENODATA) { 564 printf("Read 'interrupt-parent' failed, ret=%d\n", phandle); 565 return phandle; 566 } 567 568 ret = dev_read_u32_array(dev, "interrupts", &interrupt, 1); 569 if (ret) { 570 printf("Read 'interrupts' failed, ret=%d\n", ret); 571 return ret; 572 } 573 574 #if CONFIG_IS_ENABLED(IRQ) 575 rk8xx->irq = phandle_gpio_to_irq(phandle, interrupt); 576 if (rk8xx->irq < 0) { 577 printf("Failed to request rk8xx irq, ret=%d\n", rk8xx->irq); 578 return rk8xx->irq; 579 } 580 #endif 581 val = dev_read_u32_default(dev, "long-press-off-time-sec", 0); 582 if (val <= 6) 583 rk8xx->lp_off_time = RK8XX_LP_TIME_6S; 584 else if (val <= 8) 585 rk8xx->lp_off_time = RK8XX_LP_TIME_8S; 586 else if (val <= 10) 587 rk8xx->lp_off_time = RK8XX_LP_TIME_10S; 588 else 589 rk8xx->lp_off_time = RK8XX_LP_TIME_12S; 590 591 val = dev_read_u32_default(dev, "long-press-restart", 0); 592 if (val) 593 rk8xx->lp_action = RK8XX_LP_RESTART; 594 else 595 rk8xx->lp_action = RK8XX_LP_OFF; 596 597 rk8xx->not_save_power_en = dev_read_u32_default(dev, "not-save-power-en", 0); 598 rk8xx->sys_can_sd = dev_read_bool(dev, "vsys-off-shutdown"); 599 rk8xx->rst_fun = dev_read_u32_default(dev, "pmic-reset-func", 0); 600 /* buck5 external feedback resister disable */ 601 rk8xx->buck5_feedback_dis = dev_read_bool(dev, "buck5-feedback-disable"); 602 603 return 0; 604 } 605 606 static int rk8xx_probe(struct udevice *dev) 607 { 608 struct rk8xx_priv *priv = dev_get_priv(dev); 609 struct reg_data *init_current = NULL; 610 struct reg_data *init_data = NULL; 611 int init_current_num = 0; 612 int init_data_num = 0; 613 int ret = 0, i, show_variant; 614 uint8_t msb, lsb, id_msb, id_lsb; 615 uint8_t on_source = 0, off_source = 0; 616 uint8_t pwron_key = 0, lp_off_msk = 0, lp_act_msk = 0; 617 uint8_t power_en0, power_en1, power_en2, power_en3; 618 uint8_t on, off; 619 uint8_t value; 620 621 /* read Chip variant */ 622 if (device_is_compatible(dev, "rockchip,rk817") || 623 device_is_compatible(dev, "rockchip,rk809")) { 624 id_msb = RK817_ID_MSB; 625 id_lsb = RK817_ID_LSB; 626 } else if (device_is_compatible(dev, "rockchip,rk806")) { 627 id_msb = RK806_CHIP_NAME; 628 id_lsb = RK806_CHIP_VER; 629 } else { 630 id_msb = ID_MSB; 631 id_lsb = ID_LSB; 632 } 633 634 ret = rk8xx_read(dev, id_msb, &msb, 1); 635 if (ret) 636 return ret; 637 ret = rk8xx_read(dev, id_lsb, &lsb, 1); 638 if (ret) 639 return ret; 640 641 priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK; 642 show_variant = priv->variant; 643 switch (priv->variant) { 644 case RK806_ID: 645 on_source = RK806_ON_SOURCE; 646 off_source = RK806_OFF_SOURCE; 647 ret = rk8xx_read(dev, RK806_HW_VER, &value, 1); 648 if (ret) 649 panic("RK806: read RK806_HW_VER error!\n"); 650 651 if ((lsb & RK806_VERSION_MSK) == RK806_VERSION_AB) { 652 ret = rk8xx_read(dev, RK806_SYS_CFG1, &value, 1); 653 if (ret) { 654 dev_err(dev, "rk806 RK806_SYS_CFG1 read error: %d\n", ret); 655 return ret; 656 } 657 value |= RK806_ABNORDET_EN; 658 rk8xx_write(dev, RK806_SYS_CFG1, &value, 1); 659 } 660 661 if (priv->rst_fun) { 662 rk8xx_read(dev, RK806_SYS_CFG3, &value, 1); 663 value &= RK806_RESET_FUN_CLR; 664 if (priv->rst_fun == RK806_RST_MODE1) { 665 value |= (RK806_RST_MODE1 << 6); 666 rk8xx_write(dev, RK806_SYS_CFG3, &value, 1); 667 } else if (priv->rst_fun == RK806_RST_MODE2) { 668 value |= (RK806_RST_MODE2 << 6); 669 rk8xx_write(dev, RK806_SYS_CFG3, &value, 1); 670 } 671 } 672 673 if (priv->buck5_feedback_dis) { 674 rk8xx_read(dev, RK806_BUCK_RSERVE_REG3, &value, 1); 675 value &=( ~RK806_BUCK5_EX_RES_EN); 676 rk8xx_write(dev, RK806_BUCK_RSERVE_REG3, &value, 1); 677 } 678 break; 679 case RK808_ID: 680 show_variant = 0x808; /* RK808 hardware ID is 0 */ 681 pwron_key = RK8XX_DEVCTRL_REG; 682 lp_off_msk = RK8XX_LP_OFF_MSK; 683 break; 684 case RK805_ID: 685 case RK816_ID: 686 on_source = RK8XX_ON_SOURCE; 687 off_source = RK8XX_OFF_SOURCE; 688 pwron_key = RK8XX_DEVCTRL_REG; 689 lp_off_msk = RK8XX_LP_OFF_MSK; 690 lp_act_msk = RK8XX_LP_ACTION_MSK; 691 break; 692 case RK818_ID: 693 on_source = RK8XX_ON_SOURCE; 694 off_source = RK8XX_OFF_SOURCE; 695 pwron_key = RK8XX_DEVCTRL_REG; 696 lp_off_msk = RK8XX_LP_OFF_MSK; 697 lp_act_msk = RK8XX_LP_ACTION_MSK; 698 /* set current if no fuel gauge */ 699 if (!ofnode_valid(dev_read_subnode(dev, "battery"))) { 700 init_current = rk818_init_current; 701 init_current_num = ARRAY_SIZE(rk818_init_current); 702 } 703 break; 704 case RK809_ID: 705 case RK817_ID: 706 if (device_is_compatible(dev, "rockchip,rk809") && (priv->variant != RK809_ID)) { 707 dev_err(dev, "the dts is RK809, the hardware is RK817\n"); 708 run_command("download", 0); 709 } 710 711 if (device_is_compatible(dev, "rockchip,rk817") && (priv->variant != RK817_ID)) { 712 dev_err(dev, "the dts is RK817, the hardware is RK809\n"); 713 run_command("download", 0); 714 } 715 716 on_source = RK817_ON_SOURCE; 717 off_source = RK817_OFF_SOURCE; 718 pwron_key = RK817_PWRON_KEY; 719 lp_off_msk = RK8XX_LP_OFF_MSK; 720 lp_act_msk = RK8XX_LP_ACTION_MSK; 721 init_data = rk817_init_reg; 722 init_data_num = ARRAY_SIZE(rk817_init_reg); 723 724 /* whether the system voltage can be shutdown in PWR_off mode */ 725 if (priv->sys_can_sd) { 726 ret = rk8xx_read(dev, RK817_PMIC_CHRG_TERM, &value, 1); 727 if (ret) 728 return ret; 729 value |= 0x80; 730 ret = rk8xx_write(dev, RK817_PMIC_CHRG_TERM, &value, 1); 731 if (ret) 732 return ret; 733 } else { 734 ret = rk8xx_read(dev, RK817_PMIC_CHRG_TERM, &value, 1); 735 if (ret) 736 return ret; 737 value &= 0x7f; 738 ret = rk8xx_write(dev, RK817_PMIC_CHRG_TERM, &value, 1); 739 if (ret) 740 return ret; 741 } 742 743 /* judge whether save the PMIC_POWER_EN register */ 744 if (!priv->not_save_power_en) { 745 ret = rk8xx_read(dev, RK817_POWER_EN0, &power_en0, 1); 746 if (ret) 747 return ret; 748 ret = rk8xx_read(dev, RK817_POWER_EN1, &power_en1, 1); 749 if (ret) 750 return ret; 751 ret = rk8xx_read(dev, RK817_POWER_EN2, &power_en2, 1); 752 if (ret) 753 return ret; 754 ret = rk8xx_read(dev, RK817_POWER_EN3, &power_en3, 1); 755 if (ret) 756 return ret; 757 758 value = (power_en0 & 0x0f) | ((power_en1 & 0x0f) << 4); 759 rk8xx_write(dev, RK817_POWER_EN_SAVE0, &value, 1); 760 value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4); 761 rk8xx_write(dev, RK817_POWER_EN_SAVE1, &value, 1); 762 } 763 break; 764 default: 765 printf("Unknown PMIC: RK%x!!\n", priv->variant); 766 return -EINVAL; 767 } 768 769 /* common init */ 770 for (i = 0; i < init_data_num; i++) { 771 ret = pmic_clrsetbits(dev, 772 init_data[i].reg, 773 init_data[i].mask, 774 init_data[i].val); 775 if (ret < 0) { 776 printf("%s: i2c set reg 0x%x failed, ret=%d\n", 777 __func__, init_data[i].reg, ret); 778 } 779 } 780 781 /* current init */ 782 for (i = 0; i < init_current_num; i++) { 783 ret = pmic_clrsetbits(dev, 784 init_current[i].reg, 785 init_current[i].mask, 786 init_current[i].val); 787 if (ret < 0) { 788 printf("%s: i2c set reg 0x%x failed, ret=%d\n", 789 __func__, init_current[i].reg, ret); 790 } 791 } 792 793 printf("PMIC: RK%x ", show_variant); 794 795 if (on_source && off_source) { 796 rk8xx_read(dev, on_source, &on, 1); 797 rk8xx_read(dev, off_source, &off, 1); 798 printf("(on=0x%02x, off=0x%02x)", on, off); 799 } 800 printf("\n"); 801 802 if (pwron_key) { 803 ret = rk8xx_read(dev, pwron_key, &value, 1); 804 if (ret) 805 return ret; 806 value &= ~(lp_off_msk | lp_act_msk); 807 if (lp_off_msk) 808 value |= priv->lp_off_time; 809 if (lp_act_msk) 810 value |= priv->lp_action; 811 rk8xx_write(dev, pwron_key, &value, 1); 812 } 813 814 ret = rk8xx_irq_chip_init(dev); 815 if (ret) { 816 printf("IRQ chip initial failed\n"); 817 return ret; 818 } 819 820 return 0; 821 } 822 823 static struct dm_pmic_ops rk8xx_ops = { 824 .reg_count = rk8xx_reg_count, 825 .read = rk8xx_read, 826 .write = rk8xx_write, 827 .suspend = rk8xx_suspend, 828 .resume = rk8xx_resume, 829 .shutdown = rk8xx_shutdown, 830 }; 831 832 static const struct udevice_id rk8xx_ids[] = { 833 { .compatible = "rockchip,rk805" }, 834 { .compatible = "rockchip,rk806" }, 835 { .compatible = "rockchip,rk808" }, 836 { .compatible = "rockchip,rk809" }, 837 { .compatible = "rockchip,rk816" }, 838 { .compatible = "rockchip,rk817" }, 839 { .compatible = "rockchip,rk818" }, 840 { } 841 }; 842 843 U_BOOT_DRIVER(pmic_rk8xx) = { 844 .name = "rk8xx pmic", 845 .id = UCLASS_PMIC, 846 .of_match = rk8xx_ids, 847 #if CONFIG_IS_ENABLED(PMIC_CHILDREN) 848 .bind = rk8xx_bind, 849 #endif 850 .ofdata_to_platdata = rk8xx_ofdata_to_platdata, 851 .priv_auto_alloc_size = sizeof(struct rk8xx_priv), 852 .probe = rk8xx_probe, 853 .ops = &rk8xx_ops, 854 }; 855