1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <irq-generic.h> 12 #include <power/rk8xx_pmic.h> 13 #include <power/pmic.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #if CONFIG_IS_ENABLED(IRQ) 18 /* RK805 */ 19 static const struct virq_reg rk805_irqs[] = { 20 [RK8XX_IRQ_PWRON_FALL] = { 21 .mask = RK805_IRQ_PWRON_FALL_MSK, 22 .reg_offset = 0, 23 }, 24 [RK8XX_IRQ_PWRON_RISE] = { 25 .mask = RK805_IRQ_PWRON_RISE_MSK, 26 .reg_offset = 0, 27 }, 28 }; 29 30 static struct virq_chip rk805_irq_chip = { 31 .status_base = RK805_INT_STS_REG, 32 .mask_base = RK805_INT_MSK_REG, 33 .num_regs = 1, 34 .read = pmic_reg_read, 35 .write = pmic_reg_write, 36 .irqs = rk805_irqs, 37 .num_irqs = ARRAY_SIZE(rk805_irqs), 38 }; 39 40 /* RK806 */ 41 static const struct virq_reg rk806_irqs[] = { 42 [RK8XX_IRQ_PWRON_FALL] = { 43 .mask = RK806_IRQ_PWRON_FALL_MSK, 44 .reg_offset = 0, 45 }, 46 [RK8XX_IRQ_PWRON_RISE] = { 47 .mask = RK806_IRQ_PWRON_RISE_MSK, 48 .reg_offset = 0, 49 }, 50 }; 51 52 static struct virq_chip rk806_irq_chip = { 53 .status_base = RK806_INT_STS0, 54 .mask_base = RK806_INT_MSK0, 55 .irq_reg_stride = 2, 56 .num_regs = 2, 57 .read = pmic_reg_read, 58 .write = pmic_reg_write, 59 .irqs = rk806_irqs, 60 .num_irqs = ARRAY_SIZE(rk806_irqs), 61 }; 62 63 /* RK808 */ 64 static const struct virq_reg rk808_irqs[] = { 65 [RK8XX_IRQ_PLUG_OUT] = { 66 .mask = RK808_IRQ_PLUG_OUT_MSK, 67 .reg_offset = 1, 68 }, 69 }; 70 71 static struct virq_chip rk808_irq_chip = { 72 .status_base = RK808_INT_STS_REG1, 73 .mask_base = RK808_INT_MSK_REG1, 74 .irq_reg_stride = 2, 75 .num_regs = 2, 76 .read = pmic_reg_read, 77 .write = pmic_reg_write, 78 .irqs = rk808_irqs, 79 .num_irqs = ARRAY_SIZE(rk808_irqs), 80 }; 81 82 /* RK816 */ 83 static const struct virq_reg rk816_irqs[] = { 84 [RK8XX_IRQ_PWRON_FALL] = { 85 .mask = RK816_IRQ_PWRON_FALL_MSK, 86 .reg_offset = 0, 87 }, 88 [RK8XX_IRQ_PWRON_RISE] = { 89 .mask = RK816_IRQ_PWRON_RISE_MSK, 90 .reg_offset = 0, 91 }, 92 [RK8XX_IRQ_PLUG_OUT] = { 93 .mask = RK816_IRQ_PLUG_OUT_MSK, 94 .reg_offset = 2, 95 }, 96 [RK8XX_IRQ_CHG_OK] = { 97 .mask = RK816_IRQ_CHR_OK_MSK, 98 .reg_offset = 2, 99 }, 100 }; 101 102 static struct virq_chip rk816_irq_chip = { 103 .status_base = RK816_INT_STS_REG1, 104 .mask_base = RK816_INT_MSK_REG1, 105 .irq_unalign_reg_idx = 1, /* idx <= 1, stride = 3 */ 106 .irq_unalign_reg_stride = 3, 107 .irq_reg_stride = 2, /* idx > 1, stride = 2 */ 108 .num_regs = 3, 109 .read = pmic_reg_read, 110 .write = pmic_reg_write, 111 .irqs = rk816_irqs, 112 .num_irqs = ARRAY_SIZE(rk816_irqs), 113 }; 114 115 /* RK818 */ 116 static const struct virq_reg rk818_irqs[] = { 117 [RK8XX_IRQ_PLUG_OUT] = { 118 .mask = RK818_IRQ_PLUG_OUT_MSK, 119 .reg_offset = 1, 120 }, 121 [RK8XX_IRQ_CHG_OK] = { 122 .mask = RK818_IRQ_CHR_OK_MSK, 123 .reg_offset = 1, 124 }, 125 }; 126 127 static struct virq_chip rk818_irq_chip = { 128 .status_base = RK818_INT_STS_REG1, 129 .mask_base = RK818_INT_MSK_REG1, 130 .irq_reg_stride = 2, 131 .num_regs = 2, 132 .read = pmic_reg_read, 133 .write = pmic_reg_write, 134 .irqs = rk818_irqs, 135 .num_irqs = ARRAY_SIZE(rk818_irqs), 136 }; 137 138 /* RK817/RK809 */ 139 static const struct virq_reg rk817_irqs[] = { 140 [RK8XX_IRQ_PWRON_FALL] = { 141 .mask = RK817_IRQ_PWRON_FALL_MSK, 142 .reg_offset = 0, 143 }, 144 [RK8XX_IRQ_PWRON_RISE] = { 145 .mask = RK817_IRQ_PWRON_RISE_MSK, 146 .reg_offset = 0, 147 }, 148 [RK8XX_IRQ_PLUG_OUT] = { 149 .mask = RK817_IRQ_PLUG_OUT_MSK, 150 .reg_offset = 1, 151 }, 152 [RK8XX_IRQ_PLUG_IN] = { 153 .mask = RK817_IRQ_PLUG_IN_MSK, 154 .reg_offset = 1, 155 }, 156 }; 157 158 static struct virq_chip rk817_irq_chip = { 159 .status_base = RK817_INT_STS_REG0, 160 .mask_base = RK817_INT_MSK_REG0, 161 .irq_reg_stride = 2, 162 .num_regs = 3, 163 .read = pmic_reg_read, 164 .write = pmic_reg_write, 165 .irqs = rk817_irqs, 166 .num_irqs = ARRAY_SIZE(rk817_irqs), 167 }; 168 #endif 169 170 static struct reg_data rk817_init_reg[] = { 171 /* enable the under-voltage protection, 172 * the under-voltage protection will shutdown the LDO3 and reset the PMIC 173 */ 174 { RK817_BUCK4_CMIN, 0x6e, 0x6e}, 175 { RK817_PMIC_SYS_CFG1, 0x20, 0x70}, 176 /* Set pmic_sleep as none function */ 177 { RK817_PMIC_SYS_CFG3, 0x00, 0x18 }, 178 /* GATE pin function: gate function */ 179 { RK817_GPIO_INT_CFG, 0x00, 0x20 }, 180 #if CONFIG_IS_ENABLED(IRQ) 181 /* Set pmic_int active low */ 182 { RK817_GPIO_INT_CFG, 0x00, 0x02 }, 183 #endif 184 }; 185 186 static struct reg_data rk818_init_current[] = { 187 { REG_USB_CTRL, 0x07, 0x0f}, /* 2A */ 188 }; 189 190 /* 191 * Order WARNING: Must put "LDO" after the "NLDO" and "PLDO" ! 192 * 193 * See: pmic_bind_children() 194 * if (!strstr(node_name, info->prefix)) { 195 * ...... 196 * } 197 * 198 * Without this order, the prefix "LDO" will be matched if a regulator 199 * dts node name contains "NLDO" or "PLDO". 200 */ 201 static const struct pmic_child_info pmic_children_info[] = { 202 { .prefix = "DCDC", .driver = "rk8xx_buck"}, 203 { .prefix = "NLDO", .driver = "rk8xx_ldo"}, 204 { .prefix = "PLDO", .driver = "rk8xx_pldo"}, 205 { .prefix = "LDO", .driver = "rk8xx_ldo"}, 206 { .prefix = "SWITCH", .driver = "rk8xx_switch"}, 207 { .prefix = "BOOST", .driver = "rk8xx_boost"}, 208 209 { }, 210 }; 211 212 static const struct pmic_child_info power_key_info[] = { 213 { .prefix = "pwrkey", .driver = "rk8xx_pwrkey"}, 214 { }, 215 }; 216 217 static const struct pmic_child_info rtc_info[] = { 218 { .prefix = "rtc", .driver = "rk8xx_rtc"}, 219 { }, 220 }; 221 222 static const struct pmic_child_info fuel_gauge_info[] = { 223 { .addr = "1c", .prefix = "battery", .driver = "rk818_fg"}, 224 { .addr = "20", .prefix = "battery", .driver = "rk817_fg"}, 225 { .addr = "1a", .prefix = "battery", .driver = "rk816_fg"}, 226 { }, 227 }; 228 229 static const struct pmic_child_info rk817_codec_info[] = { 230 { .prefix = "codec", .driver = "rk817_codec"}, 231 { }, 232 }; 233 234 static int rk8xx_reg_count(struct udevice *dev) 235 { 236 struct rk8xx_priv *priv = dev_get_priv(dev); 237 238 switch (priv->variant) { 239 case RK809_ID: 240 case RK817_ID: 241 return RK817_NUM_OF_REGS; 242 default: 243 return RK808_NUM_OF_REGS; 244 } 245 } 246 247 static int rk8xx_write(struct udevice *dev, uint reg, const uint8_t *buff, 248 int len) 249 { 250 int ret; 251 252 ret = dm_i2c_write(dev, reg, buff, len); 253 if (ret) { 254 printf("%s: write reg 0x%02x failed, ret=%d\n", __func__, reg, ret); 255 return ret; 256 } 257 258 return 0; 259 } 260 261 static int rk8xx_read(struct udevice *dev, uint reg, uint8_t *buff, int len) 262 { 263 int ret; 264 265 ret = dm_i2c_read(dev, reg, buff, len); 266 if (ret) { 267 printf("%s: read reg 0x%02x failed, ret=%d\n", __func__, reg, ret); 268 return ret; 269 } 270 271 return 0; 272 } 273 274 static void rk806_shutdown_seq(struct udevice *dev) 275 { 276 struct rk8xx_priv *rk8xx = dev_get_priv(dev); 277 uint8_t value; 278 int i; 279 280 if (!rk8xx->shutdown_sequence) 281 return; 282 283 for (i = RK806_ID_DCDC1; i <= RK806_ID_DCDC10; i++) { 284 value = rk8xx->shutdown_sequence[RK806_ID_DCDC1 + i]; 285 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG0 + i, &value, 1); 286 } 287 288 for (i = RK806_ID_NLDO1; i <= RK806_ID_NLDO5; i++) { 289 value = rk8xx->shutdown_sequence[RK806_ID_NLDO1 + i]; 290 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG0 + i, &value, 1); 291 } 292 293 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG8, &value, 1); 294 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO1] << 6; 295 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG8, &value, 1); 296 297 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG11, &value, 1); 298 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO2] << 6; 299 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG11, &value, 1); 300 301 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG14, &value, 1); 302 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO3] << 6; 303 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG14, &value, 1); 304 305 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG15, &value, 1); 306 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO4]; 307 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG15, &value, 1); 308 309 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG16, &value, 1); 310 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO5]; 311 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG16, &value, 1); 312 313 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG5, &value, 1); 314 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO6] << 6; 315 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG5, &value, 1); 316 } 317 318 static void rk806_vb_shutdown_seq(struct udevice *dev) 319 { 320 struct rk8xx_priv *rk8xx = dev_get_priv(dev); 321 uint8_t value; 322 int i; 323 324 if (!rk8xx->vb_shutdown_sequence) 325 return; 326 327 for (i = RK806_ID_DCDC1; i <= RK806_ID_DCDC10; i++) { 328 value = rk8xx->vb_shutdown_sequence[RK806_ID_DCDC1 + i]; 329 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG0 + i, &value, 1); 330 } 331 332 for (i = RK806_ID_NLDO1; i <= RK806_ID_NLDO5; i++) { 333 value = rk8xx->vb_shutdown_sequence[i]; 334 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG0 + i, &value, 1); 335 } 336 337 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG8, &value, 1); 338 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO1] << 6; 339 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG8, &value, 1); 340 341 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG11, &value, 1); 342 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO2] << 6; 343 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG11, &value, 1); 344 345 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG14, &value, 1); 346 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO3] << 6; 347 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG14, &value, 1); 348 349 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG15, &value, 1); 350 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO4]; 351 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG15, &value, 1); 352 353 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG16, &value, 1); 354 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO5]; 355 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG16, &value, 1); 356 357 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG5, &value, 1); 358 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO6] << 6; 359 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG5, &value, 1); 360 } 361 362 static int rk8xx_suspend(struct udevice *dev) 363 { 364 struct rk8xx_priv *priv = dev_get_priv(dev); 365 int ret = 0; 366 u8 i, val; 367 368 switch (priv->variant) { 369 case RK806_ID: 370 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 371 if (ret) 372 return ret; 373 val &= RK806_PWRCTRL_FUN_MSK; 374 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 375 if (ret) 376 return ret; 377 378 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 379 if (ret) 380 return ret; 381 382 val &= RK806_PWRCTRL_FUN_MSK; 383 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 384 if (ret) 385 return ret; 386 387 for (i = RK806_VSEL_CTR_SEL0; i <= RK806_DVS_CTR_SEL4; i++) { 388 ret = rk8xx_read(dev, i, &val, 1); 389 if (ret) 390 return ret; 391 val &= RK806_VSEL_CTRL_MSK; 392 ret = rk8xx_write(dev, i, &val, 1); 393 if (ret) 394 return ret; 395 } 396 397 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 398 if (ret) 399 return ret; 400 val &= RK806_PWRCTRL_FUN_MSK; 401 val |= RK806_ENABLE_PWRCTRL; 402 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 403 if (ret) 404 return ret; 405 406 for (i = RK806_VSEL_CTR_SEL0; i <= RK806_DVS_CTR_SEL4; i++) { 407 ret = rk8xx_read(dev, i, &val, 1); 408 if (ret) 409 return ret; 410 val &= RK806_VSEL_CTRL_MSK; 411 val |= RK806_VSEL_PWRCTRL1; 412 ret = rk8xx_write(dev, i, &val, 1); 413 if (ret) 414 return ret; 415 } 416 break; 417 case RK809_ID: 418 case RK817_ID: 419 /* pmic_sleep active high */ 420 ret = rk8xx_read(dev, RK817_PMIC_SYS_CFG3, &val, 1); 421 if (ret) 422 return ret; 423 priv->sleep_pin = val; 424 val &= ~0x38; 425 val |= 0x28; 426 ret = rk8xx_write(dev, RK817_PMIC_SYS_CFG3, &val, 1); 427 break; 428 default: 429 return 0; 430 } 431 432 return ret; 433 } 434 435 static int rk8xx_resume(struct udevice *dev) 436 { 437 struct rk8xx_priv *priv = dev_get_priv(dev); 438 int ret = 0; 439 u8 i, val; 440 441 switch (priv->variant) { 442 case RK806_ID: 443 for (i = RK806_VSEL_CTR_SEL0; i <= RK806_DVS_CTR_SEL4; i++) { 444 ret = rk8xx_read(dev, i, &val, 1); 445 if (ret) 446 return ret; 447 val &= RK806_VSEL_CTRL_MSK; 448 ret = rk8xx_write(dev, i, &val, 1); 449 if (ret) 450 return ret; 451 } 452 453 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 454 if (ret) 455 return ret; 456 val &= RK806_PWRCTRL_FUN_MSK; 457 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 458 if (ret) 459 return ret; 460 461 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 462 if (ret) 463 return ret; 464 val &= RK806_PWRCTRL_FUN_MSK; 465 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 466 break; 467 case RK809_ID: 468 case RK817_ID: 469 ret = rk8xx_write(dev, RK817_PMIC_SYS_CFG3, &priv->sleep_pin, 1); 470 break; 471 default: 472 return 0; 473 } 474 475 return ret; 476 } 477 478 static int rk8xx_shutdown(struct udevice *dev) 479 { 480 struct rk8xx_priv *priv = dev_get_priv(dev); 481 u8 val, dev_off, devctrl_reg; 482 int ret = 0; 483 484 switch (priv->variant) { 485 case RK806_ID: 486 rk806_shutdown_seq(dev); 487 devctrl_reg = RK806_SYS_CFG3; 488 dev_off = RK806_DEV_OFF; 489 break; 490 case RK808_ID: 491 devctrl_reg = REG_DEVCTRL; 492 dev_off = BIT(3); 493 break; 494 case RK805_ID: 495 case RK816_ID: 496 case RK818_ID: 497 devctrl_reg = REG_DEVCTRL; 498 dev_off = BIT(0); 499 break; 500 case RK809_ID: 501 case RK817_ID: 502 devctrl_reg = RK817_REG_SYS_CFG3; 503 dev_off = BIT(0); 504 break; 505 default: 506 printf("Unknown PMIC: RK%x\n", priv->variant); 507 return -EINVAL; 508 } 509 510 ret = rk8xx_read(dev, devctrl_reg, &val, 1); 511 if (ret) 512 return ret; 513 514 val |= dev_off; 515 ret = rk8xx_write(dev, devctrl_reg, &val, 1); 516 if (ret) 517 return ret; 518 519 return 0; 520 } 521 522 #if CONFIG_IS_ENABLED(PMIC_CHILDREN) 523 static int rk8xx_bind(struct udevice *dev) 524 { 525 ofnode regulators_node; 526 int children; 527 528 regulators_node = dev_read_subnode(dev, "regulators"); 529 if (!ofnode_valid(regulators_node)) { 530 debug("%s: %s regulators subnode not found!\n", __func__, 531 dev->name); 532 return -ENXIO; 533 } 534 535 debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); 536 537 children = pmic_bind_children(dev, regulators_node, pmic_children_info); 538 if (!children) 539 debug("%s: %s - no child found\n", __func__, dev->name); 540 541 children = pmic_bind_children(dev, dev->node, power_key_info); 542 if (!children) 543 debug("%s: %s - no child found\n", __func__, dev->name); 544 545 children = pmic_bind_children(dev, dev->node, rtc_info); 546 if (!children) 547 debug("%s: %s - no child found\n", __func__, dev->name); 548 549 children = pmic_bind_children(dev, dev->node, fuel_gauge_info); 550 if (!children) 551 debug("%s: %s - no child found\n", __func__, dev->name); 552 553 children = pmic_bind_children(dev, dev->node, rk817_codec_info); 554 if (!children) 555 debug("%s: %s - no child found\n", __func__, dev->name); 556 557 /* Always return success for this device */ 558 return 0; 559 } 560 #endif 561 562 #if CONFIG_IS_ENABLED(IRQ) 563 /* 564 * When system suspend during U-Boot charge, make sure the plugout event 565 * be able to wakeup cpu in wfi/wfe state. 566 */ 567 #ifdef CONFIG_DM_CHARGE_DISPLAY 568 static void rk8xx_plug_out_handler(int irq, void *data) 569 { 570 printf("Plug out interrupt\n"); 571 } 572 #endif 573 574 static int rk8xx_irq_chip_init(struct udevice *dev) 575 { 576 struct rk8xx_priv *priv = dev_get_priv(dev); 577 struct virq_chip *irq_chip = NULL; 578 __maybe_unused int irq_plugout = 1; 579 uint8_t value; 580 int ret; 581 582 switch (priv->variant) { 583 case RK806_ID: 584 irq_chip = &rk806_irq_chip; 585 irq_plugout = 0; 586 ret = rk8xx_read(dev, RK806_GPIO_INT_CONFIG, &value, 1); 587 if (ret) 588 return ret; 589 /* set INT polarity active low */ 590 value &= (~RK806_INT_POL_HIGH); 591 ret = rk8xx_write(dev, RK806_GPIO_INT_CONFIG, &value, 1); 592 if (ret) 593 return ret; 594 break; 595 case RK808_ID: 596 irq_chip = &rk808_irq_chip; 597 break; 598 case RK805_ID: 599 irq_chip = &rk805_irq_chip; 600 irq_plugout = 0; 601 break; 602 case RK816_ID: 603 irq_chip = &rk816_irq_chip; 604 break; 605 case RK818_ID: 606 irq_chip = &rk818_irq_chip; 607 break; 608 case RK809_ID: 609 case RK817_ID: 610 irq_chip = &rk817_irq_chip; 611 break; 612 default: 613 return -EINVAL; 614 } 615 616 if (irq_chip) { 617 ret = virq_add_chip(dev, irq_chip, priv->irq); 618 if (ret) { 619 printf("Failed to add irqchip(irq=%d), ret=%d\n", 620 priv->irq, ret); 621 return ret; 622 } 623 624 priv->irq_chip = irq_chip; 625 626 #ifdef CONFIG_DM_CHARGE_DISPLAY 627 int irq; 628 629 if (irq_plugout) { 630 irq = virq_to_irq(irq_chip, RK8XX_IRQ_PLUG_OUT); 631 if (irq < 0) { 632 printf("Failed to register plugout irq, ret=%d\n", irq); 633 return irq; 634 } 635 irq_install_handler(irq, rk8xx_plug_out_handler, dev); 636 irq_handler_enable_suspend_only(irq); 637 } 638 #endif 639 } 640 641 return 0; 642 } 643 #else 644 static inline int rk8xx_irq_chip_init(struct udevice *dev) { return 0; } 645 #endif 646 647 static int rk8xx_ofdata_to_platdata(struct udevice *dev) 648 { 649 struct rk8xx_priv *rk8xx = dev_get_priv(dev); 650 u32 interrupt, phandle, val; 651 int ret, len; 652 653 phandle = dev_read_u32_default(dev, "interrupt-parent", -ENODATA); 654 if (phandle == -ENODATA) { 655 printf("Read 'interrupt-parent' failed, ret=%d\n", phandle); 656 return phandle; 657 } 658 659 ret = dev_read_u32_array(dev, "interrupts", &interrupt, 1); 660 if (ret) { 661 printf("Read 'interrupts' failed, ret=%d\n", ret); 662 return ret; 663 } 664 665 #if CONFIG_IS_ENABLED(IRQ) 666 rk8xx->irq = phandle_gpio_to_irq(phandle, interrupt); 667 if (rk8xx->irq < 0) { 668 printf("Failed to request rk8xx irq, ret=%d\n", rk8xx->irq); 669 return rk8xx->irq; 670 } 671 #endif 672 val = dev_read_u32_default(dev, "long-press-off-time-sec", 0); 673 if (val <= 6) 674 rk8xx->lp_off_time = RK8XX_LP_TIME_6S; 675 else if (val <= 8) 676 rk8xx->lp_off_time = RK8XX_LP_TIME_8S; 677 else if (val <= 10) 678 rk8xx->lp_off_time = RK8XX_LP_TIME_10S; 679 else 680 rk8xx->lp_off_time = RK8XX_LP_TIME_12S; 681 682 val = dev_read_u32_default(dev, "long-press-restart", 0); 683 if (val) 684 rk8xx->lp_action = RK8XX_LP_RESTART; 685 else 686 rk8xx->lp_action = RK8XX_LP_OFF; 687 688 rk8xx->not_save_power_en = dev_read_u32_default(dev, "not-save-power-en", 0); 689 rk8xx->sys_can_sd = dev_read_bool(dev, "vsys-off-shutdown"); 690 rk8xx->rst_fun = dev_read_u32_default(dev, "pmic-reset-func", 0); 691 /* buck5 external feedback resister disable */ 692 rk8xx->buck5_feedback_dis = dev_read_bool(dev, "buck5-feedback-disable"); 693 694 rk8xx->pwr_ctr[0] = dev_read_u32_default(dev, "pwrctrl1_output", -1); 695 rk8xx->pwr_ctr[1] = dev_read_u32_default(dev, "pwrctrl2_output", -1); 696 rk8xx->pwr_ctr[2] = dev_read_u32_default(dev, "pwrctrl3_output", -1); 697 698 if (!dev_read_prop(dev, "shutdown-sequence", &len)) { 699 printf("can't find shutdown-sequence prop\n"); 700 } else { 701 if (len / 4 != RK806_ID_END) 702 return 0; 703 rk8xx->shutdown_sequence = calloc(len, 1); 704 if (!rk8xx->shutdown_sequence) { 705 printf("can't calloc shutdown_sequence\n"); 706 return 0; 707 } 708 709 if (dev_read_u32_array(dev, "shutdown-sequence", 710 rk8xx->shutdown_sequence, 711 RK806_ID_END)) { 712 printf("can't read shutdown_sequence\n"); 713 free(rk8xx->shutdown_sequence); 714 return 0; 715 } 716 } 717 718 if (!dev_read_prop(dev, "vb-shutdown-sequence", &len)) { 719 printf("can't find vb-shutdown-sequence prop\n"); 720 } else { 721 if (len / 4 != RK806_ID_END) 722 return 0; 723 rk8xx->vb_shutdown_sequence = calloc(len, 1); 724 if (!rk8xx->vb_shutdown_sequence) { 725 printf("can't calloc vb_shutdown_sequence\n"); 726 return 0; 727 } 728 729 if (dev_read_u32_array(dev, "vb-shutdown-sequence", 730 rk8xx->vb_shutdown_sequence, 731 RK806_ID_END)) { 732 printf("can't read vb-shutdown-sequence\n"); 733 free(rk8xx->vb_shutdown_sequence); 734 return 0; 735 } 736 } 737 738 return 0; 739 } 740 741 static void rk806_pwrctrl_output_value(struct udevice *dev, 742 int pin, 743 int output_value) 744 { 745 u8 value; 746 747 rk8xx_read(dev, RK806_PWRCTRL_CONFIG0 + pin / 3, &value, 1); 748 if ((pin == RK806_PWRCTRL1) || (pin == RK806_PWRCTRL3)) { 749 value &= ~RK806_PWRCTR_MSK_FUN; 750 value |= RK806_PWRCTR_GPIO_FUN; 751 } else { 752 value &= ~(RK806_PWRCTR_MSK_FUN << 4); 753 value |= RK806_PWRCTR_GPIO_FUN << 4; 754 } 755 rk8xx_write(dev, RK806_PWRCTRL_CONFIG0 + pin / 3, &value, 1); 756 757 rk8xx_read(dev, RK806_PWRCTRL_GPIO, &value, 1); 758 value &= ~(RK806_PWRCTR_OUTPUT_MSK << (pin - 1)); 759 if (output_value) 760 value |= (RK806_PWRCTR_OUTPUT1 << (pin - 1)); 761 else 762 value |= (RK806_PWRCTR_OUTPUT0 << (pin - 1)); 763 rk8xx_write(dev, RK806_PWRCTRL_GPIO, &value, 1); 764 } 765 766 static int rk8xx_probe(struct udevice *dev) 767 { 768 struct rk8xx_priv *priv = dev_get_priv(dev); 769 struct reg_data *init_current = NULL; 770 struct reg_data *init_data = NULL; 771 int init_current_num = 0; 772 int init_data_num = 0; 773 int ret = 0, i, show_variant; 774 uint8_t msb, lsb, id_msb, id_lsb; 775 uint8_t on_source = 0, off_source = 0; 776 uint8_t pwron_key = 0, lp_off_msk = 0, lp_act_msk = 0; 777 uint8_t power_en0, power_en1, power_en2, power_en3; 778 uint8_t on, off; 779 uint8_t value; 780 781 /* read Chip variant */ 782 if (device_is_compatible(dev, "rockchip,rk817") || 783 device_is_compatible(dev, "rockchip,rk809")) { 784 id_msb = RK817_ID_MSB; 785 id_lsb = RK817_ID_LSB; 786 } else if (device_is_compatible(dev, "rockchip,rk806")) { 787 id_msb = RK806_CHIP_NAME; 788 id_lsb = RK806_CHIP_VER; 789 } else { 790 id_msb = ID_MSB; 791 id_lsb = ID_LSB; 792 } 793 794 ret = rk8xx_read(dev, id_msb, &msb, 1); 795 if (ret) 796 return ret; 797 ret = rk8xx_read(dev, id_lsb, &lsb, 1); 798 if (ret) 799 return ret; 800 801 priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK; 802 show_variant = priv->variant; 803 switch (priv->variant) { 804 case RK806_ID: 805 on_source = RK806_ON_SOURCE; 806 off_source = RK806_OFF_SOURCE; 807 ret = rk8xx_read(dev, RK806_HW_VER, &value, 1); 808 if (ret) 809 panic("RK806: read RK806_HW_VER error!\n"); 810 811 if ((lsb & RK806_VERSION_MSK) == RK806_VERSION_AB) { 812 ret = rk8xx_read(dev, RK806_SYS_CFG1, &value, 1); 813 if (ret) { 814 dev_err(dev, "rk806 RK806_SYS_CFG1 read error: %d\n", ret); 815 return ret; 816 } 817 value |= RK806_ABNORDET_EN; 818 rk8xx_write(dev, RK806_SYS_CFG1, &value, 1); 819 } 820 821 for (i = 0; i < 3; i++) 822 if (priv->pwr_ctr[i] >= 0 && priv->pwr_ctr[i] <= 1) 823 rk806_pwrctrl_output_value(dev, 824 i + 1, 825 priv->pwr_ctr[i]); 826 827 if (priv->rst_fun) { 828 rk8xx_read(dev, RK806_SYS_CFG3, &value, 1); 829 value &= RK806_RESET_FUN_CLR; 830 if (priv->rst_fun == RK806_RST_MODE1) { 831 value |= (RK806_RST_MODE1 << 6); 832 rk8xx_write(dev, RK806_SYS_CFG3, &value, 1); 833 } else if (priv->rst_fun == RK806_RST_MODE2) { 834 value |= (RK806_RST_MODE2 << 6); 835 rk8xx_write(dev, RK806_SYS_CFG3, &value, 1); 836 } 837 } 838 839 if (priv->buck5_feedback_dis) { 840 rk8xx_read(dev, RK806_BUCK_RSERVE_REG3, &value, 1); 841 value &= (~RK806_BUCK5_EX_RES_EN); 842 rk8xx_write(dev, RK806_BUCK_RSERVE_REG3, &value, 1); 843 } 844 rk806_vb_shutdown_seq(dev); 845 break; 846 case RK808_ID: 847 show_variant = 0x808; /* RK808 hardware ID is 0 */ 848 pwron_key = RK8XX_DEVCTRL_REG; 849 lp_off_msk = RK8XX_LP_OFF_MSK; 850 break; 851 case RK805_ID: 852 case RK816_ID: 853 on_source = RK8XX_ON_SOURCE; 854 off_source = RK8XX_OFF_SOURCE; 855 pwron_key = RK8XX_DEVCTRL_REG; 856 lp_off_msk = RK8XX_LP_OFF_MSK; 857 lp_act_msk = RK8XX_LP_ACTION_MSK; 858 break; 859 case RK818_ID: 860 on_source = RK8XX_ON_SOURCE; 861 off_source = RK8XX_OFF_SOURCE; 862 pwron_key = RK8XX_DEVCTRL_REG; 863 lp_off_msk = RK8XX_LP_OFF_MSK; 864 lp_act_msk = RK8XX_LP_ACTION_MSK; 865 /* set current if no fuel gauge */ 866 if (!ofnode_valid(dev_read_subnode(dev, "battery"))) { 867 init_current = rk818_init_current; 868 init_current_num = ARRAY_SIZE(rk818_init_current); 869 } 870 break; 871 case RK809_ID: 872 case RK817_ID: 873 if (device_is_compatible(dev, "rockchip,rk809") && (priv->variant != RK809_ID)) { 874 dev_err(dev, "the dts is RK809, the hardware is RK817\n"); 875 run_command("download", 0); 876 } 877 878 if (device_is_compatible(dev, "rockchip,rk817") && (priv->variant != RK817_ID)) { 879 dev_err(dev, "the dts is RK817, the hardware is RK809\n"); 880 run_command("download", 0); 881 } 882 883 on_source = RK817_ON_SOURCE; 884 off_source = RK817_OFF_SOURCE; 885 pwron_key = RK817_PWRON_KEY; 886 lp_off_msk = RK8XX_LP_OFF_MSK; 887 lp_act_msk = RK8XX_LP_ACTION_MSK; 888 init_data = rk817_init_reg; 889 init_data_num = ARRAY_SIZE(rk817_init_reg); 890 891 /* whether the system voltage can be shutdown in PWR_off mode */ 892 if (priv->sys_can_sd) { 893 ret = rk8xx_read(dev, RK817_PMIC_CHRG_TERM, &value, 1); 894 if (ret) 895 return ret; 896 value |= 0x80; 897 ret = rk8xx_write(dev, RK817_PMIC_CHRG_TERM, &value, 1); 898 if (ret) 899 return ret; 900 } else { 901 ret = rk8xx_read(dev, RK817_PMIC_CHRG_TERM, &value, 1); 902 if (ret) 903 return ret; 904 value &= 0x7f; 905 ret = rk8xx_write(dev, RK817_PMIC_CHRG_TERM, &value, 1); 906 if (ret) 907 return ret; 908 } 909 910 if ((priv->rst_fun > RK8xx_RST_MODE0) && 911 (priv->rst_fun <= RK8xx_RST_MODE2)) { 912 rk8xx_read(dev, RK817_PMIC_SYS_CFG3, &value, 1); 913 value &= RK8xx_RESET_FUN_CLR; 914 value |= (priv->rst_fun << 6); 915 rk8xx_write(dev, RK817_PMIC_SYS_CFG3, &value, 1); 916 } 917 /* judge whether save the PMIC_POWER_EN register */ 918 if (!priv->not_save_power_en) { 919 ret = rk8xx_read(dev, RK817_POWER_EN0, &power_en0, 1); 920 if (ret) 921 return ret; 922 ret = rk8xx_read(dev, RK817_POWER_EN1, &power_en1, 1); 923 if (ret) 924 return ret; 925 ret = rk8xx_read(dev, RK817_POWER_EN2, &power_en2, 1); 926 if (ret) 927 return ret; 928 ret = rk8xx_read(dev, RK817_POWER_EN3, &power_en3, 1); 929 if (ret) 930 return ret; 931 932 value = (power_en0 & 0x0f) | ((power_en1 & 0x0f) << 4); 933 rk8xx_write(dev, RK817_POWER_EN_SAVE0, &value, 1); 934 value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4); 935 rk8xx_write(dev, RK817_POWER_EN_SAVE1, &value, 1); 936 } 937 break; 938 default: 939 printf("Unknown PMIC: RK%x!!\n", priv->variant); 940 return -EINVAL; 941 } 942 943 /* common init */ 944 for (i = 0; i < init_data_num; i++) { 945 ret = pmic_clrsetbits(dev, 946 init_data[i].reg, 947 init_data[i].mask, 948 init_data[i].val); 949 if (ret < 0) { 950 printf("%s: i2c set reg 0x%x failed, ret=%d\n", 951 __func__, init_data[i].reg, ret); 952 } 953 } 954 955 /* current init */ 956 for (i = 0; i < init_current_num; i++) { 957 ret = pmic_clrsetbits(dev, 958 init_current[i].reg, 959 init_current[i].mask, 960 init_current[i].val); 961 if (ret < 0) { 962 printf("%s: i2c set reg 0x%x failed, ret=%d\n", 963 __func__, init_current[i].reg, ret); 964 } 965 } 966 967 printf("PMIC: RK%x ", show_variant); 968 969 if (on_source && off_source) { 970 rk8xx_read(dev, on_source, &on, 1); 971 rk8xx_read(dev, off_source, &off, 1); 972 printf("(on=0x%02x, off=0x%02x)", on, off); 973 } 974 printf("\n"); 975 976 if (pwron_key) { 977 ret = rk8xx_read(dev, pwron_key, &value, 1); 978 if (ret) 979 return ret; 980 value &= ~(lp_off_msk | lp_act_msk); 981 if (lp_off_msk) 982 value |= priv->lp_off_time; 983 if (lp_act_msk) 984 value |= priv->lp_action; 985 rk8xx_write(dev, pwron_key, &value, 1); 986 } 987 988 ret = rk8xx_irq_chip_init(dev); 989 if (ret) { 990 printf("IRQ chip initial failed\n"); 991 return ret; 992 } 993 994 return 0; 995 } 996 997 static struct dm_pmic_ops rk8xx_ops = { 998 .reg_count = rk8xx_reg_count, 999 .read = rk8xx_read, 1000 .write = rk8xx_write, 1001 .suspend = rk8xx_suspend, 1002 .resume = rk8xx_resume, 1003 .shutdown = rk8xx_shutdown, 1004 }; 1005 1006 static const struct udevice_id rk8xx_ids[] = { 1007 { .compatible = "rockchip,rk805" }, 1008 { .compatible = "rockchip,rk806" }, 1009 { .compatible = "rockchip,rk808" }, 1010 { .compatible = "rockchip,rk809" }, 1011 { .compatible = "rockchip,rk816" }, 1012 { .compatible = "rockchip,rk817" }, 1013 { .compatible = "rockchip,rk818" }, 1014 { } 1015 }; 1016 1017 U_BOOT_DRIVER(pmic_rk8xx) = { 1018 .name = "rk8xx pmic", 1019 .id = UCLASS_PMIC, 1020 .of_match = rk8xx_ids, 1021 #if CONFIG_IS_ENABLED(PMIC_CHILDREN) 1022 .bind = rk8xx_bind, 1023 #endif 1024 .ofdata_to_platdata = rk8xx_ofdata_to_platdata, 1025 .priv_auto_alloc_size = sizeof(struct rk8xx_priv), 1026 .probe = rk8xx_probe, 1027 .ops = &rk8xx_ops, 1028 }; 1029