1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <irq-generic.h> 12 #include <power/rk8xx_pmic.h> 13 #include <power/pmic.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #if CONFIG_IS_ENABLED(IRQ) 18 /* RK805 */ 19 static const struct virq_reg rk805_irqs[] = { 20 [RK8XX_IRQ_PWRON_FALL] = { 21 .mask = RK805_IRQ_PWRON_FALL_MSK, 22 .reg_offset = 0, 23 }, 24 [RK8XX_IRQ_PWRON_RISE] = { 25 .mask = RK805_IRQ_PWRON_RISE_MSK, 26 .reg_offset = 0, 27 }, 28 }; 29 30 static struct virq_chip rk805_irq_chip = { 31 .status_base = RK805_INT_STS_REG, 32 .mask_base = RK805_INT_MSK_REG, 33 .num_regs = 1, 34 .read = pmic_reg_read, 35 .write = pmic_reg_write, 36 .irqs = rk805_irqs, 37 .num_irqs = ARRAY_SIZE(rk805_irqs), 38 }; 39 40 /* RK806 */ 41 static const struct virq_reg rk806_irqs[] = { 42 [RK8XX_IRQ_PWRON_FALL] = { 43 .mask = RK806_IRQ_PWRON_FALL_MSK, 44 .reg_offset = 0, 45 }, 46 [RK8XX_IRQ_PWRON_RISE] = { 47 .mask = RK806_IRQ_PWRON_RISE_MSK, 48 .reg_offset = 0, 49 }, 50 }; 51 52 static struct virq_chip rk806_irq_chip = { 53 .status_base = RK806_INT_STS0, 54 .mask_base = RK806_INT_MSK0, 55 .irq_reg_stride = 2, 56 .num_regs = 2, 57 .read = pmic_reg_read, 58 .write = pmic_reg_write, 59 .irqs = rk806_irqs, 60 .num_irqs = ARRAY_SIZE(rk806_irqs), 61 }; 62 63 /* RK808 */ 64 static const struct virq_reg rk808_irqs[] = { 65 [RK8XX_IRQ_PLUG_OUT] = { 66 .mask = RK808_IRQ_PLUG_OUT_MSK, 67 .reg_offset = 1, 68 }, 69 }; 70 71 static struct virq_chip rk808_irq_chip = { 72 .status_base = RK808_INT_STS_REG1, 73 .mask_base = RK808_INT_MSK_REG1, 74 .irq_reg_stride = 2, 75 .num_regs = 2, 76 .read = pmic_reg_read, 77 .write = pmic_reg_write, 78 .irqs = rk808_irqs, 79 .num_irqs = ARRAY_SIZE(rk808_irqs), 80 }; 81 82 /* RK816 */ 83 static const struct virq_reg rk816_irqs[] = { 84 [RK8XX_IRQ_PWRON_FALL] = { 85 .mask = RK816_IRQ_PWRON_FALL_MSK, 86 .reg_offset = 0, 87 }, 88 [RK8XX_IRQ_PWRON_RISE] = { 89 .mask = RK816_IRQ_PWRON_RISE_MSK, 90 .reg_offset = 0, 91 }, 92 [RK8XX_IRQ_PLUG_OUT] = { 93 .mask = RK816_IRQ_PLUG_OUT_MSK, 94 .reg_offset = 2, 95 }, 96 [RK8XX_IRQ_CHG_OK] = { 97 .mask = RK816_IRQ_CHR_OK_MSK, 98 .reg_offset = 2, 99 }, 100 }; 101 102 static struct virq_chip rk816_irq_chip = { 103 .status_base = RK816_INT_STS_REG1, 104 .mask_base = RK816_INT_MSK_REG1, 105 .irq_unalign_reg_idx = 1, /* idx <= 1, stride = 3 */ 106 .irq_unalign_reg_stride = 3, 107 .irq_reg_stride = 2, /* idx > 1, stride = 2 */ 108 .num_regs = 3, 109 .read = pmic_reg_read, 110 .write = pmic_reg_write, 111 .irqs = rk816_irqs, 112 .num_irqs = ARRAY_SIZE(rk816_irqs), 113 }; 114 115 /* RK818 */ 116 static const struct virq_reg rk818_irqs[] = { 117 [RK8XX_IRQ_PLUG_OUT] = { 118 .mask = RK818_IRQ_PLUG_OUT_MSK, 119 .reg_offset = 1, 120 }, 121 [RK8XX_IRQ_CHG_OK] = { 122 .mask = RK818_IRQ_CHR_OK_MSK, 123 .reg_offset = 1, 124 }, 125 }; 126 127 static struct virq_chip rk818_irq_chip = { 128 .status_base = RK818_INT_STS_REG1, 129 .mask_base = RK818_INT_MSK_REG1, 130 .irq_reg_stride = 2, 131 .num_regs = 2, 132 .read = pmic_reg_read, 133 .write = pmic_reg_write, 134 .irqs = rk818_irqs, 135 .num_irqs = ARRAY_SIZE(rk818_irqs), 136 }; 137 138 /* RK817/RK809 */ 139 static const struct virq_reg rk817_irqs[] = { 140 [RK8XX_IRQ_PWRON_FALL] = { 141 .mask = RK817_IRQ_PWRON_FALL_MSK, 142 .reg_offset = 0, 143 }, 144 [RK8XX_IRQ_PWRON_RISE] = { 145 .mask = RK817_IRQ_PWRON_RISE_MSK, 146 .reg_offset = 0, 147 }, 148 [RK8XX_IRQ_PLUG_OUT] = { 149 .mask = RK817_IRQ_PLUG_OUT_MSK, 150 .reg_offset = 1, 151 }, 152 [RK8XX_IRQ_PLUG_IN] = { 153 .mask = RK817_IRQ_PLUG_IN_MSK, 154 .reg_offset = 1, 155 }, 156 }; 157 158 static struct virq_chip rk817_irq_chip = { 159 .status_base = RK817_INT_STS_REG0, 160 .mask_base = RK817_INT_MSK_REG0, 161 .irq_reg_stride = 2, 162 .num_regs = 3, 163 .read = pmic_reg_read, 164 .write = pmic_reg_write, 165 .irqs = rk817_irqs, 166 .num_irqs = ARRAY_SIZE(rk817_irqs), 167 }; 168 #endif 169 170 static struct reg_data rk817_init_reg[] = { 171 /* enable the under-voltage protection, 172 * the under-voltage protection will shutdown the LDO3 and reset the PMIC 173 */ 174 { RK817_BUCK4_CMIN, 0x6e, 0x6e}, 175 { RK817_PMIC_SYS_CFG1, 0x20, 0x70}, 176 /* Set pmic_sleep as none function */ 177 { RK817_PMIC_SYS_CFG3, 0x00, 0x18 }, 178 /* GATE pin function: gate function */ 179 { RK817_GPIO_INT_CFG, 0x00, 0x20 }, 180 #ifdef CONFIG_DM_CHARGE_DISPLAY 181 /* Set pmic_int active low */ 182 { RK817_GPIO_INT_CFG, 0x00, 0x02 }, 183 #endif 184 }; 185 186 static struct reg_data rk818_init_current[] = { 187 { REG_USB_CTRL, 0x07, 0x0f}, /* 2A */ 188 }; 189 190 /* 191 * Order WARNING: Must put "LDO" after the "NLDO" and "PLDO" ! 192 * 193 * See: pmic_bind_children() 194 * if (!strstr(node_name, info->prefix)) { 195 * ...... 196 * } 197 * 198 * Without this order, the prefix "LDO" will be matched if a regulator 199 * dts node name contains "NLDO" or "PLDO". 200 */ 201 static const struct pmic_child_info pmic_children_info[] = { 202 { .prefix = "DCDC", .driver = "rk8xx_buck"}, 203 { .prefix = "NLDO", .driver = "rk8xx_ldo"}, 204 { .prefix = "PLDO", .driver = "rk8xx_pldo"}, 205 { .prefix = "LDO", .driver = "rk8xx_ldo"}, 206 { .prefix = "SWITCH", .driver = "rk8xx_switch"}, 207 { }, 208 }; 209 210 static const struct pmic_child_info power_key_info[] = { 211 { .prefix = "pwrkey", .driver = "rk8xx_pwrkey"}, 212 { }, 213 }; 214 215 static const struct pmic_child_info rtc_info[] = { 216 { .prefix = "rtc", .driver = "rk8xx_rtc"}, 217 { }, 218 }; 219 220 static const struct pmic_child_info fuel_gauge_info[] = { 221 { .addr = "1c", .prefix = "battery", .driver = "rk818_fg"}, 222 { .addr = "20", .prefix = "battery", .driver = "rk817_fg"}, 223 { .addr = "1a", .prefix = "battery", .driver = "rk816_fg"}, 224 { }, 225 }; 226 227 static const struct pmic_child_info rk817_codec_info[] = { 228 { .prefix = "codec", .driver = "rk817_codec"}, 229 { }, 230 }; 231 232 static int rk8xx_reg_count(struct udevice *dev) 233 { 234 struct rk8xx_priv *priv = dev_get_priv(dev); 235 236 switch (priv->variant) { 237 case RK809_ID: 238 case RK817_ID: 239 return RK817_NUM_OF_REGS; 240 default: 241 return RK808_NUM_OF_REGS; 242 } 243 } 244 245 static int rk8xx_write(struct udevice *dev, uint reg, const uint8_t *buff, 246 int len) 247 { 248 int ret; 249 250 ret = dm_i2c_write(dev, reg, buff, len); 251 if (ret) { 252 printf("%s: write reg 0x%02x failed, ret=%d\n", __func__, reg, ret); 253 return ret; 254 } 255 256 return 0; 257 } 258 259 static int rk8xx_read(struct udevice *dev, uint reg, uint8_t *buff, int len) 260 { 261 int ret; 262 263 ret = dm_i2c_read(dev, reg, buff, len); 264 if (ret) { 265 printf("%s: read reg 0x%02x failed, ret=%d\n", __func__, reg, ret); 266 return ret; 267 } 268 269 return 0; 270 } 271 272 static void rk806_shutdown_seq(struct udevice *dev) 273 { 274 struct rk8xx_priv *rk8xx = dev_get_priv(dev); 275 uint8_t value; 276 int i; 277 278 if (!rk8xx->shutdown_sequence) 279 return; 280 281 for (i = RK806_ID_DCDC1; i <= RK806_ID_DCDC10; i++) { 282 value = rk8xx->shutdown_sequence[RK806_ID_DCDC1 + i]; 283 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG0 + i, &value, 1); 284 } 285 286 for (i = RK806_ID_NLDO1; i <= RK806_ID_NLDO5; i++) { 287 value = rk8xx->shutdown_sequence[RK806_ID_NLDO1 + i]; 288 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG0 + i, &value, 1); 289 } 290 291 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG8, &value, 1); 292 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO1] << 6; 293 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG8, &value, 1); 294 295 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG11, &value, 1); 296 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO2] << 6; 297 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG11, &value, 1); 298 299 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG14, &value, 1); 300 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO3] << 6; 301 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG14, &value, 1); 302 303 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG15, &value, 1); 304 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO4]; 305 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG15, &value, 1); 306 307 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG16, &value, 1); 308 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO5]; 309 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG16, &value, 1); 310 311 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG5, &value, 1); 312 value |= rk8xx->shutdown_sequence[RK806_ID_PLDO6] << 6; 313 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG5, &value, 1); 314 } 315 316 static void rk806_vb_shutdown_seq(struct udevice *dev) 317 { 318 struct rk8xx_priv *rk8xx = dev_get_priv(dev); 319 uint8_t value; 320 int i; 321 322 if (!rk8xx->vb_shutdown_sequence) 323 return; 324 325 for (i = RK806_ID_DCDC1; i <= RK806_ID_DCDC10; i++) { 326 value = rk8xx->vb_shutdown_sequence[RK806_ID_DCDC1 + i]; 327 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG0 + i, &value, 1); 328 } 329 330 for (i = RK806_ID_NLDO1; i <= RK806_ID_NLDO5; i++) { 331 value = rk8xx->vb_shutdown_sequence[i]; 332 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG0 + i, &value, 1); 333 } 334 335 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG8, &value, 1); 336 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO1] << 6; 337 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG8, &value, 1); 338 339 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG11, &value, 1); 340 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO2] << 6; 341 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG11, &value, 1); 342 343 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG14, &value, 1); 344 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO3] << 6; 345 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG14, &value, 1); 346 347 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG15, &value, 1); 348 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO4]; 349 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG15, &value, 1); 350 351 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG16, &value, 1); 352 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO5]; 353 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG16, &value, 1); 354 355 rk8xx_read(dev, RK806_SHUTDOWN_SEQ_REG5, &value, 1); 356 value |= rk8xx->vb_shutdown_sequence[RK806_ID_PLDO6] << 6; 357 rk8xx_write(dev, RK806_SHUTDOWN_SEQ_REG5, &value, 1); 358 } 359 360 static int rk8xx_suspend(struct udevice *dev) 361 { 362 struct rk8xx_priv *priv = dev_get_priv(dev); 363 int ret = 0; 364 u8 i, val; 365 366 switch (priv->variant) { 367 case RK806_ID: 368 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 369 if (ret) 370 return ret; 371 val &= RK806_PWRCTRL_FUN_MSK; 372 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 373 if (ret) 374 return ret; 375 376 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 377 if (ret) 378 return ret; 379 380 val &= RK806_PWRCTRL_FUN_MSK; 381 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 382 if (ret) 383 return ret; 384 385 for (i = RK806_VSEL_CTR_SEL0; i <= RK806_DVS_CTR_SEL4; i++) { 386 ret = rk8xx_read(dev, i, &val, 1); 387 if (ret) 388 return ret; 389 val &= RK806_VSEL_CTRL_MSK; 390 ret = rk8xx_write(dev, i, &val, 1); 391 if (ret) 392 return ret; 393 } 394 395 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 396 if (ret) 397 return ret; 398 val &= RK806_PWRCTRL_FUN_MSK; 399 val |= RK806_ENABLE_PWRCTRL; 400 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 401 if (ret) 402 return ret; 403 404 for (i = RK806_VSEL_CTR_SEL0; i <= RK806_DVS_CTR_SEL4; i++) { 405 ret = rk8xx_read(dev, i, &val, 1); 406 if (ret) 407 return ret; 408 val &= RK806_VSEL_CTRL_MSK; 409 val |= RK806_VSEL_PWRCTRL1; 410 ret = rk8xx_write(dev, i, &val, 1); 411 if (ret) 412 return ret; 413 } 414 break; 415 case RK809_ID: 416 case RK817_ID: 417 /* pmic_sleep active high */ 418 ret = rk8xx_read(dev, RK817_PMIC_SYS_CFG3, &val, 1); 419 if (ret) 420 return ret; 421 priv->sleep_pin = val; 422 val &= ~0x38; 423 val |= 0x28; 424 ret = rk8xx_write(dev, RK817_PMIC_SYS_CFG3, &val, 1); 425 break; 426 default: 427 return 0; 428 } 429 430 return ret; 431 } 432 433 static int rk8xx_resume(struct udevice *dev) 434 { 435 struct rk8xx_priv *priv = dev_get_priv(dev); 436 int ret = 0; 437 u8 i, val; 438 439 switch (priv->variant) { 440 case RK806_ID: 441 for (i = RK806_VSEL_CTR_SEL0; i <= RK806_DVS_CTR_SEL4; i++) { 442 ret = rk8xx_read(dev, i, &val, 1); 443 if (ret) 444 return ret; 445 val &= RK806_VSEL_CTRL_MSK; 446 ret = rk8xx_write(dev, i, &val, 1); 447 if (ret) 448 return ret; 449 } 450 451 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 452 if (ret) 453 return ret; 454 val &= RK806_PWRCTRL_FUN_MSK; 455 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG0, &val, 1); 456 if (ret) 457 return ret; 458 459 ret = rk8xx_read(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 460 if (ret) 461 return ret; 462 val &= RK806_PWRCTRL_FUN_MSK; 463 ret = rk8xx_write(dev, RK806_PWRCTRL_CONFIG1, &val, 1); 464 break; 465 case RK809_ID: 466 case RK817_ID: 467 ret = rk8xx_write(dev, RK817_PMIC_SYS_CFG3, &priv->sleep_pin, 1); 468 break; 469 default: 470 return 0; 471 } 472 473 return ret; 474 } 475 476 static int rk8xx_shutdown(struct udevice *dev) 477 { 478 struct rk8xx_priv *priv = dev_get_priv(dev); 479 u8 val, dev_off, devctrl_reg; 480 int ret = 0; 481 482 switch (priv->variant) { 483 case RK806_ID: 484 rk806_shutdown_seq(dev); 485 devctrl_reg = RK806_SYS_CFG3; 486 dev_off = RK806_DEV_OFF; 487 break; 488 case RK808_ID: 489 devctrl_reg = REG_DEVCTRL; 490 dev_off = BIT(3); 491 break; 492 case RK805_ID: 493 case RK816_ID: 494 case RK818_ID: 495 devctrl_reg = REG_DEVCTRL; 496 dev_off = BIT(0); 497 break; 498 case RK809_ID: 499 case RK817_ID: 500 devctrl_reg = RK817_REG_SYS_CFG3; 501 dev_off = BIT(0); 502 break; 503 default: 504 printf("Unknown PMIC: RK%x\n", priv->variant); 505 return -EINVAL; 506 } 507 508 ret = rk8xx_read(dev, devctrl_reg, &val, 1); 509 if (ret) 510 return ret; 511 512 val |= dev_off; 513 ret = rk8xx_write(dev, devctrl_reg, &val, 1); 514 if (ret) 515 return ret; 516 517 return 0; 518 } 519 520 #if CONFIG_IS_ENABLED(PMIC_CHILDREN) 521 static int rk8xx_bind(struct udevice *dev) 522 { 523 ofnode regulators_node; 524 int children; 525 526 regulators_node = dev_read_subnode(dev, "regulators"); 527 if (!ofnode_valid(regulators_node)) { 528 debug("%s: %s regulators subnode not found!\n", __func__, 529 dev->name); 530 return -ENXIO; 531 } 532 533 debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); 534 535 children = pmic_bind_children(dev, regulators_node, pmic_children_info); 536 if (!children) 537 debug("%s: %s - no child found\n", __func__, dev->name); 538 539 children = pmic_bind_children(dev, dev->node, power_key_info); 540 if (!children) 541 debug("%s: %s - no child found\n", __func__, dev->name); 542 543 children = pmic_bind_children(dev, dev->node, rtc_info); 544 if (!children) 545 debug("%s: %s - no child found\n", __func__, dev->name); 546 547 children = pmic_bind_children(dev, dev->node, fuel_gauge_info); 548 if (!children) 549 debug("%s: %s - no child found\n", __func__, dev->name); 550 551 children = pmic_bind_children(dev, dev->node, rk817_codec_info); 552 if (!children) 553 debug("%s: %s - no child found\n", __func__, dev->name); 554 555 /* Always return success for this device */ 556 return 0; 557 } 558 #endif 559 560 #if CONFIG_IS_ENABLED(IRQ) 561 /* 562 * When system suspend during U-Boot charge, make sure the plugout event 563 * be able to wakeup cpu in wfi/wfe state. 564 */ 565 #ifdef CONFIG_DM_CHARGE_DISPLAY 566 static void rk8xx_plug_out_handler(int irq, void *data) 567 { 568 printf("Plug out interrupt\n"); 569 } 570 #endif 571 572 static int rk8xx_irq_chip_init(struct udevice *dev) 573 { 574 struct rk8xx_priv *priv = dev_get_priv(dev); 575 struct virq_chip *irq_chip = NULL; 576 __maybe_unused int irq_plugout = 1; 577 uint8_t value; 578 int ret; 579 580 switch (priv->variant) { 581 case RK806_ID: 582 irq_chip = &rk806_irq_chip; 583 irq_plugout = 0; 584 ret = rk8xx_read(dev, RK806_GPIO_INT_CONFIG, &value, 1); 585 if (ret) 586 return ret; 587 /* set INT polarity active low */ 588 value &= (~RK806_INT_POL_HIGH); 589 ret = rk8xx_write(dev, RK806_GPIO_INT_CONFIG, &value, 1); 590 if (ret) 591 return ret; 592 break; 593 case RK808_ID: 594 irq_chip = &rk808_irq_chip; 595 break; 596 case RK805_ID: 597 irq_chip = &rk805_irq_chip; 598 irq_plugout = 0; 599 break; 600 case RK816_ID: 601 irq_chip = &rk816_irq_chip; 602 break; 603 case RK818_ID: 604 irq_chip = &rk818_irq_chip; 605 break; 606 case RK809_ID: 607 case RK817_ID: 608 irq_chip = &rk817_irq_chip; 609 break; 610 default: 611 return -EINVAL; 612 } 613 614 if (irq_chip) { 615 ret = virq_add_chip(dev, irq_chip, priv->irq); 616 if (ret) { 617 printf("Failed to add irqchip(irq=%d), ret=%d\n", 618 priv->irq, ret); 619 return ret; 620 } 621 622 priv->irq_chip = irq_chip; 623 624 #ifdef CONFIG_DM_CHARGE_DISPLAY 625 int irq; 626 627 if (irq_plugout) { 628 irq = virq_to_irq(irq_chip, RK8XX_IRQ_PLUG_OUT); 629 if (irq < 0) { 630 printf("Failed to register plugout irq, ret=%d\n", irq); 631 return irq; 632 } 633 irq_install_handler(irq, rk8xx_plug_out_handler, dev); 634 irq_handler_enable_suspend_only(irq); 635 } 636 #endif 637 } 638 639 return 0; 640 } 641 #else 642 static inline int rk8xx_irq_chip_init(struct udevice *dev) { return 0; } 643 #endif 644 645 static int rk8xx_ofdata_to_platdata(struct udevice *dev) 646 { 647 struct rk8xx_priv *rk8xx = dev_get_priv(dev); 648 u32 interrupt, phandle, val; 649 int ret, len; 650 651 phandle = dev_read_u32_default(dev, "interrupt-parent", -ENODATA); 652 if (phandle == -ENODATA) { 653 printf("Read 'interrupt-parent' failed, ret=%d\n", phandle); 654 return phandle; 655 } 656 657 ret = dev_read_u32_array(dev, "interrupts", &interrupt, 1); 658 if (ret) { 659 printf("Read 'interrupts' failed, ret=%d\n", ret); 660 return ret; 661 } 662 663 #if CONFIG_IS_ENABLED(IRQ) 664 rk8xx->irq = phandle_gpio_to_irq(phandle, interrupt); 665 if (rk8xx->irq < 0) { 666 printf("Failed to request rk8xx irq, ret=%d\n", rk8xx->irq); 667 return rk8xx->irq; 668 } 669 #endif 670 val = dev_read_u32_default(dev, "long-press-off-time-sec", 0); 671 if (val <= 6) 672 rk8xx->lp_off_time = RK8XX_LP_TIME_6S; 673 else if (val <= 8) 674 rk8xx->lp_off_time = RK8XX_LP_TIME_8S; 675 else if (val <= 10) 676 rk8xx->lp_off_time = RK8XX_LP_TIME_10S; 677 else 678 rk8xx->lp_off_time = RK8XX_LP_TIME_12S; 679 680 val = dev_read_u32_default(dev, "long-press-restart", 0); 681 if (val) 682 rk8xx->lp_action = RK8XX_LP_RESTART; 683 else 684 rk8xx->lp_action = RK8XX_LP_OFF; 685 686 rk8xx->not_save_power_en = dev_read_u32_default(dev, "not-save-power-en", 0); 687 rk8xx->sys_can_sd = dev_read_bool(dev, "vsys-off-shutdown"); 688 rk8xx->rst_fun = dev_read_u32_default(dev, "pmic-reset-func", 0); 689 /* buck5 external feedback resister disable */ 690 rk8xx->buck5_feedback_dis = dev_read_bool(dev, "buck5-feedback-disable"); 691 692 rk8xx->pwr_ctr[0] = dev_read_u32_default(dev, "pwrctrl1_output", -1); 693 rk8xx->pwr_ctr[1] = dev_read_u32_default(dev, "pwrctrl2_output", -1); 694 rk8xx->pwr_ctr[2] = dev_read_u32_default(dev, "pwrctrl3_output", -1); 695 696 if (!dev_read_prop(dev, "shutdown-sequence", &len)) { 697 printf("can't find shutdown-sequence prop\n"); 698 } else { 699 if (len / 4 != RK806_ID_END) 700 return 0; 701 rk8xx->shutdown_sequence = calloc(len, 1); 702 if (!rk8xx->shutdown_sequence) { 703 printf("can't calloc shutdown_sequence\n"); 704 return 0; 705 } 706 707 if (dev_read_u32_array(dev, "shutdown-sequence", 708 rk8xx->shutdown_sequence, 709 RK806_ID_END)) { 710 printf("can't read shutdown_sequence\n"); 711 free(rk8xx->shutdown_sequence); 712 return 0; 713 } 714 } 715 716 if (!dev_read_prop(dev, "vb-shutdown-sequence", &len)) { 717 printf("can't find vb-shutdown-sequence prop\n"); 718 } else { 719 if (len / 4 != RK806_ID_END) 720 return 0; 721 rk8xx->vb_shutdown_sequence = calloc(len, 1); 722 if (!rk8xx->vb_shutdown_sequence) { 723 printf("can't calloc vb_shutdown_sequence\n"); 724 return 0; 725 } 726 727 if (dev_read_u32_array(dev, "vb-shutdown-sequence", 728 rk8xx->vb_shutdown_sequence, 729 RK806_ID_END)) { 730 printf("can't read vb-shutdown-sequence\n"); 731 free(rk8xx->vb_shutdown_sequence); 732 return 0; 733 } 734 } 735 736 return 0; 737 } 738 739 static void rk806_pwrctrl_output_value(struct udevice *dev, 740 int pin, 741 int output_value) 742 { 743 u8 value; 744 745 rk8xx_read(dev, RK806_PWRCTRL_CONFIG0 + pin / 3, &value, 1); 746 if ((pin == RK806_PWRCTRL1) || (pin == RK806_PWRCTRL3)) { 747 value &= ~RK806_PWRCTR_MSK_FUN; 748 value |= RK806_PWRCTR_GPIO_FUN; 749 } else { 750 value &= ~(RK806_PWRCTR_MSK_FUN << 4); 751 value |= RK806_PWRCTR_GPIO_FUN << 4; 752 } 753 rk8xx_write(dev, RK806_PWRCTRL_CONFIG0 + pin / 3, &value, 1); 754 755 rk8xx_read(dev, RK806_PWRCTRL_GPIO, &value, 1); 756 value &= ~(RK806_PWRCTR_OUTPUT_MSK << (pin - 1)); 757 if (output_value) 758 value |= (RK806_PWRCTR_OUTPUT1 << (pin - 1)); 759 else 760 value |= (RK806_PWRCTR_OUTPUT0 << (pin - 1)); 761 rk8xx_write(dev, RK806_PWRCTRL_GPIO, &value, 1); 762 } 763 764 static int rk8xx_probe(struct udevice *dev) 765 { 766 struct rk8xx_priv *priv = dev_get_priv(dev); 767 struct reg_data *init_current = NULL; 768 struct reg_data *init_data = NULL; 769 int init_current_num = 0; 770 int init_data_num = 0; 771 int ret = 0, i, show_variant; 772 uint8_t msb, lsb, id_msb, id_lsb; 773 uint8_t on_source = 0, off_source = 0; 774 uint8_t pwron_key = 0, lp_off_msk = 0, lp_act_msk = 0; 775 uint8_t power_en0, power_en1, power_en2, power_en3; 776 uint8_t on, off; 777 uint8_t value; 778 779 /* read Chip variant */ 780 if (device_is_compatible(dev, "rockchip,rk817") || 781 device_is_compatible(dev, "rockchip,rk809")) { 782 id_msb = RK817_ID_MSB; 783 id_lsb = RK817_ID_LSB; 784 } else if (device_is_compatible(dev, "rockchip,rk806")) { 785 id_msb = RK806_CHIP_NAME; 786 id_lsb = RK806_CHIP_VER; 787 } else { 788 id_msb = ID_MSB; 789 id_lsb = ID_LSB; 790 } 791 792 ret = rk8xx_read(dev, id_msb, &msb, 1); 793 if (ret) 794 return ret; 795 ret = rk8xx_read(dev, id_lsb, &lsb, 1); 796 if (ret) 797 return ret; 798 799 priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK; 800 show_variant = priv->variant; 801 switch (priv->variant) { 802 case RK806_ID: 803 on_source = RK806_ON_SOURCE; 804 off_source = RK806_OFF_SOURCE; 805 ret = rk8xx_read(dev, RK806_HW_VER, &value, 1); 806 if (ret) 807 panic("RK806: read RK806_HW_VER error!\n"); 808 809 if ((lsb & RK806_VERSION_MSK) == RK806_VERSION_AB) { 810 ret = rk8xx_read(dev, RK806_SYS_CFG1, &value, 1); 811 if (ret) { 812 dev_err(dev, "rk806 RK806_SYS_CFG1 read error: %d\n", ret); 813 return ret; 814 } 815 value |= RK806_ABNORDET_EN; 816 rk8xx_write(dev, RK806_SYS_CFG1, &value, 1); 817 } 818 819 for (i = 0; i < 3; i++) 820 if (priv->pwr_ctr[i] >= 0 && priv->pwr_ctr[i] <= 1) 821 rk806_pwrctrl_output_value(dev, 822 i + 1, 823 priv->pwr_ctr[i]); 824 825 if (priv->rst_fun) { 826 rk8xx_read(dev, RK806_SYS_CFG3, &value, 1); 827 value &= RK806_RESET_FUN_CLR; 828 if (priv->rst_fun == RK806_RST_MODE1) { 829 value |= (RK806_RST_MODE1 << 6); 830 rk8xx_write(dev, RK806_SYS_CFG3, &value, 1); 831 } else if (priv->rst_fun == RK806_RST_MODE2) { 832 value |= (RK806_RST_MODE2 << 6); 833 rk8xx_write(dev, RK806_SYS_CFG3, &value, 1); 834 } 835 } 836 837 if (priv->buck5_feedback_dis) { 838 rk8xx_read(dev, RK806_BUCK_RSERVE_REG3, &value, 1); 839 value &= (~RK806_BUCK5_EX_RES_EN); 840 rk8xx_write(dev, RK806_BUCK_RSERVE_REG3, &value, 1); 841 } 842 rk806_vb_shutdown_seq(dev); 843 break; 844 case RK808_ID: 845 show_variant = 0x808; /* RK808 hardware ID is 0 */ 846 pwron_key = RK8XX_DEVCTRL_REG; 847 lp_off_msk = RK8XX_LP_OFF_MSK; 848 break; 849 case RK805_ID: 850 case RK816_ID: 851 on_source = RK8XX_ON_SOURCE; 852 off_source = RK8XX_OFF_SOURCE; 853 pwron_key = RK8XX_DEVCTRL_REG; 854 lp_off_msk = RK8XX_LP_OFF_MSK; 855 lp_act_msk = RK8XX_LP_ACTION_MSK; 856 break; 857 case RK818_ID: 858 on_source = RK8XX_ON_SOURCE; 859 off_source = RK8XX_OFF_SOURCE; 860 pwron_key = RK8XX_DEVCTRL_REG; 861 lp_off_msk = RK8XX_LP_OFF_MSK; 862 lp_act_msk = RK8XX_LP_ACTION_MSK; 863 /* set current if no fuel gauge */ 864 if (!ofnode_valid(dev_read_subnode(dev, "battery"))) { 865 init_current = rk818_init_current; 866 init_current_num = ARRAY_SIZE(rk818_init_current); 867 } 868 break; 869 case RK809_ID: 870 case RK817_ID: 871 if (device_is_compatible(dev, "rockchip,rk809") && (priv->variant != RK809_ID)) { 872 dev_err(dev, "the dts is RK809, the hardware is RK817\n"); 873 run_command("download", 0); 874 } 875 876 if (device_is_compatible(dev, "rockchip,rk817") && (priv->variant != RK817_ID)) { 877 dev_err(dev, "the dts is RK817, the hardware is RK809\n"); 878 run_command("download", 0); 879 } 880 881 on_source = RK817_ON_SOURCE; 882 off_source = RK817_OFF_SOURCE; 883 pwron_key = RK817_PWRON_KEY; 884 lp_off_msk = RK8XX_LP_OFF_MSK; 885 lp_act_msk = RK8XX_LP_ACTION_MSK; 886 init_data = rk817_init_reg; 887 init_data_num = ARRAY_SIZE(rk817_init_reg); 888 889 /* whether the system voltage can be shutdown in PWR_off mode */ 890 if (priv->sys_can_sd) { 891 ret = rk8xx_read(dev, RK817_PMIC_CHRG_TERM, &value, 1); 892 if (ret) 893 return ret; 894 value |= 0x80; 895 ret = rk8xx_write(dev, RK817_PMIC_CHRG_TERM, &value, 1); 896 if (ret) 897 return ret; 898 } else { 899 ret = rk8xx_read(dev, RK817_PMIC_CHRG_TERM, &value, 1); 900 if (ret) 901 return ret; 902 value &= 0x7f; 903 ret = rk8xx_write(dev, RK817_PMIC_CHRG_TERM, &value, 1); 904 if (ret) 905 return ret; 906 } 907 908 if ((priv->rst_fun > RK8xx_RST_MODE0) && 909 (priv->rst_fun <= RK8xx_RST_MODE2)) { 910 rk8xx_read(dev, RK817_PMIC_SYS_CFG3, &value, 1); 911 value &= RK8xx_RESET_FUN_CLR; 912 value |= (priv->rst_fun << 6); 913 rk8xx_write(dev, RK817_PMIC_SYS_CFG3, &value, 1); 914 } 915 /* judge whether save the PMIC_POWER_EN register */ 916 if (!priv->not_save_power_en) { 917 ret = rk8xx_read(dev, RK817_POWER_EN0, &power_en0, 1); 918 if (ret) 919 return ret; 920 ret = rk8xx_read(dev, RK817_POWER_EN1, &power_en1, 1); 921 if (ret) 922 return ret; 923 ret = rk8xx_read(dev, RK817_POWER_EN2, &power_en2, 1); 924 if (ret) 925 return ret; 926 ret = rk8xx_read(dev, RK817_POWER_EN3, &power_en3, 1); 927 if (ret) 928 return ret; 929 930 value = (power_en0 & 0x0f) | ((power_en1 & 0x0f) << 4); 931 rk8xx_write(dev, RK817_POWER_EN_SAVE0, &value, 1); 932 value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4); 933 rk8xx_write(dev, RK817_POWER_EN_SAVE1, &value, 1); 934 } 935 break; 936 default: 937 printf("Unknown PMIC: RK%x!!\n", priv->variant); 938 return -EINVAL; 939 } 940 941 /* common init */ 942 for (i = 0; i < init_data_num; i++) { 943 ret = pmic_clrsetbits(dev, 944 init_data[i].reg, 945 init_data[i].mask, 946 init_data[i].val); 947 if (ret < 0) { 948 printf("%s: i2c set reg 0x%x failed, ret=%d\n", 949 __func__, init_data[i].reg, ret); 950 } 951 } 952 953 /* current init */ 954 for (i = 0; i < init_current_num; i++) { 955 ret = pmic_clrsetbits(dev, 956 init_current[i].reg, 957 init_current[i].mask, 958 init_current[i].val); 959 if (ret < 0) { 960 printf("%s: i2c set reg 0x%x failed, ret=%d\n", 961 __func__, init_current[i].reg, ret); 962 } 963 } 964 965 printf("PMIC: RK%x ", show_variant); 966 967 if (on_source && off_source) { 968 rk8xx_read(dev, on_source, &on, 1); 969 rk8xx_read(dev, off_source, &off, 1); 970 printf("(on=0x%02x, off=0x%02x)", on, off); 971 } 972 printf("\n"); 973 974 if (pwron_key) { 975 ret = rk8xx_read(dev, pwron_key, &value, 1); 976 if (ret) 977 return ret; 978 value &= ~(lp_off_msk | lp_act_msk); 979 if (lp_off_msk) 980 value |= priv->lp_off_time; 981 if (lp_act_msk) 982 value |= priv->lp_action; 983 rk8xx_write(dev, pwron_key, &value, 1); 984 } 985 986 ret = rk8xx_irq_chip_init(dev); 987 if (ret) { 988 printf("IRQ chip initial failed\n"); 989 return ret; 990 } 991 992 return 0; 993 } 994 995 static struct dm_pmic_ops rk8xx_ops = { 996 .reg_count = rk8xx_reg_count, 997 .read = rk8xx_read, 998 .write = rk8xx_write, 999 .suspend = rk8xx_suspend, 1000 .resume = rk8xx_resume, 1001 .shutdown = rk8xx_shutdown, 1002 }; 1003 1004 static const struct udevice_id rk8xx_ids[] = { 1005 { .compatible = "rockchip,rk805" }, 1006 { .compatible = "rockchip,rk806" }, 1007 { .compatible = "rockchip,rk808" }, 1008 { .compatible = "rockchip,rk809" }, 1009 { .compatible = "rockchip,rk816" }, 1010 { .compatible = "rockchip,rk817" }, 1011 { .compatible = "rockchip,rk818" }, 1012 { } 1013 }; 1014 1015 U_BOOT_DRIVER(pmic_rk8xx) = { 1016 .name = "rk8xx pmic", 1017 .id = UCLASS_PMIC, 1018 .of_match = rk8xx_ids, 1019 #if CONFIG_IS_ENABLED(PMIC_CHILDREN) 1020 .bind = rk8xx_bind, 1021 #endif 1022 .ofdata_to_platdata = rk8xx_ofdata_to_platdata, 1023 .priv_auto_alloc_size = sizeof(struct rk8xx_priv), 1024 .probe = rk8xx_probe, 1025 .ops = &rk8xx_ops, 1026 }; 1027