1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/of_access.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 #include <asm/arch/clock.h> 12 #include <fdtdec.h> 13 #include <linux/compat.h> 14 #include <linux/err.h> 15 #include <power/regulator.h> 16 17 #define MAX_SUPPLIES 16 18 19 /* 20 * The max voltage for 1.8V and 3.3V come from the Rockchip datasheet under 21 * "Recommended Operating Conditions" for "Digital GPIO". When the typical 22 * is 3.3V the max is 3.6V. When the typical is 1.8V the max is 1.98V. 23 * 24 * They are used like this: 25 * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the 26 * SoC we're at 3.3. 27 * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider 28 * that to be an error. 29 */ 30 #define MAX_VOLTAGE_1_8 1980000 31 #define MAX_VOLTAGE_3_3 3600000 32 33 #define PX30_IO_VSEL 0x180 34 #define PX30_IO_VSEL_VCCIO6_SRC BIT(0) 35 #define PX30_IO_VSEL_VCCIO6_SUPPLY_NUM 1 36 37 #define RK3288_SOC_CON2 0x24c 38 #define RK3288_SOC_CON2_FLASH0 BIT(7) 39 #define RK3288_SOC_FLASH_SUPPLY_NUM 2 40 41 #define RK3308_SOC_CON0 0x300 42 #define RK3308_SOC_CON0_VCCIO3 BIT(8) 43 #define RK3308_SOC_VCCIO3_SUPPLY_NUM 3 44 45 #define RK3328_SOC_CON4 0x410 46 #define RK3328_SOC_CON4_VCCIO2 BIT(7) 47 #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1 48 49 #define RK3366_SOC_CON6 0x418 50 #define RK3366_SOC_CON6_FLASH0 BIT(14) 51 #define RK3366_SOC_FLASH_SUPPLY_NUM 2 52 53 #define RK3368_SOC_CON15 0x43c 54 #define RK3368_SOC_CON15_FLASH0 BIT(14) 55 #define RK3368_SOC_FLASH_SUPPLY_NUM 2 56 57 #define RK3399_PMUGRF_CON0 0x180 58 #define RK3399_PMUGRF_CON0_VSEL BIT(8) 59 #define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9 60 61 #define RK3568_PMU_GRF_IO_VSEL0 (0x0140) 62 #define RK3568_PMU_GRF_IO_VSEL1 (0x0144) 63 #define RK3568_PMU_GRF_IO_VSEL2 (0x0148) 64 65 #define RV1126_PMU_GRF_IO_RETENTION (0x0144) 66 67 struct rockchip_iodomain_priv; 68 69 /** 70 * @supplies: voltage settings matching the register bits. 71 */ 72 struct rockchip_iodomain_soc_data { 73 int grf_offset; 74 const char *supply_names[MAX_SUPPLIES]; 75 void (*init)(struct rockchip_iodomain_priv *iod); 76 }; 77 78 struct rockchip_iodomain_supply { 79 struct rockchip_iodomain_priv *iod; 80 struct udevice *reg; 81 int idx; 82 }; 83 84 struct rockchip_iodomain_priv { 85 struct regmap *regmap_base; 86 struct rockchip_iodomain_soc_data *sdata; 87 struct rockchip_iodomain_supply supplies[MAX_SUPPLIES]; 88 int (*write)(struct rockchip_iodomain_supply *supply, int uV); 89 }; 90 91 static int rockchip_ofdata_to_platdata(struct udevice *dev) 92 { 93 struct rockchip_iodomain_priv *priv = dev_get_priv(dev); 94 struct syscon_uc_info *syscon_priv; 95 struct regmap *regmap; 96 97 syscon_priv = dev_get_uclass_priv(dev_get_parent(dev)); 98 regmap = syscon_priv->regmap; 99 if (IS_ERR(regmap)) 100 return PTR_ERR(regmap); 101 102 priv->regmap_base = regmap; 103 104 return 0; 105 } 106 107 static int rk3568_pmu_iodomain_write(struct rockchip_iodomain_supply *supply, 108 int uV) 109 { 110 struct rockchip_iodomain_priv *priv = supply->iod; 111 struct regmap *regmap = priv->regmap_base; 112 u32 is_3v3 = uV > MAX_VOLTAGE_1_8; 113 u32 val0, val1; 114 int b; 115 116 switch (supply->idx) { 117 case 0: /* pmuio1 */ 118 case 1: /* pmuio2 */ 119 b = supply->idx; 120 val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); 121 b = supply->idx + 4; 122 val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0); 123 124 regmap_write(regmap, RK3568_PMU_GRF_IO_VSEL2, val0); 125 regmap_write(regmap, RK3568_PMU_GRF_IO_VSEL2, val1); 126 break; 127 case 2: /* vccio1 */ 128 case 3: /* vccio2 */ 129 case 4: /* vccio3 */ 130 case 5: /* vccio4 */ 131 case 6: /* vccio5 */ 132 case 7: /* vccio6 */ 133 case 8: /* vccio7 */ 134 b = supply->idx - 1; 135 val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); 136 val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0); 137 138 regmap_write(regmap, RK3568_PMU_GRF_IO_VSEL0, val0); 139 regmap_write(regmap, RK3568_PMU_GRF_IO_VSEL1, val1); 140 break; 141 default: 142 return -EINVAL; 143 }; 144 145 return 0; 146 } 147 148 static int rv1126_iodomain_write(struct rockchip_iodomain_supply *supply, 149 int uV) 150 { 151 struct rockchip_iodomain_priv *priv = supply->iod; 152 struct regmap *regmap = priv->regmap_base; 153 u32 val, vret_hold, vret_release; 154 155 /* set value bit */ 156 val = (uV > MAX_VOLTAGE_1_8) ? 0 : 1; 157 val <<= supply->idx; 158 /* apply hiword-mask */ 159 val |= (BIT(supply->idx) << 16); 160 161 vret_hold = (BIT(supply->idx) << 16); 162 vret_release = (BIT(supply->idx) << 16) | BIT(supply->idx); 163 164 printf("%s: %d uv, vsel: 0x%x\n", 165 priv->sdata->supply_names[supply->idx], uV, val); 166 167 regmap_write(regmap, RV1126_PMU_GRF_IO_RETENTION, vret_hold); 168 regmap_write(regmap, priv->sdata->grf_offset, val); 169 regmap_write(regmap, RV1126_PMU_GRF_IO_RETENTION, vret_release); 170 171 return 0; 172 } 173 174 static int rockchip_iodomain_write(struct rockchip_iodomain_supply *supply, 175 int uV) 176 { 177 struct rockchip_iodomain_priv *priv = supply->iod; 178 struct regmap *regmap = priv->regmap_base; 179 u32 val; 180 int ret; 181 182 /* set value bit */ 183 val = (uV > MAX_VOLTAGE_1_8) ? 0 : 1; 184 val <<= supply->idx; 185 186 /* apply hiword-mask */ 187 val |= (BIT(supply->idx) << 16); 188 189 ret = regmap_write(regmap, priv->sdata->grf_offset, val); 190 if (ret) { 191 dev_err(priv->dev, "Couldn't write to GRF\n"); 192 return ret; 193 } 194 195 return 0; 196 } 197 198 static void px30_iodomain_init(struct rockchip_iodomain_priv *iod) 199 { 200 int ret; 201 u32 val; 202 203 /* if no VCCIO0 supply we should leave things alone */ 204 if (!iod->supplies[PX30_IO_VSEL_VCCIO6_SUPPLY_NUM].reg) 205 return; 206 207 /* 208 * set vccio0 iodomain to also use this framework 209 * instead of a special gpio. 210 */ 211 val = PX30_IO_VSEL_VCCIO6_SRC | (PX30_IO_VSEL_VCCIO6_SRC << 16); 212 ret = regmap_write(iod->regmap_base, PX30_IO_VSEL, val); 213 if (ret < 0) 214 dev_warn(iod->dev, "couldn't update vccio0 ctrl\n"); 215 } 216 217 static void rk3288_iodomain_init(struct rockchip_iodomain_priv *iod) 218 { 219 int ret; 220 u32 val; 221 222 /* if no flash supply we should leave things alone */ 223 if (!iod->supplies[RK3288_SOC_FLASH_SUPPLY_NUM].reg) 224 return; 225 226 /* 227 * set flash0 iodomain to also use this framework 228 * instead of a special gpio. 229 */ 230 val = RK3288_SOC_CON2_FLASH0 | (RK3288_SOC_CON2_FLASH0 << 16); 231 ret = regmap_write(iod->regmap_base, RK3288_SOC_CON2, val); 232 if (ret < 0) 233 dev_warn(iod->dev, "couldn't update flash0 ctrl\n"); 234 } 235 236 static void rk3308_iodomain_init(struct rockchip_iodomain_priv *iod) 237 { 238 int ret; 239 u32 val; 240 241 /* if no vccio3 supply we should leave things alone */ 242 if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg) 243 return; 244 245 /* 246 * set vccio3 iodomain to also use this framework 247 * instead of a special gpio. 248 */ 249 val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16); 250 ret = regmap_write(iod->regmap_base, RK3308_SOC_CON0, val); 251 if (ret < 0) 252 dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n"); 253 } 254 255 static void rk3328_iodomain_init(struct rockchip_iodomain_priv *iod) 256 { 257 int ret; 258 u32 val; 259 260 /* if no vccio2 supply we should leave things alone */ 261 if (!iod->supplies[RK3328_SOC_VCCIO2_SUPPLY_NUM].reg) 262 return; 263 264 /* 265 * set vccio2 iodomain to also use this framework 266 * instead of a special gpio. 267 */ 268 val = RK3328_SOC_CON4_VCCIO2 | (RK3328_SOC_CON4_VCCIO2 << 16); 269 ret = regmap_write(iod->regmap_base, RK3328_SOC_CON4, val); 270 if (ret < 0) 271 dev_warn(iod->dev, "couldn't update vccio2 vsel ctrl\n"); 272 } 273 274 static void rk3366_iodomain_init(struct rockchip_iodomain_priv *iod) 275 { 276 int ret; 277 u32 val; 278 279 /* if no flash supply we should leave things alone */ 280 if (!iod->supplies[RK3366_SOC_FLASH_SUPPLY_NUM].reg) 281 return; 282 283 /* 284 * set flash0 iodomain to also use this framework 285 * instead of a special gpio. 286 */ 287 val = RK3366_SOC_CON6_FLASH0 | (RK3366_SOC_CON6_FLASH0 << 16); 288 ret = regmap_write(iod->regmap_base, RK3368_SOC_CON15, val); 289 if (ret < 0) 290 dev_warn(iod->dev, "couldn't update flash0 ctrl\n"); 291 } 292 293 static void rk3368_iodomain_init(struct rockchip_iodomain_priv *iod) 294 { 295 int ret; 296 u32 val; 297 298 /* if no flash supply we should leave things alone */ 299 if (!iod->supplies[RK3368_SOC_FLASH_SUPPLY_NUM].reg) 300 return; 301 302 /* 303 * set flash0 iodomain to also use this framework 304 * instead of a special gpio. 305 */ 306 val = RK3368_SOC_CON15_FLASH0 | (RK3368_SOC_CON15_FLASH0 << 16); 307 ret = regmap_write(iod->regmap_base, RK3368_SOC_CON15, val); 308 if (ret < 0) 309 dev_warn(iod->dev, "couldn't update flash0 ctrl\n"); 310 } 311 312 static void rk3399_pmu_iodomain_init(struct rockchip_iodomain_priv *iod) 313 { 314 int ret; 315 u32 val; 316 317 /* if no pmu io supply we should leave things alone */ 318 if (!iod->supplies[RK3399_PMUGRF_VSEL_SUPPLY_NUM].reg) 319 return; 320 321 /* 322 * set pmu io iodomain to also use this framework 323 * instead of a special gpio. 324 */ 325 val = RK3399_PMUGRF_CON0_VSEL | (RK3399_PMUGRF_CON0_VSEL << 16); 326 ret = regmap_write(iod->regmap_base, RK3399_PMUGRF_CON0, val); 327 if (ret < 0) 328 dev_warn(iod->dev, "couldn't update pmu io iodomain ctrl\n"); 329 } 330 331 static const struct rockchip_iodomain_soc_data soc_data_px30 = { 332 .grf_offset = 0x180, 333 .supply_names = { 334 NULL, 335 "vccio6", 336 "vccio1", 337 "vccio2", 338 "vccio3", 339 "vccio4", 340 "vccio5", 341 "vccio-oscgpi", 342 }, 343 .init = px30_iodomain_init, 344 }; 345 346 static const struct rockchip_iodomain_soc_data soc_data_px30_pmu = { 347 .grf_offset = 0x100, 348 .supply_names = { 349 NULL, 350 NULL, 351 NULL, 352 NULL, 353 NULL, 354 NULL, 355 NULL, 356 NULL, 357 NULL, 358 NULL, 359 NULL, 360 NULL, 361 NULL, 362 NULL, 363 "pmuio1", 364 "pmuio2", 365 }, 366 }; 367 368 /* 369 * On the rk3188 the io-domains are handled by a shared register with the 370 * lower 8 bits being still being continuing drive-strength settings. 371 */ 372 static const struct rockchip_iodomain_soc_data soc_data_rk3188 = { 373 .grf_offset = 0x104, 374 .supply_names = { 375 NULL, 376 NULL, 377 NULL, 378 NULL, 379 NULL, 380 NULL, 381 NULL, 382 NULL, 383 "ap0", 384 "ap1", 385 "cif", 386 "flash", 387 "vccio0", 388 "vccio1", 389 "lcdc0", 390 "lcdc1", 391 }, 392 }; 393 394 static const struct rockchip_iodomain_soc_data soc_data_rk322x = { 395 .grf_offset = 0x418, 396 .supply_names = { 397 "vccio1", 398 "vccio2", 399 "vccio3", 400 "vccio4", 401 }, 402 }; 403 404 static const struct rockchip_iodomain_soc_data soc_data_rk3288 = { 405 .grf_offset = 0x380, 406 .supply_names = { 407 "lcdc", /* LCDC_VDD */ 408 "dvp", /* DVPIO_VDD */ 409 "flash0", /* FLASH0_VDD (emmc) */ 410 "flash1", /* FLASH1_VDD (sdio1) */ 411 "wifi", /* APIO3_VDD (sdio0) */ 412 "bb", /* APIO5_VDD */ 413 "audio", /* APIO4_VDD */ 414 "sdcard", /* SDMMC0_VDD (sdmmc) */ 415 "gpio30", /* APIO1_VDD */ 416 "gpio1830", /* APIO2_VDD */ 417 }, 418 .init = rk3288_iodomain_init, 419 }; 420 421 static const struct rockchip_iodomain_soc_data soc_data_rk3308 = { 422 .grf_offset = 0x300, 423 .supply_names = { 424 "vccio0", 425 "vccio1", 426 "vccio2", 427 "vccio3", 428 "vccio4", 429 "vccio5", 430 }, 431 .init = rk3308_iodomain_init, 432 }; 433 434 static const struct rockchip_iodomain_soc_data soc_data_rk3328 = { 435 .grf_offset = 0x410, 436 .supply_names = { 437 "vccio1", 438 "vccio2", 439 "vccio3", 440 "vccio4", 441 "vccio5", 442 "vccio6", 443 "pmuio", 444 }, 445 .init = rk3328_iodomain_init, 446 }; 447 448 static const struct rockchip_iodomain_soc_data soc_data_rk3366 = { 449 .grf_offset = 0x900, 450 .supply_names = { 451 "lcdc", /* LCDC_IOVDD */ 452 "dvpts", /* DVP_IOVDD */ 453 "flash", /* FLASH_IOVDD (emmc) */ 454 "wifibt", /* APIO1_IOVDD */ 455 NULL, 456 "audio", /* AUDIO_IODVDD */ 457 "sdcard", /* SDMMC_IOVDD (sdmmc) */ 458 "tphdsor", /* APIO2_IOVDD */ 459 }, 460 .init = rk3366_iodomain_init, 461 }; 462 463 static const struct rockchip_iodomain_soc_data soc_data_rk3368 = { 464 .grf_offset = 0x900, 465 .supply_names = { 466 NULL, /* reserved */ 467 "dvp", /* DVPIO_VDD */ 468 "flash0", /* FLASH0_VDD (emmc) */ 469 "wifi", /* APIO2_VDD (sdio0) */ 470 NULL, 471 "audio", /* APIO3_VDD */ 472 "sdcard", /* SDMMC0_VDD (sdmmc) */ 473 "gpio30", /* APIO1_VDD */ 474 "gpio1830", /* APIO4_VDD (gpujtag) */ 475 }, 476 .init = rk3368_iodomain_init, 477 }; 478 479 static const struct rockchip_iodomain_soc_data soc_data_rk3368_pmu = { 480 .grf_offset = 0x100, 481 .supply_names = { 482 NULL, 483 NULL, 484 NULL, 485 NULL, 486 "pmu", /*PMU IO domain*/ 487 "vop", /*LCDC IO domain*/ 488 }, 489 }; 490 491 static const struct rockchip_iodomain_soc_data soc_data_rk3399 = { 492 .grf_offset = 0xe640, 493 .supply_names = { 494 "bt656", /* APIO2_VDD */ 495 "audio", /* APIO5_VDD */ 496 "sdmmc", /* SDMMC0_VDD */ 497 "gpio1830", /* APIO4_VDD */ 498 }, 499 }; 500 501 static const struct rockchip_iodomain_soc_data soc_data_rk3399_pmu = { 502 .grf_offset = 0x180, 503 .supply_names = { 504 NULL, 505 NULL, 506 NULL, 507 NULL, 508 NULL, 509 NULL, 510 NULL, 511 NULL, 512 NULL, 513 "pmu1830", /* PMUIO2_VDD */ 514 }, 515 .init = rk3399_pmu_iodomain_init, 516 }; 517 518 static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = { 519 .grf_offset = 0x140, 520 .supply_names = { 521 "pmuio1", 522 "pmuio2", 523 "vccio1", 524 "vccio2", 525 "vccio3", 526 "vccio4", 527 "vccio5", 528 "vccio6", 529 "vccio7", 530 }, 531 }; 532 533 static const struct rockchip_iodomain_soc_data soc_data_rv1108 = { 534 .grf_offset = 0x404, 535 .supply_names = { 536 NULL, 537 NULL, 538 NULL, 539 NULL, 540 NULL, 541 NULL, 542 NULL, 543 NULL, 544 NULL, 545 NULL, 546 NULL, 547 "vccio1", 548 "vccio2", 549 "vccio3", 550 "vccio5", 551 "vccio6", 552 }, 553 554 }; 555 556 static const struct rockchip_iodomain_soc_data soc_data_rv1108_pmu = { 557 .grf_offset = 0x104, 558 .supply_names = { 559 "pmu", 560 }, 561 }; 562 563 static const struct rockchip_iodomain_soc_data soc_data_rv1126_pmu = { 564 .grf_offset = 0x140, 565 .supply_names = { 566 NULL, 567 "vccio1", 568 "vccio2", 569 "vccio3", 570 "vccio4", 571 "vccio5", 572 "vccio6", 573 "vccio7", 574 "pmuio0", 575 "pmuio1", 576 }, 577 }; 578 579 static struct udevice *of_get_regulator(ofnode node, const char *supply) 580 { 581 char sname[32]; /* 32 is max size of property name */ 582 struct udevice *sudev = NULL; 583 ofnode snode; 584 u32 phandle; 585 int ret; 586 587 snprintf(sname, 32, "%s-supply", supply); 588 589 /* Get regulator and clk */ 590 if (!ofnode_read_u32(node, sname, &phandle)) { 591 snode = ofnode_get_by_phandle(phandle); 592 ret = regulator_get_by_devname(snode.np->name, &sudev); 593 if (ret) { 594 printf("%s: Get (%s) regulator: %s failed, ret=%d\n", 595 __func__, 596 sname, snode.np->full_name, ret); 597 return NULL; 598 } 599 debug("IO-DOMAIN: supply: %s\n", snode.np->full_name); 600 } 601 602 return sudev; 603 } 604 605 static int rockchip_iodomain_probe(struct udevice *dev) 606 { 607 struct rockchip_iodomain_priv *priv = dev_get_priv(dev); 608 struct rockchip_iodomain_soc_data *sdata; 609 int i, ret; 610 611 sdata = (struct rockchip_iodomain_soc_data *)dev_get_driver_data(dev); 612 priv->sdata = sdata; 613 if (sdata == &soc_data_rk3568_pmu) 614 priv->write = rk3568_pmu_iodomain_write; 615 else if (sdata == &soc_data_rv1126_pmu) 616 priv->write = rv1126_iodomain_write; 617 else 618 priv->write = rockchip_iodomain_write; 619 620 if (!priv->regmap_base) 621 return -1; 622 623 for (i = 0; i < MAX_SUPPLIES; i++) { 624 const char *supply_name = priv->sdata->supply_names[i]; 625 struct rockchip_iodomain_supply *supply = &priv->supplies[i]; 626 struct udevice *reg; 627 u32 uV; 628 629 if (!supply_name) 630 continue; 631 632 reg = of_get_regulator(dev_ofnode(dev), supply_name); 633 if (!reg) 634 continue; 635 636 uV = regulator_get_value(reg); 637 if (uV <= 0) { 638 printf("voltage(%d uV) is invalid from %s\n", uV, reg->name); 639 continue; 640 } 641 642 if (uV > MAX_VOLTAGE_3_3) { 643 printf("%d uV is too high from %s\n", uV, reg->name); 644 continue; 645 } 646 647 /* setup our supply */ 648 supply->idx = i; 649 supply->iod = priv; 650 supply->reg = reg; 651 652 ret = priv->write(supply, uV); 653 if (ret) 654 supply->reg = NULL; 655 } 656 657 if (priv->sdata->init) 658 priv->sdata->init(priv); 659 660 return 0; 661 } 662 663 static const struct udevice_id rockchip_iodomain_match[] = { 664 { 665 .compatible = "rockchip,px30-io-voltage-domain", 666 .data = (ulong)&soc_data_px30 667 }, 668 { 669 .compatible = "rockchip,px30-pmu-io-voltage-domain", 670 .data = (ulong)&soc_data_px30_pmu 671 }, 672 { 673 .compatible = "rockchip,rk3188-io-voltage-domain", 674 .data = (ulong)&soc_data_rk3188 675 }, 676 { 677 .compatible = "rockchip,rk322x-io-voltage-domain", 678 .data = (ulong)&soc_data_rk322x 679 }, 680 { 681 .compatible = "rockchip,rk3288-io-voltage-domain", 682 .data = (ulong)&soc_data_rk3288 683 }, 684 { 685 .compatible = "rockchip,rk3308-io-voltage-domain", 686 .data = (ulong)&soc_data_rk3308 687 }, 688 { 689 .compatible = "rockchip,rk3328-io-voltage-domain", 690 .data = (ulong)&soc_data_rk3328 691 }, 692 { 693 .compatible = "rockchip,rk3366-io-voltage-domain", 694 .data = (ulong)&soc_data_rk3366 695 }, 696 { 697 .compatible = "rockchip,rk3368-io-voltage-domain", 698 .data = (ulong)&soc_data_rk3368 699 }, 700 { 701 .compatible = "rockchip,rk3368-pmu-io-voltage-domain", 702 .data = (ulong)&soc_data_rk3368_pmu 703 }, 704 { 705 .compatible = "rockchip,rk3399-io-voltage-domain", 706 .data = (ulong)&soc_data_rk3399 707 }, 708 { 709 .compatible = "rockchip,rk3399-pmu-io-voltage-domain", 710 .data = (ulong)&soc_data_rk3399_pmu 711 }, 712 { 713 .compatible = "rockchip,rk3568-pmu-io-voltage-domain", 714 .data = (ulong)&soc_data_rk3568_pmu 715 }, 716 { 717 .compatible = "rockchip,rv1108-io-voltage-domain", 718 .data = (ulong)&soc_data_rv1108 719 }, 720 { 721 .compatible = "rockchip,rv1108-pmu-io-voltage-domain", 722 .data = (ulong)&soc_data_rv1108_pmu 723 }, 724 { 725 .compatible = "rockchip,rv1126-pmu-io-voltage-domain", 726 .data = (ulong)&soc_data_rv1126_pmu 727 }, 728 { /* sentinel */ }, 729 }; 730 731 U_BOOT_DRIVER(io_domain) = { 732 .name = "io_domain", 733 .id = UCLASS_IO_DOMAIN, 734 .of_match = rockchip_iodomain_match, 735 .priv_auto_alloc_size = sizeof(struct rockchip_iodomain_priv), 736 .ofdata_to_platdata = rockchip_ofdata_to_platdata, 737 .probe = rockchip_iodomain_probe, 738 }; 739