1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 12 #include "pinctrl-rockchip.h" 13 14 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 15 { 16 .num = 0, 17 .pin = 20, 18 .reg = 0x10000, 19 .bit = 0, 20 .mask = 0xf 21 }, 22 { 23 .num = 0, 24 .pin = 21, 25 .reg = 0x10000, 26 .bit = 4, 27 .mask = 0xf 28 }, 29 { 30 .num = 0, 31 .pin = 22, 32 .reg = 0x10000, 33 .bit = 8, 34 .mask = 0xf 35 }, 36 { 37 .num = 0, 38 .pin = 23, 39 .reg = 0x10000, 40 .bit = 12, 41 .mask = 0xf 42 }, 43 }; 44 45 static struct rockchip_mux_route_data rv1126_mux_route_data[] = { 46 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ 47 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ 48 49 MR_TOPGRF(RK_GPIO0, RK_PD4, RK_FUNC_4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ 50 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ 51 MR_TOPGRF(RK_GPIO2, RK_PC7, RK_FUNC_6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ 52 53 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ 54 MR_TOPGRF(RK_GPIO2, RK_PB3, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ 55 56 MR_TOPGRF(RK_GPIO3, RK_PD4, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ 57 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ 58 59 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ 60 MR_TOPGRF(RK_GPIO2, RK_PD1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ 61 62 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ 63 MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ 64 MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ 65 66 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ 67 MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ 68 69 MR_TOPGRF(RK_GPIO2, RK_PA5, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ 70 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ 71 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ 72 73 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ 74 MR_TOPGRF(RK_GPIO1, RK_PC6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ 75 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ 76 77 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ 78 MR_TOPGRF(RK_GPIO2, RK_PB7, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ 79 80 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ 81 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ 82 83 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */ 84 MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */ 85 86 MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */ 87 MR_TOPGRF(RK_GPIO2, RK_PD6, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */ 88 89 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */ 90 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */ 91 92 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ 93 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ 94 95 MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ 96 MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ 97 98 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ 99 MR_TOPGRF(RK_GPIO1, RK_PA7, RK_FUNC_2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ 100 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ 101 102 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ 103 MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ 104 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ 105 106 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ 107 MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ 108 MR_TOPGRF(RK_GPIO2, RK_PA0, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ 109 110 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */ 111 MR_PMUGRF(RK_GPIO2, RK_PB3, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */ 112 113 MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */ 114 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */ 115 116 MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */ 117 MR_PMUGRF(RK_GPIO2, RK_PB1, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */ 118 119 MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ 120 MR_PMUGRF(RK_GPIO2, RK_PB0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ 121 122 MR_PMUGRF(RK_GPIO0, RK_PC2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */ 123 MR_PMUGRF(RK_GPIO2, RK_PA7, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */ 124 125 MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */ 126 MR_PMUGRF(RK_GPIO2, RK_PA6, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */ 127 128 MR_PMUGRF(RK_GPIO0, RK_PB2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */ 129 MR_PMUGRF(RK_GPIO2, RK_PD4, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */ 130 131 MR_PMUGRF(RK_GPIO0, RK_PB1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ 132 MR_PMUGRF(RK_GPIO3, RK_PA0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ 133 134 MR_PMUGRF(RK_GPIO0, RK_PB0, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ 135 MR_PMUGRF(RK_GPIO2, RK_PA1, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ 136 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ 137 138 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ 139 MR_PMUGRF(RK_GPIO1, RK_PD0, RK_FUNC_5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ 140 MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */ 141 }; 142 143 static int rv1126_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 144 { 145 struct rockchip_pinctrl_priv *priv = bank->priv; 146 int iomux_num = (pin / 8); 147 struct regmap *regmap; 148 int reg, ret, mask, mux_type; 149 u8 bit; 150 u32 data; 151 152 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 153 154 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 155 regmap = priv->regmap_pmu; 156 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 157 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 158 else 159 regmap = priv->regmap_base; 160 161 /* get basic quadrupel of mux registers and the correct reg inside */ 162 mux_type = bank->iomux[iomux_num].type; 163 reg = bank->iomux[iomux_num].offset; 164 if (mux_type & IOMUX_WIDTH_4BIT) { 165 if ((pin % 8) >= 4) 166 reg += 0x4; 167 bit = (pin % 4) * 4; 168 mask = 0xf; 169 } else { 170 bit = (pin % 8) * 2; 171 mask = 0x3; 172 } 173 174 if (bank->recalced_mask & BIT(pin)) 175 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 176 177 data = (mask << (bit + 16)); 178 data |= (mux & mask) << bit; 179 ret = regmap_write(regmap, reg, data); 180 181 return ret; 182 } 183 184 #define RV1126_PULL_PMU_OFFSET 0x40 185 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 186 #define RV1126_PULL_PINS_PER_REG 8 187 #define RV1126_PULL_BITS_PER_PIN 2 188 #define RV1126_PULL_BANK_STRIDE 16 189 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 190 191 static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 192 int pin_num, struct regmap **regmap, 193 int *reg, u8 *bit) 194 { 195 struct rockchip_pinctrl_priv *priv = bank->priv; 196 197 /* The first 24 pins of the first bank are located in PMU */ 198 if (bank->bank_num == 0) { 199 if (RV1126_GPIO_C4_D7(pin_num)) { 200 *regmap = priv->regmap_base; 201 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 202 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 203 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 204 *bit *= RV1126_PULL_BITS_PER_PIN; 205 return; 206 } 207 *regmap = priv->regmap_pmu; 208 *reg = RV1126_PULL_PMU_OFFSET; 209 } else { 210 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 211 *regmap = priv->regmap_base; 212 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; 213 } 214 215 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 216 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 217 *bit *= RV1126_PULL_BITS_PER_PIN; 218 } 219 220 static int rv1126_set_pull(struct rockchip_pin_bank *bank, 221 int pin_num, int pull) 222 { 223 struct regmap *regmap; 224 int reg, ret; 225 u8 bit, type; 226 u32 data; 227 228 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) 229 return -ENOTSUPP; 230 231 rv1126_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); 232 type = bank->pull_type[pin_num / 8]; 233 ret = rockchip_translate_pull_value(type, pull); 234 if (ret < 0) { 235 debug("unsupported pull setting %d\n", pull); 236 return ret; 237 } 238 239 /* enable the write to the equivalent lower bits */ 240 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); 241 242 data |= (ret << bit); 243 ret = regmap_write(regmap, reg, data); 244 245 return ret; 246 } 247 248 #define RV1126_DRV_PMU_OFFSET 0x20 249 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 250 #define RV1126_DRV_BITS_PER_PIN 4 251 #define RV1126_DRV_PINS_PER_REG 4 252 #define RV1126_DRV_BANK_STRIDE 32 253 254 static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 255 int pin_num, struct regmap **regmap, 256 int *reg, u8 *bit) 257 { 258 struct rockchip_pinctrl_priv *priv = bank->priv; 259 260 /* The first 24 pins of the first bank are located in PMU */ 261 if (bank->bank_num == 0) { 262 if (RV1126_GPIO_C4_D7(pin_num)) { 263 *regmap = priv->regmap_base; 264 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 265 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 266 *reg -= 0x4; 267 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 268 *bit *= RV1126_DRV_BITS_PER_PIN; 269 return; 270 } 271 *regmap = priv->regmap_pmu; 272 *reg = RV1126_DRV_PMU_OFFSET; 273 } else { 274 *regmap = priv->regmap_base; 275 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 276 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; 277 } 278 279 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 280 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 281 *bit *= RV1126_DRV_BITS_PER_PIN; 282 } 283 284 static int rv1126_set_drive(struct rockchip_pin_bank *bank, 285 int pin_num, int strength) 286 { 287 struct regmap *regmap; 288 int reg; 289 u32 data; 290 u8 bit; 291 292 rv1126_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 293 294 /* enable the write to the equivalent lower bits */ 295 data = ((1 << RV1126_DRV_BITS_PER_PIN) - 1) << (bit + 16); 296 data |= (strength << bit); 297 298 return regmap_write(regmap, reg, data); 299 } 300 301 #define RV1126_SCHMITT_PMU_OFFSET 0x60 302 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 303 #define RV1126_SCHMITT_BANK_STRIDE 16 304 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8 305 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8 306 307 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 308 int pin_num, 309 struct regmap **regmap, 310 int *reg, u8 *bit) 311 { 312 struct rockchip_pinctrl_priv *priv = bank->priv; 313 int pins_per_reg; 314 315 if (bank->bank_num == 0) { 316 if (RV1126_GPIO_C4_D7(pin_num)) { 317 *regmap = priv->regmap_base; 318 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 319 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 320 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 321 return 0; 322 } 323 *regmap = priv->regmap_pmu; 324 *reg = RV1126_SCHMITT_PMU_OFFSET; 325 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 326 } else { 327 *regmap = priv->regmap_base; 328 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 329 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 330 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; 331 } 332 *reg += ((pin_num / pins_per_reg) * 4); 333 *bit = pin_num % pins_per_reg; 334 335 return 0; 336 } 337 338 static int rv1126_set_schmitt(struct rockchip_pin_bank *bank, 339 int pin_num, int enable) 340 { 341 struct regmap *regmap; 342 int reg; 343 u8 bit; 344 u32 data; 345 346 rv1126_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); 347 /* enable the write to the equivalent lower bits */ 348 data = BIT(bit + 16) | (enable << bit); 349 350 return regmap_write(regmap, reg, data); 351 } 352 353 static struct rockchip_pin_bank rv1126_pin_banks[] = { 354 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 355 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 356 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 357 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 358 IOMUX_WIDTH_4BIT), 359 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 360 IOMUX_WIDTH_4BIT, 361 IOMUX_WIDTH_4BIT, 362 IOMUX_WIDTH_4BIT, 363 IOMUX_WIDTH_4BIT, 364 0x10010, 0x10018, 0x10020, 0x10028), 365 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 366 IOMUX_WIDTH_4BIT, 367 IOMUX_WIDTH_4BIT, 368 IOMUX_WIDTH_4BIT, 369 IOMUX_WIDTH_4BIT), 370 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 371 IOMUX_WIDTH_4BIT, 372 IOMUX_WIDTH_4BIT, 373 IOMUX_WIDTH_4BIT, 374 IOMUX_WIDTH_4BIT), 375 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 376 IOMUX_WIDTH_4BIT, 0, 0, 0), 377 }; 378 379 static const struct rockchip_pin_ctrl rv1126_pin_ctrl = { 380 .pin_banks = rv1126_pin_banks, 381 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 382 .nr_pins = 130, 383 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 384 .pmu_mux_offset = 0x0, 385 .iomux_routes = rv1126_mux_route_data, 386 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), 387 .iomux_recalced = rv1126_mux_recalced_data, 388 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 389 .set_mux = rv1126_set_mux, 390 .set_pull = rv1126_set_pull, 391 .set_drive = rv1126_set_drive, 392 .set_schmitt = rv1126_set_schmitt, 393 }; 394 395 static const struct udevice_id rv1126_pinctrl_ids[] = { 396 { 397 .compatible = "rockchip,rv1126-pinctrl", 398 .data = (ulong)&rv1126_pin_ctrl 399 }, 400 { } 401 }; 402 403 U_BOOT_DRIVER(pinctrl_rv1126) = { 404 .name = "rockchip_rv1126_pinctrl", 405 .id = UCLASS_PINCTRL, 406 .of_match = rv1126_pinctrl_ids, 407 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 408 .ops = &rockchip_pinctrl_ops, 409 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 410 .bind = dm_scan_fdt_dev, 411 #endif 412 .probe = rockchip_pinctrl_probe, 413 }; 414