1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2024 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 12 #include "pinctrl-rockchip.h" 13 14 static int rk3576_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 15 { 16 struct rockchip_pinctrl_priv *priv = bank->priv; 17 int iomux_num = (pin / 8); 18 struct regmap *regmap; 19 int reg, ret, mask; 20 u8 bit; 21 u32 data; 22 23 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 24 25 regmap = priv->regmap_base; 26 reg = bank->iomux[iomux_num].offset; 27 if ((pin % 8) >= 4) 28 reg += 0x4; 29 bit = (pin % 4) * 4; 30 mask = 0xf; 31 32 data = (mask << (bit + 16)); 33 data |= (mux & mask) << bit; 34 35 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) 36 reg += 0x1FF4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */ 37 38 debug("iomux write reg = %x data = %x\n", reg, data); 39 40 ret = regmap_write(regmap, reg, data); 41 42 return ret; 43 } 44 45 #define RK3576_DRV_BITS_PER_PIN 4 46 #define RK3576_DRV_PINS_PER_REG 4 47 #define RK3576_DRV_GPIO0_AL_OFFSET 0x10 48 #define RK3576_DRV_GPIO0_BH_OFFSET 0x2014 49 #define RK3576_DRV_GPIO1_OFFSET 0x6020 50 #define RK3576_DRV_GPIO2_OFFSET 0x6040 51 #define RK3576_DRV_GPIO3_OFFSET 0x6060 52 #define RK3576_DRV_GPIO4_AL_OFFSET 0x6080 53 #define RK3576_DRV_GPIO4_CL_OFFSET 0xA090 54 #define RK3576_DRV_GPIO4_DL_OFFSET 0xB098 55 56 static void rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 57 int pin_num, struct regmap **regmap, 58 int *reg, u8 *bit) 59 { 60 struct rockchip_pinctrl_priv *priv = bank->priv; 61 62 *regmap = priv->regmap_base; 63 if (bank->bank_num == 0 && pin_num < 12) 64 *reg = RK3576_DRV_GPIO0_AL_OFFSET; 65 else if (bank->bank_num == 0) 66 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc; 67 else if (bank->bank_num == 1) 68 *reg = RK3576_DRV_GPIO1_OFFSET; 69 else if (bank->bank_num == 2) 70 *reg = RK3576_DRV_GPIO2_OFFSET; 71 else if (bank->bank_num == 3) 72 *reg = RK3576_DRV_GPIO3_OFFSET; 73 else if (bank->bank_num == 4 && pin_num < 16) 74 *reg = RK3576_DRV_GPIO4_AL_OFFSET; 75 else if (bank->bank_num == 4 && pin_num < 24) 76 *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10; 77 else if (bank->bank_num == 4) 78 *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18; 79 else { 80 *reg = 0; 81 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 82 } 83 84 *reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4); 85 *bit = pin_num % RK3576_DRV_PINS_PER_REG; 86 *bit *= RK3576_DRV_BITS_PER_PIN; 87 } 88 89 static int rk3576_set_drive(struct rockchip_pin_bank *bank, 90 int pin_num, int strength) 91 { 92 struct regmap *regmap; 93 int reg, ret; 94 u32 data; 95 u8 bit; 96 int drv = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1)); 97 98 rk3576_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 99 100 /* enable the write to the equivalent lower bits */ 101 data = ((1 << RK3576_DRV_BITS_PER_PIN) - 1) << (bit + 16); 102 data |= (drv << bit); 103 ret = regmap_write(regmap, reg, data); 104 105 return ret; 106 } 107 108 #define RK3576_PULL_BITS_PER_PIN 2 109 #define RK3576_PULL_PINS_PER_REG 8 110 #define RK3576_PULL_GPIO0_AL_OFFSET 0x20 111 #define RK3576_PULL_GPIO0_BH_OFFSET 0x2028 112 #define RK3576_PULL_GPIO1_OFFSET 0x6110 113 #define RK3576_PULL_GPIO2_OFFSET 0x6120 114 #define RK3576_PULL_GPIO3_OFFSET 0x6130 115 #define RK3576_PULL_GPIO4_AL_OFFSET 0x6140 116 #define RK3576_PULL_GPIO4_CL_OFFSET 0xA148 117 #define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C 118 119 static void rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 120 int pin_num, struct regmap **regmap, 121 int *reg, u8 *bit) 122 { 123 struct rockchip_pinctrl_priv *priv = bank->priv; 124 125 *regmap = priv->regmap_base; 126 if (bank->bank_num == 0 && pin_num < 12) 127 *reg = RK3576_PULL_GPIO0_AL_OFFSET; 128 else if (bank->bank_num == 0) 129 *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4; 130 else if (bank->bank_num == 1) 131 *reg = RK3576_PULL_GPIO1_OFFSET; 132 else if (bank->bank_num == 2) 133 *reg = RK3576_PULL_GPIO2_OFFSET; 134 else if (bank->bank_num == 3) 135 *reg = RK3576_PULL_GPIO3_OFFSET; 136 else if (bank->bank_num == 4 && pin_num < 16) 137 *reg = RK3576_PULL_GPIO4_AL_OFFSET; 138 else if (bank->bank_num == 4 && pin_num < 24) 139 *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8; 140 else if (bank->bank_num == 4) 141 *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc; 142 else { 143 *reg = 0; 144 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 145 } 146 147 *reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4); 148 *bit = pin_num % RK3576_PULL_PINS_PER_REG; 149 *bit *= RK3576_PULL_BITS_PER_PIN; 150 } 151 152 static int rk3576_set_pull(struct rockchip_pin_bank *bank, 153 int pin_num, int pull) 154 { 155 struct regmap *regmap; 156 int reg, ret; 157 u8 bit, type; 158 u32 data; 159 160 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) 161 return -ENOTSUPP; 162 163 rk3576_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); 164 type = bank->pull_type[pin_num / 8]; 165 ret = rockchip_translate_pull_value(type, pull); 166 if (ret < 0) { 167 debug("unsupported pull setting %d\n", pull); 168 return ret; 169 } 170 171 /* enable the write to the equivalent lower bits */ 172 data = ((1 << RK3576_PULL_BITS_PER_PIN) - 1) << (bit + 16); 173 174 data |= (ret << bit); 175 ret = regmap_write(regmap, reg, data); 176 177 return ret; 178 } 179 180 #define RK3576_SMT_BITS_PER_PIN 1 181 #define RK3576_SMT_PINS_PER_REG 8 182 #define RK3576_SMT_GPIO0_AL_OFFSET 0x30 183 #define RK3576_SMT_GPIO0_BH_OFFSET 0x2040 184 #define RK3576_SMT_GPIO1_OFFSET 0x6210 185 #define RK3576_SMT_GPIO2_OFFSET 0x6220 186 #define RK3576_SMT_GPIO3_OFFSET 0x6230 187 #define RK3576_SMT_GPIO4_AL_OFFSET 0x6240 188 #define RK3576_SMT_GPIO4_CL_OFFSET 0xA248 189 #define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C 190 191 static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 192 int pin_num, 193 struct regmap **regmap, 194 int *reg, u8 *bit) 195 { 196 struct rockchip_pinctrl_priv *priv = bank->priv; 197 198 *regmap = priv->regmap_base; 199 if (bank->bank_num == 0 && pin_num < 12) 200 *reg = RK3576_SMT_GPIO0_AL_OFFSET; 201 else if (bank->bank_num == 0) 202 *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4; 203 else if (bank->bank_num == 1) 204 *reg = RK3576_SMT_GPIO1_OFFSET; 205 else if (bank->bank_num == 2) 206 *reg = RK3576_SMT_GPIO2_OFFSET; 207 else if (bank->bank_num == 3) 208 *reg = RK3576_SMT_GPIO3_OFFSET; 209 else if (bank->bank_num == 4 && pin_num < 16) 210 *reg = RK3576_SMT_GPIO4_AL_OFFSET; 211 else if (bank->bank_num == 4 && pin_num < 24) 212 *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8; 213 else if (bank->bank_num == 4) 214 *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc; 215 else { 216 *reg = 0; 217 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 218 } 219 220 *reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4); 221 *bit = pin_num % RK3576_SMT_PINS_PER_REG; 222 *bit *= RK3576_SMT_BITS_PER_PIN; 223 224 return 0; 225 } 226 227 static int rk3576_set_schmitt(struct rockchip_pin_bank *bank, 228 int pin_num, int enable) 229 { 230 struct regmap *regmap; 231 int reg, ret; 232 u32 data; 233 u8 bit; 234 235 rk3576_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); 236 237 /* enable the write to the equivalent lower bits */ 238 data = ((1 << RK3576_SMT_BITS_PER_PIN) - 1) << (bit + 16); 239 data |= (enable << bit); 240 ret = regmap_write(regmap, reg, data); 241 242 return ret; 243 } 244 245 #define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \ 246 PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \ 247 IOMUX_WIDTH_4BIT, \ 248 IOMUX_WIDTH_4BIT, \ 249 IOMUX_WIDTH_4BIT, \ 250 IOMUX_WIDTH_4BIT, \ 251 OFFSET0, OFFSET1, \ 252 OFFSET2, OFFSET3, \ 253 PULL_TYPE_IO_1, PULL_TYPE_IO_1, \ 254 PULL_TYPE_IO_1, PULL_TYPE_IO_1) 255 256 static struct rockchip_pin_bank rk3576_pin_banks[] = { 257 RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C), 258 RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038), 259 RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058), 260 RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078), 261 RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398), 262 }; 263 264 static const struct rockchip_pin_ctrl rk3576_pin_ctrl = { 265 .pin_banks = rk3576_pin_banks, 266 .nr_banks = ARRAY_SIZE(rk3576_pin_banks), 267 .nr_pins = 160, 268 .grf_mux_offset = 0x0, 269 .set_mux = rk3576_set_mux, 270 .set_pull = rk3576_set_pull, 271 .set_drive = rk3576_set_drive, 272 .set_schmitt = rk3576_set_schmitt, 273 }; 274 275 static const struct udevice_id rk3576_pinctrl_ids[] = { 276 { 277 .compatible = "rockchip,rk3576-pinctrl", 278 .data = (ulong)&rk3576_pin_ctrl 279 }, 280 { } 281 }; 282 283 U_BOOT_DRIVER(pinctrl_rk3576) = { 284 .name = "rockchip_rk3576_pinctrl", 285 .id = UCLASS_PINCTRL, 286 .of_match = rk3576_pinctrl_ids, 287 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 288 .ops = &rockchip_pinctrl_ops, 289 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 290 .bind = dm_scan_fdt_dev, 291 #endif 292 .probe = rockchip_pinctrl_probe, 293 }; 294