1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 12 #include "pinctrl-rockchip.h" 13 14 static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 15 MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ 16 MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ 17 MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ 18 MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */ 19 MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */ 20 MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */ 21 MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */ 22 MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */ 23 MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */ 24 MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */ 25 MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */ 26 MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */ 27 MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */ 28 MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */ 29 MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */ 30 MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */ 31 MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */ 32 MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ 33 MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ 34 MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ 35 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */ 36 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */ 37 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */ 38 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */ 39 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */ 40 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */ 41 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */ 42 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */ 43 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ 44 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ 45 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ 46 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ 47 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ 48 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ 49 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ 50 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ 51 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ 52 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ 53 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ 54 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ 55 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ 56 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ 57 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ 58 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ 59 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ 60 MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ 61 MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ 62 MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */ 63 MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */ 64 MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */ 65 MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */ 66 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */ 67 MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ 68 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ 69 MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ 70 MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ 71 MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ 72 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ 73 MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ 74 MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */ 75 MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */ 76 MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */ 77 MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */ 78 MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */ 79 MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */ 80 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ 81 MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ 82 MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ 83 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ 84 MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ 85 MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ 86 MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ 87 MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */ 88 MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */ 89 MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */ 90 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */ 91 MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */ 92 MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */ 93 MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ 94 MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ 95 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ 96 MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */ 97 MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */ 98 MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ 99 MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ 100 MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ 101 MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */ 102 MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */ 103 MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */ 104 MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */ 105 MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */ 106 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */ 107 }; 108 109 static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 110 { 111 struct rockchip_pinctrl_priv *priv = bank->priv; 112 int iomux_num = (pin / 8); 113 struct regmap *regmap; 114 int reg, ret, mask; 115 u8 bit; 116 u32 data; 117 118 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 119 120 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 121 regmap = priv->regmap_pmu; 122 else 123 regmap = priv->regmap_base; 124 125 reg = bank->iomux[iomux_num].offset; 126 if ((pin % 8) >= 4) 127 reg += 0x4; 128 bit = (pin % 4) * 4; 129 mask = 0xf; 130 131 data = (mask << (bit + 16)); 132 data |= (mux & mask) << bit; 133 ret = regmap_write(regmap, reg, data); 134 135 return ret; 136 } 137 138 #define RK3568_PULL_PMU_OFFSET 0x20 139 #define RK3568_PULL_GRF_OFFSET 0x80 140 #define RK3568_PULL_BITS_PER_PIN 2 141 #define RK3568_PULL_PINS_PER_REG 8 142 #define RK3568_PULL_BANK_STRIDE 0x10 143 144 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 145 int pin_num, struct regmap **regmap, 146 int *reg, u8 *bit) 147 { 148 struct rockchip_pinctrl_priv *info = bank->priv; 149 150 if (bank->bank_num == 0) { 151 *regmap = info->regmap_pmu; 152 *reg = RK3568_PULL_PMU_OFFSET; 153 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 154 } else { 155 *regmap = info->regmap_base; 156 *reg = RK3568_PULL_GRF_OFFSET; 157 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 158 } 159 160 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 161 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 162 *bit *= RK3568_PULL_BITS_PER_PIN; 163 } 164 165 #define RK3568_DRV_PMU_OFFSET 0x70 166 #define RK3568_DRV_GRF_OFFSET 0x200 167 #define RK3568_DRV_BITS_PER_PIN 8 168 #define RK3568_DRV_PINS_PER_REG 2 169 #define RK3568_DRV_BANK_STRIDE 0x40 170 171 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 172 int pin_num, struct regmap **regmap, 173 int *reg, u8 *bit) 174 { 175 struct rockchip_pinctrl_priv *info = bank->priv; 176 177 /* The first 32 pins of the first bank are located in PMU */ 178 if (bank->bank_num == 0) { 179 *regmap = info->regmap_pmu; 180 *reg = RK3568_DRV_PMU_OFFSET; 181 } else { 182 *regmap = info->regmap_base; 183 *reg = RK3568_DRV_GRF_OFFSET; 184 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 185 } 186 187 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 188 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 189 *bit *= RK3568_DRV_BITS_PER_PIN; 190 } 191 192 #define RK3568_SCHMITT_BITS_PER_PIN 2 193 #define RK3568_SCHMITT_PINS_PER_REG 8 194 #define RK3568_SCHMITT_BANK_STRIDE 0x10 195 #define RK3568_SCHMITT_GRF_OFFSET 0xc0 196 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 197 198 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 199 int pin_num, struct regmap **regmap, 200 int *reg, u8 *bit) 201 { 202 struct rockchip_pinctrl_priv *info = bank->priv; 203 204 if (bank->bank_num == 0) { 205 *regmap = info->regmap_pmu; 206 *reg = RK3568_SCHMITT_PMUGRF_OFFSET; 207 } else { 208 *regmap = info->regmap_base; 209 *reg = RK3568_SCHMITT_GRF_OFFSET; 210 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; 211 } 212 213 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); 214 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; 215 *bit *= RK3568_SCHMITT_BITS_PER_PIN; 216 217 return 0; 218 } 219 220 static int rk3568_set_pull(struct rockchip_pin_bank *bank, 221 int pin_num, int pull) 222 { 223 struct regmap *regmap; 224 int reg, ret; 225 u8 bit, type; 226 u32 data; 227 228 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) 229 return -ENOTSUPP; 230 231 rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); 232 type = bank->pull_type[pin_num / 8]; 233 ret = rockchip_translate_pull_value(type, pull); 234 if (ret < 0) { 235 debug("unsupported pull setting %d\n", pull); 236 return ret; 237 } 238 239 /* enable the write to the equivalent lower bits */ 240 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); 241 242 data |= (ret << bit); 243 ret = regmap_write(regmap, reg, data); 244 245 return ret; 246 } 247 248 static int rk3568_set_drive(struct rockchip_pin_bank *bank, 249 int pin_num, int strength) 250 { 251 struct regmap *regmap; 252 int reg; 253 u32 data; 254 u8 bit; 255 int drv = (1 << (strength + 1)) - 1; 256 int ret = 0; 257 258 rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 259 260 /* enable the write to the equivalent lower bits */ 261 data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16); 262 data |= (drv << bit); 263 264 ret = regmap_write(regmap, reg, data); 265 if (ret) 266 return ret; 267 268 if (bank->bank_num == 1 && pin_num == 21) 269 reg = 0x0840; 270 else if (bank->bank_num == 2 && pin_num == 2) 271 reg = 0x0844; 272 else if (bank->bank_num == 2 && pin_num == 8) 273 reg = 0x0848; 274 else if (bank->bank_num == 3 && pin_num == 0) 275 reg = 0x084c; 276 else if (bank->bank_num == 3 && pin_num == 6) 277 reg = 0x0850; 278 else if (bank->bank_num == 4 && pin_num == 0) 279 reg = 0x0854; 280 else 281 return 0; 282 283 data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16; 284 data |= drv; 285 286 return regmap_write(regmap, reg, data); 287 } 288 289 static int rk3568_set_schmitt(struct rockchip_pin_bank *bank, 290 int pin_num, int enable) 291 { 292 struct regmap *regmap; 293 int reg; 294 u32 data; 295 u8 bit; 296 297 rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); 298 299 /* enable the write to the equivalent lower bits */ 300 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); 301 data |= (enable << bit); 302 303 return regmap_write(regmap, reg, data); 304 } 305 static struct rockchip_pin_bank rk3568_pin_banks[] = { 306 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 307 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 308 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 309 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 310 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 311 IOMUX_WIDTH_4BIT, 312 IOMUX_WIDTH_4BIT, 313 IOMUX_WIDTH_4BIT), 314 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 315 IOMUX_WIDTH_4BIT, 316 IOMUX_WIDTH_4BIT, 317 IOMUX_WIDTH_4BIT), 318 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 319 IOMUX_WIDTH_4BIT, 320 IOMUX_WIDTH_4BIT, 321 IOMUX_WIDTH_4BIT), 322 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 323 IOMUX_WIDTH_4BIT, 324 IOMUX_WIDTH_4BIT, 325 IOMUX_WIDTH_4BIT), 326 }; 327 328 static const struct rockchip_pin_ctrl rk3568_pin_ctrl = { 329 .pin_banks = rk3568_pin_banks, 330 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 331 .nr_pins = 160, 332 .grf_mux_offset = 0x0, 333 .pmu_mux_offset = 0x0, 334 .iomux_routes = rk3568_mux_route_data, 335 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 336 .set_mux = rk3568_set_mux, 337 .set_pull = rk3568_set_pull, 338 .set_drive = rk3568_set_drive, 339 .set_schmitt = rk3568_set_schmitt, 340 }; 341 342 static const struct udevice_id rk3568_pinctrl_ids[] = { 343 { 344 .compatible = "rockchip,rk3568-pinctrl", 345 .data = (ulong)&rk3568_pin_ctrl 346 }, 347 { } 348 }; 349 350 U_BOOT_DRIVER(pinctrl_rk3568) = { 351 .name = "rockchip_rk3568_pinctrl", 352 .id = UCLASS_PINCTRL, 353 .of_match = rk3568_pinctrl_ids, 354 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 355 .ops = &rockchip_pinctrl_ops, 356 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 357 .bind = dm_scan_fdt_dev, 358 #endif 359 .probe = rockchip_pinctrl_probe, 360 }; 361