1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 12 #include "pinctrl-rockchip.h" 13 14 static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 15 MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ 16 MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ 17 MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ 18 MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */ 19 MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */ 20 MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */ 21 MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */ 22 MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */ 23 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */ 24 MR_TOPGRF(RK_GPIO4, RK_PC1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */ 25 MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */ 26 MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */ 27 MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */ 28 MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */ 29 MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */ 30 MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */ 31 MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */ 32 MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ 33 MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ 34 MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ 35 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */ 36 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */ 37 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */ 38 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */ 39 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */ 40 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */ 41 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */ 42 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */ 43 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ 44 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ 45 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ 46 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ 47 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ 48 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ 49 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ 50 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ 51 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ 52 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ 53 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ 54 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ 55 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ 56 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ 57 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ 58 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ 59 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ 60 MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ 61 MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ 62 MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */ 63 MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */ 64 MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */ 65 MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */ 66 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */ 67 MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ 68 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ 69 MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ 70 MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ 71 MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ 72 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ 73 MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ 74 MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */ 75 MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */ 76 MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */ 77 MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */ 78 MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */ 79 MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */ 80 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ 81 MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ 82 MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ 83 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ 84 MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ 85 MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ 86 MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ 87 MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */ 88 MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */ 89 MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */ 90 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */ 91 MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */ 92 MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */ 93 MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ 94 MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ 95 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ 96 MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */ 97 MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */ 98 MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ 99 MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ 100 MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ 101 MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */ 102 MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */ 103 MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */ 104 MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */ 105 MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */ 106 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */ 107 }; 108 109 110 static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 111 { 112 struct rockchip_pinctrl_priv *priv = bank->priv; 113 int iomux_num = (pin / 8); 114 struct regmap *regmap; 115 int reg, ret, mask; 116 u8 bit; 117 u32 data; 118 119 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 120 121 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 122 regmap = priv->regmap_pmu; 123 else 124 regmap = priv->regmap_base; 125 126 reg = bank->iomux[iomux_num].offset; 127 if ((pin % 8) >= 4) 128 reg += 0x4; 129 bit = (pin % 4) * 4; 130 mask = 0xf; 131 132 data = (mask << (bit + 16)); 133 data |= (mux & mask) << bit; 134 ret = regmap_write(regmap, reg, data); 135 136 return ret; 137 } 138 139 #define RK3568_PULL_GRF_OFFSET 0x20 140 #define RK3568_PULL_PMU_OFFSET 0x80 141 #define RK3568_PULL_BITS_PER_PIN 2 142 #define RK3568_PULL_PINS_PER_REG 8 143 #define RK3568_PULL_BANK_STRIDE 0x10 144 145 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 146 int pin_num, struct regmap **regmap, 147 int *reg, u8 *bit) 148 { 149 struct rockchip_pinctrl_priv *info = bank->priv; 150 151 if (bank->bank_num == 0) { 152 *regmap = info->regmap_pmu; 153 *reg = RK3568_PULL_PMU_OFFSET; 154 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 155 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 156 157 *bit = pin_num % RK3568_PULL_PINS_PER_REG; 158 *bit *= RK3568_PULL_BITS_PER_PIN; 159 } else { 160 *regmap = info->regmap_base; 161 *reg = RK3568_PULL_GRF_OFFSET; 162 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 163 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 164 165 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 166 *bit *= RK3568_PULL_BITS_PER_PIN; 167 } 168 } 169 170 #define RK3568_DRV_PMU_OFFSET 0x70 171 #define RK3568_DRV_GRF_OFFSET 0x200 172 #define RK3568_DRV_BITS_PER_PIN 8 173 #define RK3568_DRV_PINS_PER_REG 2 174 #define RK3568_DRV_BANK_STRIDE 0x40 175 176 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 177 int pin_num, struct regmap **regmap, 178 int *reg, u8 *bit) 179 { 180 struct rockchip_pinctrl_priv *info = bank->priv; 181 182 /* The first 32 pins of the first bank are located in PMU */ 183 if (bank->bank_num == 0) { 184 *regmap = info->regmap_pmu; 185 *reg = RK3568_DRV_PMU_OFFSET; 186 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 187 188 *bit = pin_num % RK3568_DRV_PINS_PER_REG; 189 *bit *= RK3568_DRV_BITS_PER_PIN; 190 } else { 191 *regmap = info->regmap_base; 192 *reg = RK3568_DRV_GRF_OFFSET; 193 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 194 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 195 196 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 197 *bit *= RK3568_DRV_BITS_PER_PIN; 198 } 199 } 200 201 static int rk3568_set_pull(struct rockchip_pin_bank *bank, 202 int pin_num, int pull) 203 { 204 struct regmap *regmap; 205 int reg, ret; 206 u8 bit, type; 207 u32 data; 208 209 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) 210 return -ENOTSUPP; 211 212 rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); 213 type = bank->pull_type[pin_num / 8]; 214 ret = rockchip_translate_pull_value(type, pull); 215 if (ret < 0) { 216 debug("unsupported pull setting %d\n", pull); 217 return ret; 218 } 219 220 /* enable the write to the equivalent lower bits */ 221 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); 222 223 data |= (ret << bit); 224 ret = regmap_write(regmap, reg, data); 225 226 return ret; 227 } 228 229 static int rk3568_set_drive(struct rockchip_pin_bank *bank, 230 int pin_num, int strength) 231 { 232 struct regmap *regmap; 233 int reg; 234 u32 data; 235 u8 bit; 236 237 rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 238 239 /* enable the write to the equivalent lower bits */ 240 data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16); 241 data |= (strength << bit); 242 243 return regmap_write(regmap, reg, data); 244 } 245 246 static struct rockchip_pin_bank rk3568_pin_banks[] = { 247 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 248 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 249 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 250 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 251 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 252 IOMUX_WIDTH_4BIT, 253 IOMUX_WIDTH_4BIT, 254 IOMUX_WIDTH_4BIT), 255 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 256 IOMUX_WIDTH_4BIT, 257 IOMUX_WIDTH_4BIT, 258 IOMUX_WIDTH_4BIT), 259 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 260 IOMUX_WIDTH_4BIT, 261 IOMUX_WIDTH_4BIT, 262 IOMUX_WIDTH_4BIT), 263 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 264 IOMUX_WIDTH_4BIT, 265 IOMUX_WIDTH_4BIT, 266 IOMUX_WIDTH_4BIT), 267 }; 268 269 static const struct rockchip_pin_ctrl rk3568_pin_ctrl = { 270 .pin_banks = rk3568_pin_banks, 271 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 272 .nr_pins = 160, 273 .grf_mux_offset = 0x0, 274 .pmu_mux_offset = 0x0, 275 .iomux_routes = rk3568_mux_route_data, 276 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 277 .set_mux = rk3568_set_mux, 278 .set_pull = rk3568_set_pull, 279 .set_drive = rk3568_set_drive, 280 }; 281 282 static const struct udevice_id rk3568_pinctrl_ids[] = { 283 { 284 .compatible = "rockchip,rk3568-pinctrl", 285 .data = (ulong)&rk3568_pin_ctrl 286 }, 287 { } 288 }; 289 290 U_BOOT_DRIVER(pinctrl_rk3568) = { 291 .name = "rockchip_rk3568_pinctrl", 292 .id = UCLASS_PINCTRL, 293 .of_match = rk3568_pinctrl_ids, 294 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 295 .ops = &rockchip_pinctrl_ops, 296 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 297 .bind = dm_scan_fdt_dev, 298 #endif 299 .probe = rockchip_pinctrl_probe, 300 }; 301