1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 11 #include "pinctrl-rockchip.h" 12 13 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 14 { 15 /* edphdmi_cecinoutt1 */ 16 .bank_num = 7, 17 .pin = 16, 18 .func = 2, 19 .route_offset = 0x264, 20 .route_val = BIT(16 + 12) | BIT(12), 21 }, { 22 /* edphdmi_cecinout */ 23 .bank_num = 7, 24 .pin = 23, 25 .func = 4, 26 .route_offset = 0x264, 27 .route_val = BIT(16 + 12), 28 }, 29 }; 30 31 static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 32 { 33 struct rockchip_pinctrl_priv *priv = bank->priv; 34 int iomux_num = (pin / 8); 35 struct regmap *regmap; 36 int reg, ret, mask, mux_type; 37 u8 bit; 38 u32 data; 39 40 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 41 ? priv->regmap_pmu : priv->regmap_base; 42 43 /* get basic quadrupel of mux registers and the correct reg inside */ 44 mux_type = bank->iomux[iomux_num].type; 45 reg = bank->iomux[iomux_num].offset; 46 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); 47 48 /* bank0 is special, there are no higher 16 bit writing bits. */ 49 if (bank->bank_num == 0) { 50 regmap_read(regmap, reg, &data); 51 data &= ~(mask << bit); 52 } else { 53 /* enable the write to the equivalent lower bits */ 54 data = (mask << (bit + 16)); 55 } 56 57 data |= (mux & mask) << bit; 58 ret = regmap_write(regmap, reg, data); 59 60 return ret; 61 } 62 63 #define RK3288_PULL_OFFSET 0x140 64 #define RK3288_PULL_PMU_OFFSET 0x64 65 66 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 67 int pin_num, struct regmap **regmap, 68 int *reg, u8 *bit) 69 { 70 struct rockchip_pinctrl_priv *priv = bank->priv; 71 72 /* The first 24 pins of the first bank are located in PMU */ 73 if (bank->bank_num == 0) { 74 *regmap = priv->regmap_pmu; 75 *reg = RK3288_PULL_PMU_OFFSET; 76 } else { 77 *regmap = priv->regmap_base; 78 *reg = RK3288_PULL_OFFSET; 79 80 /* correct the offset, as we're starting with the 2nd bank */ 81 *reg -= 0x10; 82 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; 83 } 84 85 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); 86 87 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); 88 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; 89 } 90 91 static int rk3288_set_pull(struct rockchip_pin_bank *bank, 92 int pin_num, int pull) 93 { 94 struct regmap *regmap; 95 int reg, ret; 96 u8 bit, type; 97 u32 data; 98 99 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) 100 return -ENOTSUPP; 101 102 rk3288_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); 103 type = bank->pull_type[pin_num / 8]; 104 ret = rockchip_translate_pull_value(type, pull); 105 if (ret < 0) { 106 debug("unsupported pull setting %d\n", pull); 107 return ret; 108 } 109 110 /* bank0 is special, there are no higher 16 bit writing bits */ 111 if (bank->bank_num == 0) { 112 regmap_read(regmap, reg, &data); 113 data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit); 114 } else { 115 /* enable the write to the equivalent lower bits */ 116 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); 117 } 118 119 data |= (ret << bit); 120 ret = regmap_write(regmap, reg, data); 121 122 return ret; 123 } 124 125 #define RK3288_DRV_PMU_OFFSET 0x70 126 #define RK3288_DRV_GRF_OFFSET 0x1c0 127 128 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 129 int pin_num, struct regmap **regmap, 130 int *reg, u8 *bit) 131 { 132 struct rockchip_pinctrl_priv *priv = bank->priv; 133 134 /* The first 24 pins of the first bank are located in PMU */ 135 if (bank->bank_num == 0) { 136 *regmap = priv->regmap_pmu; 137 *reg = RK3288_DRV_PMU_OFFSET; 138 } else { 139 *regmap = priv->regmap_base; 140 *reg = RK3288_DRV_GRF_OFFSET; 141 142 /* correct the offset, as we're starting with the 2nd bank */ 143 *reg -= 0x10; 144 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; 145 } 146 147 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); 148 *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); 149 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; 150 } 151 152 static int rk3288_set_drive(struct rockchip_pin_bank *bank, 153 int pin_num, int strength) 154 { 155 struct regmap *regmap; 156 int reg, ret; 157 u32 data; 158 u8 bit; 159 int type = bank->drv[pin_num / 8].drv_type; 160 161 rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 162 ret = rockchip_translate_drive_value(type, strength); 163 if (ret < 0) { 164 debug("unsupported driver strength %d\n", strength); 165 return ret; 166 } 167 168 /* bank0 is special, there are no higher 16 bit writing bits. */ 169 if (bank->bank_num == 0) { 170 regmap_read(regmap, reg, &data); 171 data &= ~(((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << bit); 172 } else { 173 /* enable the write to the equivalent lower bits */ 174 data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); 175 } 176 177 data |= (ret << bit); 178 ret = regmap_write(regmap, reg, data); 179 return ret; 180 } 181 182 static struct rockchip_pin_bank rk3288_pin_banks[] = { 183 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 184 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 185 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 186 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 187 IOMUX_UNROUTED, 188 DRV_TYPE_WRITABLE_32BIT, 189 DRV_TYPE_WRITABLE_32BIT, 190 DRV_TYPE_WRITABLE_32BIT, 191 0, 192 PULL_TYPE_WRITABLE_32BIT, 193 PULL_TYPE_WRITABLE_32BIT, 194 PULL_TYPE_WRITABLE_32BIT, 195 0 196 ), 197 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 198 IOMUX_UNROUTED, 199 IOMUX_UNROUTED, 200 0 201 ), 202 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 203 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 204 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 205 IOMUX_WIDTH_4BIT, 206 0, 207 0 208 ), 209 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 210 0, 211 0, 212 IOMUX_UNROUTED 213 ), 214 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 215 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 216 0, 217 IOMUX_WIDTH_4BIT, 218 IOMUX_UNROUTED 219 ), 220 PIN_BANK(8, 16, "gpio8"), 221 }; 222 223 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 224 .pin_banks = rk3288_pin_banks, 225 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 226 .nr_pins = 264, 227 .grf_mux_offset = 0x0, 228 .pmu_mux_offset = 0x84, 229 .iomux_routes = rk3288_mux_route_data, 230 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 231 .set_mux = rk3288_set_mux, 232 .set_pull = rk3288_set_pull, 233 .set_drive = rk3288_set_drive, 234 }; 235 236 static const struct udevice_id rk3288_pinctrl_ids[] = { 237 { 238 .compatible = "rockchip,rk3288-pinctrl", 239 .data = (ulong)&rk3288_pin_ctrl 240 }, 241 { } 242 }; 243 244 U_BOOT_DRIVER(pinctrl_rk3288) = { 245 .name = "rockchip_rk3288_pinctrl", 246 .id = UCLASS_PINCTRL, 247 .of_match = rk3288_pinctrl_ids, 248 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 249 .ops = &rockchip_pinctrl_ops, 250 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 251 .bind = dm_scan_fdt_dev, 252 #endif 253 .probe = rockchip_pinctrl_probe, 254 }; 255