1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 11 #include "pinctrl-rockchip.h" 12 13 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 14 { 15 /* edphdmi_cecinoutt1 */ 16 .bank_num = 7, 17 .pin = 16, 18 .func = 2, 19 .route_offset = 0x264, 20 .route_val = BIT(16 + 12) | BIT(12), 21 }, { 22 /* edphdmi_cecinout */ 23 .bank_num = 7, 24 .pin = 23, 25 .func = 4, 26 .route_offset = 0x264, 27 .route_val = BIT(16 + 12), 28 }, 29 }; 30 31 static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 32 { 33 struct rockchip_pinctrl_priv *priv = bank->priv; 34 int iomux_num = (pin / 8); 35 struct regmap *regmap; 36 int reg, ret, mask, mux_type; 37 u8 bit; 38 u32 data, route_reg, route_val; 39 40 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 41 ? priv->regmap_pmu : priv->regmap_base; 42 43 /* get basic quadrupel of mux registers and the correct reg inside */ 44 mux_type = bank->iomux[iomux_num].type; 45 reg = bank->iomux[iomux_num].offset; 46 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); 47 48 if (bank->route_mask & BIT(pin)) { 49 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 50 &route_val)) { 51 ret = regmap_write(regmap, route_reg, route_val); 52 if (ret) 53 return ret; 54 } 55 } 56 57 /* bank0 is special, there are no higher 16 bit writing bits. */ 58 if (bank->bank_num == 0) { 59 regmap_read(regmap, reg, &data); 60 data &= ~(mask << bit); 61 } else { 62 /* enable the write to the equivalent lower bits */ 63 data = (mask << (bit + 16)); 64 } 65 66 data |= (mux & mask) << bit; 67 ret = regmap_write(regmap, reg, data); 68 69 return ret; 70 } 71 72 #define RK3288_PULL_OFFSET 0x140 73 #define RK3288_PULL_PMU_OFFSET 0x64 74 75 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 76 int pin_num, struct regmap **regmap, 77 int *reg, u8 *bit) 78 { 79 struct rockchip_pinctrl_priv *priv = bank->priv; 80 81 /* The first 24 pins of the first bank are located in PMU */ 82 if (bank->bank_num == 0) { 83 *regmap = priv->regmap_pmu; 84 *reg = RK3288_PULL_PMU_OFFSET; 85 86 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); 87 *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; 88 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; 89 } else { 90 *regmap = priv->regmap_base; 91 *reg = RK3288_PULL_OFFSET; 92 93 /* correct the offset, as we're starting with the 2nd bank */ 94 *reg -= 0x10; 95 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; 96 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); 97 98 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); 99 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; 100 } 101 } 102 103 #define RK3288_DRV_PMU_OFFSET 0x70 104 #define RK3288_DRV_GRF_OFFSET 0x1c0 105 106 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 107 int pin_num, struct regmap **regmap, 108 int *reg, u8 *bit) 109 { 110 struct rockchip_pinctrl_priv *priv = bank->priv; 111 112 /* The first 24 pins of the first bank are located in PMU */ 113 if (bank->bank_num == 0) { 114 *regmap = priv->regmap_pmu; 115 *reg = RK3288_DRV_PMU_OFFSET; 116 117 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); 118 *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; 119 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; 120 } else { 121 *regmap = priv->regmap_base; 122 *reg = RK3288_DRV_GRF_OFFSET; 123 124 /* correct the offset, as we're starting with the 2nd bank */ 125 *reg -= 0x10; 126 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; 127 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); 128 129 *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); 130 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; 131 } 132 } 133 134 static struct rockchip_pin_bank rk3288_pin_banks[] = { 135 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 136 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 137 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 138 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 139 IOMUX_UNROUTED, 140 DRV_TYPE_WRITABLE_32BIT, 141 DRV_TYPE_WRITABLE_32BIT, 142 DRV_TYPE_WRITABLE_32BIT, 143 0, 144 PULL_TYPE_WRITABLE_32BIT, 145 PULL_TYPE_WRITABLE_32BIT, 146 PULL_TYPE_WRITABLE_32BIT, 147 0 148 ), 149 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 150 IOMUX_UNROUTED, 151 IOMUX_UNROUTED, 152 0 153 ), 154 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 155 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 156 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 157 IOMUX_WIDTH_4BIT, 158 0, 159 0 160 ), 161 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 162 0, 163 0, 164 IOMUX_UNROUTED 165 ), 166 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 167 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 168 0, 169 IOMUX_WIDTH_4BIT, 170 IOMUX_UNROUTED 171 ), 172 PIN_BANK(8, 16, "gpio8"), 173 }; 174 175 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 176 .pin_banks = rk3288_pin_banks, 177 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 178 .label = "RK3288-GPIO", 179 .type = RK3288, 180 .grf_mux_offset = 0x0, 181 .pmu_mux_offset = 0x84, 182 .iomux_routes = rk3288_mux_route_data, 183 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 184 .set_mux = rk3288_set_mux, 185 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 186 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 187 }; 188 189 static const struct udevice_id rk3288_pinctrl_ids[] = { 190 { 191 .compatible = "rockchip,rk3288-pinctrl", 192 .data = (ulong)&rk3288_pin_ctrl 193 }, 194 { } 195 }; 196 197 U_BOOT_DRIVER(pinctrl_rk3288) = { 198 .name = "rockchip_rk3288_pinctrl", 199 .id = UCLASS_PINCTRL, 200 .of_match = rk3288_pinctrl_ids, 201 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 202 .ops = &rockchip_pinctrl_ops, 203 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 204 .bind = dm_scan_fdt_dev, 205 #endif 206 .probe = rockchip_pinctrl_probe, 207 }; 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