1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 #include <asm/arch/cpu.h> 14 15 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 16 #define RK_FUNC_GPIO 0 17 #define MAX_ROCKCHIP_PINS_ENTRIES 30 18 19 enum rockchip_pinctrl_type { 20 PX30, 21 RV1108, 22 RK1808, 23 RK2928, 24 RK3066B, 25 RK3128, 26 RK3188, 27 RK3288, 28 RK3308, 29 RK3368, 30 RK3399, 31 }; 32 33 /** 34 * Encode variants of iomux registers into a type variable 35 */ 36 #define IOMUX_GPIO_ONLY BIT(0) 37 #define IOMUX_WIDTH_4BIT BIT(1) 38 #define IOMUX_SOURCE_PMU BIT(2) 39 #define IOMUX_UNROUTED BIT(3) 40 #define IOMUX_WIDTH_3BIT BIT(4) 41 #define IOMUX_8WIDTH_2BIT BIT(5) 42 #define IOMUX_WRITABLE_32BIT BIT(6) 43 44 /** 45 * @type: iomux variant using IOMUX_* constants 46 * @offset: if initialized to -1 it will be autocalculated, by specifying 47 * an initial offset value the relevant source offset can be reset 48 * to a new value for autocalculating the following iomux registers. 49 */ 50 struct rockchip_iomux { 51 int type; 52 int offset; 53 }; 54 55 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 56 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 57 58 /** 59 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 60 */ 61 enum rockchip_pin_drv_type { 62 DRV_TYPE_IO_DEFAULT = 0, 63 DRV_TYPE_IO_1V8_OR_3V0, 64 DRV_TYPE_IO_1V8_ONLY, 65 DRV_TYPE_IO_1V8_3V0_AUTO, 66 DRV_TYPE_IO_3V3_ONLY, 67 DRV_TYPE_MAX 68 }; 69 70 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 71 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 72 73 /** 74 * enum type index corresponding to rockchip_pull_list arrays index. 75 */ 76 enum rockchip_pin_pull_type { 77 PULL_TYPE_IO_DEFAULT = 0, 78 PULL_TYPE_IO_1V8_ONLY, 79 PULL_TYPE_MAX 80 }; 81 82 /** 83 * @drv_type: drive strength variant using rockchip_perpin_drv_type 84 * @offset: if initialized to -1 it will be autocalculated, by specifying 85 * an initial offset value the relevant source offset can be reset 86 * to a new value for autocalculating the following drive strength 87 * registers. if used chips own cal_drv func instead to calculate 88 * registers offset, the variant could be ignored. 89 */ 90 struct rockchip_drv { 91 enum rockchip_pin_drv_type drv_type; 92 int offset; 93 }; 94 95 /** 96 * @priv: common pinctrl private basedata 97 * @pin_base: first pin number 98 * @nr_pins: number of pins in this bank 99 * @name: name of the bank 100 * @bank_num: number of the bank, to account for holes 101 * @iomux: array describing the 4 iomux sources of the bank 102 * @drv: array describing the 4 drive strength sources of the bank 103 * @pull_type: array describing the 4 pull type sources of the bank 104 * @recalced_mask: bits describing the mux recalced pins of per bank 105 * @route_mask: bits describing the routing pins of per bank 106 */ 107 struct rockchip_pin_bank { 108 struct rockchip_pinctrl_priv *priv; 109 u32 pin_base; 110 u8 nr_pins; 111 char *name; 112 u8 bank_num; 113 struct rockchip_iomux iomux[4]; 114 struct rockchip_drv drv[4]; 115 enum rockchip_pin_pull_type pull_type[4]; 116 u32 recalced_mask; 117 u32 route_mask; 118 }; 119 120 #define PIN_BANK(id, pins, label) \ 121 { \ 122 .bank_num = id, \ 123 .nr_pins = pins, \ 124 .name = label, \ 125 .iomux = { \ 126 { .offset = -1 }, \ 127 { .offset = -1 }, \ 128 { .offset = -1 }, \ 129 { .offset = -1 }, \ 130 }, \ 131 } 132 133 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 134 { \ 135 .bank_num = id, \ 136 .nr_pins = pins, \ 137 .name = label, \ 138 .iomux = { \ 139 { .type = iom0, .offset = -1 }, \ 140 { .type = iom1, .offset = -1 }, \ 141 { .type = iom2, .offset = -1 }, \ 142 { .type = iom3, .offset = -1 }, \ 143 }, \ 144 } 145 146 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 147 { \ 148 .bank_num = id, \ 149 .nr_pins = pins, \ 150 .name = label, \ 151 .iomux = { \ 152 { .offset = -1 }, \ 153 { .offset = -1 }, \ 154 { .offset = -1 }, \ 155 { .offset = -1 }, \ 156 }, \ 157 .drv = { \ 158 { .drv_type = type0, .offset = -1 }, \ 159 { .drv_type = type1, .offset = -1 }, \ 160 { .drv_type = type2, .offset = -1 }, \ 161 { .drv_type = type3, .offset = -1 }, \ 162 }, \ 163 } 164 165 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 166 drv2, drv3, pull0, pull1, \ 167 pull2, pull3) \ 168 { \ 169 .bank_num = id, \ 170 .nr_pins = pins, \ 171 .name = label, \ 172 .iomux = { \ 173 { .offset = -1 }, \ 174 { .offset = -1 }, \ 175 { .offset = -1 }, \ 176 { .offset = -1 }, \ 177 }, \ 178 .drv = { \ 179 { .drv_type = drv0, .offset = -1 }, \ 180 { .drv_type = drv1, .offset = -1 }, \ 181 { .drv_type = drv2, .offset = -1 }, \ 182 { .drv_type = drv3, .offset = -1 }, \ 183 }, \ 184 .pull_type[0] = pull0, \ 185 .pull_type[1] = pull1, \ 186 .pull_type[2] = pull2, \ 187 .pull_type[3] = pull3, \ 188 } 189 190 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 191 iom2, iom3, drv0, drv1, drv2, \ 192 drv3, offset0, offset1, \ 193 offset2, offset3) \ 194 { \ 195 .bank_num = id, \ 196 .nr_pins = pins, \ 197 .name = label, \ 198 .iomux = { \ 199 { .type = iom0, .offset = -1 }, \ 200 { .type = iom1, .offset = -1 }, \ 201 { .type = iom2, .offset = -1 }, \ 202 { .type = iom3, .offset = -1 }, \ 203 }, \ 204 .drv = { \ 205 { .drv_type = drv0, .offset = offset0 }, \ 206 { .drv_type = drv1, .offset = offset1 }, \ 207 { .drv_type = drv2, .offset = offset2 }, \ 208 { .drv_type = drv3, .offset = offset3 }, \ 209 }, \ 210 } 211 212 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 213 iom2, iom3, drv0, drv1, drv2, \ 214 drv3, pull0, pull1, pull2, \ 215 pull3) \ 216 { \ 217 .bank_num = id, \ 218 .nr_pins = pins, \ 219 .name = label, \ 220 .iomux = { \ 221 { .type = iom0, .offset = -1 }, \ 222 { .type = iom1, .offset = -1 }, \ 223 { .type = iom2, .offset = -1 }, \ 224 { .type = iom3, .offset = -1 }, \ 225 }, \ 226 .drv = { \ 227 { .drv_type = drv0, .offset = -1 }, \ 228 { .drv_type = drv1, .offset = -1 }, \ 229 { .drv_type = drv2, .offset = -1 }, \ 230 { .drv_type = drv3, .offset = -1 }, \ 231 }, \ 232 .pull_type[0] = pull0, \ 233 .pull_type[1] = pull1, \ 234 .pull_type[2] = pull2, \ 235 .pull_type[3] = pull3, \ 236 } 237 238 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 239 label, iom0, iom1, iom2, \ 240 iom3, drv0, drv1, drv2, \ 241 drv3, offset0, offset1, \ 242 offset2, offset3, pull0, \ 243 pull1, pull2, pull3) \ 244 { \ 245 .bank_num = id, \ 246 .nr_pins = pins, \ 247 .name = label, \ 248 .iomux = { \ 249 { .type = iom0, .offset = -1 }, \ 250 { .type = iom1, .offset = -1 }, \ 251 { .type = iom2, .offset = -1 }, \ 252 { .type = iom3, .offset = -1 }, \ 253 }, \ 254 .drv = { \ 255 { .drv_type = drv0, .offset = offset0 }, \ 256 { .drv_type = drv1, .offset = offset1 }, \ 257 { .drv_type = drv2, .offset = offset2 }, \ 258 { .drv_type = drv3, .offset = offset3 }, \ 259 }, \ 260 .pull_type[0] = pull0, \ 261 .pull_type[1] = pull1, \ 262 .pull_type[2] = pull2, \ 263 .pull_type[3] = pull3, \ 264 } 265 266 /** 267 * struct rockchip_mux_recalced_data: represent a pin iomux data. 268 * @num: bank number. 269 * @pin: pin number. 270 * @bit: index at register. 271 * @reg: register offset. 272 * @mask: mask bit 273 */ 274 struct rockchip_mux_recalced_data { 275 u8 num; 276 u8 pin; 277 u32 reg; 278 u8 bit; 279 u8 mask; 280 }; 281 282 /** 283 * struct rockchip_mux_recalced_data: represent a pin iomux data. 284 * @bank_num: bank number. 285 * @pin: index at register or used to calc index. 286 * @func: the min pin. 287 * @route_offset: the max pin. 288 * @route_val: the register offset. 289 */ 290 struct rockchip_mux_route_data { 291 u8 bank_num; 292 u8 pin; 293 u8 func; 294 u32 route_offset; 295 u32 route_val; 296 }; 297 298 /** 299 */ 300 struct rockchip_pin_ctrl { 301 struct rockchip_pin_bank *pin_banks; 302 u32 nr_banks; 303 u32 nr_pins; 304 char *label; 305 enum rockchip_pinctrl_type type; 306 int grf_mux_offset; 307 int pmu_mux_offset; 308 int grf_drv_offset; 309 int pmu_drv_offset; 310 struct rockchip_mux_recalced_data *iomux_recalced; 311 u32 niomux_recalced; 312 struct rockchip_mux_route_data *iomux_routes; 313 u32 niomux_routes; 314 315 int (*ctrl_data_re_init)(struct rockchip_pin_ctrl *ctrl); 316 317 int (*soc_data_init)(struct rockchip_pinctrl_priv *info); 318 319 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 320 int pin_num, struct regmap **regmap, 321 int *reg, u8 *bit); 322 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 323 int pin_num, struct regmap **regmap, 324 int *reg, u8 *bit); 325 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 326 int pin_num, struct regmap **regmap, 327 int *reg, u8 *bit); 328 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank, 329 int pin_num, struct regmap **regmap, 330 int *reg, u8 *bit); 331 }; 332 333 /** 334 */ 335 struct rockchip_pinctrl_priv { 336 struct rockchip_pin_ctrl *ctrl; 337 struct regmap *regmap_base; 338 struct regmap *regmap_pmu; 339 340 }; 341 342 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 343 { 344 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 345 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 346 347 if (bank >= ctrl->nr_banks) { 348 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 349 return -EINVAL; 350 } 351 352 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 353 debug("pin conf pin %d >= %d\n", pin, 354 MAX_ROCKCHIP_GPIO_PER_BANK); 355 return -EINVAL; 356 } 357 358 return 0; 359 } 360 361 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 362 { 363 .num = 1, 364 .pin = 0, 365 .reg = 0x418, 366 .bit = 0, 367 .mask = 0x3 368 }, { 369 .num = 1, 370 .pin = 1, 371 .reg = 0x418, 372 .bit = 2, 373 .mask = 0x3 374 }, { 375 .num = 1, 376 .pin = 2, 377 .reg = 0x418, 378 .bit = 4, 379 .mask = 0x3 380 }, { 381 .num = 1, 382 .pin = 3, 383 .reg = 0x418, 384 .bit = 6, 385 .mask = 0x3 386 }, { 387 .num = 1, 388 .pin = 4, 389 .reg = 0x418, 390 .bit = 8, 391 .mask = 0x3 392 }, { 393 .num = 1, 394 .pin = 5, 395 .reg = 0x418, 396 .bit = 10, 397 .mask = 0x3 398 }, { 399 .num = 1, 400 .pin = 6, 401 .reg = 0x418, 402 .bit = 12, 403 .mask = 0x3 404 }, { 405 .num = 1, 406 .pin = 7, 407 .reg = 0x418, 408 .bit = 14, 409 .mask = 0x3 410 }, { 411 .num = 1, 412 .pin = 8, 413 .reg = 0x41c, 414 .bit = 0, 415 .mask = 0x3 416 }, { 417 .num = 1, 418 .pin = 9, 419 .reg = 0x41c, 420 .bit = 2, 421 .mask = 0x3 422 }, 423 }; 424 425 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 426 { 427 .num = 2, 428 .pin = 20, 429 .reg = 0xe8, 430 .bit = 0, 431 .mask = 0x7 432 }, { 433 .num = 2, 434 .pin = 21, 435 .reg = 0xe8, 436 .bit = 4, 437 .mask = 0x7 438 }, { 439 .num = 2, 440 .pin = 22, 441 .reg = 0xe8, 442 .bit = 8, 443 .mask = 0x7 444 }, { 445 .num = 2, 446 .pin = 23, 447 .reg = 0xe8, 448 .bit = 12, 449 .mask = 0x7 450 }, { 451 .num = 2, 452 .pin = 24, 453 .reg = 0xd4, 454 .bit = 12, 455 .mask = 0x7 456 }, 457 }; 458 459 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 460 { 461 .num = 1, 462 .pin = 14, 463 .reg = 0x28, 464 .bit = 12, 465 .mask = 0x7 466 }, { 467 .num = 1, 468 .pin = 15, 469 .reg = 0x2c, 470 .bit = 0, 471 .mask = 0x3 472 }, { 473 .num = 1, 474 .pin = 18, 475 .reg = 0x30, 476 .bit = 4, 477 .mask = 0x7 478 }, { 479 .num = 1, 480 .pin = 19, 481 .reg = 0x30, 482 .bit = 8, 483 .mask = 0x7 484 }, { 485 .num = 1, 486 .pin = 20, 487 .reg = 0x30, 488 .bit = 12, 489 .mask = 0x7 490 }, { 491 .num = 1, 492 .pin = 21, 493 .reg = 0x34, 494 .bit = 0, 495 .mask = 0x7 496 }, { 497 .num = 1, 498 .pin = 22, 499 .reg = 0x34, 500 .bit = 4, 501 .mask = 0x7 502 }, { 503 .num = 1, 504 .pin = 23, 505 .reg = 0x34, 506 .bit = 8, 507 .mask = 0x7 508 }, { 509 .num = 3, 510 .pin = 12, 511 .reg = 0x68, 512 .bit = 8, 513 .mask = 0x7 514 }, { 515 .num = 3, 516 .pin = 13, 517 .reg = 0x68, 518 .bit = 12, 519 .mask = 0x7 520 }, 521 }; 522 523 static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { 524 { 525 .num = 1, 526 .pin = 14, 527 .reg = 0x28, 528 .bit = 12, 529 .mask = 0xf 530 }, { 531 .num = 1, 532 .pin = 15, 533 .reg = 0x2c, 534 .bit = 0, 535 .mask = 0x3 536 }, { 537 .num = 1, 538 .pin = 18, 539 .reg = 0x30, 540 .bit = 4, 541 .mask = 0xf 542 }, { 543 .num = 1, 544 .pin = 19, 545 .reg = 0x30, 546 .bit = 8, 547 .mask = 0xf 548 }, { 549 .num = 1, 550 .pin = 20, 551 .reg = 0x30, 552 .bit = 12, 553 .mask = 0xf 554 }, { 555 .num = 1, 556 .pin = 21, 557 .reg = 0x34, 558 .bit = 0, 559 .mask = 0xf 560 }, { 561 .num = 1, 562 .pin = 22, 563 .reg = 0x34, 564 .bit = 4, 565 .mask = 0xf 566 }, { 567 .num = 1, 568 .pin = 23, 569 .reg = 0x34, 570 .bit = 8, 571 .mask = 0xf 572 }, { 573 .num = 3, 574 .pin = 13, 575 .reg = 0x68, 576 .bit = 12, 577 .mask = 0xf 578 }, { 579 .num = 2, 580 .pin = 2, 581 .reg = 0x608, 582 .bit = 0, 583 .mask = 0x7 584 }, { 585 .num = 2, 586 .pin = 3, 587 .reg = 0x608, 588 .bit = 4, 589 .mask = 0x7 590 }, { 591 .num = 2, 592 .pin = 16, 593 .reg = 0x610, 594 .bit = 8, 595 .mask = 0x7 596 }, { 597 .num = 3, 598 .pin = 10, 599 .reg = 0x610, 600 .bit = 0, 601 .mask = 0x7 602 }, { 603 .num = 3, 604 .pin = 11, 605 .reg = 0x610, 606 .bit = 4, 607 .mask = 0x7 608 }, 609 }; 610 611 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 612 { 613 .num = 2, 614 .pin = 12, 615 .reg = 0x24, 616 .bit = 8, 617 .mask = 0x3 618 }, { 619 .num = 2, 620 .pin = 15, 621 .reg = 0x28, 622 .bit = 0, 623 .mask = 0x7 624 }, { 625 .num = 2, 626 .pin = 23, 627 .reg = 0x30, 628 .bit = 14, 629 .mask = 0x3 630 }, 631 }; 632 633 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 634 int *reg, u8 *bit, int *mask) 635 { 636 struct rockchip_pinctrl_priv *priv = bank->priv; 637 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 638 struct rockchip_mux_recalced_data *data; 639 int i; 640 641 for (i = 0; i < ctrl->niomux_recalced; i++) { 642 data = &ctrl->iomux_recalced[i]; 643 if (data->num == bank->bank_num && 644 data->pin == pin) 645 break; 646 } 647 648 if (i >= ctrl->niomux_recalced) 649 return; 650 651 *reg = data->reg; 652 *mask = data->mask; 653 *bit = data->bit; 654 } 655 656 static struct rockchip_mux_route_data px30_mux_route_data[] = { 657 { 658 /* cif-d2m0 */ 659 .bank_num = 2, 660 .pin = 0, 661 .func = 1, 662 .route_offset = 0x184, 663 .route_val = BIT(16 + 7), 664 }, { 665 /* cif-d2m1 */ 666 .bank_num = 3, 667 .pin = 3, 668 .func = 3, 669 .route_offset = 0x184, 670 .route_val = BIT(16 + 7) | BIT(7), 671 }, { 672 /* pdm-m0 */ 673 .bank_num = 3, 674 .pin = 22, 675 .func = 2, 676 .route_offset = 0x184, 677 .route_val = BIT(16 + 8), 678 }, { 679 /* pdm-m1 */ 680 .bank_num = 2, 681 .pin = 22, 682 .func = 1, 683 .route_offset = 0x184, 684 .route_val = BIT(16 + 8) | BIT(8), 685 }, { 686 /* uart2-rxm0 */ 687 .bank_num = 1, 688 .pin = 27, 689 .func = 2, 690 .route_offset = 0x184, 691 .route_val = BIT(16 + 10), 692 }, { 693 /* uart2-rxm1 */ 694 .bank_num = 2, 695 .pin = 14, 696 .func = 2, 697 .route_offset = 0x184, 698 .route_val = BIT(16 + 10) | BIT(10), 699 }, { 700 /* uart3-rxm0 */ 701 .bank_num = 0, 702 .pin = 17, 703 .func = 2, 704 .route_offset = 0x184, 705 .route_val = BIT(16 + 9), 706 }, { 707 /* uart3-rxm1 */ 708 .bank_num = 1, 709 .pin = 15, 710 .func = 2, 711 .route_offset = 0x184, 712 .route_val = BIT(16 + 9) | BIT(9), 713 }, 714 }; 715 716 static struct rockchip_mux_route_data rk1808_mux_route_data[] = { 717 { 718 /* i2c2m0_sda */ 719 .bank_num = 3, 720 .pin = 12, 721 .func = 2, 722 .route_offset = 0x190, 723 .route_val = BIT(16 + 3), 724 }, { 725 /* i2c2m1_sda */ 726 .bank_num = 1, 727 .pin = 13, 728 .func = 2, 729 .route_offset = 0x190, 730 .route_val = BIT(16 + 3) | BIT(3), 731 }, { 732 /* uart2_rxm0 */ 733 .bank_num = 4, 734 .pin = 3, 735 .func = 2, 736 .route_offset = 0x190, 737 .route_val = BIT(16 + 14) | BIT(16 + 15), 738 }, { 739 /* uart2_rxm1 */ 740 .bank_num = 2, 741 .pin = 25, 742 .func = 2, 743 .route_offset = 0x190, 744 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15), 745 }, { 746 /* uart2_rxm2 */ 747 .bank_num = 3, 748 .pin = 4, 749 .func = 2, 750 .route_offset = 0x190, 751 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15), 752 }, 753 }; 754 755 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 756 { 757 /* spi-0 */ 758 .bank_num = 1, 759 .pin = 10, 760 .func = 1, 761 .route_offset = 0x144, 762 .route_val = BIT(16 + 3) | BIT(16 + 4), 763 }, { 764 /* spi-1 */ 765 .bank_num = 1, 766 .pin = 27, 767 .func = 3, 768 .route_offset = 0x144, 769 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 770 }, { 771 /* spi-2 */ 772 .bank_num = 0, 773 .pin = 13, 774 .func = 2, 775 .route_offset = 0x144, 776 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 777 }, { 778 /* i2s-0 */ 779 .bank_num = 1, 780 .pin = 5, 781 .func = 1, 782 .route_offset = 0x144, 783 .route_val = BIT(16 + 5), 784 }, { 785 /* i2s-1 */ 786 .bank_num = 0, 787 .pin = 14, 788 .func = 1, 789 .route_offset = 0x144, 790 .route_val = BIT(16 + 5) | BIT(5), 791 }, { 792 /* emmc-0 */ 793 .bank_num = 1, 794 .pin = 22, 795 .func = 2, 796 .route_offset = 0x144, 797 .route_val = BIT(16 + 6), 798 }, { 799 /* emmc-1 */ 800 .bank_num = 2, 801 .pin = 4, 802 .func = 2, 803 .route_offset = 0x144, 804 .route_val = BIT(16 + 6) | BIT(6), 805 }, 806 }; 807 808 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 809 { 810 /* pwm0-0 */ 811 .bank_num = 0, 812 .pin = 26, 813 .func = 1, 814 .route_offset = 0x50, 815 .route_val = BIT(16), 816 }, { 817 /* pwm0-1 */ 818 .bank_num = 3, 819 .pin = 21, 820 .func = 1, 821 .route_offset = 0x50, 822 .route_val = BIT(16) | BIT(0), 823 }, { 824 /* pwm1-0 */ 825 .bank_num = 0, 826 .pin = 27, 827 .func = 1, 828 .route_offset = 0x50, 829 .route_val = BIT(16 + 1), 830 }, { 831 /* pwm1-1 */ 832 .bank_num = 0, 833 .pin = 30, 834 .func = 2, 835 .route_offset = 0x50, 836 .route_val = BIT(16 + 1) | BIT(1), 837 }, { 838 /* pwm2-0 */ 839 .bank_num = 0, 840 .pin = 28, 841 .func = 1, 842 .route_offset = 0x50, 843 .route_val = BIT(16 + 2), 844 }, { 845 /* pwm2-1 */ 846 .bank_num = 1, 847 .pin = 12, 848 .func = 2, 849 .route_offset = 0x50, 850 .route_val = BIT(16 + 2) | BIT(2), 851 }, { 852 /* pwm3-0 */ 853 .bank_num = 3, 854 .pin = 26, 855 .func = 1, 856 .route_offset = 0x50, 857 .route_val = BIT(16 + 3), 858 }, { 859 /* pwm3-1 */ 860 .bank_num = 1, 861 .pin = 11, 862 .func = 2, 863 .route_offset = 0x50, 864 .route_val = BIT(16 + 3) | BIT(3), 865 }, { 866 /* sdio-0_d0 */ 867 .bank_num = 1, 868 .pin = 1, 869 .func = 1, 870 .route_offset = 0x50, 871 .route_val = BIT(16 + 4), 872 }, { 873 /* sdio-1_d0 */ 874 .bank_num = 3, 875 .pin = 2, 876 .func = 1, 877 .route_offset = 0x50, 878 .route_val = BIT(16 + 4) | BIT(4), 879 }, { 880 /* spi-0_rx */ 881 .bank_num = 0, 882 .pin = 13, 883 .func = 2, 884 .route_offset = 0x50, 885 .route_val = BIT(16 + 5), 886 }, { 887 /* spi-1_rx */ 888 .bank_num = 2, 889 .pin = 0, 890 .func = 2, 891 .route_offset = 0x50, 892 .route_val = BIT(16 + 5) | BIT(5), 893 }, { 894 /* emmc-0_cmd */ 895 .bank_num = 1, 896 .pin = 22, 897 .func = 2, 898 .route_offset = 0x50, 899 .route_val = BIT(16 + 7), 900 }, { 901 /* emmc-1_cmd */ 902 .bank_num = 2, 903 .pin = 4, 904 .func = 2, 905 .route_offset = 0x50, 906 .route_val = BIT(16 + 7) | BIT(7), 907 }, { 908 /* uart2-0_rx */ 909 .bank_num = 1, 910 .pin = 19, 911 .func = 2, 912 .route_offset = 0x50, 913 .route_val = BIT(16 + 8), 914 }, { 915 /* uart2-1_rx */ 916 .bank_num = 1, 917 .pin = 10, 918 .func = 2, 919 .route_offset = 0x50, 920 .route_val = BIT(16 + 8) | BIT(8), 921 }, { 922 /* uart1-0_rx */ 923 .bank_num = 1, 924 .pin = 10, 925 .func = 1, 926 .route_offset = 0x50, 927 .route_val = BIT(16 + 11), 928 }, { 929 /* uart1-1_rx */ 930 .bank_num = 3, 931 .pin = 13, 932 .func = 1, 933 .route_offset = 0x50, 934 .route_val = BIT(16 + 11) | BIT(11), 935 }, 936 }; 937 938 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 939 { 940 /* edphdmi_cecinoutt1 */ 941 .bank_num = 7, 942 .pin = 16, 943 .func = 2, 944 .route_offset = 0x264, 945 .route_val = BIT(16 + 12) | BIT(12), 946 }, { 947 /* edphdmi_cecinout */ 948 .bank_num = 7, 949 .pin = 23, 950 .func = 4, 951 .route_offset = 0x264, 952 .route_val = BIT(16 + 12), 953 }, 954 }; 955 956 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 957 { 958 /* rtc_clk */ 959 .bank_num = 0, 960 .pin = 19, 961 .func = 1, 962 .route_offset = 0x314, 963 .route_val = BIT(16 + 0) | BIT(0), 964 }, { 965 /* uart2_rxm0 */ 966 .bank_num = 1, 967 .pin = 22, 968 .func = 2, 969 .route_offset = 0x314, 970 .route_val = BIT(16 + 2) | BIT(16 + 3), 971 }, { 972 /* uart2_rxm1 */ 973 .bank_num = 4, 974 .pin = 26, 975 .func = 2, 976 .route_offset = 0x314, 977 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 978 }, { 979 /* i2c3_sdam0 */ 980 .bank_num = 0, 981 .pin = 23, 982 .func = 2, 983 .route_offset = 0x314, 984 .route_val = BIT(16 + 4), 985 }, { 986 /* i2c3_sdam1 */ 987 .bank_num = 3, 988 .pin = 12, 989 .func = 2, 990 .route_offset = 0x314, 991 .route_val = BIT(16 + 4) | BIT(4), 992 }, { 993 /* i2s-8ch-1-sclktxm0 */ 994 .bank_num = 1, 995 .pin = 3, 996 .func = 2, 997 .route_offset = 0x308, 998 .route_val = BIT(16 + 3), 999 }, { 1000 /* i2s-8ch-1-sclkrxm0 */ 1001 .bank_num = 1, 1002 .pin = 4, 1003 .func = 2, 1004 .route_offset = 0x308, 1005 .route_val = BIT(16 + 3), 1006 }, { 1007 /* i2s-8ch-1-sclktxm1 */ 1008 .bank_num = 1, 1009 .pin = 13, 1010 .func = 2, 1011 .route_offset = 0x308, 1012 .route_val = BIT(16 + 3) | BIT(3), 1013 }, { 1014 /* i2s-8ch-1-sclkrxm1 */ 1015 .bank_num = 1, 1016 .pin = 14, 1017 .func = 2, 1018 .route_offset = 0x308, 1019 .route_val = BIT(16 + 3) | BIT(3), 1020 }, { 1021 /* pdm-clkm0 */ 1022 .bank_num = 1, 1023 .pin = 4, 1024 .func = 3, 1025 .route_offset = 0x308, 1026 .route_val = BIT(16 + 12) | BIT(16 + 13), 1027 }, { 1028 /* pdm-clkm1 */ 1029 .bank_num = 1, 1030 .pin = 14, 1031 .func = 4, 1032 .route_offset = 0x308, 1033 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1034 }, { 1035 /* pdm-clkm2 */ 1036 .bank_num = 2, 1037 .pin = 6, 1038 .func = 2, 1039 .route_offset = 0x308, 1040 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1041 }, { 1042 /* pdm-clkm-m2 */ 1043 .bank_num = 2, 1044 .pin = 4, 1045 .func = 3, 1046 .route_offset = 0x600, 1047 .route_val = BIT(16 + 2) | BIT(2), 1048 }, 1049 }; 1050 1051 static struct rockchip_mux_route_data rk3308b_mux_route_data[] = { 1052 { 1053 /* rtc_clk */ 1054 .bank_num = 0, 1055 .pin = 19, 1056 .func = 1, 1057 .route_offset = 0x314, 1058 .route_val = BIT(16 + 0) | BIT(0), 1059 }, { 1060 /* uart2_rxm0 */ 1061 .bank_num = 1, 1062 .pin = 22, 1063 .func = 2, 1064 .route_offset = 0x314, 1065 .route_val = BIT(16 + 2) | BIT(16 + 3), 1066 }, { 1067 /* uart2_rxm1 */ 1068 .bank_num = 4, 1069 .pin = 26, 1070 .func = 2, 1071 .route_offset = 0x314, 1072 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1073 }, { 1074 /* i2c3_sdam0 */ 1075 .bank_num = 0, 1076 .pin = 15, 1077 .func = 2, 1078 .route_offset = 0x608, 1079 .route_val = BIT(16 + 8) | BIT(16 + 9), 1080 }, { 1081 /* i2c3_sdam1 */ 1082 .bank_num = 3, 1083 .pin = 12, 1084 .func = 2, 1085 .route_offset = 0x608, 1086 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 1087 }, { 1088 /* i2c3_sdam2 */ 1089 .bank_num = 2, 1090 .pin = 0, 1091 .func = 3, 1092 .route_offset = 0x608, 1093 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 1094 }, { 1095 /* i2s-8ch-1-sclktxm0 */ 1096 .bank_num = 1, 1097 .pin = 3, 1098 .func = 2, 1099 .route_offset = 0x308, 1100 .route_val = BIT(16 + 3), 1101 }, { 1102 /* i2s-8ch-1-sclkrxm0 */ 1103 .bank_num = 1, 1104 .pin = 4, 1105 .func = 2, 1106 .route_offset = 0x308, 1107 .route_val = BIT(16 + 3), 1108 }, { 1109 /* i2s-8ch-1-sclktxm1 */ 1110 .bank_num = 1, 1111 .pin = 13, 1112 .func = 2, 1113 .route_offset = 0x308, 1114 .route_val = BIT(16 + 3) | BIT(3), 1115 }, { 1116 /* i2s-8ch-1-sclkrxm1 */ 1117 .bank_num = 1, 1118 .pin = 14, 1119 .func = 2, 1120 .route_offset = 0x308, 1121 .route_val = BIT(16 + 3) | BIT(3), 1122 }, { 1123 /* pdm-clkm0 */ 1124 .bank_num = 1, 1125 .pin = 4, 1126 .func = 3, 1127 .route_offset = 0x308, 1128 .route_val = BIT(16 + 12) | BIT(16 + 13), 1129 }, { 1130 /* pdm-clkm1 */ 1131 .bank_num = 1, 1132 .pin = 14, 1133 .func = 4, 1134 .route_offset = 0x308, 1135 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1136 }, { 1137 /* pdm-clkm2 */ 1138 .bank_num = 2, 1139 .pin = 6, 1140 .func = 2, 1141 .route_offset = 0x308, 1142 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1143 }, { 1144 /* pdm-clkm-m2 */ 1145 .bank_num = 2, 1146 .pin = 4, 1147 .func = 3, 1148 .route_offset = 0x600, 1149 .route_val = BIT(16 + 2) | BIT(2), 1150 }, { 1151 /* spi1_miso */ 1152 .bank_num = 3, 1153 .pin = 10, 1154 .func = 3, 1155 .route_offset = 0x314, 1156 .route_val = BIT(16 + 9), 1157 }, { 1158 /* spi1_miso_m1 */ 1159 .bank_num = 2, 1160 .pin = 4, 1161 .func = 2, 1162 .route_offset = 0x314, 1163 .route_val = BIT(16 + 9) | BIT(9), 1164 }, { 1165 /* owire_m0 */ 1166 .bank_num = 0, 1167 .pin = 11, 1168 .func = 3, 1169 .route_offset = 0x314, 1170 .route_val = BIT(16 + 10) | BIT(16 + 11), 1171 }, { 1172 /* owire_m1 */ 1173 .bank_num = 1, 1174 .pin = 22, 1175 .func = 7, 1176 .route_offset = 0x314, 1177 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1178 }, { 1179 /* owire_m2 */ 1180 .bank_num = 2, 1181 .pin = 2, 1182 .func = 5, 1183 .route_offset = 0x314, 1184 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1185 }, { 1186 /* can_rxd_m0 */ 1187 .bank_num = 0, 1188 .pin = 11, 1189 .func = 2, 1190 .route_offset = 0x314, 1191 .route_val = BIT(16 + 12) | BIT(16 + 13), 1192 }, { 1193 /* can_rxd_m1 */ 1194 .bank_num = 1, 1195 .pin = 22, 1196 .func = 5, 1197 .route_offset = 0x314, 1198 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1199 }, { 1200 /* can_rxd_m2 */ 1201 .bank_num = 2, 1202 .pin = 2, 1203 .func = 4, 1204 .route_offset = 0x314, 1205 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1206 }, { 1207 /* mac_rxd0_m0 */ 1208 .bank_num = 1, 1209 .pin = 20, 1210 .func = 3, 1211 .route_offset = 0x314, 1212 .route_val = BIT(16 + 14), 1213 }, { 1214 /* mac_rxd0_m1 */ 1215 .bank_num = 4, 1216 .pin = 2, 1217 .func = 2, 1218 .route_offset = 0x314, 1219 .route_val = BIT(16 + 14) | BIT(14), 1220 }, { 1221 /* uart3_rx */ 1222 .bank_num = 3, 1223 .pin = 12, 1224 .func = 4, 1225 .route_offset = 0x314, 1226 .route_val = BIT(16 + 15), 1227 }, { 1228 /* uart3_rx_m1 */ 1229 .bank_num = 0, 1230 .pin = 17, 1231 .func = 3, 1232 .route_offset = 0x314, 1233 .route_val = BIT(16 + 15) | BIT(15), 1234 }, 1235 }; 1236 1237 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1238 { 1239 /* uart2dbg_rxm0 */ 1240 .bank_num = 1, 1241 .pin = 1, 1242 .func = 2, 1243 .route_offset = 0x50, 1244 .route_val = BIT(16) | BIT(16 + 1), 1245 }, { 1246 /* uart2dbg_rxm1 */ 1247 .bank_num = 2, 1248 .pin = 1, 1249 .func = 1, 1250 .route_offset = 0x50, 1251 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1252 }, { 1253 /* gmac-m1_rxd0 */ 1254 .bank_num = 1, 1255 .pin = 11, 1256 .func = 2, 1257 .route_offset = 0x50, 1258 .route_val = BIT(16 + 2) | BIT(2), 1259 }, { 1260 /* gmac-m1-optimized_rxd3 */ 1261 .bank_num = 1, 1262 .pin = 14, 1263 .func = 2, 1264 .route_offset = 0x50, 1265 .route_val = BIT(16 + 10) | BIT(10), 1266 }, { 1267 /* pdm_sdi0m0 */ 1268 .bank_num = 2, 1269 .pin = 19, 1270 .func = 2, 1271 .route_offset = 0x50, 1272 .route_val = BIT(16 + 3), 1273 }, { 1274 /* pdm_sdi0m1 */ 1275 .bank_num = 1, 1276 .pin = 23, 1277 .func = 3, 1278 .route_offset = 0x50, 1279 .route_val = BIT(16 + 3) | BIT(3), 1280 }, { 1281 /* spi_rxdm2 */ 1282 .bank_num = 3, 1283 .pin = 2, 1284 .func = 4, 1285 .route_offset = 0x50, 1286 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1287 }, { 1288 /* i2s2_sdim0 */ 1289 .bank_num = 1, 1290 .pin = 24, 1291 .func = 1, 1292 .route_offset = 0x50, 1293 .route_val = BIT(16 + 6), 1294 }, { 1295 /* i2s2_sdim1 */ 1296 .bank_num = 3, 1297 .pin = 2, 1298 .func = 6, 1299 .route_offset = 0x50, 1300 .route_val = BIT(16 + 6) | BIT(6), 1301 }, { 1302 /* card_iom1 */ 1303 .bank_num = 2, 1304 .pin = 22, 1305 .func = 3, 1306 .route_offset = 0x50, 1307 .route_val = BIT(16 + 7) | BIT(7), 1308 }, { 1309 /* tsp_d5m1 */ 1310 .bank_num = 2, 1311 .pin = 16, 1312 .func = 3, 1313 .route_offset = 0x50, 1314 .route_val = BIT(16 + 8) | BIT(8), 1315 }, { 1316 /* cif_data5m1 */ 1317 .bank_num = 2, 1318 .pin = 16, 1319 .func = 4, 1320 .route_offset = 0x50, 1321 .route_val = BIT(16 + 9) | BIT(9), 1322 }, 1323 }; 1324 1325 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1326 { 1327 /* uart2dbga_rx */ 1328 .bank_num = 4, 1329 .pin = 8, 1330 .func = 2, 1331 .route_offset = 0xe21c, 1332 .route_val = BIT(16 + 10) | BIT(16 + 11), 1333 }, { 1334 /* uart2dbgb_rx */ 1335 .bank_num = 4, 1336 .pin = 16, 1337 .func = 2, 1338 .route_offset = 0xe21c, 1339 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1340 }, { 1341 /* uart2dbgc_rx */ 1342 .bank_num = 4, 1343 .pin = 19, 1344 .func = 1, 1345 .route_offset = 0xe21c, 1346 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1347 }, { 1348 /* pcie_clkreqn */ 1349 .bank_num = 2, 1350 .pin = 26, 1351 .func = 2, 1352 .route_offset = 0xe21c, 1353 .route_val = BIT(16 + 14), 1354 }, { 1355 /* pcie_clkreqnb */ 1356 .bank_num = 4, 1357 .pin = 24, 1358 .func = 1, 1359 .route_offset = 0xe21c, 1360 .route_val = BIT(16 + 14) | BIT(14), 1361 }, 1362 }; 1363 1364 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1365 int mux, u32 *reg, u32 *value) 1366 { 1367 struct rockchip_pinctrl_priv *priv = bank->priv; 1368 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1369 struct rockchip_mux_route_data *data; 1370 int i; 1371 1372 for (i = 0; i < ctrl->niomux_routes; i++) { 1373 data = &ctrl->iomux_routes[i]; 1374 if ((data->bank_num == bank->bank_num) && 1375 (data->pin == pin) && (data->func == mux)) 1376 break; 1377 } 1378 1379 if (i >= ctrl->niomux_routes) 1380 return false; 1381 1382 *reg = data->route_offset; 1383 *value = data->route_val; 1384 1385 return true; 1386 } 1387 1388 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1389 { 1390 struct rockchip_pinctrl_priv *priv = bank->priv; 1391 int iomux_num = (pin / 8); 1392 struct regmap *regmap; 1393 unsigned int val; 1394 int reg, ret, mask, mux_type; 1395 u8 bit; 1396 1397 if (iomux_num > 3) 1398 return -EINVAL; 1399 1400 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1401 debug("pin %d is unrouted\n", pin); 1402 return -EINVAL; 1403 } 1404 1405 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1406 return RK_FUNC_GPIO; 1407 1408 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1409 ? priv->regmap_pmu : priv->regmap_base; 1410 1411 /* get basic quadrupel of mux registers and the correct reg inside */ 1412 mux_type = bank->iomux[iomux_num].type; 1413 reg = bank->iomux[iomux_num].offset; 1414 if (mux_type & IOMUX_WIDTH_4BIT) { 1415 if ((pin % 8) >= 4) 1416 reg += 0x4; 1417 bit = (pin % 4) * 4; 1418 mask = 0xf; 1419 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1420 if ((pin % 8) >= 5) 1421 reg += 0x4; 1422 bit = (pin % 8 % 5) * 3; 1423 mask = 0x7; 1424 } else { 1425 bit = (pin % 8) * 2; 1426 mask = 0x3; 1427 } 1428 1429 if (bank->recalced_mask & BIT(pin)) 1430 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1431 1432 ret = regmap_read(regmap, reg, &val); 1433 if (ret) 1434 return ret; 1435 1436 return ((val >> bit) & mask); 1437 } 1438 1439 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1440 int index) 1441 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1442 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1443 1444 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1445 } 1446 1447 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1448 int pin, int mux) 1449 { 1450 int iomux_num = (pin / 8); 1451 1452 if (iomux_num > 3) 1453 return -EINVAL; 1454 1455 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1456 debug("pin %d is unrouted\n", pin); 1457 return -EINVAL; 1458 } 1459 1460 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1461 if (mux != IOMUX_GPIO_ONLY) { 1462 debug("pin %d only supports a gpio mux\n", pin); 1463 return -ENOTSUPP; 1464 } 1465 } 1466 1467 return 0; 1468 } 1469 1470 /* 1471 * Set a new mux function for a pin. 1472 * 1473 * The register is divided into the upper and lower 16 bit. When changing 1474 * a value, the previous register value is not read and changed. Instead 1475 * it seems the changed bits are marked in the upper 16 bit, while the 1476 * changed value gets set in the same offset in the lower 16 bit. 1477 * All pin settings seem to be 2 bit wide in both the upper and lower 1478 * parts. 1479 * @bank: pin bank to change 1480 * @pin: pin to change 1481 * @mux: new mux function to set 1482 */ 1483 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1484 { 1485 struct rockchip_pinctrl_priv *priv = bank->priv; 1486 int iomux_num = (pin / 8); 1487 struct regmap *regmap; 1488 int reg, ret, mask, mux_type; 1489 u8 bit; 1490 u32 data, route_reg, route_val; 1491 1492 ret = rockchip_verify_mux(bank, pin, mux); 1493 if (ret < 0) 1494 return ret; 1495 1496 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1497 return 0; 1498 1499 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1500 1501 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1502 ? priv->regmap_pmu : priv->regmap_base; 1503 1504 /* get basic quadrupel of mux registers and the correct reg inside */ 1505 mux_type = bank->iomux[iomux_num].type; 1506 reg = bank->iomux[iomux_num].offset; 1507 if (mux_type & IOMUX_WIDTH_4BIT) { 1508 if ((pin % 8) >= 4) 1509 reg += 0x4; 1510 bit = (pin % 4) * 4; 1511 mask = 0xf; 1512 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1513 if ((pin % 8) >= 5) 1514 reg += 0x4; 1515 bit = (pin % 8 % 5) * 3; 1516 mask = 0x7; 1517 } else { 1518 bit = (pin % 8) * 2; 1519 mask = 0x3; 1520 } 1521 1522 if (bank->recalced_mask & BIT(pin)) 1523 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1524 1525 if (bank->route_mask & BIT(pin)) { 1526 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1527 &route_val)) { 1528 ret = regmap_write(regmap, route_reg, route_val); 1529 if (ret) 1530 return ret; 1531 } 1532 } 1533 1534 if (mux_type & IOMUX_WRITABLE_32BIT) { 1535 regmap_read(regmap, reg, &data); 1536 data &= ~(mask << bit); 1537 } else { 1538 data = (mask << (bit + 16)); 1539 } 1540 1541 data |= (mux & mask) << bit; 1542 ret = regmap_write(regmap, reg, data); 1543 1544 return ret; 1545 } 1546 1547 #define PX30_PULL_PMU_OFFSET 0x10 1548 #define PX30_PULL_GRF_OFFSET 0x60 1549 #define PX30_PULL_BITS_PER_PIN 2 1550 #define PX30_PULL_PINS_PER_REG 8 1551 #define PX30_PULL_BANK_STRIDE 16 1552 1553 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1554 int pin_num, struct regmap **regmap, 1555 int *reg, u8 *bit) 1556 { 1557 struct rockchip_pinctrl_priv *priv = bank->priv; 1558 1559 /* The first 32 pins of the first bank are located in PMU */ 1560 if (bank->bank_num == 0) { 1561 *regmap = priv->regmap_pmu; 1562 *reg = PX30_PULL_PMU_OFFSET; 1563 } else { 1564 *regmap = priv->regmap_base; 1565 *reg = PX30_PULL_GRF_OFFSET; 1566 1567 /* correct the offset, as we're starting with the 2nd bank */ 1568 *reg -= 0x10; 1569 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1570 } 1571 1572 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1573 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1574 *bit *= PX30_PULL_BITS_PER_PIN; 1575 } 1576 1577 #define PX30_DRV_PMU_OFFSET 0x20 1578 #define PX30_DRV_GRF_OFFSET 0xf0 1579 #define PX30_DRV_BITS_PER_PIN 2 1580 #define PX30_DRV_PINS_PER_REG 8 1581 #define PX30_DRV_BANK_STRIDE 16 1582 1583 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1584 int pin_num, struct regmap **regmap, 1585 int *reg, u8 *bit) 1586 { 1587 struct rockchip_pinctrl_priv *priv = bank->priv; 1588 1589 /* The first 32 pins of the first bank are located in PMU */ 1590 if (bank->bank_num == 0) { 1591 *regmap = priv->regmap_pmu; 1592 *reg = PX30_DRV_PMU_OFFSET; 1593 } else { 1594 *regmap = priv->regmap_base; 1595 *reg = PX30_DRV_GRF_OFFSET; 1596 1597 /* correct the offset, as we're starting with the 2nd bank */ 1598 *reg -= 0x10; 1599 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1600 } 1601 1602 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1603 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1604 *bit *= PX30_DRV_BITS_PER_PIN; 1605 } 1606 1607 #define PX30_SCHMITT_PMU_OFFSET 0x38 1608 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1609 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1610 #define PX30_SCHMITT_BANK_STRIDE 16 1611 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1612 1613 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1614 int pin_num, 1615 struct regmap **regmap, 1616 int *reg, u8 *bit) 1617 { 1618 struct rockchip_pinctrl_priv *priv = bank->priv; 1619 int pins_per_reg; 1620 1621 if (bank->bank_num == 0) { 1622 *regmap = priv->regmap_pmu; 1623 *reg = PX30_SCHMITT_PMU_OFFSET; 1624 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1625 } else { 1626 *regmap = priv->regmap_base; 1627 *reg = PX30_SCHMITT_GRF_OFFSET; 1628 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1629 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1630 } 1631 *reg += ((pin_num / pins_per_reg) * 4); 1632 *bit = pin_num % pins_per_reg; 1633 1634 return 0; 1635 } 1636 1637 #define RV1108_PULL_PMU_OFFSET 0x10 1638 #define RV1108_PULL_OFFSET 0x110 1639 #define RV1108_PULL_PINS_PER_REG 8 1640 #define RV1108_PULL_BITS_PER_PIN 2 1641 #define RV1108_PULL_BANK_STRIDE 16 1642 1643 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1644 int pin_num, struct regmap **regmap, 1645 int *reg, u8 *bit) 1646 { 1647 struct rockchip_pinctrl_priv *priv = bank->priv; 1648 1649 /* The first 24 pins of the first bank are located in PMU */ 1650 if (bank->bank_num == 0) { 1651 *regmap = priv->regmap_pmu; 1652 *reg = RV1108_PULL_PMU_OFFSET; 1653 } else { 1654 *reg = RV1108_PULL_OFFSET; 1655 *regmap = priv->regmap_base; 1656 /* correct the offset, as we're starting with the 2nd bank */ 1657 *reg -= 0x10; 1658 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1659 } 1660 1661 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1662 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1663 *bit *= RV1108_PULL_BITS_PER_PIN; 1664 } 1665 1666 #define RV1108_DRV_PMU_OFFSET 0x20 1667 #define RV1108_DRV_GRF_OFFSET 0x210 1668 #define RV1108_DRV_BITS_PER_PIN 2 1669 #define RV1108_DRV_PINS_PER_REG 8 1670 #define RV1108_DRV_BANK_STRIDE 16 1671 1672 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1673 int pin_num, struct regmap **regmap, 1674 int *reg, u8 *bit) 1675 { 1676 struct rockchip_pinctrl_priv *priv = bank->priv; 1677 1678 /* The first 24 pins of the first bank are located in PMU */ 1679 if (bank->bank_num == 0) { 1680 *regmap = priv->regmap_pmu; 1681 *reg = RV1108_DRV_PMU_OFFSET; 1682 } else { 1683 *regmap = priv->regmap_base; 1684 *reg = RV1108_DRV_GRF_OFFSET; 1685 1686 /* correct the offset, as we're starting with the 2nd bank */ 1687 *reg -= 0x10; 1688 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1689 } 1690 1691 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1692 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1693 *bit *= RV1108_DRV_BITS_PER_PIN; 1694 } 1695 1696 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1697 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1698 #define RV1108_SCHMITT_BANK_STRIDE 8 1699 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1700 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1701 1702 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1703 int pin_num, 1704 struct regmap **regmap, 1705 int *reg, u8 *bit) 1706 { 1707 struct rockchip_pinctrl_priv *priv = bank->priv; 1708 int pins_per_reg; 1709 1710 if (bank->bank_num == 0) { 1711 *regmap = priv->regmap_pmu; 1712 *reg = RV1108_SCHMITT_PMU_OFFSET; 1713 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1714 } else { 1715 *regmap = priv->regmap_base; 1716 *reg = RV1108_SCHMITT_GRF_OFFSET; 1717 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1718 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1719 } 1720 *reg += ((pin_num / pins_per_reg) * 4); 1721 *bit = pin_num % pins_per_reg; 1722 1723 return 0; 1724 } 1725 1726 #define RK1808_PULL_PMU_OFFSET 0x10 1727 #define RK1808_PULL_GRF_OFFSET 0x80 1728 #define RK1808_PULL_PINS_PER_REG 8 1729 #define RK1808_PULL_BITS_PER_PIN 2 1730 #define RK1808_PULL_BANK_STRIDE 16 1731 1732 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1733 int pin_num, 1734 struct regmap **regmap, 1735 int *reg, u8 *bit) 1736 { 1737 struct rockchip_pinctrl_priv *priv = bank->priv; 1738 1739 if (bank->bank_num == 0) { 1740 *regmap = priv->regmap_pmu; 1741 *reg = RK1808_PULL_PMU_OFFSET; 1742 } else { 1743 *reg = RK1808_PULL_GRF_OFFSET; 1744 *regmap = priv->regmap_base; 1745 } 1746 1747 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4); 1748 *bit = (pin_num % RK1808_PULL_PINS_PER_REG); 1749 *bit *= RK1808_PULL_BITS_PER_PIN; 1750 } 1751 1752 #define RK1808_DRV_PMU_OFFSET 0x20 1753 #define RK1808_DRV_GRF_OFFSET 0x140 1754 #define RK1808_DRV_BITS_PER_PIN 2 1755 #define RK1808_DRV_PINS_PER_REG 8 1756 #define RK1808_DRV_BANK_STRIDE 16 1757 1758 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1759 int pin_num, 1760 struct regmap **regmap, 1761 int *reg, u8 *bit) 1762 { 1763 struct rockchip_pinctrl_priv *priv = bank->priv; 1764 1765 if (bank->bank_num == 0) { 1766 *regmap = priv->regmap_pmu; 1767 *reg = RK1808_DRV_PMU_OFFSET; 1768 } else { 1769 *regmap = priv->regmap_base; 1770 *reg = RK1808_DRV_GRF_OFFSET; 1771 } 1772 1773 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4); 1774 *bit = pin_num % RK1808_DRV_PINS_PER_REG; 1775 *bit *= RK1808_DRV_BITS_PER_PIN; 1776 } 1777 1778 #define RK1808_SCHMITT_PMU_OFFSET 0x0040 1779 #define RK1808_SCHMITT_GRF_OFFSET 0x0100 1780 #define RK1808_SCHMITT_BANK_STRIDE 16 1781 #define RK1808_SCHMITT_PINS_PER_REG 8 1782 1783 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1784 int pin_num, 1785 struct regmap **regmap, 1786 int *reg, u8 *bit) 1787 { 1788 struct rockchip_pinctrl_priv *priv = bank->priv; 1789 1790 if (bank->bank_num == 0) { 1791 *regmap = priv->regmap_pmu; 1792 *reg = RK1808_SCHMITT_PMU_OFFSET; 1793 } else { 1794 *regmap = priv->regmap_base; 1795 *reg = RK1808_SCHMITT_GRF_OFFSET; 1796 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE; 1797 } 1798 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4); 1799 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG; 1800 1801 return 0; 1802 } 1803 1804 #define RK2928_PULL_OFFSET 0x118 1805 #define RK2928_PULL_PINS_PER_REG 16 1806 #define RK2928_PULL_BANK_STRIDE 8 1807 1808 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1809 int pin_num, struct regmap **regmap, 1810 int *reg, u8 *bit) 1811 { 1812 struct rockchip_pinctrl_priv *priv = bank->priv; 1813 1814 *regmap = priv->regmap_base; 1815 *reg = RK2928_PULL_OFFSET; 1816 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1817 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1818 1819 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1820 }; 1821 1822 #define RK3128_PULL_OFFSET 0x118 1823 1824 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1825 int pin_num, struct regmap **regmap, 1826 int *reg, u8 *bit) 1827 { 1828 struct rockchip_pinctrl_priv *priv = bank->priv; 1829 1830 *regmap = priv->regmap_base; 1831 *reg = RK3128_PULL_OFFSET; 1832 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1833 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1834 1835 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1836 } 1837 1838 #define RK3188_PULL_OFFSET 0x164 1839 #define RK3188_PULL_BITS_PER_PIN 2 1840 #define RK3188_PULL_PINS_PER_REG 8 1841 #define RK3188_PULL_BANK_STRIDE 16 1842 #define RK3188_PULL_PMU_OFFSET 0x64 1843 1844 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1845 int pin_num, struct regmap **regmap, 1846 int *reg, u8 *bit) 1847 { 1848 struct rockchip_pinctrl_priv *priv = bank->priv; 1849 1850 /* The first 12 pins of the first bank are located elsewhere */ 1851 if (bank->bank_num == 0 && pin_num < 12) { 1852 *regmap = priv->regmap_pmu; 1853 *reg = RK3188_PULL_PMU_OFFSET; 1854 1855 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1856 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1857 *bit *= RK3188_PULL_BITS_PER_PIN; 1858 } else { 1859 *regmap = priv->regmap_base; 1860 *reg = RK3188_PULL_OFFSET; 1861 1862 /* correct the offset, as it is the 2nd pull register */ 1863 *reg -= 4; 1864 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1865 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1866 1867 /* 1868 * The bits in these registers have an inverse ordering 1869 * with the lowest pin being in bits 15:14 and the highest 1870 * pin in bits 1:0 1871 */ 1872 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1873 *bit *= RK3188_PULL_BITS_PER_PIN; 1874 } 1875 } 1876 1877 #define RK3288_PULL_OFFSET 0x140 1878 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1879 int pin_num, struct regmap **regmap, 1880 int *reg, u8 *bit) 1881 { 1882 struct rockchip_pinctrl_priv *priv = bank->priv; 1883 1884 /* The first 24 pins of the first bank are located in PMU */ 1885 if (bank->bank_num == 0) { 1886 *regmap = priv->regmap_pmu; 1887 *reg = RK3188_PULL_PMU_OFFSET; 1888 1889 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1890 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1891 *bit *= RK3188_PULL_BITS_PER_PIN; 1892 } else { 1893 *regmap = priv->regmap_base; 1894 *reg = RK3288_PULL_OFFSET; 1895 1896 /* correct the offset, as we're starting with the 2nd bank */ 1897 *reg -= 0x10; 1898 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1899 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1900 1901 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1902 *bit *= RK3188_PULL_BITS_PER_PIN; 1903 } 1904 } 1905 1906 #define RK3288_DRV_PMU_OFFSET 0x70 1907 #define RK3288_DRV_GRF_OFFSET 0x1c0 1908 #define RK3288_DRV_BITS_PER_PIN 2 1909 #define RK3288_DRV_PINS_PER_REG 8 1910 #define RK3288_DRV_BANK_STRIDE 16 1911 1912 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1913 int pin_num, struct regmap **regmap, 1914 int *reg, u8 *bit) 1915 { 1916 struct rockchip_pinctrl_priv *priv = bank->priv; 1917 1918 /* The first 24 pins of the first bank are located in PMU */ 1919 if (bank->bank_num == 0) { 1920 *regmap = priv->regmap_pmu; 1921 *reg = RK3288_DRV_PMU_OFFSET; 1922 1923 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1924 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1925 *bit *= RK3288_DRV_BITS_PER_PIN; 1926 } else { 1927 *regmap = priv->regmap_base; 1928 *reg = RK3288_DRV_GRF_OFFSET; 1929 1930 /* correct the offset, as we're starting with the 2nd bank */ 1931 *reg -= 0x10; 1932 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1933 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1934 1935 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1936 *bit *= RK3288_DRV_BITS_PER_PIN; 1937 } 1938 } 1939 1940 #define RK3228_PULL_OFFSET 0x100 1941 1942 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1943 int pin_num, struct regmap **regmap, 1944 int *reg, u8 *bit) 1945 { 1946 struct rockchip_pinctrl_priv *priv = bank->priv; 1947 1948 *regmap = priv->regmap_base; 1949 *reg = RK3228_PULL_OFFSET; 1950 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1951 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1952 1953 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1954 *bit *= RK3188_PULL_BITS_PER_PIN; 1955 } 1956 1957 #define RK3228_DRV_GRF_OFFSET 0x200 1958 1959 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1960 int pin_num, struct regmap **regmap, 1961 int *reg, u8 *bit) 1962 { 1963 struct rockchip_pinctrl_priv *priv = bank->priv; 1964 1965 *regmap = priv->regmap_base; 1966 *reg = RK3228_DRV_GRF_OFFSET; 1967 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1968 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1969 1970 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1971 *bit *= RK3288_DRV_BITS_PER_PIN; 1972 } 1973 1974 #define RK3308_PULL_OFFSET 0xa0 1975 1976 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1977 int pin_num, struct regmap **regmap, 1978 int *reg, u8 *bit) 1979 { 1980 struct rockchip_pinctrl_priv *priv = bank->priv; 1981 1982 *regmap = priv->regmap_base; 1983 *reg = RK3308_PULL_OFFSET; 1984 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1985 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1986 1987 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1988 *bit *= RK3188_PULL_BITS_PER_PIN; 1989 } 1990 1991 #define RK3308_DRV_GRF_OFFSET 0x100 1992 1993 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1994 int pin_num, struct regmap **regmap, 1995 int *reg, u8 *bit) 1996 { 1997 struct rockchip_pinctrl_priv *priv = bank->priv; 1998 1999 *regmap = priv->regmap_base; 2000 *reg = RK3308_DRV_GRF_OFFSET; 2001 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2002 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2003 2004 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2005 *bit *= RK3288_DRV_BITS_PER_PIN; 2006 } 2007 2008 #define RK3308_SCHMITT_PINS_PER_REG 8 2009 #define RK3308_SCHMITT_BANK_STRIDE 16 2010 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 2011 2012 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2013 int pin_num, 2014 struct regmap **regmap, 2015 int *reg, u8 *bit) 2016 { 2017 struct rockchip_pinctrl_priv *priv = bank->priv; 2018 2019 *regmap = priv->regmap_base; 2020 *reg = RK3308_SCHMITT_GRF_OFFSET; 2021 2022 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 2023 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 2024 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 2025 2026 return 0; 2027 } 2028 2029 #define RK3368_PULL_GRF_OFFSET 0x100 2030 #define RK3368_PULL_PMU_OFFSET 0x10 2031 2032 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2033 int pin_num, struct regmap **regmap, 2034 int *reg, u8 *bit) 2035 { 2036 struct rockchip_pinctrl_priv *priv = bank->priv; 2037 2038 /* The first 32 pins of the first bank are located in PMU */ 2039 if (bank->bank_num == 0) { 2040 *regmap = priv->regmap_pmu; 2041 *reg = RK3368_PULL_PMU_OFFSET; 2042 2043 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2044 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2045 *bit *= RK3188_PULL_BITS_PER_PIN; 2046 } else { 2047 *regmap = priv->regmap_base; 2048 *reg = RK3368_PULL_GRF_OFFSET; 2049 2050 /* correct the offset, as we're starting with the 2nd bank */ 2051 *reg -= 0x10; 2052 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2053 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2054 2055 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2056 *bit *= RK3188_PULL_BITS_PER_PIN; 2057 } 2058 } 2059 2060 #define RK3368_DRV_PMU_OFFSET 0x20 2061 #define RK3368_DRV_GRF_OFFSET 0x200 2062 2063 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2064 int pin_num, struct regmap **regmap, 2065 int *reg, u8 *bit) 2066 { 2067 struct rockchip_pinctrl_priv *priv = bank->priv; 2068 2069 /* The first 32 pins of the first bank are located in PMU */ 2070 if (bank->bank_num == 0) { 2071 *regmap = priv->regmap_pmu; 2072 *reg = RK3368_DRV_PMU_OFFSET; 2073 2074 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2075 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2076 *bit *= RK3288_DRV_BITS_PER_PIN; 2077 } else { 2078 *regmap = priv->regmap_base; 2079 *reg = RK3368_DRV_GRF_OFFSET; 2080 2081 /* correct the offset, as we're starting with the 2nd bank */ 2082 *reg -= 0x10; 2083 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2084 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2085 2086 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2087 *bit *= RK3288_DRV_BITS_PER_PIN; 2088 } 2089 } 2090 2091 #define RK3399_PULL_GRF_OFFSET 0xe040 2092 #define RK3399_PULL_PMU_OFFSET 0x40 2093 #define RK3399_DRV_3BITS_PER_PIN 3 2094 2095 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2096 int pin_num, struct regmap **regmap, 2097 int *reg, u8 *bit) 2098 { 2099 struct rockchip_pinctrl_priv *priv = bank->priv; 2100 2101 /* The bank0:16 and bank1:32 pins are located in PMU */ 2102 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2103 *regmap = priv->regmap_pmu; 2104 *reg = RK3399_PULL_PMU_OFFSET; 2105 2106 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2107 2108 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2109 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2110 *bit *= RK3188_PULL_BITS_PER_PIN; 2111 } else { 2112 *regmap = priv->regmap_base; 2113 *reg = RK3399_PULL_GRF_OFFSET; 2114 2115 /* correct the offset, as we're starting with the 3rd bank */ 2116 *reg -= 0x20; 2117 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2118 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2119 2120 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2121 *bit *= RK3188_PULL_BITS_PER_PIN; 2122 } 2123 } 2124 2125 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2126 int pin_num, struct regmap **regmap, 2127 int *reg, u8 *bit) 2128 { 2129 struct rockchip_pinctrl_priv *priv = bank->priv; 2130 int drv_num = (pin_num / 8); 2131 2132 /* The bank0:16 and bank1:32 pins are located in PMU */ 2133 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2134 *regmap = priv->regmap_pmu; 2135 else 2136 *regmap = priv->regmap_base; 2137 2138 *reg = bank->drv[drv_num].offset; 2139 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2140 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2141 *bit = (pin_num % 8) * 3; 2142 else 2143 *bit = (pin_num % 8) * 2; 2144 } 2145 2146 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2147 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2148 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2149 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2150 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2151 { 4, 7, 10, 13, 16, 19, 22, 26 } 2152 }; 2153 2154 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2155 int pin_num, int strength) 2156 { 2157 struct rockchip_pinctrl_priv *priv = bank->priv; 2158 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2159 struct regmap *regmap; 2160 int reg, ret, i; 2161 u32 data, rmask_bits, temp; 2162 u8 bit; 2163 /* Where need to clean the special mask for rockchip_perpin_drv_list */ 2164 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); 2165 2166 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 2167 pin_num, strength); 2168 2169 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2170 2171 ret = -EINVAL; 2172 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2173 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2174 ret = i; 2175 break; 2176 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2177 ret = rockchip_perpin_drv_list[drv_type][i]; 2178 break; 2179 } 2180 } 2181 2182 if (ret < 0) { 2183 debug("unsupported driver strength %d\n", strength); 2184 return ret; 2185 } 2186 2187 switch (drv_type) { 2188 case DRV_TYPE_IO_1V8_3V0_AUTO: 2189 case DRV_TYPE_IO_3V3_ONLY: 2190 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2191 switch (bit) { 2192 case 0 ... 12: 2193 /* regular case, nothing to do */ 2194 break; 2195 case 15: 2196 /* 2197 * drive-strength offset is special, as it is spread 2198 * over 2 registers, the bit data[15] contains bit 0 2199 * of the value while temp[1:0] contains bits 2 and 1 2200 */ 2201 data = (ret & 0x1) << 15; 2202 temp = (ret >> 0x1) & 0x3; 2203 2204 data |= BIT(31); 2205 ret = regmap_write(regmap, reg, data); 2206 if (ret) 2207 return ret; 2208 2209 temp |= (0x3 << 16); 2210 reg += 0x4; 2211 ret = regmap_write(regmap, reg, temp); 2212 2213 return ret; 2214 case 18 ... 21: 2215 /* setting fully enclosed in the second register */ 2216 reg += 4; 2217 bit -= 16; 2218 break; 2219 default: 2220 debug("unsupported bit: %d for pinctrl drive type: %d\n", 2221 bit, drv_type); 2222 return -EINVAL; 2223 } 2224 break; 2225 case DRV_TYPE_IO_DEFAULT: 2226 case DRV_TYPE_IO_1V8_OR_3V0: 2227 case DRV_TYPE_IO_1V8_ONLY: 2228 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2229 break; 2230 default: 2231 debug("unsupported pinctrl drive type: %d\n", 2232 drv_type); 2233 return -EINVAL; 2234 } 2235 2236 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 2237 regmap_read(regmap, reg, &data); 2238 data &= ~(((1 << rmask_bits) - 1) << bit); 2239 } else { 2240 /* enable the write to the equivalent lower bits */ 2241 data = ((1 << rmask_bits) - 1) << (bit + 16); 2242 } 2243 2244 data |= (ret << bit); 2245 ret = regmap_write(regmap, reg, data); 2246 return ret; 2247 } 2248 2249 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2250 { 2251 PIN_CONFIG_BIAS_DISABLE, 2252 PIN_CONFIG_BIAS_PULL_UP, 2253 PIN_CONFIG_BIAS_PULL_DOWN, 2254 PIN_CONFIG_BIAS_BUS_HOLD 2255 }, 2256 { 2257 PIN_CONFIG_BIAS_DISABLE, 2258 PIN_CONFIG_BIAS_PULL_DOWN, 2259 PIN_CONFIG_BIAS_DISABLE, 2260 PIN_CONFIG_BIAS_PULL_UP 2261 }, 2262 }; 2263 2264 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2265 int pin_num, int pull) 2266 { 2267 struct rockchip_pinctrl_priv *priv = bank->priv; 2268 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2269 struct regmap *regmap; 2270 int reg, ret, i, pull_type; 2271 u8 bit; 2272 u32 data; 2273 2274 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 2275 pin_num, pull); 2276 2277 /* rk3066b does support any pulls */ 2278 if (ctrl->type == RK3066B) 2279 return pull ? -EINVAL : 0; 2280 2281 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2282 2283 switch (ctrl->type) { 2284 case RK2928: 2285 case RK3128: 2286 data = BIT(bit + 16); 2287 if (pull == PIN_CONFIG_BIAS_DISABLE) 2288 data |= BIT(bit); 2289 ret = regmap_write(regmap, reg, data); 2290 break; 2291 case PX30: 2292 case RV1108: 2293 case RK1808: 2294 case RK3188: 2295 case RK3288: 2296 case RK3308: 2297 case RK3368: 2298 case RK3399: 2299 /* 2300 * Where need to clean the special mask for 2301 * rockchip_pull_list. 2302 */ 2303 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); 2304 ret = -EINVAL; 2305 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2306 i++) { 2307 if (rockchip_pull_list[pull_type][i] == pull) { 2308 ret = i; 2309 break; 2310 } 2311 } 2312 2313 if (ret < 0) { 2314 debug("unsupported pull setting %d\n", pull); 2315 return ret; 2316 } 2317 2318 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 2319 regmap_read(regmap, reg, &data); 2320 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); 2321 } else { 2322 /* enable the write to the equivalent lower bits */ 2323 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2324 } 2325 2326 data |= (ret << bit); 2327 ret = regmap_write(regmap, reg, data); 2328 break; 2329 default: 2330 debug("unsupported pinctrl type\n"); 2331 return -EINVAL; 2332 } 2333 2334 return ret; 2335 } 2336 2337 #define RK3328_SCHMITT_BITS_PER_PIN 1 2338 #define RK3328_SCHMITT_PINS_PER_REG 16 2339 #define RK3328_SCHMITT_BANK_STRIDE 8 2340 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2341 2342 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2343 int pin_num, 2344 struct regmap **regmap, 2345 int *reg, u8 *bit) 2346 { 2347 struct rockchip_pinctrl_priv *priv = bank->priv; 2348 2349 *regmap = priv->regmap_base; 2350 *reg = RK3328_SCHMITT_GRF_OFFSET; 2351 2352 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2353 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2354 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2355 2356 return 0; 2357 } 2358 2359 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2360 int pin_num, int enable) 2361 { 2362 struct rockchip_pinctrl_priv *priv = bank->priv; 2363 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2364 struct regmap *regmap; 2365 int reg, ret; 2366 u8 bit; 2367 u32 data; 2368 2369 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 2370 pin_num, enable); 2371 2372 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2373 if (ret) 2374 return ret; 2375 2376 /* enable the write to the equivalent lower bits */ 2377 data = BIT(bit + 16) | (enable << bit); 2378 2379 return regmap_write(regmap, reg, data); 2380 } 2381 2382 #define PX30_SLEW_RATE_PMU_OFFSET 0x30 2383 #define PX30_SLEW_RATE_GRF_OFFSET 0x90 2384 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16 2385 #define PX30_SLEW_RATE_BANK_STRIDE 16 2386 #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8 2387 2388 static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, 2389 int pin_num, 2390 struct regmap **regmap, 2391 int *reg, u8 *bit) 2392 { 2393 struct rockchip_pinctrl_priv *priv = bank->priv; 2394 int pins_per_reg; 2395 2396 if (bank->bank_num == 0) { 2397 *regmap = priv->regmap_pmu; 2398 *reg = PX30_SLEW_RATE_PMU_OFFSET; 2399 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 2400 } else { 2401 *regmap = priv->regmap_base; 2402 *reg = PX30_SCHMITT_GRF_OFFSET; 2403 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 2404 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 2405 } 2406 *reg += ((pin_num / pins_per_reg) * 4); 2407 *bit = pin_num % pins_per_reg; 2408 2409 return 0; 2410 } 2411 2412 static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank, 2413 int pin_num, int speed) 2414 { 2415 struct rockchip_pinctrl_priv *priv = bank->priv; 2416 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2417 struct regmap *regmap; 2418 int reg, ret; 2419 u8 bit; 2420 u32 data; 2421 2422 debug("setting slew rate of GPIO%d-%d to %d\n", bank->bank_num, 2423 pin_num, speed); 2424 2425 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit); 2426 if (ret) 2427 return ret; 2428 2429 /* enable the write to the equivalent lower bits */ 2430 data = BIT(bit + 16) | (speed << bit); 2431 2432 return regmap_write(regmap, reg, data); 2433 } 2434 2435 /* 2436 * Pinconf_ops handling 2437 */ 2438 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2439 unsigned int pull) 2440 { 2441 switch (ctrl->type) { 2442 case RK2928: 2443 case RK3128: 2444 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2445 pull == PIN_CONFIG_BIAS_DISABLE); 2446 case RK3066B: 2447 return pull ? false : true; 2448 case PX30: 2449 case RV1108: 2450 case RK1808: 2451 case RK3188: 2452 case RK3288: 2453 case RK3308: 2454 case RK3368: 2455 case RK3399: 2456 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2457 } 2458 2459 return false; 2460 } 2461 2462 /* set the pin config settings for a specified pin */ 2463 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 2464 u32 pin, u32 param, u32 arg) 2465 { 2466 struct rockchip_pinctrl_priv *priv = bank->priv; 2467 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2468 int rc; 2469 2470 switch (param) { 2471 case PIN_CONFIG_BIAS_DISABLE: 2472 rc = rockchip_set_pull(bank, pin, param); 2473 if (rc) 2474 return rc; 2475 break; 2476 2477 case PIN_CONFIG_BIAS_PULL_UP: 2478 case PIN_CONFIG_BIAS_PULL_DOWN: 2479 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2480 case PIN_CONFIG_BIAS_BUS_HOLD: 2481 if (!rockchip_pinconf_pull_valid(ctrl, param)) 2482 return -ENOTSUPP; 2483 2484 if (!arg) 2485 return -EINVAL; 2486 2487 rc = rockchip_set_pull(bank, pin, param); 2488 if (rc) 2489 return rc; 2490 break; 2491 2492 case PIN_CONFIG_DRIVE_STRENGTH: 2493 if (!ctrl->drv_calc_reg) 2494 return -ENOTSUPP; 2495 2496 rc = rockchip_set_drive_perpin(bank, pin, arg); 2497 if (rc < 0) 2498 return rc; 2499 break; 2500 2501 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2502 if (!ctrl->schmitt_calc_reg) 2503 return -ENOTSUPP; 2504 2505 rc = rockchip_set_schmitt(bank, pin, arg); 2506 if (rc < 0) 2507 return rc; 2508 break; 2509 2510 case PIN_CONFIG_SLEW_RATE: 2511 if (!ctrl->slew_rate_calc_reg) 2512 return -ENOTSUPP; 2513 2514 rc = rockchip_set_slew_rate(bank, 2515 pin - bank->pin_base, arg); 2516 if (rc < 0) 2517 return rc; 2518 break; 2519 2520 default: 2521 break; 2522 } 2523 2524 return 0; 2525 } 2526 2527 static const struct pinconf_param rockchip_conf_params[] = { 2528 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 2529 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 2530 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 2531 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 2532 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 2533 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 2534 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 2535 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 2536 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 2537 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, 2538 }; 2539 2540 static int rockchip_pinconf_prop_name_to_param(const char *property, 2541 u32 *default_value) 2542 { 2543 const struct pinconf_param *p, *end; 2544 2545 p = rockchip_conf_params; 2546 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 2547 2548 /* See if this pctldev supports this parameter */ 2549 for (; p < end; p++) { 2550 if (!strcmp(property, p->property)) { 2551 *default_value = p->default_value; 2552 return p->param; 2553 } 2554 } 2555 2556 *default_value = 0; 2557 return -EPERM; 2558 } 2559 2560 static int rockchip_pinctrl_set_state(struct udevice *dev, 2561 struct udevice *config) 2562 { 2563 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2564 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2565 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 2566 u32 bank, pin, mux, conf, arg, default_val; 2567 int ret, count, i; 2568 const char *prop_name; 2569 const void *value; 2570 int prop_len, param; 2571 const u32 *data; 2572 ofnode node; 2573 #ifdef CONFIG_OF_LIVE 2574 const struct device_node *np; 2575 struct property *pp; 2576 #else 2577 int property_offset, pcfg_node; 2578 const void *blob = gd->fdt_blob; 2579 #endif 2580 data = dev_read_prop(config, "rockchip,pins", &count); 2581 if (count < 0) { 2582 debug("%s: bad array size %d\n", __func__, count); 2583 return -EINVAL; 2584 } 2585 2586 count /= sizeof(u32); 2587 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2588 debug("%s: unsupported pins array count %d\n", 2589 __func__, count); 2590 return -EINVAL; 2591 } 2592 2593 for (i = 0; i < count; i++) 2594 cells[i] = fdt32_to_cpu(data[i]); 2595 2596 for (i = 0; i < (count >> 2); i++) { 2597 bank = cells[4 * i + 0]; 2598 pin = cells[4 * i + 1]; 2599 mux = cells[4 * i + 2]; 2600 conf = cells[4 * i + 3]; 2601 2602 ret = rockchip_verify_config(dev, bank, pin); 2603 if (ret) 2604 return ret; 2605 2606 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2607 if (ret) 2608 return ret; 2609 2610 node = ofnode_get_by_phandle(conf); 2611 if (!ofnode_valid(node)) 2612 return -ENODEV; 2613 #ifdef CONFIG_OF_LIVE 2614 np = ofnode_to_np(node); 2615 for (pp = np->properties; pp; pp = pp->next) { 2616 prop_name = pp->name; 2617 prop_len = pp->length; 2618 value = pp->value; 2619 #else 2620 pcfg_node = ofnode_to_offset(node); 2621 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2622 value = fdt_getprop_by_offset(blob, property_offset, 2623 &prop_name, &prop_len); 2624 if (!value) 2625 return -ENOENT; 2626 #endif 2627 param = rockchip_pinconf_prop_name_to_param(prop_name, 2628 &default_val); 2629 if (param < 0) 2630 break; 2631 2632 if (prop_len >= sizeof(fdt32_t)) 2633 arg = fdt32_to_cpu(*(fdt32_t *)value); 2634 else 2635 arg = default_val; 2636 2637 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2638 param, arg); 2639 if (ret) { 2640 debug("%s: rockchip_pinconf_set fail: %d\n", 2641 __func__, ret); 2642 return ret; 2643 } 2644 } 2645 } 2646 2647 return 0; 2648 } 2649 2650 static struct pinctrl_ops rockchip_pinctrl_ops = { 2651 .set_state = rockchip_pinctrl_set_state, 2652 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2653 }; 2654 2655 /* Ctrl data specially handle */ 2656 static int rk3308b_ctrl_data_re_init(struct rockchip_pin_ctrl *ctrl) 2657 { 2658 /* 2659 * Special for rk3308b, where we need to replace the recalced 2660 * and routed arrays. 2661 */ 2662 if (soc_is_rk3308b()) { 2663 ctrl->iomux_recalced = rk3308b_mux_recalced_data; 2664 ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data); 2665 ctrl->iomux_routes = rk3308b_mux_route_data; 2666 ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data); 2667 } 2668 2669 return 0; 2670 } 2671 2672 /* retrieve the soc specific data */ 2673 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 2674 { 2675 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2676 struct rockchip_pin_ctrl *ctrl = 2677 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 2678 struct rockchip_pin_bank *bank; 2679 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2680 2681 grf_offs = ctrl->grf_mux_offset; 2682 pmu_offs = ctrl->pmu_mux_offset; 2683 drv_pmu_offs = ctrl->pmu_drv_offset; 2684 drv_grf_offs = ctrl->grf_drv_offset; 2685 bank = ctrl->pin_banks; 2686 2687 /* Ctrl data re-initialize for some Socs */ 2688 if (ctrl->ctrl_data_re_init) { 2689 if (ctrl->ctrl_data_re_init(ctrl)) 2690 return NULL; 2691 } 2692 2693 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2694 int bank_pins = 0; 2695 2696 bank->priv = priv; 2697 bank->pin_base = ctrl->nr_pins; 2698 ctrl->nr_pins += bank->nr_pins; 2699 2700 /* calculate iomux and drv offsets */ 2701 for (j = 0; j < 4; j++) { 2702 struct rockchip_iomux *iom = &bank->iomux[j]; 2703 struct rockchip_drv *drv = &bank->drv[j]; 2704 int inc; 2705 2706 if (bank_pins >= bank->nr_pins) 2707 break; 2708 2709 /* preset iomux offset value, set new start value */ 2710 if (iom->offset >= 0) { 2711 if (iom->type & IOMUX_SOURCE_PMU) 2712 pmu_offs = iom->offset; 2713 else 2714 grf_offs = iom->offset; 2715 } else { /* set current iomux offset */ 2716 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2717 pmu_offs : grf_offs; 2718 } 2719 2720 /* preset drv offset value, set new start value */ 2721 if (drv->offset >= 0) { 2722 if (iom->type & IOMUX_SOURCE_PMU) 2723 drv_pmu_offs = drv->offset; 2724 else 2725 drv_grf_offs = drv->offset; 2726 } else { /* set current drv offset */ 2727 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2728 drv_pmu_offs : drv_grf_offs; 2729 } 2730 2731 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2732 i, j, iom->offset, drv->offset); 2733 2734 /* 2735 * Increase offset according to iomux width. 2736 * 4bit iomux'es are spread over two registers. 2737 */ 2738 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2739 IOMUX_WIDTH_3BIT | 2740 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 2741 if (iom->type & IOMUX_SOURCE_PMU) 2742 pmu_offs += inc; 2743 else 2744 grf_offs += inc; 2745 2746 /* 2747 * Increase offset according to drv width. 2748 * 3bit drive-strenth'es are spread over two registers. 2749 */ 2750 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2751 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2752 inc = 8; 2753 else 2754 inc = 4; 2755 2756 if (iom->type & IOMUX_SOURCE_PMU) 2757 drv_pmu_offs += inc; 2758 else 2759 drv_grf_offs += inc; 2760 2761 bank_pins += 8; 2762 } 2763 2764 /* calculate the per-bank recalced_mask */ 2765 for (j = 0; j < ctrl->niomux_recalced; j++) { 2766 int pin = 0; 2767 2768 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2769 pin = ctrl->iomux_recalced[j].pin; 2770 bank->recalced_mask |= BIT(pin); 2771 } 2772 } 2773 2774 /* calculate the per-bank route_mask */ 2775 for (j = 0; j < ctrl->niomux_routes; j++) { 2776 int pin = 0; 2777 2778 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2779 pin = ctrl->iomux_routes[j].pin; 2780 bank->route_mask |= BIT(pin); 2781 } 2782 } 2783 } 2784 2785 return ctrl; 2786 } 2787 2788 /* SoC data specially handle */ 2789 2790 /* rk3308b SoC data initialize */ 2791 #define RK3308B_GRF_SOC_CON13 0x608 2792 #define RK3308B_GRF_SOC_CON15 0x610 2793 2794 /* RK3308B_GRF_SOC_CON13 */ 2795 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) 2796 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 2797 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 2798 2799 /* RK3308B_GRF_SOC_CON15 */ 2800 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) 2801 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 2802 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 2803 2804 static int rk3308b_soc_data_init(struct rockchip_pinctrl_priv *priv) 2805 { 2806 int ret; 2807 2808 /* 2809 * Enable the special ctrl of selected sources. 2810 */ 2811 if (soc_is_rk3308b()) { 2812 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13, 2813 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | 2814 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | 2815 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); 2816 if (ret) 2817 return ret; 2818 2819 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15, 2820 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | 2821 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | 2822 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); 2823 if (ret) 2824 return ret; 2825 } 2826 2827 return 0; 2828 } 2829 2830 static int rockchip_pinctrl_probe(struct udevice *dev) 2831 { 2832 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2833 struct rockchip_pin_ctrl *ctrl; 2834 struct udevice *syscon; 2835 struct regmap *regmap; 2836 int ret = 0; 2837 2838 /* get rockchip grf syscon phandle */ 2839 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2840 &syscon); 2841 if (ret) { 2842 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 2843 return ret; 2844 } 2845 2846 /* get grf-reg base address */ 2847 regmap = syscon_get_regmap(syscon); 2848 if (!regmap) { 2849 debug("unable to find rockchip grf regmap\n"); 2850 return -ENODEV; 2851 } 2852 priv->regmap_base = regmap; 2853 2854 /* option: get pmu-reg base address */ 2855 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 2856 &syscon); 2857 if (!ret) { 2858 /* get pmugrf-reg base address */ 2859 regmap = syscon_get_regmap(syscon); 2860 if (!regmap) { 2861 debug("unable to find rockchip pmu regmap\n"); 2862 return -ENODEV; 2863 } 2864 priv->regmap_pmu = regmap; 2865 } 2866 2867 ctrl = rockchip_pinctrl_get_soc_data(dev); 2868 if (!ctrl) { 2869 debug("driver data not available\n"); 2870 return -EINVAL; 2871 } 2872 2873 /* Special handle for some Socs */ 2874 if (ctrl->soc_data_init) { 2875 ret = ctrl->soc_data_init(priv); 2876 if (ret) 2877 return ret; 2878 } 2879 2880 priv->ctrl = ctrl; 2881 return 0; 2882 } 2883 2884 static struct rockchip_pin_bank px30_pin_banks[] = { 2885 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2886 IOMUX_SOURCE_PMU, 2887 IOMUX_SOURCE_PMU, 2888 IOMUX_SOURCE_PMU 2889 ), 2890 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2891 IOMUX_WIDTH_4BIT, 2892 IOMUX_WIDTH_4BIT, 2893 IOMUX_WIDTH_4BIT 2894 ), 2895 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2896 IOMUX_WIDTH_4BIT, 2897 IOMUX_WIDTH_4BIT, 2898 IOMUX_WIDTH_4BIT 2899 ), 2900 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2901 IOMUX_WIDTH_4BIT, 2902 IOMUX_WIDTH_4BIT, 2903 IOMUX_WIDTH_4BIT 2904 ), 2905 }; 2906 2907 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2908 .pin_banks = px30_pin_banks, 2909 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2910 .label = "PX30-GPIO", 2911 .type = PX30, 2912 .grf_mux_offset = 0x0, 2913 .pmu_mux_offset = 0x0, 2914 .iomux_routes = px30_mux_route_data, 2915 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2916 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2917 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2918 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2919 .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit, 2920 }; 2921 2922 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2923 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2924 IOMUX_SOURCE_PMU, 2925 IOMUX_SOURCE_PMU, 2926 IOMUX_SOURCE_PMU), 2927 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2928 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2929 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2930 }; 2931 2932 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2933 .pin_banks = rv1108_pin_banks, 2934 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2935 .label = "RV1108-GPIO", 2936 .type = RV1108, 2937 .grf_mux_offset = 0x10, 2938 .pmu_mux_offset = 0x0, 2939 .iomux_recalced = rv1108_mux_recalced_data, 2940 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2941 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2942 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2943 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2944 }; 2945 2946 static struct rockchip_pin_bank rk1808_pin_banks[] = { 2947 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 2948 IOMUX_SOURCE_PMU, 2949 IOMUX_SOURCE_PMU, 2950 IOMUX_SOURCE_PMU, 2951 IOMUX_SOURCE_PMU), 2952 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 2953 IOMUX_WIDTH_4BIT, 2954 IOMUX_WIDTH_4BIT, 2955 IOMUX_WIDTH_4BIT, 2956 IOMUX_WIDTH_4BIT), 2957 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 2958 IOMUX_WIDTH_4BIT, 2959 IOMUX_WIDTH_4BIT, 2960 IOMUX_WIDTH_4BIT, 2961 IOMUX_WIDTH_4BIT), 2962 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2963 IOMUX_WIDTH_4BIT, 2964 IOMUX_WIDTH_4BIT, 2965 IOMUX_WIDTH_4BIT, 2966 IOMUX_WIDTH_4BIT), 2967 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", 2968 IOMUX_WIDTH_4BIT, 2969 IOMUX_WIDTH_4BIT, 2970 IOMUX_WIDTH_4BIT, 2971 IOMUX_WIDTH_4BIT), 2972 }; 2973 2974 static struct rockchip_pin_ctrl rk1808_pin_ctrl = { 2975 .pin_banks = rk1808_pin_banks, 2976 .nr_banks = ARRAY_SIZE(rk1808_pin_banks), 2977 .label = "RK1808-GPIO", 2978 .type = RK1808, 2979 .iomux_routes = rk1808_mux_route_data, 2980 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data), 2981 .grf_mux_offset = 0x0, 2982 .pmu_mux_offset = 0x0, 2983 .pull_calc_reg = rk1808_calc_pull_reg_and_bit, 2984 .drv_calc_reg = rk1808_calc_drv_reg_and_bit, 2985 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit, 2986 }; 2987 2988 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2989 PIN_BANK(0, 32, "gpio0"), 2990 PIN_BANK(1, 32, "gpio1"), 2991 PIN_BANK(2, 32, "gpio2"), 2992 PIN_BANK(3, 32, "gpio3"), 2993 }; 2994 2995 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2996 .pin_banks = rk2928_pin_banks, 2997 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2998 .label = "RK2928-GPIO", 2999 .type = RK2928, 3000 .grf_mux_offset = 0xa8, 3001 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3002 }; 3003 3004 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3005 PIN_BANK(0, 32, "gpio0"), 3006 PIN_BANK(1, 32, "gpio1"), 3007 PIN_BANK(2, 32, "gpio2"), 3008 }; 3009 3010 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3011 .pin_banks = rk3036_pin_banks, 3012 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3013 .label = "RK3036-GPIO", 3014 .type = RK2928, 3015 .grf_mux_offset = 0xa8, 3016 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3017 }; 3018 3019 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3020 PIN_BANK(0, 32, "gpio0"), 3021 PIN_BANK(1, 32, "gpio1"), 3022 PIN_BANK(2, 32, "gpio2"), 3023 PIN_BANK(3, 32, "gpio3"), 3024 PIN_BANK(4, 32, "gpio4"), 3025 PIN_BANK(6, 16, "gpio6"), 3026 }; 3027 3028 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3029 .pin_banks = rk3066a_pin_banks, 3030 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3031 .label = "RK3066a-GPIO", 3032 .type = RK2928, 3033 .grf_mux_offset = 0xa8, 3034 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3035 }; 3036 3037 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3038 PIN_BANK(0, 32, "gpio0"), 3039 PIN_BANK(1, 32, "gpio1"), 3040 PIN_BANK(2, 32, "gpio2"), 3041 PIN_BANK(3, 32, "gpio3"), 3042 }; 3043 3044 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3045 .pin_banks = rk3066b_pin_banks, 3046 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3047 .label = "RK3066b-GPIO", 3048 .type = RK3066B, 3049 .grf_mux_offset = 0x60, 3050 }; 3051 3052 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3053 PIN_BANK(0, 32, "gpio0"), 3054 PIN_BANK(1, 32, "gpio1"), 3055 PIN_BANK(2, 32, "gpio2"), 3056 PIN_BANK(3, 32, "gpio3"), 3057 }; 3058 3059 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3060 .pin_banks = rk3128_pin_banks, 3061 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3062 .label = "RK3128-GPIO", 3063 .type = RK3128, 3064 .grf_mux_offset = 0xa8, 3065 .iomux_recalced = rk3128_mux_recalced_data, 3066 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3067 .iomux_routes = rk3128_mux_route_data, 3068 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3069 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3070 }; 3071 3072 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3073 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3074 PIN_BANK(1, 32, "gpio1"), 3075 PIN_BANK(2, 32, "gpio2"), 3076 PIN_BANK(3, 32, "gpio3"), 3077 }; 3078 3079 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3080 .pin_banks = rk3188_pin_banks, 3081 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3082 .label = "RK3188-GPIO", 3083 .type = RK3188, 3084 .grf_mux_offset = 0x60, 3085 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3086 }; 3087 3088 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3089 PIN_BANK(0, 32, "gpio0"), 3090 PIN_BANK(1, 32, "gpio1"), 3091 PIN_BANK(2, 32, "gpio2"), 3092 PIN_BANK(3, 32, "gpio3"), 3093 }; 3094 3095 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3096 .pin_banks = rk3228_pin_banks, 3097 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3098 .label = "RK3228-GPIO", 3099 .type = RK3288, 3100 .grf_mux_offset = 0x0, 3101 .iomux_routes = rk3228_mux_route_data, 3102 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3103 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3104 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3105 }; 3106 3107 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3108 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 3109 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3110 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3111 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3112 IOMUX_UNROUTED, 3113 DRV_TYPE_WRITABLE_32BIT, 3114 DRV_TYPE_WRITABLE_32BIT, 3115 DRV_TYPE_WRITABLE_32BIT, 3116 0, 3117 PULL_TYPE_WRITABLE_32BIT, 3118 PULL_TYPE_WRITABLE_32BIT, 3119 PULL_TYPE_WRITABLE_32BIT, 3120 0 3121 ), 3122 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3123 IOMUX_UNROUTED, 3124 IOMUX_UNROUTED, 3125 0 3126 ), 3127 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3128 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3129 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3130 IOMUX_WIDTH_4BIT, 3131 0, 3132 0 3133 ), 3134 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3135 0, 3136 0, 3137 IOMUX_UNROUTED 3138 ), 3139 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3140 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3141 0, 3142 IOMUX_WIDTH_4BIT, 3143 IOMUX_UNROUTED 3144 ), 3145 PIN_BANK(8, 16, "gpio8"), 3146 }; 3147 3148 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3149 .pin_banks = rk3288_pin_banks, 3150 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3151 .label = "RK3288-GPIO", 3152 .type = RK3288, 3153 .grf_mux_offset = 0x0, 3154 .pmu_mux_offset = 0x84, 3155 .iomux_routes = rk3288_mux_route_data, 3156 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3157 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3158 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3159 }; 3160 3161 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3162 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 3163 IOMUX_8WIDTH_2BIT, 3164 IOMUX_8WIDTH_2BIT, 3165 IOMUX_8WIDTH_2BIT), 3166 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 3167 IOMUX_8WIDTH_2BIT, 3168 IOMUX_8WIDTH_2BIT, 3169 IOMUX_8WIDTH_2BIT), 3170 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 3171 IOMUX_8WIDTH_2BIT, 3172 IOMUX_8WIDTH_2BIT, 3173 IOMUX_8WIDTH_2BIT), 3174 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 3175 IOMUX_8WIDTH_2BIT, 3176 IOMUX_8WIDTH_2BIT, 3177 IOMUX_8WIDTH_2BIT), 3178 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 3179 IOMUX_8WIDTH_2BIT, 3180 IOMUX_8WIDTH_2BIT, 3181 IOMUX_8WIDTH_2BIT), 3182 }; 3183 3184 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3185 .pin_banks = rk3308_pin_banks, 3186 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3187 .label = "RK3308-GPIO", 3188 .type = RK3308, 3189 .grf_mux_offset = 0x0, 3190 .iomux_recalced = rk3308_mux_recalced_data, 3191 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3192 .iomux_routes = rk3308_mux_route_data, 3193 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3194 .ctrl_data_re_init = rk3308b_ctrl_data_re_init, 3195 .soc_data_init = rk3308b_soc_data_init, 3196 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3197 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3198 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3199 }; 3200 3201 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3202 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3203 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3204 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3205 IOMUX_WIDTH_3BIT, 3206 IOMUX_WIDTH_3BIT, 3207 0), 3208 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3209 IOMUX_WIDTH_3BIT, 3210 IOMUX_WIDTH_3BIT, 3211 0, 3212 0), 3213 }; 3214 3215 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3216 .pin_banks = rk3328_pin_banks, 3217 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3218 .label = "RK3328-GPIO", 3219 .type = RK3288, 3220 .grf_mux_offset = 0x0, 3221 .iomux_recalced = rk3328_mux_recalced_data, 3222 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3223 .iomux_routes = rk3328_mux_route_data, 3224 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3225 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3226 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3227 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3228 }; 3229 3230 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3231 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3232 IOMUX_SOURCE_PMU, 3233 IOMUX_SOURCE_PMU, 3234 IOMUX_SOURCE_PMU 3235 ), 3236 PIN_BANK(1, 32, "gpio1"), 3237 PIN_BANK(2, 32, "gpio2"), 3238 PIN_BANK(3, 32, "gpio3"), 3239 }; 3240 3241 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3242 .pin_banks = rk3368_pin_banks, 3243 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3244 .label = "RK3368-GPIO", 3245 .type = RK3368, 3246 .grf_mux_offset = 0x0, 3247 .pmu_mux_offset = 0x0, 3248 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3249 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3250 }; 3251 3252 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3253 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3254 IOMUX_SOURCE_PMU, 3255 IOMUX_SOURCE_PMU, 3256 IOMUX_SOURCE_PMU, 3257 IOMUX_SOURCE_PMU, 3258 DRV_TYPE_IO_1V8_ONLY, 3259 DRV_TYPE_IO_1V8_ONLY, 3260 DRV_TYPE_IO_DEFAULT, 3261 DRV_TYPE_IO_DEFAULT, 3262 0x80, 3263 0x88, 3264 -1, 3265 -1, 3266 PULL_TYPE_IO_1V8_ONLY, 3267 PULL_TYPE_IO_1V8_ONLY, 3268 PULL_TYPE_IO_DEFAULT, 3269 PULL_TYPE_IO_DEFAULT 3270 ), 3271 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3272 IOMUX_SOURCE_PMU, 3273 IOMUX_SOURCE_PMU, 3274 IOMUX_SOURCE_PMU, 3275 DRV_TYPE_IO_1V8_OR_3V0, 3276 DRV_TYPE_IO_1V8_OR_3V0, 3277 DRV_TYPE_IO_1V8_OR_3V0, 3278 DRV_TYPE_IO_1V8_OR_3V0, 3279 0xa0, 3280 0xa8, 3281 0xb0, 3282 0xb8 3283 ), 3284 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3285 DRV_TYPE_IO_1V8_OR_3V0, 3286 DRV_TYPE_IO_1V8_ONLY, 3287 DRV_TYPE_IO_1V8_ONLY, 3288 PULL_TYPE_IO_DEFAULT, 3289 PULL_TYPE_IO_DEFAULT, 3290 PULL_TYPE_IO_1V8_ONLY, 3291 PULL_TYPE_IO_1V8_ONLY 3292 ), 3293 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3294 DRV_TYPE_IO_3V3_ONLY, 3295 DRV_TYPE_IO_3V3_ONLY, 3296 DRV_TYPE_IO_1V8_OR_3V0 3297 ), 3298 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3299 DRV_TYPE_IO_1V8_3V0_AUTO, 3300 DRV_TYPE_IO_1V8_OR_3V0, 3301 DRV_TYPE_IO_1V8_OR_3V0 3302 ), 3303 }; 3304 3305 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3306 .pin_banks = rk3399_pin_banks, 3307 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3308 .label = "RK3399-GPIO", 3309 .type = RK3399, 3310 .grf_mux_offset = 0xe000, 3311 .pmu_mux_offset = 0x0, 3312 .grf_drv_offset = 0xe100, 3313 .pmu_drv_offset = 0x80, 3314 .iomux_routes = rk3399_mux_route_data, 3315 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3316 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3317 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3318 }; 3319 3320 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 3321 { .compatible = "rockchip,px30-pinctrl", 3322 .data = (ulong)&px30_pin_ctrl }, 3323 { .compatible = "rockchip,rv1108-pinctrl", 3324 .data = (ulong)&rv1108_pin_ctrl }, 3325 { .compatible = "rockchip,rk1808-pinctrl", 3326 .data = (ulong)&rk1808_pin_ctrl }, 3327 { .compatible = "rockchip,rk2928-pinctrl", 3328 .data = (ulong)&rk2928_pin_ctrl }, 3329 { .compatible = "rockchip,rk3036-pinctrl", 3330 .data = (ulong)&rk3036_pin_ctrl }, 3331 { .compatible = "rockchip,rk3066a-pinctrl", 3332 .data = (ulong)&rk3066a_pin_ctrl }, 3333 { .compatible = "rockchip,rk3066b-pinctrl", 3334 .data = (ulong)&rk3066b_pin_ctrl }, 3335 { .compatible = "rockchip,rk3128-pinctrl", 3336 .data = (ulong)&rk3128_pin_ctrl }, 3337 { .compatible = "rockchip,rk3188-pinctrl", 3338 .data = (ulong)&rk3188_pin_ctrl }, 3339 { .compatible = "rockchip,rk3228-pinctrl", 3340 .data = (ulong)&rk3228_pin_ctrl }, 3341 { .compatible = "rockchip,rk3288-pinctrl", 3342 .data = (ulong)&rk3288_pin_ctrl }, 3343 { .compatible = "rockchip,rk3308-pinctrl", 3344 .data = (ulong)&rk3308_pin_ctrl }, 3345 { .compatible = "rockchip,rk3328-pinctrl", 3346 .data = (ulong)&rk3328_pin_ctrl }, 3347 { .compatible = "rockchip,rk3368-pinctrl", 3348 .data = (ulong)&rk3368_pin_ctrl }, 3349 { .compatible = "rockchip,rk3399-pinctrl", 3350 .data = (ulong)&rk3399_pin_ctrl }, 3351 {}, 3352 }; 3353 3354 U_BOOT_DRIVER(pinctrl_rockchip) = { 3355 .name = "rockchip_pinctrl", 3356 .id = UCLASS_PINCTRL, 3357 .of_match = rockchip_pinctrl_dt_match, 3358 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 3359 .ops = &rockchip_pinctrl_ops, 3360 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 3361 .bind = dm_scan_fdt_dev, 3362 #endif 3363 .probe = rockchip_pinctrl_probe, 3364 }; 3365