1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 #include <asm/arch/cpu.h> 14 15 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 16 #define RK_FUNC_GPIO 0 17 #define MAX_ROCKCHIP_PINS_ENTRIES 30 18 19 enum rockchip_pinctrl_type { 20 PX30, 21 RV1108, 22 RK1808, 23 RK2928, 24 RK3066B, 25 RK3128, 26 RK3188, 27 RK3288, 28 RK3308, 29 RK3368, 30 RK3399, 31 }; 32 33 /** 34 * Encode variants of iomux registers into a type variable 35 */ 36 #define IOMUX_GPIO_ONLY BIT(0) 37 #define IOMUX_WIDTH_4BIT BIT(1) 38 #define IOMUX_SOURCE_PMU BIT(2) 39 #define IOMUX_UNROUTED BIT(3) 40 #define IOMUX_WIDTH_3BIT BIT(4) 41 #define IOMUX_8WIDTH_2BIT BIT(5) 42 #define IOMUX_WRITABLE_32BIT BIT(6) 43 44 /** 45 * @type: iomux variant using IOMUX_* constants 46 * @offset: if initialized to -1 it will be autocalculated, by specifying 47 * an initial offset value the relevant source offset can be reset 48 * to a new value for autocalculating the following iomux registers. 49 */ 50 struct rockchip_iomux { 51 int type; 52 int offset; 53 }; 54 55 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 56 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 57 58 /** 59 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 60 */ 61 enum rockchip_pin_drv_type { 62 DRV_TYPE_IO_DEFAULT = 0, 63 DRV_TYPE_IO_1V8_OR_3V0, 64 DRV_TYPE_IO_1V8_ONLY, 65 DRV_TYPE_IO_1V8_3V0_AUTO, 66 DRV_TYPE_IO_3V3_ONLY, 67 DRV_TYPE_MAX 68 }; 69 70 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 71 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 72 73 /** 74 * enum type index corresponding to rockchip_pull_list arrays index. 75 */ 76 enum rockchip_pin_pull_type { 77 PULL_TYPE_IO_DEFAULT = 0, 78 PULL_TYPE_IO_1V8_ONLY, 79 PULL_TYPE_MAX 80 }; 81 82 /** 83 * enum mux route register type, should be invalid/default/topgrf/pmugrf. 84 * INVALID: means do not need to set mux route 85 * DEFAULT: means same regmap as pin iomux 86 * TOPGRF: means mux route setting in topgrf 87 * PMUGRF: means mux route setting in pmugrf 88 */ 89 enum rockchip_pin_route_type { 90 ROUTE_TYPE_DEFAULT = 0, 91 ROUTE_TYPE_TOPGRF = 1, 92 ROUTE_TYPE_PMUGRF = 2, 93 94 ROUTE_TYPE_INVALID = -1, 95 }; 96 /** 97 * @drv_type: drive strength variant using rockchip_perpin_drv_type 98 * @offset: if initialized to -1 it will be autocalculated, by specifying 99 * an initial offset value the relevant source offset can be reset 100 * to a new value for autocalculating the following drive strength 101 * registers. if used chips own cal_drv func instead to calculate 102 * registers offset, the variant could be ignored. 103 */ 104 struct rockchip_drv { 105 enum rockchip_pin_drv_type drv_type; 106 int offset; 107 }; 108 109 /** 110 * @priv: common pinctrl private basedata 111 * @pin_base: first pin number 112 * @nr_pins: number of pins in this bank 113 * @name: name of the bank 114 * @bank_num: number of the bank, to account for holes 115 * @iomux: array describing the 4 iomux sources of the bank 116 * @drv: array describing the 4 drive strength sources of the bank 117 * @pull_type: array describing the 4 pull type sources of the bank 118 * @recalced_mask: bits describing the mux recalced pins of per bank 119 * @route_mask: bits describing the routing pins of per bank 120 */ 121 struct rockchip_pin_bank { 122 struct rockchip_pinctrl_priv *priv; 123 u32 pin_base; 124 u8 nr_pins; 125 char *name; 126 u8 bank_num; 127 struct rockchip_iomux iomux[4]; 128 struct rockchip_drv drv[4]; 129 enum rockchip_pin_pull_type pull_type[4]; 130 u32 recalced_mask; 131 u32 route_mask; 132 }; 133 134 #define PIN_BANK(id, pins, label) \ 135 { \ 136 .bank_num = id, \ 137 .nr_pins = pins, \ 138 .name = label, \ 139 .iomux = { \ 140 { .offset = -1 }, \ 141 { .offset = -1 }, \ 142 { .offset = -1 }, \ 143 { .offset = -1 }, \ 144 }, \ 145 } 146 147 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 148 { \ 149 .bank_num = id, \ 150 .nr_pins = pins, \ 151 .name = label, \ 152 .iomux = { \ 153 { .type = iom0, .offset = -1 }, \ 154 { .type = iom1, .offset = -1 }, \ 155 { .type = iom2, .offset = -1 }, \ 156 { .type = iom3, .offset = -1 }, \ 157 }, \ 158 } 159 160 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 161 { \ 162 .bank_num = id, \ 163 .nr_pins = pins, \ 164 .name = label, \ 165 .iomux = { \ 166 { .offset = -1 }, \ 167 { .offset = -1 }, \ 168 { .offset = -1 }, \ 169 { .offset = -1 }, \ 170 }, \ 171 .drv = { \ 172 { .drv_type = type0, .offset = -1 }, \ 173 { .drv_type = type1, .offset = -1 }, \ 174 { .drv_type = type2, .offset = -1 }, \ 175 { .drv_type = type3, .offset = -1 }, \ 176 }, \ 177 } 178 179 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 180 drv2, drv3, pull0, pull1, \ 181 pull2, pull3) \ 182 { \ 183 .bank_num = id, \ 184 .nr_pins = pins, \ 185 .name = label, \ 186 .iomux = { \ 187 { .offset = -1 }, \ 188 { .offset = -1 }, \ 189 { .offset = -1 }, \ 190 { .offset = -1 }, \ 191 }, \ 192 .drv = { \ 193 { .drv_type = drv0, .offset = -1 }, \ 194 { .drv_type = drv1, .offset = -1 }, \ 195 { .drv_type = drv2, .offset = -1 }, \ 196 { .drv_type = drv3, .offset = -1 }, \ 197 }, \ 198 .pull_type[0] = pull0, \ 199 .pull_type[1] = pull1, \ 200 .pull_type[2] = pull2, \ 201 .pull_type[3] = pull3, \ 202 } 203 204 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 205 iom2, iom3, drv0, drv1, drv2, \ 206 drv3, offset0, offset1, \ 207 offset2, offset3) \ 208 { \ 209 .bank_num = id, \ 210 .nr_pins = pins, \ 211 .name = label, \ 212 .iomux = { \ 213 { .type = iom0, .offset = -1 }, \ 214 { .type = iom1, .offset = -1 }, \ 215 { .type = iom2, .offset = -1 }, \ 216 { .type = iom3, .offset = -1 }, \ 217 }, \ 218 .drv = { \ 219 { .drv_type = drv0, .offset = offset0 }, \ 220 { .drv_type = drv1, .offset = offset1 }, \ 221 { .drv_type = drv2, .offset = offset2 }, \ 222 { .drv_type = drv3, .offset = offset3 }, \ 223 }, \ 224 } 225 226 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 227 iom2, iom3, drv0, drv1, drv2, \ 228 drv3, pull0, pull1, pull2, \ 229 pull3) \ 230 { \ 231 .bank_num = id, \ 232 .nr_pins = pins, \ 233 .name = label, \ 234 .iomux = { \ 235 { .type = iom0, .offset = -1 }, \ 236 { .type = iom1, .offset = -1 }, \ 237 { .type = iom2, .offset = -1 }, \ 238 { .type = iom3, .offset = -1 }, \ 239 }, \ 240 .drv = { \ 241 { .drv_type = drv0, .offset = -1 }, \ 242 { .drv_type = drv1, .offset = -1 }, \ 243 { .drv_type = drv2, .offset = -1 }, \ 244 { .drv_type = drv3, .offset = -1 }, \ 245 }, \ 246 .pull_type[0] = pull0, \ 247 .pull_type[1] = pull1, \ 248 .pull_type[2] = pull2, \ 249 .pull_type[3] = pull3, \ 250 } 251 252 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 253 label, iom0, iom1, iom2, \ 254 iom3, drv0, drv1, drv2, \ 255 drv3, offset0, offset1, \ 256 offset2, offset3, pull0, \ 257 pull1, pull2, pull3) \ 258 { \ 259 .bank_num = id, \ 260 .nr_pins = pins, \ 261 .name = label, \ 262 .iomux = { \ 263 { .type = iom0, .offset = -1 }, \ 264 { .type = iom1, .offset = -1 }, \ 265 { .type = iom2, .offset = -1 }, \ 266 { .type = iom3, .offset = -1 }, \ 267 }, \ 268 .drv = { \ 269 { .drv_type = drv0, .offset = offset0 }, \ 270 { .drv_type = drv1, .offset = offset1 }, \ 271 { .drv_type = drv2, .offset = offset2 }, \ 272 { .drv_type = drv3, .offset = offset3 }, \ 273 }, \ 274 .pull_type[0] = pull0, \ 275 .pull_type[1] = pull1, \ 276 .pull_type[2] = pull2, \ 277 .pull_type[3] = pull3, \ 278 } 279 280 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 281 { \ 282 .bank_num = ID, \ 283 .pin = PIN, \ 284 .func = FUNC, \ 285 .route_offset = REG, \ 286 .route_val = VAL, \ 287 .route_type = FLAG, \ 288 } 289 290 #define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ 291 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT) 292 293 #define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ 294 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF) 295 296 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ 297 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF) 298 299 /** 300 * struct rockchip_mux_recalced_data: represent a pin iomux data. 301 * @num: bank number. 302 * @pin: pin number. 303 * @bit: index at register. 304 * @reg: register offset. 305 * @mask: mask bit 306 */ 307 struct rockchip_mux_recalced_data { 308 u8 num; 309 u8 pin; 310 u32 reg; 311 u8 bit; 312 u8 mask; 313 }; 314 315 /** 316 * struct rockchip_mux_recalced_data: represent a pin iomux data. 317 * @bank_num: bank number. 318 * @pin: index at register or used to calc index. 319 * @func: the min pin. 320 * @route_type: mux route setting in grf or pmugrf. 321 * @route_offset: the max pin. 322 * @route_val: the register offset. 323 */ 324 struct rockchip_mux_route_data { 325 u8 bank_num; 326 u8 pin; 327 u8 func; 328 enum rockchip_pin_route_type route_type : 8; 329 u32 route_offset; 330 u32 route_val; 331 }; 332 333 /** 334 */ 335 struct rockchip_pin_ctrl { 336 struct rockchip_pin_bank *pin_banks; 337 u32 nr_banks; 338 u32 nr_pins; 339 char *label; 340 enum rockchip_pinctrl_type type; 341 int grf_mux_offset; 342 int pmu_mux_offset; 343 int grf_drv_offset; 344 int pmu_drv_offset; 345 struct rockchip_mux_recalced_data *iomux_recalced; 346 u32 niomux_recalced; 347 struct rockchip_mux_route_data *iomux_routes; 348 u32 niomux_routes; 349 350 int (*ctrl_data_re_init)(struct rockchip_pin_ctrl *ctrl); 351 352 int (*soc_data_init)(struct rockchip_pinctrl_priv *info); 353 354 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 355 int pin_num, struct regmap **regmap, 356 int *reg, u8 *bit); 357 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 358 int pin_num, struct regmap **regmap, 359 int *reg, u8 *bit); 360 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 361 int pin_num, struct regmap **regmap, 362 int *reg, u8 *bit); 363 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank, 364 int pin_num, struct regmap **regmap, 365 int *reg, u8 *bit); 366 }; 367 368 /** 369 */ 370 struct rockchip_pinctrl_priv { 371 struct rockchip_pin_ctrl *ctrl; 372 struct regmap *regmap_base; 373 struct regmap *regmap_pmu; 374 375 }; 376 377 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 378 { 379 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 380 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 381 382 if (bank >= ctrl->nr_banks) { 383 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 384 return -EINVAL; 385 } 386 387 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 388 debug("pin conf pin %d >= %d\n", pin, 389 MAX_ROCKCHIP_GPIO_PER_BANK); 390 return -EINVAL; 391 } 392 393 return 0; 394 } 395 396 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 397 { 398 .num = 1, 399 .pin = 0, 400 .reg = 0x418, 401 .bit = 0, 402 .mask = 0x3 403 }, { 404 .num = 1, 405 .pin = 1, 406 .reg = 0x418, 407 .bit = 2, 408 .mask = 0x3 409 }, { 410 .num = 1, 411 .pin = 2, 412 .reg = 0x418, 413 .bit = 4, 414 .mask = 0x3 415 }, { 416 .num = 1, 417 .pin = 3, 418 .reg = 0x418, 419 .bit = 6, 420 .mask = 0x3 421 }, { 422 .num = 1, 423 .pin = 4, 424 .reg = 0x418, 425 .bit = 8, 426 .mask = 0x3 427 }, { 428 .num = 1, 429 .pin = 5, 430 .reg = 0x418, 431 .bit = 10, 432 .mask = 0x3 433 }, { 434 .num = 1, 435 .pin = 6, 436 .reg = 0x418, 437 .bit = 12, 438 .mask = 0x3 439 }, { 440 .num = 1, 441 .pin = 7, 442 .reg = 0x418, 443 .bit = 14, 444 .mask = 0x3 445 }, { 446 .num = 1, 447 .pin = 8, 448 .reg = 0x41c, 449 .bit = 0, 450 .mask = 0x3 451 }, { 452 .num = 1, 453 .pin = 9, 454 .reg = 0x41c, 455 .bit = 2, 456 .mask = 0x3 457 }, 458 }; 459 460 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 461 { 462 .num = 2, 463 .pin = 20, 464 .reg = 0xe8, 465 .bit = 0, 466 .mask = 0x7 467 }, { 468 .num = 2, 469 .pin = 21, 470 .reg = 0xe8, 471 .bit = 4, 472 .mask = 0x7 473 }, { 474 .num = 2, 475 .pin = 22, 476 .reg = 0xe8, 477 .bit = 8, 478 .mask = 0x7 479 }, { 480 .num = 2, 481 .pin = 23, 482 .reg = 0xe8, 483 .bit = 12, 484 .mask = 0x7 485 }, { 486 .num = 2, 487 .pin = 24, 488 .reg = 0xd4, 489 .bit = 12, 490 .mask = 0x7 491 }, 492 }; 493 494 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 495 { 496 .num = 1, 497 .pin = 14, 498 .reg = 0x28, 499 .bit = 12, 500 .mask = 0x7 501 }, { 502 .num = 1, 503 .pin = 15, 504 .reg = 0x2c, 505 .bit = 0, 506 .mask = 0x3 507 }, { 508 .num = 1, 509 .pin = 18, 510 .reg = 0x30, 511 .bit = 4, 512 .mask = 0x7 513 }, { 514 .num = 1, 515 .pin = 19, 516 .reg = 0x30, 517 .bit = 8, 518 .mask = 0x7 519 }, { 520 .num = 1, 521 .pin = 20, 522 .reg = 0x30, 523 .bit = 12, 524 .mask = 0x7 525 }, { 526 .num = 1, 527 .pin = 21, 528 .reg = 0x34, 529 .bit = 0, 530 .mask = 0x7 531 }, { 532 .num = 1, 533 .pin = 22, 534 .reg = 0x34, 535 .bit = 4, 536 .mask = 0x7 537 }, { 538 .num = 1, 539 .pin = 23, 540 .reg = 0x34, 541 .bit = 8, 542 .mask = 0x7 543 }, { 544 .num = 3, 545 .pin = 12, 546 .reg = 0x68, 547 .bit = 8, 548 .mask = 0x7 549 }, { 550 .num = 3, 551 .pin = 13, 552 .reg = 0x68, 553 .bit = 12, 554 .mask = 0x7 555 }, 556 }; 557 558 static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { 559 { 560 .num = 1, 561 .pin = 14, 562 .reg = 0x28, 563 .bit = 12, 564 .mask = 0xf 565 }, { 566 .num = 1, 567 .pin = 15, 568 .reg = 0x2c, 569 .bit = 0, 570 .mask = 0x3 571 }, { 572 .num = 1, 573 .pin = 18, 574 .reg = 0x30, 575 .bit = 4, 576 .mask = 0xf 577 }, { 578 .num = 1, 579 .pin = 19, 580 .reg = 0x30, 581 .bit = 8, 582 .mask = 0xf 583 }, { 584 .num = 1, 585 .pin = 20, 586 .reg = 0x30, 587 .bit = 12, 588 .mask = 0xf 589 }, { 590 .num = 1, 591 .pin = 21, 592 .reg = 0x34, 593 .bit = 0, 594 .mask = 0xf 595 }, { 596 .num = 1, 597 .pin = 22, 598 .reg = 0x34, 599 .bit = 4, 600 .mask = 0xf 601 }, { 602 .num = 1, 603 .pin = 23, 604 .reg = 0x34, 605 .bit = 8, 606 .mask = 0xf 607 }, { 608 .num = 3, 609 .pin = 12, 610 .reg = 0x68, 611 .bit = 8, 612 .mask = 0xf 613 }, { 614 .num = 3, 615 .pin = 13, 616 .reg = 0x68, 617 .bit = 12, 618 .mask = 0xf 619 }, { 620 .num = 2, 621 .pin = 2, 622 .reg = 0x608, 623 .bit = 0, 624 .mask = 0x7 625 }, { 626 .num = 2, 627 .pin = 3, 628 .reg = 0x608, 629 .bit = 4, 630 .mask = 0x7 631 }, { 632 .num = 2, 633 .pin = 16, 634 .reg = 0x610, 635 .bit = 8, 636 .mask = 0x7 637 }, { 638 .num = 3, 639 .pin = 10, 640 .reg = 0x610, 641 .bit = 0, 642 .mask = 0x7 643 }, { 644 .num = 3, 645 .pin = 11, 646 .reg = 0x610, 647 .bit = 4, 648 .mask = 0x7 649 }, 650 }; 651 652 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 653 { 654 .num = 2, 655 .pin = 12, 656 .reg = 0x24, 657 .bit = 8, 658 .mask = 0x3 659 }, { 660 .num = 2, 661 .pin = 15, 662 .reg = 0x28, 663 .bit = 0, 664 .mask = 0x7 665 }, { 666 .num = 2, 667 .pin = 23, 668 .reg = 0x30, 669 .bit = 14, 670 .mask = 0x3 671 }, 672 }; 673 674 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 675 int *reg, u8 *bit, int *mask) 676 { 677 struct rockchip_pinctrl_priv *priv = bank->priv; 678 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 679 struct rockchip_mux_recalced_data *data; 680 int i; 681 682 for (i = 0; i < ctrl->niomux_recalced; i++) { 683 data = &ctrl->iomux_recalced[i]; 684 if (data->num == bank->bank_num && 685 data->pin == pin) 686 break; 687 } 688 689 if (i >= ctrl->niomux_recalced) 690 return; 691 692 *reg = data->reg; 693 *mask = data->mask; 694 *bit = data->bit; 695 } 696 697 static struct rockchip_mux_route_data px30_mux_route_data[] = { 698 { 699 /* cif-d2m0 */ 700 .bank_num = 2, 701 .pin = 0, 702 .func = 1, 703 .route_offset = 0x184, 704 .route_val = BIT(16 + 7), 705 }, { 706 /* cif-d2m1 */ 707 .bank_num = 3, 708 .pin = 3, 709 .func = 3, 710 .route_offset = 0x184, 711 .route_val = BIT(16 + 7) | BIT(7), 712 }, { 713 /* pdm-m0 */ 714 .bank_num = 3, 715 .pin = 22, 716 .func = 2, 717 .route_offset = 0x184, 718 .route_val = BIT(16 + 8), 719 }, { 720 /* pdm-m1 */ 721 .bank_num = 2, 722 .pin = 22, 723 .func = 1, 724 .route_offset = 0x184, 725 .route_val = BIT(16 + 8) | BIT(8), 726 }, { 727 /* uart2-rxm0 */ 728 .bank_num = 1, 729 .pin = 27, 730 .func = 2, 731 .route_offset = 0x184, 732 .route_val = BIT(16 + 10), 733 }, { 734 /* uart2-rxm1 */ 735 .bank_num = 2, 736 .pin = 14, 737 .func = 2, 738 .route_offset = 0x184, 739 .route_val = BIT(16 + 10) | BIT(10), 740 }, { 741 /* uart3-rxm0 */ 742 .bank_num = 0, 743 .pin = 17, 744 .func = 2, 745 .route_offset = 0x184, 746 .route_val = BIT(16 + 9), 747 }, { 748 /* uart3-rxm1 */ 749 .bank_num = 1, 750 .pin = 15, 751 .func = 2, 752 .route_offset = 0x184, 753 .route_val = BIT(16 + 9) | BIT(9), 754 }, 755 }; 756 757 static struct rockchip_mux_route_data rk1808_mux_route_data[] = { 758 { 759 /* i2c2m0_sda */ 760 .bank_num = 3, 761 .pin = 12, 762 .func = 2, 763 .route_offset = 0x190, 764 .route_val = BIT(16 + 3), 765 }, { 766 /* i2c2m1_sda */ 767 .bank_num = 1, 768 .pin = 13, 769 .func = 2, 770 .route_offset = 0x190, 771 .route_val = BIT(16 + 3) | BIT(3), 772 }, { 773 /* uart2_rxm0 */ 774 .bank_num = 4, 775 .pin = 3, 776 .func = 2, 777 .route_offset = 0x190, 778 .route_val = BIT(16 + 14) | BIT(16 + 15), 779 }, { 780 /* uart2_rxm1 */ 781 .bank_num = 2, 782 .pin = 25, 783 .func = 2, 784 .route_offset = 0x190, 785 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15), 786 }, { 787 /* uart2_rxm2 */ 788 .bank_num = 3, 789 .pin = 4, 790 .func = 2, 791 .route_offset = 0x190, 792 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15), 793 }, 794 }; 795 796 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 797 { 798 /* spi-0 */ 799 .bank_num = 1, 800 .pin = 10, 801 .func = 1, 802 .route_offset = 0x144, 803 .route_val = BIT(16 + 3) | BIT(16 + 4), 804 }, { 805 /* spi-1 */ 806 .bank_num = 1, 807 .pin = 27, 808 .func = 3, 809 .route_offset = 0x144, 810 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 811 }, { 812 /* spi-2 */ 813 .bank_num = 0, 814 .pin = 13, 815 .func = 2, 816 .route_offset = 0x144, 817 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 818 }, { 819 /* i2s-0 */ 820 .bank_num = 1, 821 .pin = 5, 822 .func = 1, 823 .route_offset = 0x144, 824 .route_val = BIT(16 + 5), 825 }, { 826 /* i2s-1 */ 827 .bank_num = 0, 828 .pin = 14, 829 .func = 1, 830 .route_offset = 0x144, 831 .route_val = BIT(16 + 5) | BIT(5), 832 }, { 833 /* emmc-0 */ 834 .bank_num = 1, 835 .pin = 22, 836 .func = 2, 837 .route_offset = 0x144, 838 .route_val = BIT(16 + 6), 839 }, { 840 /* emmc-1 */ 841 .bank_num = 2, 842 .pin = 4, 843 .func = 2, 844 .route_offset = 0x144, 845 .route_val = BIT(16 + 6) | BIT(6), 846 }, 847 }; 848 849 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 850 { 851 /* pwm0-0 */ 852 .bank_num = 0, 853 .pin = 26, 854 .func = 1, 855 .route_offset = 0x50, 856 .route_val = BIT(16), 857 }, { 858 /* pwm0-1 */ 859 .bank_num = 3, 860 .pin = 21, 861 .func = 1, 862 .route_offset = 0x50, 863 .route_val = BIT(16) | BIT(0), 864 }, { 865 /* pwm1-0 */ 866 .bank_num = 0, 867 .pin = 27, 868 .func = 1, 869 .route_offset = 0x50, 870 .route_val = BIT(16 + 1), 871 }, { 872 /* pwm1-1 */ 873 .bank_num = 0, 874 .pin = 30, 875 .func = 2, 876 .route_offset = 0x50, 877 .route_val = BIT(16 + 1) | BIT(1), 878 }, { 879 /* pwm2-0 */ 880 .bank_num = 0, 881 .pin = 28, 882 .func = 1, 883 .route_offset = 0x50, 884 .route_val = BIT(16 + 2), 885 }, { 886 /* pwm2-1 */ 887 .bank_num = 1, 888 .pin = 12, 889 .func = 2, 890 .route_offset = 0x50, 891 .route_val = BIT(16 + 2) | BIT(2), 892 }, { 893 /* pwm3-0 */ 894 .bank_num = 3, 895 .pin = 26, 896 .func = 1, 897 .route_offset = 0x50, 898 .route_val = BIT(16 + 3), 899 }, { 900 /* pwm3-1 */ 901 .bank_num = 1, 902 .pin = 11, 903 .func = 2, 904 .route_offset = 0x50, 905 .route_val = BIT(16 + 3) | BIT(3), 906 }, { 907 /* sdio-0_d0 */ 908 .bank_num = 1, 909 .pin = 1, 910 .func = 1, 911 .route_offset = 0x50, 912 .route_val = BIT(16 + 4), 913 }, { 914 /* sdio-1_d0 */ 915 .bank_num = 3, 916 .pin = 2, 917 .func = 1, 918 .route_offset = 0x50, 919 .route_val = BIT(16 + 4) | BIT(4), 920 }, { 921 /* spi-0_rx */ 922 .bank_num = 0, 923 .pin = 13, 924 .func = 2, 925 .route_offset = 0x50, 926 .route_val = BIT(16 + 5), 927 }, { 928 /* spi-1_rx */ 929 .bank_num = 2, 930 .pin = 0, 931 .func = 2, 932 .route_offset = 0x50, 933 .route_val = BIT(16 + 5) | BIT(5), 934 }, { 935 /* emmc-0_cmd */ 936 .bank_num = 1, 937 .pin = 22, 938 .func = 2, 939 .route_offset = 0x50, 940 .route_val = BIT(16 + 7), 941 }, { 942 /* emmc-1_cmd */ 943 .bank_num = 2, 944 .pin = 4, 945 .func = 2, 946 .route_offset = 0x50, 947 .route_val = BIT(16 + 7) | BIT(7), 948 }, { 949 /* uart2-0_rx */ 950 .bank_num = 1, 951 .pin = 19, 952 .func = 2, 953 .route_offset = 0x50, 954 .route_val = BIT(16 + 8), 955 }, { 956 /* uart2-1_rx */ 957 .bank_num = 1, 958 .pin = 10, 959 .func = 2, 960 .route_offset = 0x50, 961 .route_val = BIT(16 + 8) | BIT(8), 962 }, { 963 /* uart1-0_rx */ 964 .bank_num = 1, 965 .pin = 10, 966 .func = 1, 967 .route_offset = 0x50, 968 .route_val = BIT(16 + 11), 969 }, { 970 /* uart1-1_rx */ 971 .bank_num = 3, 972 .pin = 13, 973 .func = 1, 974 .route_offset = 0x50, 975 .route_val = BIT(16 + 11) | BIT(11), 976 }, 977 }; 978 979 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 980 { 981 /* edphdmi_cecinoutt1 */ 982 .bank_num = 7, 983 .pin = 16, 984 .func = 2, 985 .route_offset = 0x264, 986 .route_val = BIT(16 + 12) | BIT(12), 987 }, { 988 /* edphdmi_cecinout */ 989 .bank_num = 7, 990 .pin = 23, 991 .func = 4, 992 .route_offset = 0x264, 993 .route_val = BIT(16 + 12), 994 }, 995 }; 996 997 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 998 { 999 /* rtc_clk */ 1000 .bank_num = 0, 1001 .pin = 19, 1002 .func = 1, 1003 .route_offset = 0x314, 1004 .route_val = BIT(16 + 0) | BIT(0), 1005 }, { 1006 /* uart2_rxm0 */ 1007 .bank_num = 1, 1008 .pin = 22, 1009 .func = 2, 1010 .route_offset = 0x314, 1011 .route_val = BIT(16 + 2) | BIT(16 + 3), 1012 }, { 1013 /* uart2_rxm1 */ 1014 .bank_num = 4, 1015 .pin = 26, 1016 .func = 2, 1017 .route_offset = 0x314, 1018 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1019 }, { 1020 /* i2c3_sdam0 */ 1021 .bank_num = 0, 1022 .pin = 23, 1023 .func = 2, 1024 .route_offset = 0x314, 1025 .route_val = BIT(16 + 4), 1026 }, { 1027 /* i2c3_sdam1 */ 1028 .bank_num = 3, 1029 .pin = 12, 1030 .func = 2, 1031 .route_offset = 0x314, 1032 .route_val = BIT(16 + 4) | BIT(4), 1033 }, { 1034 /* i2s-8ch-1-sclktxm0 */ 1035 .bank_num = 1, 1036 .pin = 3, 1037 .func = 2, 1038 .route_offset = 0x308, 1039 .route_val = BIT(16 + 3), 1040 }, { 1041 /* i2s-8ch-1-sclkrxm0 */ 1042 .bank_num = 1, 1043 .pin = 4, 1044 .func = 2, 1045 .route_offset = 0x308, 1046 .route_val = BIT(16 + 3), 1047 }, { 1048 /* i2s-8ch-1-sclktxm1 */ 1049 .bank_num = 1, 1050 .pin = 13, 1051 .func = 2, 1052 .route_offset = 0x308, 1053 .route_val = BIT(16 + 3) | BIT(3), 1054 }, { 1055 /* i2s-8ch-1-sclkrxm1 */ 1056 .bank_num = 1, 1057 .pin = 14, 1058 .func = 2, 1059 .route_offset = 0x308, 1060 .route_val = BIT(16 + 3) | BIT(3), 1061 }, { 1062 /* pdm-clkm0 */ 1063 .bank_num = 1, 1064 .pin = 4, 1065 .func = 3, 1066 .route_offset = 0x308, 1067 .route_val = BIT(16 + 12) | BIT(16 + 13), 1068 }, { 1069 /* pdm-clkm1 */ 1070 .bank_num = 1, 1071 .pin = 14, 1072 .func = 4, 1073 .route_offset = 0x308, 1074 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1075 }, { 1076 /* pdm-clkm2 */ 1077 .bank_num = 2, 1078 .pin = 6, 1079 .func = 2, 1080 .route_offset = 0x308, 1081 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1082 }, { 1083 /* pdm-clkm-m2 */ 1084 .bank_num = 2, 1085 .pin = 4, 1086 .func = 3, 1087 .route_offset = 0x600, 1088 .route_val = BIT(16 + 2) | BIT(2), 1089 }, 1090 }; 1091 1092 static struct rockchip_mux_route_data rk3308b_mux_route_data[] = { 1093 { 1094 /* rtc_clk */ 1095 .bank_num = 0, 1096 .pin = 19, 1097 .func = 1, 1098 .route_offset = 0x314, 1099 .route_val = BIT(16 + 0) | BIT(0), 1100 }, { 1101 /* uart2_rxm0 */ 1102 .bank_num = 1, 1103 .pin = 22, 1104 .func = 2, 1105 .route_offset = 0x314, 1106 .route_val = BIT(16 + 2) | BIT(16 + 3), 1107 }, { 1108 /* uart2_rxm1 */ 1109 .bank_num = 4, 1110 .pin = 26, 1111 .func = 2, 1112 .route_offset = 0x314, 1113 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1114 }, { 1115 /* i2c3_sdam0 */ 1116 .bank_num = 0, 1117 .pin = 15, 1118 .func = 2, 1119 .route_offset = 0x608, 1120 .route_val = BIT(16 + 8) | BIT(16 + 9), 1121 }, { 1122 /* i2c3_sdam1 */ 1123 .bank_num = 3, 1124 .pin = 12, 1125 .func = 2, 1126 .route_offset = 0x608, 1127 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 1128 }, { 1129 /* i2c3_sdam2 */ 1130 .bank_num = 2, 1131 .pin = 0, 1132 .func = 3, 1133 .route_offset = 0x608, 1134 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 1135 }, { 1136 /* i2s-8ch-1-sclktxm0 */ 1137 .bank_num = 1, 1138 .pin = 3, 1139 .func = 2, 1140 .route_offset = 0x308, 1141 .route_val = BIT(16 + 3), 1142 }, { 1143 /* i2s-8ch-1-sclkrxm0 */ 1144 .bank_num = 1, 1145 .pin = 4, 1146 .func = 2, 1147 .route_offset = 0x308, 1148 .route_val = BIT(16 + 3), 1149 }, { 1150 /* i2s-8ch-1-sclktxm1 */ 1151 .bank_num = 1, 1152 .pin = 13, 1153 .func = 2, 1154 .route_offset = 0x308, 1155 .route_val = BIT(16 + 3) | BIT(3), 1156 }, { 1157 /* i2s-8ch-1-sclkrxm1 */ 1158 .bank_num = 1, 1159 .pin = 14, 1160 .func = 2, 1161 .route_offset = 0x308, 1162 .route_val = BIT(16 + 3) | BIT(3), 1163 }, { 1164 /* pdm-clkm0 */ 1165 .bank_num = 1, 1166 .pin = 4, 1167 .func = 3, 1168 .route_offset = 0x308, 1169 .route_val = BIT(16 + 12) | BIT(16 + 13), 1170 }, { 1171 /* pdm-clkm1 */ 1172 .bank_num = 1, 1173 .pin = 14, 1174 .func = 4, 1175 .route_offset = 0x308, 1176 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1177 }, { 1178 /* pdm-clkm2 */ 1179 .bank_num = 2, 1180 .pin = 6, 1181 .func = 2, 1182 .route_offset = 0x308, 1183 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1184 }, { 1185 /* pdm-clkm-m2 */ 1186 .bank_num = 2, 1187 .pin = 4, 1188 .func = 3, 1189 .route_offset = 0x600, 1190 .route_val = BIT(16 + 2) | BIT(2), 1191 }, { 1192 /* spi1_miso */ 1193 .bank_num = 3, 1194 .pin = 10, 1195 .func = 3, 1196 .route_offset = 0x314, 1197 .route_val = BIT(16 + 9), 1198 }, { 1199 /* spi1_miso_m1 */ 1200 .bank_num = 2, 1201 .pin = 4, 1202 .func = 2, 1203 .route_offset = 0x314, 1204 .route_val = BIT(16 + 9) | BIT(9), 1205 }, { 1206 /* owire_m0 */ 1207 .bank_num = 0, 1208 .pin = 11, 1209 .func = 3, 1210 .route_offset = 0x314, 1211 .route_val = BIT(16 + 10) | BIT(16 + 11), 1212 }, { 1213 /* owire_m1 */ 1214 .bank_num = 1, 1215 .pin = 22, 1216 .func = 7, 1217 .route_offset = 0x314, 1218 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1219 }, { 1220 /* owire_m2 */ 1221 .bank_num = 2, 1222 .pin = 2, 1223 .func = 5, 1224 .route_offset = 0x314, 1225 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1226 }, { 1227 /* can_rxd_m0 */ 1228 .bank_num = 0, 1229 .pin = 11, 1230 .func = 2, 1231 .route_offset = 0x314, 1232 .route_val = BIT(16 + 12) | BIT(16 + 13), 1233 }, { 1234 /* can_rxd_m1 */ 1235 .bank_num = 1, 1236 .pin = 22, 1237 .func = 5, 1238 .route_offset = 0x314, 1239 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1240 }, { 1241 /* can_rxd_m2 */ 1242 .bank_num = 2, 1243 .pin = 2, 1244 .func = 4, 1245 .route_offset = 0x314, 1246 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1247 }, { 1248 /* mac_rxd0_m0 */ 1249 .bank_num = 1, 1250 .pin = 20, 1251 .func = 3, 1252 .route_offset = 0x314, 1253 .route_val = BIT(16 + 14), 1254 }, { 1255 /* mac_rxd0_m1 */ 1256 .bank_num = 4, 1257 .pin = 2, 1258 .func = 2, 1259 .route_offset = 0x314, 1260 .route_val = BIT(16 + 14) | BIT(14), 1261 }, { 1262 /* uart3_rx */ 1263 .bank_num = 3, 1264 .pin = 12, 1265 .func = 4, 1266 .route_offset = 0x314, 1267 .route_val = BIT(16 + 15), 1268 }, { 1269 /* uart3_rx_m1 */ 1270 .bank_num = 0, 1271 .pin = 17, 1272 .func = 3, 1273 .route_offset = 0x314, 1274 .route_val = BIT(16 + 15) | BIT(15), 1275 }, 1276 }; 1277 1278 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1279 { 1280 /* uart2dbg_rxm0 */ 1281 .bank_num = 1, 1282 .pin = 1, 1283 .func = 2, 1284 .route_offset = 0x50, 1285 .route_val = BIT(16) | BIT(16 + 1), 1286 }, { 1287 /* uart2dbg_rxm1 */ 1288 .bank_num = 2, 1289 .pin = 1, 1290 .func = 1, 1291 .route_offset = 0x50, 1292 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1293 }, { 1294 /* gmac-m1_rxd0 */ 1295 .bank_num = 1, 1296 .pin = 11, 1297 .func = 2, 1298 .route_offset = 0x50, 1299 .route_val = BIT(16 + 2) | BIT(2), 1300 }, { 1301 /* gmac-m1-optimized_rxd3 */ 1302 .bank_num = 1, 1303 .pin = 14, 1304 .func = 2, 1305 .route_offset = 0x50, 1306 .route_val = BIT(16 + 10) | BIT(10), 1307 }, { 1308 /* pdm_sdi0m0 */ 1309 .bank_num = 2, 1310 .pin = 19, 1311 .func = 2, 1312 .route_offset = 0x50, 1313 .route_val = BIT(16 + 3), 1314 }, { 1315 /* pdm_sdi0m1 */ 1316 .bank_num = 1, 1317 .pin = 23, 1318 .func = 3, 1319 .route_offset = 0x50, 1320 .route_val = BIT(16 + 3) | BIT(3), 1321 }, { 1322 /* spi_rxdm2 */ 1323 .bank_num = 3, 1324 .pin = 2, 1325 .func = 4, 1326 .route_offset = 0x50, 1327 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1328 }, { 1329 /* i2s2_sdim0 */ 1330 .bank_num = 1, 1331 .pin = 24, 1332 .func = 1, 1333 .route_offset = 0x50, 1334 .route_val = BIT(16 + 6), 1335 }, { 1336 /* i2s2_sdim1 */ 1337 .bank_num = 3, 1338 .pin = 2, 1339 .func = 6, 1340 .route_offset = 0x50, 1341 .route_val = BIT(16 + 6) | BIT(6), 1342 }, { 1343 /* card_iom1 */ 1344 .bank_num = 2, 1345 .pin = 22, 1346 .func = 3, 1347 .route_offset = 0x50, 1348 .route_val = BIT(16 + 7) | BIT(7), 1349 }, { 1350 /* tsp_d5m1 */ 1351 .bank_num = 2, 1352 .pin = 16, 1353 .func = 3, 1354 .route_offset = 0x50, 1355 .route_val = BIT(16 + 8) | BIT(8), 1356 }, { 1357 /* cif_data5m1 */ 1358 .bank_num = 2, 1359 .pin = 16, 1360 .func = 4, 1361 .route_offset = 0x50, 1362 .route_val = BIT(16 + 9) | BIT(9), 1363 }, 1364 }; 1365 1366 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1367 { 1368 /* uart2dbga_rx */ 1369 .bank_num = 4, 1370 .pin = 8, 1371 .func = 2, 1372 .route_offset = 0xe21c, 1373 .route_val = BIT(16 + 10) | BIT(16 + 11), 1374 }, { 1375 /* uart2dbgb_rx */ 1376 .bank_num = 4, 1377 .pin = 16, 1378 .func = 2, 1379 .route_offset = 0xe21c, 1380 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1381 }, { 1382 /* uart2dbgc_rx */ 1383 .bank_num = 4, 1384 .pin = 19, 1385 .func = 1, 1386 .route_offset = 0xe21c, 1387 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1388 }, { 1389 /* pcie_clkreqn */ 1390 .bank_num = 2, 1391 .pin = 26, 1392 .func = 2, 1393 .route_offset = 0xe21c, 1394 .route_val = BIT(16 + 14), 1395 }, { 1396 /* pcie_clkreqnb */ 1397 .bank_num = 4, 1398 .pin = 24, 1399 .func = 1, 1400 .route_offset = 0xe21c, 1401 .route_val = BIT(16 + 14) | BIT(14), 1402 }, 1403 }; 1404 1405 static enum rockchip_pin_route_type 1406 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1407 int mux, u32 *reg, u32 *value) 1408 { 1409 struct rockchip_pinctrl_priv *priv = bank->priv; 1410 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1411 struct rockchip_mux_route_data *data; 1412 int i; 1413 1414 for (i = 0; i < ctrl->niomux_routes; i++) { 1415 data = &ctrl->iomux_routes[i]; 1416 if ((data->bank_num == bank->bank_num) && 1417 (data->pin == pin) && (data->func == mux)) 1418 break; 1419 } 1420 1421 if (i >= ctrl->niomux_routes) 1422 return ROUTE_TYPE_INVALID; 1423 1424 *reg = data->route_offset; 1425 *value = data->route_val; 1426 1427 return data->route_type; 1428 } 1429 1430 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1431 { 1432 struct rockchip_pinctrl_priv *priv = bank->priv; 1433 int iomux_num = (pin / 8); 1434 struct regmap *regmap; 1435 unsigned int val; 1436 int reg, ret, mask, mux_type; 1437 u8 bit; 1438 1439 if (iomux_num > 3) 1440 return -EINVAL; 1441 1442 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1443 debug("pin %d is unrouted\n", pin); 1444 return -EINVAL; 1445 } 1446 1447 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1448 return RK_FUNC_GPIO; 1449 1450 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1451 ? priv->regmap_pmu : priv->regmap_base; 1452 1453 /* get basic quadrupel of mux registers and the correct reg inside */ 1454 mux_type = bank->iomux[iomux_num].type; 1455 reg = bank->iomux[iomux_num].offset; 1456 if (mux_type & IOMUX_WIDTH_4BIT) { 1457 if ((pin % 8) >= 4) 1458 reg += 0x4; 1459 bit = (pin % 4) * 4; 1460 mask = 0xf; 1461 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1462 if ((pin % 8) >= 5) 1463 reg += 0x4; 1464 bit = (pin % 8 % 5) * 3; 1465 mask = 0x7; 1466 } else { 1467 bit = (pin % 8) * 2; 1468 mask = 0x3; 1469 } 1470 1471 if (bank->recalced_mask & BIT(pin)) 1472 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1473 1474 ret = regmap_read(regmap, reg, &val); 1475 if (ret) 1476 return ret; 1477 1478 return ((val >> bit) & mask); 1479 } 1480 1481 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1482 int index) 1483 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1484 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1485 1486 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1487 } 1488 1489 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1490 int pin, int mux) 1491 { 1492 int iomux_num = (pin / 8); 1493 1494 if (iomux_num > 3) 1495 return -EINVAL; 1496 1497 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1498 debug("pin %d is unrouted\n", pin); 1499 return -EINVAL; 1500 } 1501 1502 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1503 if (mux != IOMUX_GPIO_ONLY) { 1504 debug("pin %d only supports a gpio mux\n", pin); 1505 return -ENOTSUPP; 1506 } 1507 } 1508 1509 return 0; 1510 } 1511 1512 /* 1513 * Set a new mux function for a pin. 1514 * 1515 * The register is divided into the upper and lower 16 bit. When changing 1516 * a value, the previous register value is not read and changed. Instead 1517 * it seems the changed bits are marked in the upper 16 bit, while the 1518 * changed value gets set in the same offset in the lower 16 bit. 1519 * All pin settings seem to be 2 bit wide in both the upper and lower 1520 * parts. 1521 * @bank: pin bank to change 1522 * @pin: pin to change 1523 * @mux: new mux function to set 1524 */ 1525 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1526 { 1527 struct rockchip_pinctrl_priv *priv = bank->priv; 1528 int iomux_num = (pin / 8); 1529 struct regmap *regmap; 1530 int reg, ret, mask, mux_type; 1531 u8 bit; 1532 u32 data; 1533 1534 ret = rockchip_verify_mux(bank, pin, mux); 1535 if (ret < 0) 1536 return ret; 1537 1538 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1539 return 0; 1540 1541 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1542 1543 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1544 ? priv->regmap_pmu : priv->regmap_base; 1545 1546 /* get basic quadrupel of mux registers and the correct reg inside */ 1547 mux_type = bank->iomux[iomux_num].type; 1548 reg = bank->iomux[iomux_num].offset; 1549 if (mux_type & IOMUX_WIDTH_4BIT) { 1550 if ((pin % 8) >= 4) 1551 reg += 0x4; 1552 bit = (pin % 4) * 4; 1553 mask = 0xf; 1554 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1555 if ((pin % 8) >= 5) 1556 reg += 0x4; 1557 bit = (pin % 8 % 5) * 3; 1558 mask = 0x7; 1559 } else { 1560 bit = (pin % 8) * 2; 1561 mask = 0x3; 1562 } 1563 1564 if (bank->recalced_mask & BIT(pin)) 1565 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1566 1567 if (bank->route_mask & BIT(pin)) { 1568 u32 route_reg = 0, route_val = 0; 1569 1570 ret = rockchip_get_mux_route(bank, pin, mux, 1571 &route_reg, &route_val); 1572 switch (ret) { 1573 case ROUTE_TYPE_DEFAULT: 1574 regmap_write(regmap, route_reg, route_val); 1575 break; 1576 case ROUTE_TYPE_TOPGRF: 1577 regmap_write(priv->regmap_base, route_reg, route_val); 1578 break; 1579 case ROUTE_TYPE_PMUGRF: 1580 regmap_write(priv->regmap_pmu, route_reg, route_val); 1581 break; 1582 case ROUTE_TYPE_INVALID: /* Fall through */ 1583 default: 1584 break; 1585 } 1586 } 1587 1588 if (mux_type & IOMUX_WRITABLE_32BIT) { 1589 regmap_read(regmap, reg, &data); 1590 data &= ~(mask << bit); 1591 } else { 1592 data = (mask << (bit + 16)); 1593 } 1594 1595 data |= (mux & mask) << bit; 1596 ret = regmap_write(regmap, reg, data); 1597 1598 return ret; 1599 } 1600 1601 #define PX30_PULL_PMU_OFFSET 0x10 1602 #define PX30_PULL_GRF_OFFSET 0x60 1603 #define PX30_PULL_BITS_PER_PIN 2 1604 #define PX30_PULL_PINS_PER_REG 8 1605 #define PX30_PULL_BANK_STRIDE 16 1606 1607 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1608 int pin_num, struct regmap **regmap, 1609 int *reg, u8 *bit) 1610 { 1611 struct rockchip_pinctrl_priv *priv = bank->priv; 1612 1613 /* The first 32 pins of the first bank are located in PMU */ 1614 if (bank->bank_num == 0) { 1615 *regmap = priv->regmap_pmu; 1616 *reg = PX30_PULL_PMU_OFFSET; 1617 } else { 1618 *regmap = priv->regmap_base; 1619 *reg = PX30_PULL_GRF_OFFSET; 1620 1621 /* correct the offset, as we're starting with the 2nd bank */ 1622 *reg -= 0x10; 1623 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1624 } 1625 1626 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1627 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1628 *bit *= PX30_PULL_BITS_PER_PIN; 1629 } 1630 1631 #define PX30_DRV_PMU_OFFSET 0x20 1632 #define PX30_DRV_GRF_OFFSET 0xf0 1633 #define PX30_DRV_BITS_PER_PIN 2 1634 #define PX30_DRV_PINS_PER_REG 8 1635 #define PX30_DRV_BANK_STRIDE 16 1636 1637 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1638 int pin_num, struct regmap **regmap, 1639 int *reg, u8 *bit) 1640 { 1641 struct rockchip_pinctrl_priv *priv = bank->priv; 1642 1643 /* The first 32 pins of the first bank are located in PMU */ 1644 if (bank->bank_num == 0) { 1645 *regmap = priv->regmap_pmu; 1646 *reg = PX30_DRV_PMU_OFFSET; 1647 } else { 1648 *regmap = priv->regmap_base; 1649 *reg = PX30_DRV_GRF_OFFSET; 1650 1651 /* correct the offset, as we're starting with the 2nd bank */ 1652 *reg -= 0x10; 1653 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1654 } 1655 1656 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1657 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1658 *bit *= PX30_DRV_BITS_PER_PIN; 1659 } 1660 1661 #define PX30_SCHMITT_PMU_OFFSET 0x38 1662 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1663 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1664 #define PX30_SCHMITT_BANK_STRIDE 16 1665 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1666 1667 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1668 int pin_num, 1669 struct regmap **regmap, 1670 int *reg, u8 *bit) 1671 { 1672 struct rockchip_pinctrl_priv *priv = bank->priv; 1673 int pins_per_reg; 1674 1675 if (bank->bank_num == 0) { 1676 *regmap = priv->regmap_pmu; 1677 *reg = PX30_SCHMITT_PMU_OFFSET; 1678 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1679 } else { 1680 *regmap = priv->regmap_base; 1681 *reg = PX30_SCHMITT_GRF_OFFSET; 1682 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1683 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1684 } 1685 *reg += ((pin_num / pins_per_reg) * 4); 1686 *bit = pin_num % pins_per_reg; 1687 1688 return 0; 1689 } 1690 1691 #define RV1108_PULL_PMU_OFFSET 0x10 1692 #define RV1108_PULL_OFFSET 0x110 1693 #define RV1108_PULL_PINS_PER_REG 8 1694 #define RV1108_PULL_BITS_PER_PIN 2 1695 #define RV1108_PULL_BANK_STRIDE 16 1696 1697 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1698 int pin_num, struct regmap **regmap, 1699 int *reg, u8 *bit) 1700 { 1701 struct rockchip_pinctrl_priv *priv = bank->priv; 1702 1703 /* The first 24 pins of the first bank are located in PMU */ 1704 if (bank->bank_num == 0) { 1705 *regmap = priv->regmap_pmu; 1706 *reg = RV1108_PULL_PMU_OFFSET; 1707 } else { 1708 *reg = RV1108_PULL_OFFSET; 1709 *regmap = priv->regmap_base; 1710 /* correct the offset, as we're starting with the 2nd bank */ 1711 *reg -= 0x10; 1712 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1713 } 1714 1715 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1716 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1717 *bit *= RV1108_PULL_BITS_PER_PIN; 1718 } 1719 1720 #define RV1108_DRV_PMU_OFFSET 0x20 1721 #define RV1108_DRV_GRF_OFFSET 0x210 1722 #define RV1108_DRV_BITS_PER_PIN 2 1723 #define RV1108_DRV_PINS_PER_REG 8 1724 #define RV1108_DRV_BANK_STRIDE 16 1725 1726 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1727 int pin_num, struct regmap **regmap, 1728 int *reg, u8 *bit) 1729 { 1730 struct rockchip_pinctrl_priv *priv = bank->priv; 1731 1732 /* The first 24 pins of the first bank are located in PMU */ 1733 if (bank->bank_num == 0) { 1734 *regmap = priv->regmap_pmu; 1735 *reg = RV1108_DRV_PMU_OFFSET; 1736 } else { 1737 *regmap = priv->regmap_base; 1738 *reg = RV1108_DRV_GRF_OFFSET; 1739 1740 /* correct the offset, as we're starting with the 2nd bank */ 1741 *reg -= 0x10; 1742 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1743 } 1744 1745 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1746 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1747 *bit *= RV1108_DRV_BITS_PER_PIN; 1748 } 1749 1750 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1751 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1752 #define RV1108_SCHMITT_BANK_STRIDE 8 1753 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1754 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1755 1756 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1757 int pin_num, 1758 struct regmap **regmap, 1759 int *reg, u8 *bit) 1760 { 1761 struct rockchip_pinctrl_priv *priv = bank->priv; 1762 int pins_per_reg; 1763 1764 if (bank->bank_num == 0) { 1765 *regmap = priv->regmap_pmu; 1766 *reg = RV1108_SCHMITT_PMU_OFFSET; 1767 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1768 } else { 1769 *regmap = priv->regmap_base; 1770 *reg = RV1108_SCHMITT_GRF_OFFSET; 1771 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1772 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1773 } 1774 *reg += ((pin_num / pins_per_reg) * 4); 1775 *bit = pin_num % pins_per_reg; 1776 1777 return 0; 1778 } 1779 1780 #define RK1808_PULL_PMU_OFFSET 0x10 1781 #define RK1808_PULL_GRF_OFFSET 0x80 1782 #define RK1808_PULL_PINS_PER_REG 8 1783 #define RK1808_PULL_BITS_PER_PIN 2 1784 #define RK1808_PULL_BANK_STRIDE 16 1785 1786 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1787 int pin_num, 1788 struct regmap **regmap, 1789 int *reg, u8 *bit) 1790 { 1791 struct rockchip_pinctrl_priv *priv = bank->priv; 1792 1793 if (bank->bank_num == 0) { 1794 *regmap = priv->regmap_pmu; 1795 *reg = RK1808_PULL_PMU_OFFSET; 1796 } else { 1797 *reg = RK1808_PULL_GRF_OFFSET; 1798 *regmap = priv->regmap_base; 1799 } 1800 1801 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4); 1802 *bit = (pin_num % RK1808_PULL_PINS_PER_REG); 1803 *bit *= RK1808_PULL_BITS_PER_PIN; 1804 } 1805 1806 #define RK1808_DRV_PMU_OFFSET 0x20 1807 #define RK1808_DRV_GRF_OFFSET 0x140 1808 #define RK1808_DRV_BITS_PER_PIN 2 1809 #define RK1808_DRV_PINS_PER_REG 8 1810 #define RK1808_DRV_BANK_STRIDE 16 1811 1812 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1813 int pin_num, 1814 struct regmap **regmap, 1815 int *reg, u8 *bit) 1816 { 1817 struct rockchip_pinctrl_priv *priv = bank->priv; 1818 1819 if (bank->bank_num == 0) { 1820 *regmap = priv->regmap_pmu; 1821 *reg = RK1808_DRV_PMU_OFFSET; 1822 } else { 1823 *regmap = priv->regmap_base; 1824 *reg = RK1808_DRV_GRF_OFFSET; 1825 } 1826 1827 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4); 1828 *bit = pin_num % RK1808_DRV_PINS_PER_REG; 1829 *bit *= RK1808_DRV_BITS_PER_PIN; 1830 } 1831 1832 #define RK1808_SCHMITT_PMU_OFFSET 0x0040 1833 #define RK1808_SCHMITT_GRF_OFFSET 0x0100 1834 #define RK1808_SCHMITT_BANK_STRIDE 16 1835 #define RK1808_SCHMITT_PINS_PER_REG 8 1836 1837 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1838 int pin_num, 1839 struct regmap **regmap, 1840 int *reg, u8 *bit) 1841 { 1842 struct rockchip_pinctrl_priv *priv = bank->priv; 1843 1844 if (bank->bank_num == 0) { 1845 *regmap = priv->regmap_pmu; 1846 *reg = RK1808_SCHMITT_PMU_OFFSET; 1847 } else { 1848 *regmap = priv->regmap_base; 1849 *reg = RK1808_SCHMITT_GRF_OFFSET; 1850 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE; 1851 } 1852 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4); 1853 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG; 1854 1855 return 0; 1856 } 1857 1858 #define RK2928_PULL_OFFSET 0x118 1859 #define RK2928_PULL_PINS_PER_REG 16 1860 #define RK2928_PULL_BANK_STRIDE 8 1861 1862 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1863 int pin_num, struct regmap **regmap, 1864 int *reg, u8 *bit) 1865 { 1866 struct rockchip_pinctrl_priv *priv = bank->priv; 1867 1868 *regmap = priv->regmap_base; 1869 *reg = RK2928_PULL_OFFSET; 1870 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1871 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1872 1873 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1874 }; 1875 1876 #define RK3128_PULL_OFFSET 0x118 1877 1878 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1879 int pin_num, struct regmap **regmap, 1880 int *reg, u8 *bit) 1881 { 1882 struct rockchip_pinctrl_priv *priv = bank->priv; 1883 1884 *regmap = priv->regmap_base; 1885 *reg = RK3128_PULL_OFFSET; 1886 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1887 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1888 1889 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1890 } 1891 1892 #define RK3188_PULL_OFFSET 0x164 1893 #define RK3188_PULL_BITS_PER_PIN 2 1894 #define RK3188_PULL_PINS_PER_REG 8 1895 #define RK3188_PULL_BANK_STRIDE 16 1896 #define RK3188_PULL_PMU_OFFSET 0x64 1897 1898 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1899 int pin_num, struct regmap **regmap, 1900 int *reg, u8 *bit) 1901 { 1902 struct rockchip_pinctrl_priv *priv = bank->priv; 1903 1904 /* The first 12 pins of the first bank are located elsewhere */ 1905 if (bank->bank_num == 0 && pin_num < 12) { 1906 *regmap = priv->regmap_pmu; 1907 *reg = RK3188_PULL_PMU_OFFSET; 1908 1909 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1910 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1911 *bit *= RK3188_PULL_BITS_PER_PIN; 1912 } else { 1913 *regmap = priv->regmap_base; 1914 *reg = RK3188_PULL_OFFSET; 1915 1916 /* correct the offset, as it is the 2nd pull register */ 1917 *reg -= 4; 1918 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1919 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1920 1921 /* 1922 * The bits in these registers have an inverse ordering 1923 * with the lowest pin being in bits 15:14 and the highest 1924 * pin in bits 1:0 1925 */ 1926 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1927 *bit *= RK3188_PULL_BITS_PER_PIN; 1928 } 1929 } 1930 1931 #define RK3288_PULL_OFFSET 0x140 1932 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1933 int pin_num, struct regmap **regmap, 1934 int *reg, u8 *bit) 1935 { 1936 struct rockchip_pinctrl_priv *priv = bank->priv; 1937 1938 /* The first 24 pins of the first bank are located in PMU */ 1939 if (bank->bank_num == 0) { 1940 *regmap = priv->regmap_pmu; 1941 *reg = RK3188_PULL_PMU_OFFSET; 1942 1943 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1944 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1945 *bit *= RK3188_PULL_BITS_PER_PIN; 1946 } else { 1947 *regmap = priv->regmap_base; 1948 *reg = RK3288_PULL_OFFSET; 1949 1950 /* correct the offset, as we're starting with the 2nd bank */ 1951 *reg -= 0x10; 1952 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1953 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1954 1955 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1956 *bit *= RK3188_PULL_BITS_PER_PIN; 1957 } 1958 } 1959 1960 #define RK3288_DRV_PMU_OFFSET 0x70 1961 #define RK3288_DRV_GRF_OFFSET 0x1c0 1962 #define RK3288_DRV_BITS_PER_PIN 2 1963 #define RK3288_DRV_PINS_PER_REG 8 1964 #define RK3288_DRV_BANK_STRIDE 16 1965 1966 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1967 int pin_num, struct regmap **regmap, 1968 int *reg, u8 *bit) 1969 { 1970 struct rockchip_pinctrl_priv *priv = bank->priv; 1971 1972 /* The first 24 pins of the first bank are located in PMU */ 1973 if (bank->bank_num == 0) { 1974 *regmap = priv->regmap_pmu; 1975 *reg = RK3288_DRV_PMU_OFFSET; 1976 1977 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1978 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1979 *bit *= RK3288_DRV_BITS_PER_PIN; 1980 } else { 1981 *regmap = priv->regmap_base; 1982 *reg = RK3288_DRV_GRF_OFFSET; 1983 1984 /* correct the offset, as we're starting with the 2nd bank */ 1985 *reg -= 0x10; 1986 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1987 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1988 1989 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1990 *bit *= RK3288_DRV_BITS_PER_PIN; 1991 } 1992 } 1993 1994 #define RK3228_PULL_OFFSET 0x100 1995 1996 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1997 int pin_num, struct regmap **regmap, 1998 int *reg, u8 *bit) 1999 { 2000 struct rockchip_pinctrl_priv *priv = bank->priv; 2001 2002 *regmap = priv->regmap_base; 2003 *reg = RK3228_PULL_OFFSET; 2004 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2005 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2006 2007 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2008 *bit *= RK3188_PULL_BITS_PER_PIN; 2009 } 2010 2011 #define RK3228_DRV_GRF_OFFSET 0x200 2012 2013 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2014 int pin_num, struct regmap **regmap, 2015 int *reg, u8 *bit) 2016 { 2017 struct rockchip_pinctrl_priv *priv = bank->priv; 2018 2019 *regmap = priv->regmap_base; 2020 *reg = RK3228_DRV_GRF_OFFSET; 2021 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2022 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2023 2024 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2025 *bit *= RK3288_DRV_BITS_PER_PIN; 2026 } 2027 2028 #define RK3308_PULL_OFFSET 0xa0 2029 2030 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2031 int pin_num, struct regmap **regmap, 2032 int *reg, u8 *bit) 2033 { 2034 struct rockchip_pinctrl_priv *priv = bank->priv; 2035 2036 *regmap = priv->regmap_base; 2037 *reg = RK3308_PULL_OFFSET; 2038 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2039 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2040 2041 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2042 *bit *= RK3188_PULL_BITS_PER_PIN; 2043 } 2044 2045 #define RK3308_DRV_GRF_OFFSET 0x100 2046 2047 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2048 int pin_num, struct regmap **regmap, 2049 int *reg, u8 *bit) 2050 { 2051 struct rockchip_pinctrl_priv *priv = bank->priv; 2052 2053 *regmap = priv->regmap_base; 2054 *reg = RK3308_DRV_GRF_OFFSET; 2055 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2056 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2057 2058 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2059 *bit *= RK3288_DRV_BITS_PER_PIN; 2060 } 2061 2062 #define RK3308_SCHMITT_PINS_PER_REG 8 2063 #define RK3308_SCHMITT_BANK_STRIDE 16 2064 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 2065 2066 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2067 int pin_num, 2068 struct regmap **regmap, 2069 int *reg, u8 *bit) 2070 { 2071 struct rockchip_pinctrl_priv *priv = bank->priv; 2072 2073 *regmap = priv->regmap_base; 2074 *reg = RK3308_SCHMITT_GRF_OFFSET; 2075 2076 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 2077 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 2078 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 2079 2080 return 0; 2081 } 2082 2083 #define RK3368_PULL_GRF_OFFSET 0x100 2084 #define RK3368_PULL_PMU_OFFSET 0x10 2085 2086 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2087 int pin_num, struct regmap **regmap, 2088 int *reg, u8 *bit) 2089 { 2090 struct rockchip_pinctrl_priv *priv = bank->priv; 2091 2092 /* The first 32 pins of the first bank are located in PMU */ 2093 if (bank->bank_num == 0) { 2094 *regmap = priv->regmap_pmu; 2095 *reg = RK3368_PULL_PMU_OFFSET; 2096 2097 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2098 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2099 *bit *= RK3188_PULL_BITS_PER_PIN; 2100 } else { 2101 *regmap = priv->regmap_base; 2102 *reg = RK3368_PULL_GRF_OFFSET; 2103 2104 /* correct the offset, as we're starting with the 2nd bank */ 2105 *reg -= 0x10; 2106 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2107 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2108 2109 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2110 *bit *= RK3188_PULL_BITS_PER_PIN; 2111 } 2112 } 2113 2114 #define RK3368_DRV_PMU_OFFSET 0x20 2115 #define RK3368_DRV_GRF_OFFSET 0x200 2116 2117 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2118 int pin_num, struct regmap **regmap, 2119 int *reg, u8 *bit) 2120 { 2121 struct rockchip_pinctrl_priv *priv = bank->priv; 2122 2123 /* The first 32 pins of the first bank are located in PMU */ 2124 if (bank->bank_num == 0) { 2125 *regmap = priv->regmap_pmu; 2126 *reg = RK3368_DRV_PMU_OFFSET; 2127 2128 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2129 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2130 *bit *= RK3288_DRV_BITS_PER_PIN; 2131 } else { 2132 *regmap = priv->regmap_base; 2133 *reg = RK3368_DRV_GRF_OFFSET; 2134 2135 /* correct the offset, as we're starting with the 2nd bank */ 2136 *reg -= 0x10; 2137 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2138 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2139 2140 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2141 *bit *= RK3288_DRV_BITS_PER_PIN; 2142 } 2143 } 2144 2145 #define RK3399_PULL_GRF_OFFSET 0xe040 2146 #define RK3399_PULL_PMU_OFFSET 0x40 2147 #define RK3399_DRV_3BITS_PER_PIN 3 2148 2149 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2150 int pin_num, struct regmap **regmap, 2151 int *reg, u8 *bit) 2152 { 2153 struct rockchip_pinctrl_priv *priv = bank->priv; 2154 2155 /* The bank0:16 and bank1:32 pins are located in PMU */ 2156 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2157 *regmap = priv->regmap_pmu; 2158 *reg = RK3399_PULL_PMU_OFFSET; 2159 2160 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2161 2162 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2163 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2164 *bit *= RK3188_PULL_BITS_PER_PIN; 2165 } else { 2166 *regmap = priv->regmap_base; 2167 *reg = RK3399_PULL_GRF_OFFSET; 2168 2169 /* correct the offset, as we're starting with the 3rd bank */ 2170 *reg -= 0x20; 2171 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2172 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2173 2174 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2175 *bit *= RK3188_PULL_BITS_PER_PIN; 2176 } 2177 } 2178 2179 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2180 int pin_num, struct regmap **regmap, 2181 int *reg, u8 *bit) 2182 { 2183 struct rockchip_pinctrl_priv *priv = bank->priv; 2184 int drv_num = (pin_num / 8); 2185 2186 /* The bank0:16 and bank1:32 pins are located in PMU */ 2187 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2188 *regmap = priv->regmap_pmu; 2189 else 2190 *regmap = priv->regmap_base; 2191 2192 *reg = bank->drv[drv_num].offset; 2193 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2194 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2195 *bit = (pin_num % 8) * 3; 2196 else 2197 *bit = (pin_num % 8) * 2; 2198 } 2199 2200 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2201 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2202 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2203 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2204 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2205 { 4, 7, 10, 13, 16, 19, 22, 26 } 2206 }; 2207 2208 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2209 int pin_num, int strength) 2210 { 2211 struct rockchip_pinctrl_priv *priv = bank->priv; 2212 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2213 struct regmap *regmap; 2214 int reg, ret, i; 2215 u32 data, rmask_bits, temp; 2216 u8 bit; 2217 /* Where need to clean the special mask for rockchip_perpin_drv_list */ 2218 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); 2219 2220 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 2221 pin_num, strength); 2222 2223 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2224 2225 ret = -EINVAL; 2226 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2227 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2228 ret = i; 2229 break; 2230 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2231 ret = rockchip_perpin_drv_list[drv_type][i]; 2232 break; 2233 } 2234 } 2235 2236 if (ret < 0) { 2237 debug("unsupported driver strength %d\n", strength); 2238 return ret; 2239 } 2240 2241 switch (drv_type) { 2242 case DRV_TYPE_IO_1V8_3V0_AUTO: 2243 case DRV_TYPE_IO_3V3_ONLY: 2244 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2245 switch (bit) { 2246 case 0 ... 12: 2247 /* regular case, nothing to do */ 2248 break; 2249 case 15: 2250 /* 2251 * drive-strength offset is special, as it is spread 2252 * over 2 registers, the bit data[15] contains bit 0 2253 * of the value while temp[1:0] contains bits 2 and 1 2254 */ 2255 data = (ret & 0x1) << 15; 2256 temp = (ret >> 0x1) & 0x3; 2257 2258 data |= BIT(31); 2259 ret = regmap_write(regmap, reg, data); 2260 if (ret) 2261 return ret; 2262 2263 temp |= (0x3 << 16); 2264 reg += 0x4; 2265 ret = regmap_write(regmap, reg, temp); 2266 2267 return ret; 2268 case 18 ... 21: 2269 /* setting fully enclosed in the second register */ 2270 reg += 4; 2271 bit -= 16; 2272 break; 2273 default: 2274 debug("unsupported bit: %d for pinctrl drive type: %d\n", 2275 bit, drv_type); 2276 return -EINVAL; 2277 } 2278 break; 2279 case DRV_TYPE_IO_DEFAULT: 2280 case DRV_TYPE_IO_1V8_OR_3V0: 2281 case DRV_TYPE_IO_1V8_ONLY: 2282 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2283 break; 2284 default: 2285 debug("unsupported pinctrl drive type: %d\n", 2286 drv_type); 2287 return -EINVAL; 2288 } 2289 2290 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 2291 regmap_read(regmap, reg, &data); 2292 data &= ~(((1 << rmask_bits) - 1) << bit); 2293 } else { 2294 /* enable the write to the equivalent lower bits */ 2295 data = ((1 << rmask_bits) - 1) << (bit + 16); 2296 } 2297 2298 data |= (ret << bit); 2299 ret = regmap_write(regmap, reg, data); 2300 return ret; 2301 } 2302 2303 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2304 { 2305 PIN_CONFIG_BIAS_DISABLE, 2306 PIN_CONFIG_BIAS_PULL_UP, 2307 PIN_CONFIG_BIAS_PULL_DOWN, 2308 PIN_CONFIG_BIAS_BUS_HOLD 2309 }, 2310 { 2311 PIN_CONFIG_BIAS_DISABLE, 2312 PIN_CONFIG_BIAS_PULL_DOWN, 2313 PIN_CONFIG_BIAS_DISABLE, 2314 PIN_CONFIG_BIAS_PULL_UP 2315 }, 2316 }; 2317 2318 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2319 int pin_num, int pull) 2320 { 2321 struct rockchip_pinctrl_priv *priv = bank->priv; 2322 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2323 struct regmap *regmap; 2324 int reg, ret, i, pull_type; 2325 u8 bit; 2326 u32 data; 2327 2328 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 2329 pin_num, pull); 2330 2331 /* rk3066b does support any pulls */ 2332 if (ctrl->type == RK3066B) 2333 return pull ? -EINVAL : 0; 2334 2335 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2336 2337 switch (ctrl->type) { 2338 case RK2928: 2339 case RK3128: 2340 data = BIT(bit + 16); 2341 if (pull == PIN_CONFIG_BIAS_DISABLE) 2342 data |= BIT(bit); 2343 ret = regmap_write(regmap, reg, data); 2344 break; 2345 case PX30: 2346 case RV1108: 2347 case RK1808: 2348 case RK3188: 2349 case RK3288: 2350 case RK3308: 2351 case RK3368: 2352 case RK3399: 2353 /* 2354 * Where need to clean the special mask for 2355 * rockchip_pull_list. 2356 */ 2357 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); 2358 ret = -EINVAL; 2359 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2360 i++) { 2361 if (rockchip_pull_list[pull_type][i] == pull) { 2362 ret = i; 2363 break; 2364 } 2365 } 2366 2367 if (ret < 0) { 2368 debug("unsupported pull setting %d\n", pull); 2369 return ret; 2370 } 2371 2372 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 2373 regmap_read(regmap, reg, &data); 2374 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); 2375 } else { 2376 /* enable the write to the equivalent lower bits */ 2377 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2378 } 2379 2380 data |= (ret << bit); 2381 ret = regmap_write(regmap, reg, data); 2382 break; 2383 default: 2384 debug("unsupported pinctrl type\n"); 2385 return -EINVAL; 2386 } 2387 2388 return ret; 2389 } 2390 2391 #define RK3328_SCHMITT_BITS_PER_PIN 1 2392 #define RK3328_SCHMITT_PINS_PER_REG 16 2393 #define RK3328_SCHMITT_BANK_STRIDE 8 2394 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2395 2396 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2397 int pin_num, 2398 struct regmap **regmap, 2399 int *reg, u8 *bit) 2400 { 2401 struct rockchip_pinctrl_priv *priv = bank->priv; 2402 2403 *regmap = priv->regmap_base; 2404 *reg = RK3328_SCHMITT_GRF_OFFSET; 2405 2406 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2407 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2408 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2409 2410 return 0; 2411 } 2412 2413 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2414 int pin_num, int enable) 2415 { 2416 struct rockchip_pinctrl_priv *priv = bank->priv; 2417 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2418 struct regmap *regmap; 2419 int reg, ret; 2420 u8 bit; 2421 u32 data; 2422 2423 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 2424 pin_num, enable); 2425 2426 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2427 if (ret) 2428 return ret; 2429 2430 /* enable the write to the equivalent lower bits */ 2431 data = BIT(bit + 16) | (enable << bit); 2432 2433 return regmap_write(regmap, reg, data); 2434 } 2435 2436 #define PX30_SLEW_RATE_PMU_OFFSET 0x30 2437 #define PX30_SLEW_RATE_GRF_OFFSET 0x90 2438 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16 2439 #define PX30_SLEW_RATE_BANK_STRIDE 16 2440 #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8 2441 2442 static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, 2443 int pin_num, 2444 struct regmap **regmap, 2445 int *reg, u8 *bit) 2446 { 2447 struct rockchip_pinctrl_priv *priv = bank->priv; 2448 int pins_per_reg; 2449 2450 if (bank->bank_num == 0) { 2451 *regmap = priv->regmap_pmu; 2452 *reg = PX30_SLEW_RATE_PMU_OFFSET; 2453 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 2454 } else { 2455 *regmap = priv->regmap_base; 2456 *reg = PX30_SCHMITT_GRF_OFFSET; 2457 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 2458 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 2459 } 2460 *reg += ((pin_num / pins_per_reg) * 4); 2461 *bit = pin_num % pins_per_reg; 2462 2463 return 0; 2464 } 2465 2466 static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank, 2467 int pin_num, int speed) 2468 { 2469 struct rockchip_pinctrl_priv *priv = bank->priv; 2470 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2471 struct regmap *regmap; 2472 int reg, ret; 2473 u8 bit; 2474 u32 data; 2475 2476 debug("setting slew rate of GPIO%d-%d to %d\n", bank->bank_num, 2477 pin_num, speed); 2478 2479 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit); 2480 if (ret) 2481 return ret; 2482 2483 /* enable the write to the equivalent lower bits */ 2484 data = BIT(bit + 16) | (speed << bit); 2485 2486 return regmap_write(regmap, reg, data); 2487 } 2488 2489 /* 2490 * Pinconf_ops handling 2491 */ 2492 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2493 unsigned int pull) 2494 { 2495 switch (ctrl->type) { 2496 case RK2928: 2497 case RK3128: 2498 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2499 pull == PIN_CONFIG_BIAS_DISABLE); 2500 case RK3066B: 2501 return pull ? false : true; 2502 case PX30: 2503 case RV1108: 2504 case RK1808: 2505 case RK3188: 2506 case RK3288: 2507 case RK3308: 2508 case RK3368: 2509 case RK3399: 2510 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2511 } 2512 2513 return false; 2514 } 2515 2516 /* set the pin config settings for a specified pin */ 2517 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 2518 u32 pin, u32 param, u32 arg) 2519 { 2520 struct rockchip_pinctrl_priv *priv = bank->priv; 2521 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2522 int rc; 2523 2524 switch (param) { 2525 case PIN_CONFIG_BIAS_DISABLE: 2526 rc = rockchip_set_pull(bank, pin, param); 2527 if (rc) 2528 return rc; 2529 break; 2530 2531 case PIN_CONFIG_BIAS_PULL_UP: 2532 case PIN_CONFIG_BIAS_PULL_DOWN: 2533 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2534 case PIN_CONFIG_BIAS_BUS_HOLD: 2535 if (!rockchip_pinconf_pull_valid(ctrl, param)) 2536 return -ENOTSUPP; 2537 2538 if (!arg) 2539 return -EINVAL; 2540 2541 rc = rockchip_set_pull(bank, pin, param); 2542 if (rc) 2543 return rc; 2544 break; 2545 2546 case PIN_CONFIG_DRIVE_STRENGTH: 2547 if (!ctrl->drv_calc_reg) 2548 return -ENOTSUPP; 2549 2550 rc = rockchip_set_drive_perpin(bank, pin, arg); 2551 if (rc < 0) 2552 return rc; 2553 break; 2554 2555 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2556 if (!ctrl->schmitt_calc_reg) 2557 return -ENOTSUPP; 2558 2559 rc = rockchip_set_schmitt(bank, pin, arg); 2560 if (rc < 0) 2561 return rc; 2562 break; 2563 2564 case PIN_CONFIG_SLEW_RATE: 2565 if (!ctrl->slew_rate_calc_reg) 2566 return -ENOTSUPP; 2567 2568 rc = rockchip_set_slew_rate(bank, 2569 pin - bank->pin_base, arg); 2570 if (rc < 0) 2571 return rc; 2572 break; 2573 2574 default: 2575 break; 2576 } 2577 2578 return 0; 2579 } 2580 2581 static const struct pinconf_param rockchip_conf_params[] = { 2582 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 2583 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 2584 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 2585 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 2586 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 2587 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 2588 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 2589 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 2590 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 2591 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, 2592 }; 2593 2594 static int rockchip_pinconf_prop_name_to_param(const char *property, 2595 u32 *default_value) 2596 { 2597 const struct pinconf_param *p, *end; 2598 2599 p = rockchip_conf_params; 2600 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 2601 2602 /* See if this pctldev supports this parameter */ 2603 for (; p < end; p++) { 2604 if (!strcmp(property, p->property)) { 2605 *default_value = p->default_value; 2606 return p->param; 2607 } 2608 } 2609 2610 *default_value = 0; 2611 return -EPERM; 2612 } 2613 2614 static int rockchip_pinctrl_set_state(struct udevice *dev, 2615 struct udevice *config) 2616 { 2617 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2618 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2619 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 2620 u32 bank, pin, mux, conf, arg, default_val; 2621 int ret, count, i; 2622 const char *prop_name; 2623 const void *value; 2624 int prop_len, param; 2625 const u32 *data; 2626 ofnode node; 2627 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 2628 const struct device_node *np; 2629 struct property *pp; 2630 #else 2631 int property_offset, pcfg_node; 2632 const void *blob = gd->fdt_blob; 2633 #endif 2634 data = dev_read_prop(config, "rockchip,pins", &count); 2635 if (count < 0) { 2636 debug("%s: bad array size %d\n", __func__, count); 2637 return -EINVAL; 2638 } 2639 2640 count /= sizeof(u32); 2641 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2642 debug("%s: unsupported pins array count %d\n", 2643 __func__, count); 2644 return -EINVAL; 2645 } 2646 2647 for (i = 0; i < count; i++) 2648 cells[i] = fdt32_to_cpu(data[i]); 2649 2650 for (i = 0; i < (count >> 2); i++) { 2651 bank = cells[4 * i + 0]; 2652 pin = cells[4 * i + 1]; 2653 mux = cells[4 * i + 2]; 2654 conf = cells[4 * i + 3]; 2655 2656 ret = rockchip_verify_config(dev, bank, pin); 2657 if (ret) 2658 return ret; 2659 2660 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2661 if (ret) 2662 return ret; 2663 2664 node = ofnode_get_by_phandle(conf); 2665 if (!ofnode_valid(node)) 2666 return -ENODEV; 2667 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 2668 np = ofnode_to_np(node); 2669 for (pp = np->properties; pp; pp = pp->next) { 2670 prop_name = pp->name; 2671 prop_len = pp->length; 2672 value = pp->value; 2673 #else 2674 pcfg_node = ofnode_to_offset(node); 2675 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2676 value = fdt_getprop_by_offset(blob, property_offset, 2677 &prop_name, &prop_len); 2678 if (!value) 2679 return -ENOENT; 2680 #endif 2681 param = rockchip_pinconf_prop_name_to_param(prop_name, 2682 &default_val); 2683 if (param < 0) 2684 break; 2685 2686 if (prop_len >= sizeof(fdt32_t)) 2687 arg = fdt32_to_cpu(*(fdt32_t *)value); 2688 else 2689 arg = default_val; 2690 2691 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2692 param, arg); 2693 if (ret) { 2694 debug("%s: rockchip_pinconf_set fail: %d\n", 2695 __func__, ret); 2696 return ret; 2697 } 2698 } 2699 } 2700 2701 return 0; 2702 } 2703 2704 static struct pinctrl_ops rockchip_pinctrl_ops = { 2705 .set_state = rockchip_pinctrl_set_state, 2706 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2707 }; 2708 2709 /* Ctrl data specially handle */ 2710 static int rk3308b_ctrl_data_re_init(struct rockchip_pin_ctrl *ctrl) 2711 { 2712 /* 2713 * Special for rk3308b, where we need to replace the recalced 2714 * and routed arrays. 2715 */ 2716 if (soc_is_rk3308b()) { 2717 ctrl->iomux_recalced = rk3308b_mux_recalced_data; 2718 ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data); 2719 ctrl->iomux_routes = rk3308b_mux_route_data; 2720 ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data); 2721 } 2722 2723 return 0; 2724 } 2725 2726 /* retrieve the soc specific data */ 2727 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 2728 { 2729 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2730 struct rockchip_pin_ctrl *ctrl = 2731 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 2732 struct rockchip_pin_bank *bank; 2733 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2734 2735 grf_offs = ctrl->grf_mux_offset; 2736 pmu_offs = ctrl->pmu_mux_offset; 2737 drv_pmu_offs = ctrl->pmu_drv_offset; 2738 drv_grf_offs = ctrl->grf_drv_offset; 2739 bank = ctrl->pin_banks; 2740 2741 /* Ctrl data re-initialize for some Socs */ 2742 if (ctrl->ctrl_data_re_init) { 2743 if (ctrl->ctrl_data_re_init(ctrl)) 2744 return NULL; 2745 } 2746 2747 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2748 int bank_pins = 0; 2749 2750 bank->priv = priv; 2751 bank->pin_base = ctrl->nr_pins; 2752 ctrl->nr_pins += bank->nr_pins; 2753 2754 /* calculate iomux and drv offsets */ 2755 for (j = 0; j < 4; j++) { 2756 struct rockchip_iomux *iom = &bank->iomux[j]; 2757 struct rockchip_drv *drv = &bank->drv[j]; 2758 int inc; 2759 2760 if (bank_pins >= bank->nr_pins) 2761 break; 2762 2763 /* preset iomux offset value, set new start value */ 2764 if (iom->offset >= 0) { 2765 if (iom->type & IOMUX_SOURCE_PMU) 2766 pmu_offs = iom->offset; 2767 else 2768 grf_offs = iom->offset; 2769 } else { /* set current iomux offset */ 2770 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2771 pmu_offs : grf_offs; 2772 } 2773 2774 /* preset drv offset value, set new start value */ 2775 if (drv->offset >= 0) { 2776 if (iom->type & IOMUX_SOURCE_PMU) 2777 drv_pmu_offs = drv->offset; 2778 else 2779 drv_grf_offs = drv->offset; 2780 } else { /* set current drv offset */ 2781 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2782 drv_pmu_offs : drv_grf_offs; 2783 } 2784 2785 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2786 i, j, iom->offset, drv->offset); 2787 2788 /* 2789 * Increase offset according to iomux width. 2790 * 4bit iomux'es are spread over two registers. 2791 */ 2792 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2793 IOMUX_WIDTH_3BIT | 2794 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 2795 if (iom->type & IOMUX_SOURCE_PMU) 2796 pmu_offs += inc; 2797 else 2798 grf_offs += inc; 2799 2800 /* 2801 * Increase offset according to drv width. 2802 * 3bit drive-strenth'es are spread over two registers. 2803 */ 2804 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2805 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2806 inc = 8; 2807 else 2808 inc = 4; 2809 2810 if (iom->type & IOMUX_SOURCE_PMU) 2811 drv_pmu_offs += inc; 2812 else 2813 drv_grf_offs += inc; 2814 2815 bank_pins += 8; 2816 } 2817 2818 /* calculate the per-bank recalced_mask */ 2819 for (j = 0; j < ctrl->niomux_recalced; j++) { 2820 int pin = 0; 2821 2822 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2823 pin = ctrl->iomux_recalced[j].pin; 2824 bank->recalced_mask |= BIT(pin); 2825 } 2826 } 2827 2828 /* calculate the per-bank route_mask */ 2829 for (j = 0; j < ctrl->niomux_routes; j++) { 2830 int pin = 0; 2831 2832 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2833 pin = ctrl->iomux_routes[j].pin; 2834 bank->route_mask |= BIT(pin); 2835 } 2836 } 2837 } 2838 2839 return ctrl; 2840 } 2841 2842 /* SoC data specially handle */ 2843 2844 /* rk3308b SoC data initialize */ 2845 #define RK3308B_GRF_SOC_CON13 0x608 2846 #define RK3308B_GRF_SOC_CON15 0x610 2847 2848 /* RK3308B_GRF_SOC_CON13 */ 2849 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) 2850 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 2851 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 2852 2853 /* RK3308B_GRF_SOC_CON15 */ 2854 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) 2855 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 2856 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 2857 2858 static int rk3308b_soc_data_init(struct rockchip_pinctrl_priv *priv) 2859 { 2860 int ret; 2861 2862 /* 2863 * Enable the special ctrl of selected sources. 2864 */ 2865 if (soc_is_rk3308b()) { 2866 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13, 2867 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | 2868 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | 2869 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); 2870 if (ret) 2871 return ret; 2872 2873 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15, 2874 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | 2875 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | 2876 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); 2877 if (ret) 2878 return ret; 2879 } 2880 2881 return 0; 2882 } 2883 2884 static int rockchip_pinctrl_probe(struct udevice *dev) 2885 { 2886 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2887 struct rockchip_pin_ctrl *ctrl; 2888 struct udevice *syscon; 2889 struct regmap *regmap; 2890 int ret = 0; 2891 2892 /* get rockchip grf syscon phandle */ 2893 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2894 &syscon); 2895 if (ret) { 2896 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 2897 return ret; 2898 } 2899 2900 /* get grf-reg base address */ 2901 regmap = syscon_get_regmap(syscon); 2902 if (!regmap) { 2903 debug("unable to find rockchip grf regmap\n"); 2904 return -ENODEV; 2905 } 2906 priv->regmap_base = regmap; 2907 2908 /* option: get pmu-reg base address */ 2909 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 2910 &syscon); 2911 if (!ret) { 2912 /* get pmugrf-reg base address */ 2913 regmap = syscon_get_regmap(syscon); 2914 if (!regmap) { 2915 debug("unable to find rockchip pmu regmap\n"); 2916 return -ENODEV; 2917 } 2918 priv->regmap_pmu = regmap; 2919 } 2920 2921 ctrl = rockchip_pinctrl_get_soc_data(dev); 2922 if (!ctrl) { 2923 debug("driver data not available\n"); 2924 return -EINVAL; 2925 } 2926 2927 /* Special handle for some Socs */ 2928 if (ctrl->soc_data_init) { 2929 ret = ctrl->soc_data_init(priv); 2930 if (ret) 2931 return ret; 2932 } 2933 2934 priv->ctrl = ctrl; 2935 return 0; 2936 } 2937 2938 static struct rockchip_pin_bank px30_pin_banks[] = { 2939 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2940 IOMUX_SOURCE_PMU, 2941 IOMUX_SOURCE_PMU, 2942 IOMUX_SOURCE_PMU 2943 ), 2944 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2945 IOMUX_WIDTH_4BIT, 2946 IOMUX_WIDTH_4BIT, 2947 IOMUX_WIDTH_4BIT 2948 ), 2949 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2950 IOMUX_WIDTH_4BIT, 2951 IOMUX_WIDTH_4BIT, 2952 IOMUX_WIDTH_4BIT 2953 ), 2954 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2955 IOMUX_WIDTH_4BIT, 2956 IOMUX_WIDTH_4BIT, 2957 IOMUX_WIDTH_4BIT 2958 ), 2959 }; 2960 2961 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2962 .pin_banks = px30_pin_banks, 2963 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2964 .label = "PX30-GPIO", 2965 .type = PX30, 2966 .grf_mux_offset = 0x0, 2967 .pmu_mux_offset = 0x0, 2968 .iomux_routes = px30_mux_route_data, 2969 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2970 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2971 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2972 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2973 .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit, 2974 }; 2975 2976 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2977 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2978 IOMUX_SOURCE_PMU, 2979 IOMUX_SOURCE_PMU, 2980 IOMUX_SOURCE_PMU), 2981 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2982 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2983 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2984 }; 2985 2986 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2987 .pin_banks = rv1108_pin_banks, 2988 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2989 .label = "RV1108-GPIO", 2990 .type = RV1108, 2991 .grf_mux_offset = 0x10, 2992 .pmu_mux_offset = 0x0, 2993 .iomux_recalced = rv1108_mux_recalced_data, 2994 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2995 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2996 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2997 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2998 }; 2999 3000 static struct rockchip_pin_bank rk1808_pin_banks[] = { 3001 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3002 IOMUX_SOURCE_PMU, 3003 IOMUX_SOURCE_PMU, 3004 IOMUX_SOURCE_PMU, 3005 IOMUX_SOURCE_PMU), 3006 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 3007 IOMUX_WIDTH_4BIT, 3008 IOMUX_WIDTH_4BIT, 3009 IOMUX_WIDTH_4BIT, 3010 IOMUX_WIDTH_4BIT), 3011 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3012 IOMUX_WIDTH_4BIT, 3013 IOMUX_WIDTH_4BIT, 3014 IOMUX_WIDTH_4BIT, 3015 IOMUX_WIDTH_4BIT), 3016 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3017 IOMUX_WIDTH_4BIT, 3018 IOMUX_WIDTH_4BIT, 3019 IOMUX_WIDTH_4BIT, 3020 IOMUX_WIDTH_4BIT), 3021 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", 3022 IOMUX_WIDTH_4BIT, 3023 IOMUX_WIDTH_4BIT, 3024 IOMUX_WIDTH_4BIT, 3025 IOMUX_WIDTH_4BIT), 3026 }; 3027 3028 static struct rockchip_pin_ctrl rk1808_pin_ctrl = { 3029 .pin_banks = rk1808_pin_banks, 3030 .nr_banks = ARRAY_SIZE(rk1808_pin_banks), 3031 .label = "RK1808-GPIO", 3032 .type = RK1808, 3033 .iomux_routes = rk1808_mux_route_data, 3034 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data), 3035 .grf_mux_offset = 0x0, 3036 .pmu_mux_offset = 0x0, 3037 .pull_calc_reg = rk1808_calc_pull_reg_and_bit, 3038 .drv_calc_reg = rk1808_calc_drv_reg_and_bit, 3039 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit, 3040 }; 3041 3042 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3043 PIN_BANK(0, 32, "gpio0"), 3044 PIN_BANK(1, 32, "gpio1"), 3045 PIN_BANK(2, 32, "gpio2"), 3046 PIN_BANK(3, 32, "gpio3"), 3047 }; 3048 3049 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3050 .pin_banks = rk2928_pin_banks, 3051 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3052 .label = "RK2928-GPIO", 3053 .type = RK2928, 3054 .grf_mux_offset = 0xa8, 3055 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3056 }; 3057 3058 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3059 PIN_BANK(0, 32, "gpio0"), 3060 PIN_BANK(1, 32, "gpio1"), 3061 PIN_BANK(2, 32, "gpio2"), 3062 }; 3063 3064 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3065 .pin_banks = rk3036_pin_banks, 3066 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3067 .label = "RK3036-GPIO", 3068 .type = RK2928, 3069 .grf_mux_offset = 0xa8, 3070 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3071 }; 3072 3073 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3074 PIN_BANK(0, 32, "gpio0"), 3075 PIN_BANK(1, 32, "gpio1"), 3076 PIN_BANK(2, 32, "gpio2"), 3077 PIN_BANK(3, 32, "gpio3"), 3078 PIN_BANK(4, 32, "gpio4"), 3079 PIN_BANK(6, 16, "gpio6"), 3080 }; 3081 3082 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3083 .pin_banks = rk3066a_pin_banks, 3084 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3085 .label = "RK3066a-GPIO", 3086 .type = RK2928, 3087 .grf_mux_offset = 0xa8, 3088 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3089 }; 3090 3091 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3092 PIN_BANK(0, 32, "gpio0"), 3093 PIN_BANK(1, 32, "gpio1"), 3094 PIN_BANK(2, 32, "gpio2"), 3095 PIN_BANK(3, 32, "gpio3"), 3096 }; 3097 3098 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3099 .pin_banks = rk3066b_pin_banks, 3100 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3101 .label = "RK3066b-GPIO", 3102 .type = RK3066B, 3103 .grf_mux_offset = 0x60, 3104 }; 3105 3106 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3107 PIN_BANK(0, 32, "gpio0"), 3108 PIN_BANK(1, 32, "gpio1"), 3109 PIN_BANK(2, 32, "gpio2"), 3110 PIN_BANK(3, 32, "gpio3"), 3111 }; 3112 3113 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3114 .pin_banks = rk3128_pin_banks, 3115 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3116 .label = "RK3128-GPIO", 3117 .type = RK3128, 3118 .grf_mux_offset = 0xa8, 3119 .iomux_recalced = rk3128_mux_recalced_data, 3120 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3121 .iomux_routes = rk3128_mux_route_data, 3122 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3123 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3124 }; 3125 3126 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3127 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3128 PIN_BANK(1, 32, "gpio1"), 3129 PIN_BANK(2, 32, "gpio2"), 3130 PIN_BANK(3, 32, "gpio3"), 3131 }; 3132 3133 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3134 .pin_banks = rk3188_pin_banks, 3135 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3136 .label = "RK3188-GPIO", 3137 .type = RK3188, 3138 .grf_mux_offset = 0x60, 3139 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3140 }; 3141 3142 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3143 PIN_BANK(0, 32, "gpio0"), 3144 PIN_BANK(1, 32, "gpio1"), 3145 PIN_BANK(2, 32, "gpio2"), 3146 PIN_BANK(3, 32, "gpio3"), 3147 }; 3148 3149 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3150 .pin_banks = rk3228_pin_banks, 3151 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3152 .label = "RK3228-GPIO", 3153 .type = RK3288, 3154 .grf_mux_offset = 0x0, 3155 .iomux_routes = rk3228_mux_route_data, 3156 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3157 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3158 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3159 }; 3160 3161 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3162 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 3163 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3164 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3165 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3166 IOMUX_UNROUTED, 3167 DRV_TYPE_WRITABLE_32BIT, 3168 DRV_TYPE_WRITABLE_32BIT, 3169 DRV_TYPE_WRITABLE_32BIT, 3170 0, 3171 PULL_TYPE_WRITABLE_32BIT, 3172 PULL_TYPE_WRITABLE_32BIT, 3173 PULL_TYPE_WRITABLE_32BIT, 3174 0 3175 ), 3176 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3177 IOMUX_UNROUTED, 3178 IOMUX_UNROUTED, 3179 0 3180 ), 3181 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3182 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3183 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3184 IOMUX_WIDTH_4BIT, 3185 0, 3186 0 3187 ), 3188 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3189 0, 3190 0, 3191 IOMUX_UNROUTED 3192 ), 3193 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3194 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3195 0, 3196 IOMUX_WIDTH_4BIT, 3197 IOMUX_UNROUTED 3198 ), 3199 PIN_BANK(8, 16, "gpio8"), 3200 }; 3201 3202 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3203 .pin_banks = rk3288_pin_banks, 3204 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3205 .label = "RK3288-GPIO", 3206 .type = RK3288, 3207 .grf_mux_offset = 0x0, 3208 .pmu_mux_offset = 0x84, 3209 .iomux_routes = rk3288_mux_route_data, 3210 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3211 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3212 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3213 }; 3214 3215 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3216 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 3217 IOMUX_8WIDTH_2BIT, 3218 IOMUX_8WIDTH_2BIT, 3219 IOMUX_8WIDTH_2BIT), 3220 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 3221 IOMUX_8WIDTH_2BIT, 3222 IOMUX_8WIDTH_2BIT, 3223 IOMUX_8WIDTH_2BIT), 3224 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 3225 IOMUX_8WIDTH_2BIT, 3226 IOMUX_8WIDTH_2BIT, 3227 IOMUX_8WIDTH_2BIT), 3228 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 3229 IOMUX_8WIDTH_2BIT, 3230 IOMUX_8WIDTH_2BIT, 3231 IOMUX_8WIDTH_2BIT), 3232 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 3233 IOMUX_8WIDTH_2BIT, 3234 IOMUX_8WIDTH_2BIT, 3235 IOMUX_8WIDTH_2BIT), 3236 }; 3237 3238 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3239 .pin_banks = rk3308_pin_banks, 3240 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3241 .label = "RK3308-GPIO", 3242 .type = RK3308, 3243 .grf_mux_offset = 0x0, 3244 .iomux_recalced = rk3308_mux_recalced_data, 3245 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3246 .iomux_routes = rk3308_mux_route_data, 3247 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3248 .ctrl_data_re_init = rk3308b_ctrl_data_re_init, 3249 .soc_data_init = rk3308b_soc_data_init, 3250 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3251 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3252 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3253 }; 3254 3255 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3256 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3257 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3258 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3259 IOMUX_WIDTH_3BIT, 3260 IOMUX_WIDTH_3BIT, 3261 0), 3262 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3263 IOMUX_WIDTH_3BIT, 3264 IOMUX_WIDTH_3BIT, 3265 0, 3266 0), 3267 }; 3268 3269 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3270 .pin_banks = rk3328_pin_banks, 3271 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3272 .label = "RK3328-GPIO", 3273 .type = RK3288, 3274 .grf_mux_offset = 0x0, 3275 .iomux_recalced = rk3328_mux_recalced_data, 3276 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3277 .iomux_routes = rk3328_mux_route_data, 3278 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3279 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3280 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3281 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3282 }; 3283 3284 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3285 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3286 IOMUX_SOURCE_PMU, 3287 IOMUX_SOURCE_PMU, 3288 IOMUX_SOURCE_PMU 3289 ), 3290 PIN_BANK(1, 32, "gpio1"), 3291 PIN_BANK(2, 32, "gpio2"), 3292 PIN_BANK(3, 32, "gpio3"), 3293 }; 3294 3295 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3296 .pin_banks = rk3368_pin_banks, 3297 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3298 .label = "RK3368-GPIO", 3299 .type = RK3368, 3300 .grf_mux_offset = 0x0, 3301 .pmu_mux_offset = 0x0, 3302 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3303 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3304 }; 3305 3306 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3307 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3308 IOMUX_SOURCE_PMU, 3309 IOMUX_SOURCE_PMU, 3310 IOMUX_SOURCE_PMU, 3311 IOMUX_SOURCE_PMU, 3312 DRV_TYPE_IO_1V8_ONLY, 3313 DRV_TYPE_IO_1V8_ONLY, 3314 DRV_TYPE_IO_DEFAULT, 3315 DRV_TYPE_IO_DEFAULT, 3316 0x80, 3317 0x88, 3318 -1, 3319 -1, 3320 PULL_TYPE_IO_1V8_ONLY, 3321 PULL_TYPE_IO_1V8_ONLY, 3322 PULL_TYPE_IO_DEFAULT, 3323 PULL_TYPE_IO_DEFAULT 3324 ), 3325 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3326 IOMUX_SOURCE_PMU, 3327 IOMUX_SOURCE_PMU, 3328 IOMUX_SOURCE_PMU, 3329 DRV_TYPE_IO_1V8_OR_3V0, 3330 DRV_TYPE_IO_1V8_OR_3V0, 3331 DRV_TYPE_IO_1V8_OR_3V0, 3332 DRV_TYPE_IO_1V8_OR_3V0, 3333 0xa0, 3334 0xa8, 3335 0xb0, 3336 0xb8 3337 ), 3338 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3339 DRV_TYPE_IO_1V8_OR_3V0, 3340 DRV_TYPE_IO_1V8_ONLY, 3341 DRV_TYPE_IO_1V8_ONLY, 3342 PULL_TYPE_IO_DEFAULT, 3343 PULL_TYPE_IO_DEFAULT, 3344 PULL_TYPE_IO_1V8_ONLY, 3345 PULL_TYPE_IO_1V8_ONLY 3346 ), 3347 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3348 DRV_TYPE_IO_3V3_ONLY, 3349 DRV_TYPE_IO_3V3_ONLY, 3350 DRV_TYPE_IO_1V8_OR_3V0 3351 ), 3352 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3353 DRV_TYPE_IO_1V8_3V0_AUTO, 3354 DRV_TYPE_IO_1V8_OR_3V0, 3355 DRV_TYPE_IO_1V8_OR_3V0 3356 ), 3357 }; 3358 3359 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3360 .pin_banks = rk3399_pin_banks, 3361 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3362 .label = "RK3399-GPIO", 3363 .type = RK3399, 3364 .grf_mux_offset = 0xe000, 3365 .pmu_mux_offset = 0x0, 3366 .grf_drv_offset = 0xe100, 3367 .pmu_drv_offset = 0x80, 3368 .iomux_routes = rk3399_mux_route_data, 3369 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3370 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3371 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3372 }; 3373 3374 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 3375 { .compatible = "rockchip,px30-pinctrl", 3376 .data = (ulong)&px30_pin_ctrl }, 3377 { .compatible = "rockchip,rv1108-pinctrl", 3378 .data = (ulong)&rv1108_pin_ctrl }, 3379 { .compatible = "rockchip,rk1808-pinctrl", 3380 .data = (ulong)&rk1808_pin_ctrl }, 3381 { .compatible = "rockchip,rk2928-pinctrl", 3382 .data = (ulong)&rk2928_pin_ctrl }, 3383 { .compatible = "rockchip,rk3036-pinctrl", 3384 .data = (ulong)&rk3036_pin_ctrl }, 3385 { .compatible = "rockchip,rk3066a-pinctrl", 3386 .data = (ulong)&rk3066a_pin_ctrl }, 3387 { .compatible = "rockchip,rk3066b-pinctrl", 3388 .data = (ulong)&rk3066b_pin_ctrl }, 3389 { .compatible = "rockchip,rk3128-pinctrl", 3390 .data = (ulong)&rk3128_pin_ctrl }, 3391 { .compatible = "rockchip,rk3188-pinctrl", 3392 .data = (ulong)&rk3188_pin_ctrl }, 3393 { .compatible = "rockchip,rk3228-pinctrl", 3394 .data = (ulong)&rk3228_pin_ctrl }, 3395 { .compatible = "rockchip,rk3288-pinctrl", 3396 .data = (ulong)&rk3288_pin_ctrl }, 3397 { .compatible = "rockchip,rk3308-pinctrl", 3398 .data = (ulong)&rk3308_pin_ctrl }, 3399 { .compatible = "rockchip,rk3328-pinctrl", 3400 .data = (ulong)&rk3328_pin_ctrl }, 3401 { .compatible = "rockchip,rk3368-pinctrl", 3402 .data = (ulong)&rk3368_pin_ctrl }, 3403 { .compatible = "rockchip,rk3399-pinctrl", 3404 .data = (ulong)&rk3399_pin_ctrl }, 3405 {}, 3406 }; 3407 3408 U_BOOT_DRIVER(pinctrl_rockchip) = { 3409 .name = "rockchip_pinctrl", 3410 .id = UCLASS_PINCTRL, 3411 .of_match = rockchip_pinctrl_dt_match, 3412 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 3413 .ops = &rockchip_pinctrl_ops, 3414 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 3415 .bind = dm_scan_fdt_dev, 3416 #endif 3417 .probe = rockchip_pinctrl_probe, 3418 }; 3419