1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 14 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 15 #define RK_FUNC_GPIO 0 16 #define MAX_ROCKCHIP_PINS_ENTRIES 30 17 18 enum rockchip_pinctrl_type { 19 PX30, 20 RV1108, 21 RK2928, 22 RK3066B, 23 RK3128, 24 RK3188, 25 RK3288, 26 RK3368, 27 RK3399, 28 }; 29 30 /** 31 * Encode variants of iomux registers into a type variable 32 */ 33 #define IOMUX_GPIO_ONLY BIT(0) 34 #define IOMUX_WIDTH_4BIT BIT(1) 35 #define IOMUX_SOURCE_PMU BIT(2) 36 #define IOMUX_UNROUTED BIT(3) 37 #define IOMUX_WIDTH_3BIT BIT(4) 38 39 /** 40 * @type: iomux variant using IOMUX_* constants 41 * @offset: if initialized to -1 it will be autocalculated, by specifying 42 * an initial offset value the relevant source offset can be reset 43 * to a new value for autocalculating the following iomux registers. 44 */ 45 struct rockchip_iomux { 46 int type; 47 int offset; 48 }; 49 50 /** 51 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 52 */ 53 enum rockchip_pin_drv_type { 54 DRV_TYPE_IO_DEFAULT = 0, 55 DRV_TYPE_IO_1V8_OR_3V0, 56 DRV_TYPE_IO_1V8_ONLY, 57 DRV_TYPE_IO_1V8_3V0_AUTO, 58 DRV_TYPE_IO_3V3_ONLY, 59 DRV_TYPE_MAX 60 }; 61 62 /** 63 * enum type index corresponding to rockchip_pull_list arrays index. 64 */ 65 enum rockchip_pin_pull_type { 66 PULL_TYPE_IO_DEFAULT = 0, 67 PULL_TYPE_IO_1V8_ONLY, 68 PULL_TYPE_MAX 69 }; 70 71 /** 72 * @drv_type: drive strength variant using rockchip_perpin_drv_type 73 * @offset: if initialized to -1 it will be autocalculated, by specifying 74 * an initial offset value the relevant source offset can be reset 75 * to a new value for autocalculating the following drive strength 76 * registers. if used chips own cal_drv func instead to calculate 77 * registers offset, the variant could be ignored. 78 */ 79 struct rockchip_drv { 80 enum rockchip_pin_drv_type drv_type; 81 int offset; 82 }; 83 84 /** 85 * @priv: common pinctrl private basedata 86 * @pin_base: first pin number 87 * @nr_pins: number of pins in this bank 88 * @name: name of the bank 89 * @bank_num: number of the bank, to account for holes 90 * @iomux: array describing the 4 iomux sources of the bank 91 * @drv: array describing the 4 drive strength sources of the bank 92 * @pull_type: array describing the 4 pull type sources of the bank 93 * @recalced_mask: bits describing the mux recalced pins of per bank 94 * @route_mask: bits describing the routing pins of per bank 95 */ 96 struct rockchip_pin_bank { 97 struct rockchip_pinctrl_priv *priv; 98 u32 pin_base; 99 u8 nr_pins; 100 char *name; 101 u8 bank_num; 102 struct rockchip_iomux iomux[4]; 103 struct rockchip_drv drv[4]; 104 enum rockchip_pin_pull_type pull_type[4]; 105 u32 recalced_mask; 106 u32 route_mask; 107 }; 108 109 #define PIN_BANK(id, pins, label) \ 110 { \ 111 .bank_num = id, \ 112 .nr_pins = pins, \ 113 .name = label, \ 114 .iomux = { \ 115 { .offset = -1 }, \ 116 { .offset = -1 }, \ 117 { .offset = -1 }, \ 118 { .offset = -1 }, \ 119 }, \ 120 } 121 122 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 123 { \ 124 .bank_num = id, \ 125 .nr_pins = pins, \ 126 .name = label, \ 127 .iomux = { \ 128 { .type = iom0, .offset = -1 }, \ 129 { .type = iom1, .offset = -1 }, \ 130 { .type = iom2, .offset = -1 }, \ 131 { .type = iom3, .offset = -1 }, \ 132 }, \ 133 } 134 135 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 136 { \ 137 .bank_num = id, \ 138 .nr_pins = pins, \ 139 .name = label, \ 140 .iomux = { \ 141 { .offset = -1 }, \ 142 { .offset = -1 }, \ 143 { .offset = -1 }, \ 144 { .offset = -1 }, \ 145 }, \ 146 .drv = { \ 147 { .drv_type = type0, .offset = -1 }, \ 148 { .drv_type = type1, .offset = -1 }, \ 149 { .drv_type = type2, .offset = -1 }, \ 150 { .drv_type = type3, .offset = -1 }, \ 151 }, \ 152 } 153 154 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 155 drv2, drv3, pull0, pull1, \ 156 pull2, pull3) \ 157 { \ 158 .bank_num = id, \ 159 .nr_pins = pins, \ 160 .name = label, \ 161 .iomux = { \ 162 { .offset = -1 }, \ 163 { .offset = -1 }, \ 164 { .offset = -1 }, \ 165 { .offset = -1 }, \ 166 }, \ 167 .drv = { \ 168 { .drv_type = drv0, .offset = -1 }, \ 169 { .drv_type = drv1, .offset = -1 }, \ 170 { .drv_type = drv2, .offset = -1 }, \ 171 { .drv_type = drv3, .offset = -1 }, \ 172 }, \ 173 .pull_type[0] = pull0, \ 174 .pull_type[1] = pull1, \ 175 .pull_type[2] = pull2, \ 176 .pull_type[3] = pull3, \ 177 } 178 179 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 180 iom2, iom3, drv0, drv1, drv2, \ 181 drv3, offset0, offset1, \ 182 offset2, offset3) \ 183 { \ 184 .bank_num = id, \ 185 .nr_pins = pins, \ 186 .name = label, \ 187 .iomux = { \ 188 { .type = iom0, .offset = -1 }, \ 189 { .type = iom1, .offset = -1 }, \ 190 { .type = iom2, .offset = -1 }, \ 191 { .type = iom3, .offset = -1 }, \ 192 }, \ 193 .drv = { \ 194 { .drv_type = drv0, .offset = offset0 }, \ 195 { .drv_type = drv1, .offset = offset1 }, \ 196 { .drv_type = drv2, .offset = offset2 }, \ 197 { .drv_type = drv3, .offset = offset3 }, \ 198 }, \ 199 } 200 201 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 202 label, iom0, iom1, iom2, \ 203 iom3, drv0, drv1, drv2, \ 204 drv3, offset0, offset1, \ 205 offset2, offset3, pull0, \ 206 pull1, pull2, pull3) \ 207 { \ 208 .bank_num = id, \ 209 .nr_pins = pins, \ 210 .name = label, \ 211 .iomux = { \ 212 { .type = iom0, .offset = -1 }, \ 213 { .type = iom1, .offset = -1 }, \ 214 { .type = iom2, .offset = -1 }, \ 215 { .type = iom3, .offset = -1 }, \ 216 }, \ 217 .drv = { \ 218 { .drv_type = drv0, .offset = offset0 }, \ 219 { .drv_type = drv1, .offset = offset1 }, \ 220 { .drv_type = drv2, .offset = offset2 }, \ 221 { .drv_type = drv3, .offset = offset3 }, \ 222 }, \ 223 .pull_type[0] = pull0, \ 224 .pull_type[1] = pull1, \ 225 .pull_type[2] = pull2, \ 226 .pull_type[3] = pull3, \ 227 } 228 229 /** 230 * struct rockchip_mux_recalced_data: represent a pin iomux data. 231 * @num: bank number. 232 * @pin: pin number. 233 * @bit: index at register. 234 * @reg: register offset. 235 * @mask: mask bit 236 */ 237 struct rockchip_mux_recalced_data { 238 u8 num; 239 u8 pin; 240 u32 reg; 241 u8 bit; 242 u8 mask; 243 }; 244 245 /** 246 * struct rockchip_mux_recalced_data: represent a pin iomux data. 247 * @bank_num: bank number. 248 * @pin: index at register or used to calc index. 249 * @func: the min pin. 250 * @route_offset: the max pin. 251 * @route_val: the register offset. 252 */ 253 struct rockchip_mux_route_data { 254 u8 bank_num; 255 u8 pin; 256 u8 func; 257 u32 route_offset; 258 u32 route_val; 259 }; 260 261 /** 262 */ 263 struct rockchip_pin_ctrl { 264 struct rockchip_pin_bank *pin_banks; 265 u32 nr_banks; 266 u32 nr_pins; 267 char *label; 268 enum rockchip_pinctrl_type type; 269 int grf_mux_offset; 270 int pmu_mux_offset; 271 int grf_drv_offset; 272 int pmu_drv_offset; 273 struct rockchip_mux_recalced_data *iomux_recalced; 274 u32 niomux_recalced; 275 struct rockchip_mux_route_data *iomux_routes; 276 u32 niomux_routes; 277 278 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 279 int pin_num, struct regmap **regmap, 280 int *reg, u8 *bit); 281 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 282 int pin_num, struct regmap **regmap, 283 int *reg, u8 *bit); 284 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 285 int pin_num, struct regmap **regmap, 286 int *reg, u8 *bit); 287 }; 288 289 /** 290 */ 291 struct rockchip_pinctrl_priv { 292 struct rockchip_pin_ctrl *ctrl; 293 struct regmap *regmap_base; 294 struct regmap *regmap_pmu; 295 296 }; 297 298 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 299 { 300 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 301 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 302 303 if (bank >= ctrl->nr_banks) { 304 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 305 return -EINVAL; 306 } 307 308 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 309 debug("pin conf pin %d >= %d\n", pin, 310 MAX_ROCKCHIP_GPIO_PER_BANK); 311 return -EINVAL; 312 } 313 314 return 0; 315 } 316 317 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 318 { 319 .num = 1, 320 .pin = 0, 321 .reg = 0x418, 322 .bit = 0, 323 .mask = 0x3 324 }, { 325 .num = 1, 326 .pin = 1, 327 .reg = 0x418, 328 .bit = 2, 329 .mask = 0x3 330 }, { 331 .num = 1, 332 .pin = 2, 333 .reg = 0x418, 334 .bit = 4, 335 .mask = 0x3 336 }, { 337 .num = 1, 338 .pin = 3, 339 .reg = 0x418, 340 .bit = 6, 341 .mask = 0x3 342 }, { 343 .num = 1, 344 .pin = 4, 345 .reg = 0x418, 346 .bit = 8, 347 .mask = 0x3 348 }, { 349 .num = 1, 350 .pin = 5, 351 .reg = 0x418, 352 .bit = 10, 353 .mask = 0x3 354 }, { 355 .num = 1, 356 .pin = 6, 357 .reg = 0x418, 358 .bit = 12, 359 .mask = 0x3 360 }, { 361 .num = 1, 362 .pin = 7, 363 .reg = 0x418, 364 .bit = 14, 365 .mask = 0x3 366 }, { 367 .num = 1, 368 .pin = 8, 369 .reg = 0x41c, 370 .bit = 0, 371 .mask = 0x3 372 }, { 373 .num = 1, 374 .pin = 9, 375 .reg = 0x41c, 376 .bit = 2, 377 .mask = 0x3 378 }, 379 }; 380 381 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 382 { 383 .num = 2, 384 .pin = 20, 385 .reg = 0xe8, 386 .bit = 0, 387 .mask = 0x7 388 }, { 389 .num = 2, 390 .pin = 21, 391 .reg = 0xe8, 392 .bit = 4, 393 .mask = 0x7 394 }, { 395 .num = 2, 396 .pin = 22, 397 .reg = 0xe8, 398 .bit = 8, 399 .mask = 0x7 400 }, { 401 .num = 2, 402 .pin = 23, 403 .reg = 0xe8, 404 .bit = 12, 405 .mask = 0x7 406 }, { 407 .num = 2, 408 .pin = 24, 409 .reg = 0xd4, 410 .bit = 12, 411 .mask = 0x7 412 }, 413 }; 414 415 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 416 { 417 .num = 2, 418 .pin = 12, 419 .reg = 0x24, 420 .bit = 8, 421 .mask = 0x3 422 }, { 423 .num = 2, 424 .pin = 15, 425 .reg = 0x28, 426 .bit = 0, 427 .mask = 0x7 428 }, { 429 .num = 2, 430 .pin = 23, 431 .reg = 0x30, 432 .bit = 14, 433 .mask = 0x3 434 }, 435 }; 436 437 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 438 int *reg, u8 *bit, int *mask) 439 { 440 struct rockchip_pinctrl_priv *priv = bank->priv; 441 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 442 struct rockchip_mux_recalced_data *data; 443 int i; 444 445 for (i = 0; i < ctrl->niomux_recalced; i++) { 446 data = &ctrl->iomux_recalced[i]; 447 if (data->num == bank->bank_num && 448 data->pin == pin) 449 break; 450 } 451 452 if (i >= ctrl->niomux_recalced) 453 return; 454 455 *reg = data->reg; 456 *mask = data->mask; 457 *bit = data->bit; 458 } 459 460 static struct rockchip_mux_route_data px30_mux_route_data[] = { 461 { 462 /* cif-d2m0 */ 463 .bank_num = 2, 464 .pin = 0, 465 .func = 1, 466 .route_offset = 0x184, 467 .route_val = BIT(16 + 7), 468 }, { 469 /* cif-d2m1 */ 470 .bank_num = 3, 471 .pin = 3, 472 .func = 3, 473 .route_offset = 0x184, 474 .route_val = BIT(16 + 7) | BIT(7), 475 }, { 476 /* pdm-m0 */ 477 .bank_num = 3, 478 .pin = 22, 479 .func = 2, 480 .route_offset = 0x184, 481 .route_val = BIT(16 + 8), 482 }, { 483 /* pdm-m1 */ 484 .bank_num = 2, 485 .pin = 22, 486 .func = 1, 487 .route_offset = 0x184, 488 .route_val = BIT(16 + 8) | BIT(8), 489 }, { 490 /* uart2-rxm0 */ 491 .bank_num = 1, 492 .pin = 27, 493 .func = 2, 494 .route_offset = 0x184, 495 .route_val = BIT(16 + 10), 496 }, { 497 /* uart2-rxm1 */ 498 .bank_num = 2, 499 .pin = 14, 500 .func = 2, 501 .route_offset = 0x184, 502 .route_val = BIT(16 + 10) | BIT(10), 503 }, { 504 /* uart3-rxm0 */ 505 .bank_num = 0, 506 .pin = 17, 507 .func = 2, 508 .route_offset = 0x184, 509 .route_val = BIT(16 + 9), 510 }, { 511 /* uart3-rxm1 */ 512 .bank_num = 1, 513 .pin = 15, 514 .func = 2, 515 .route_offset = 0x184, 516 .route_val = BIT(16 + 9) | BIT(9), 517 }, 518 }; 519 520 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 521 { 522 /* spi-0 */ 523 .bank_num = 1, 524 .pin = 10, 525 .func = 1, 526 .route_offset = 0x144, 527 .route_val = BIT(16 + 3) | BIT(16 + 4), 528 }, { 529 /* spi-1 */ 530 .bank_num = 1, 531 .pin = 27, 532 .func = 3, 533 .route_offset = 0x144, 534 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 535 }, { 536 /* spi-2 */ 537 .bank_num = 0, 538 .pin = 13, 539 .func = 2, 540 .route_offset = 0x144, 541 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 542 }, { 543 /* i2s-0 */ 544 .bank_num = 1, 545 .pin = 5, 546 .func = 1, 547 .route_offset = 0x144, 548 .route_val = BIT(16 + 5), 549 }, { 550 /* i2s-1 */ 551 .bank_num = 0, 552 .pin = 14, 553 .func = 1, 554 .route_offset = 0x144, 555 .route_val = BIT(16 + 5) | BIT(5), 556 }, { 557 /* emmc-0 */ 558 .bank_num = 1, 559 .pin = 22, 560 .func = 2, 561 .route_offset = 0x144, 562 .route_val = BIT(16 + 6), 563 }, { 564 /* emmc-1 */ 565 .bank_num = 2, 566 .pin = 4, 567 .func = 2, 568 .route_offset = 0x144, 569 .route_val = BIT(16 + 6) | BIT(6), 570 }, 571 }; 572 573 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 574 { 575 /* pwm0-0 */ 576 .bank_num = 0, 577 .pin = 26, 578 .func = 1, 579 .route_offset = 0x50, 580 .route_val = BIT(16), 581 }, { 582 /* pwm0-1 */ 583 .bank_num = 3, 584 .pin = 21, 585 .func = 1, 586 .route_offset = 0x50, 587 .route_val = BIT(16) | BIT(0), 588 }, { 589 /* pwm1-0 */ 590 .bank_num = 0, 591 .pin = 27, 592 .func = 1, 593 .route_offset = 0x50, 594 .route_val = BIT(16 + 1), 595 }, { 596 /* pwm1-1 */ 597 .bank_num = 0, 598 .pin = 30, 599 .func = 2, 600 .route_offset = 0x50, 601 .route_val = BIT(16 + 1) | BIT(1), 602 }, { 603 /* pwm2-0 */ 604 .bank_num = 0, 605 .pin = 28, 606 .func = 1, 607 .route_offset = 0x50, 608 .route_val = BIT(16 + 2), 609 }, { 610 /* pwm2-1 */ 611 .bank_num = 1, 612 .pin = 12, 613 .func = 2, 614 .route_offset = 0x50, 615 .route_val = BIT(16 + 2) | BIT(2), 616 }, { 617 /* pwm3-0 */ 618 .bank_num = 3, 619 .pin = 26, 620 .func = 1, 621 .route_offset = 0x50, 622 .route_val = BIT(16 + 3), 623 }, { 624 /* pwm3-1 */ 625 .bank_num = 1, 626 .pin = 11, 627 .func = 2, 628 .route_offset = 0x50, 629 .route_val = BIT(16 + 3) | BIT(3), 630 }, { 631 /* sdio-0_d0 */ 632 .bank_num = 1, 633 .pin = 1, 634 .func = 1, 635 .route_offset = 0x50, 636 .route_val = BIT(16 + 4), 637 }, { 638 /* sdio-1_d0 */ 639 .bank_num = 3, 640 .pin = 2, 641 .func = 1, 642 .route_offset = 0x50, 643 .route_val = BIT(16 + 4) | BIT(4), 644 }, { 645 /* spi-0_rx */ 646 .bank_num = 0, 647 .pin = 13, 648 .func = 2, 649 .route_offset = 0x50, 650 .route_val = BIT(16 + 5), 651 }, { 652 /* spi-1_rx */ 653 .bank_num = 2, 654 .pin = 0, 655 .func = 2, 656 .route_offset = 0x50, 657 .route_val = BIT(16 + 5) | BIT(5), 658 }, { 659 /* emmc-0_cmd */ 660 .bank_num = 1, 661 .pin = 22, 662 .func = 2, 663 .route_offset = 0x50, 664 .route_val = BIT(16 + 7), 665 }, { 666 /* emmc-1_cmd */ 667 .bank_num = 2, 668 .pin = 4, 669 .func = 2, 670 .route_offset = 0x50, 671 .route_val = BIT(16 + 7) | BIT(7), 672 }, { 673 /* uart2-0_rx */ 674 .bank_num = 1, 675 .pin = 19, 676 .func = 2, 677 .route_offset = 0x50, 678 .route_val = BIT(16 + 8), 679 }, { 680 /* uart2-1_rx */ 681 .bank_num = 1, 682 .pin = 10, 683 .func = 2, 684 .route_offset = 0x50, 685 .route_val = BIT(16 + 8) | BIT(8), 686 }, { 687 /* uart1-0_rx */ 688 .bank_num = 1, 689 .pin = 10, 690 .func = 1, 691 .route_offset = 0x50, 692 .route_val = BIT(16 + 11), 693 }, { 694 /* uart1-1_rx */ 695 .bank_num = 3, 696 .pin = 13, 697 .func = 1, 698 .route_offset = 0x50, 699 .route_val = BIT(16 + 11) | BIT(11), 700 }, 701 }; 702 703 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 704 { 705 /* edphdmi_cecinoutt1 */ 706 .bank_num = 7, 707 .pin = 16, 708 .func = 2, 709 .route_offset = 0x264, 710 .route_val = BIT(16 + 12) | BIT(12), 711 }, { 712 /* edphdmi_cecinout */ 713 .bank_num = 7, 714 .pin = 23, 715 .func = 4, 716 .route_offset = 0x264, 717 .route_val = BIT(16 + 12), 718 }, 719 }; 720 721 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 722 { 723 /* uart2dbg_rxm0 */ 724 .bank_num = 1, 725 .pin = 1, 726 .func = 2, 727 .route_offset = 0x50, 728 .route_val = BIT(16) | BIT(16 + 1), 729 }, { 730 /* uart2dbg_rxm1 */ 731 .bank_num = 2, 732 .pin = 1, 733 .func = 1, 734 .route_offset = 0x50, 735 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 736 }, { 737 /* gmac-m1_rxd0 */ 738 .bank_num = 1, 739 .pin = 11, 740 .func = 2, 741 .route_offset = 0x50, 742 .route_val = BIT(16 + 2) | BIT(2), 743 }, { 744 /* gmac-m1-optimized_rxd3 */ 745 .bank_num = 1, 746 .pin = 14, 747 .func = 2, 748 .route_offset = 0x50, 749 .route_val = BIT(16 + 10) | BIT(10), 750 }, { 751 /* pdm_sdi0m0 */ 752 .bank_num = 2, 753 .pin = 19, 754 .func = 2, 755 .route_offset = 0x50, 756 .route_val = BIT(16 + 3), 757 }, { 758 /* pdm_sdi0m1 */ 759 .bank_num = 1, 760 .pin = 23, 761 .func = 3, 762 .route_offset = 0x50, 763 .route_val = BIT(16 + 3) | BIT(3), 764 }, { 765 /* spi_rxdm2 */ 766 .bank_num = 3, 767 .pin = 2, 768 .func = 4, 769 .route_offset = 0x50, 770 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 771 }, { 772 /* i2s2_sdim0 */ 773 .bank_num = 1, 774 .pin = 24, 775 .func = 1, 776 .route_offset = 0x50, 777 .route_val = BIT(16 + 6), 778 }, { 779 /* i2s2_sdim1 */ 780 .bank_num = 3, 781 .pin = 2, 782 .func = 6, 783 .route_offset = 0x50, 784 .route_val = BIT(16 + 6) | BIT(6), 785 }, { 786 /* card_iom1 */ 787 .bank_num = 2, 788 .pin = 22, 789 .func = 3, 790 .route_offset = 0x50, 791 .route_val = BIT(16 + 7) | BIT(7), 792 }, { 793 /* tsp_d5m1 */ 794 .bank_num = 2, 795 .pin = 16, 796 .func = 3, 797 .route_offset = 0x50, 798 .route_val = BIT(16 + 8) | BIT(8), 799 }, { 800 /* cif_data5m1 */ 801 .bank_num = 2, 802 .pin = 16, 803 .func = 4, 804 .route_offset = 0x50, 805 .route_val = BIT(16 + 9) | BIT(9), 806 }, 807 }; 808 809 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 810 { 811 /* uart2dbga_rx */ 812 .bank_num = 4, 813 .pin = 8, 814 .func = 2, 815 .route_offset = 0xe21c, 816 .route_val = BIT(16 + 10) | BIT(16 + 11), 817 }, { 818 /* uart2dbgb_rx */ 819 .bank_num = 4, 820 .pin = 16, 821 .func = 2, 822 .route_offset = 0xe21c, 823 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 824 }, { 825 /* uart2dbgc_rx */ 826 .bank_num = 4, 827 .pin = 19, 828 .func = 1, 829 .route_offset = 0xe21c, 830 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 831 }, { 832 /* pcie_clkreqn */ 833 .bank_num = 2, 834 .pin = 26, 835 .func = 2, 836 .route_offset = 0xe21c, 837 .route_val = BIT(16 + 14), 838 }, { 839 /* pcie_clkreqnb */ 840 .bank_num = 4, 841 .pin = 24, 842 .func = 1, 843 .route_offset = 0xe21c, 844 .route_val = BIT(16 + 14) | BIT(14), 845 }, 846 }; 847 848 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 849 int mux, u32 *reg, u32 *value) 850 { 851 struct rockchip_pinctrl_priv *priv = bank->priv; 852 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 853 struct rockchip_mux_route_data *data; 854 int i; 855 856 for (i = 0; i < ctrl->niomux_routes; i++) { 857 data = &ctrl->iomux_routes[i]; 858 if ((data->bank_num == bank->bank_num) && 859 (data->pin == pin) && (data->func == mux)) 860 break; 861 } 862 863 if (i >= ctrl->niomux_routes) 864 return false; 865 866 *reg = data->route_offset; 867 *value = data->route_val; 868 869 return true; 870 } 871 872 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 873 { 874 struct rockchip_pinctrl_priv *priv = bank->priv; 875 int iomux_num = (pin / 8); 876 struct regmap *regmap; 877 unsigned int val; 878 int reg, ret, mask, mux_type; 879 u8 bit; 880 881 if (iomux_num > 3) 882 return -EINVAL; 883 884 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 885 debug("pin %d is unrouted\n", pin); 886 return -EINVAL; 887 } 888 889 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 890 return RK_FUNC_GPIO; 891 892 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 893 ? priv->regmap_pmu : priv->regmap_base; 894 895 /* get basic quadrupel of mux registers and the correct reg inside */ 896 mux_type = bank->iomux[iomux_num].type; 897 reg = bank->iomux[iomux_num].offset; 898 if (mux_type & IOMUX_WIDTH_4BIT) { 899 if ((pin % 8) >= 4) 900 reg += 0x4; 901 bit = (pin % 4) * 4; 902 mask = 0xf; 903 } else if (mux_type & IOMUX_WIDTH_3BIT) { 904 if ((pin % 8) >= 5) 905 reg += 0x4; 906 bit = (pin % 8 % 5) * 3; 907 mask = 0x7; 908 } else { 909 bit = (pin % 8) * 2; 910 mask = 0x3; 911 } 912 913 if (bank->recalced_mask & BIT(pin)) 914 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 915 916 ret = regmap_read(regmap, reg, &val); 917 if (ret) 918 return ret; 919 920 return ((val >> bit) & mask); 921 } 922 923 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 924 int index) 925 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 926 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 927 928 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 929 } 930 931 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 932 int pin, int mux) 933 { 934 int iomux_num = (pin / 8); 935 936 if (iomux_num > 3) 937 return -EINVAL; 938 939 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 940 debug("pin %d is unrouted\n", pin); 941 return -EINVAL; 942 } 943 944 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 945 if (mux != IOMUX_GPIO_ONLY) { 946 debug("pin %d only supports a gpio mux\n", pin); 947 return -ENOTSUPP; 948 } 949 } 950 951 return 0; 952 } 953 954 /* 955 * Set a new mux function for a pin. 956 * 957 * The register is divided into the upper and lower 16 bit. When changing 958 * a value, the previous register value is not read and changed. Instead 959 * it seems the changed bits are marked in the upper 16 bit, while the 960 * changed value gets set in the same offset in the lower 16 bit. 961 * All pin settings seem to be 2 bit wide in both the upper and lower 962 * parts. 963 * @bank: pin bank to change 964 * @pin: pin to change 965 * @mux: new mux function to set 966 */ 967 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 968 { 969 struct rockchip_pinctrl_priv *priv = bank->priv; 970 int iomux_num = (pin / 8); 971 struct regmap *regmap; 972 int reg, ret, mask, mux_type; 973 u8 bit; 974 u32 data, route_reg, route_val; 975 976 ret = rockchip_verify_mux(bank, pin, mux); 977 if (ret < 0) 978 return ret; 979 980 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 981 return 0; 982 983 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 984 985 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 986 ? priv->regmap_pmu : priv->regmap_base; 987 988 /* get basic quadrupel of mux registers and the correct reg inside */ 989 mux_type = bank->iomux[iomux_num].type; 990 reg = bank->iomux[iomux_num].offset; 991 if (mux_type & IOMUX_WIDTH_4BIT) { 992 if ((pin % 8) >= 4) 993 reg += 0x4; 994 bit = (pin % 4) * 4; 995 mask = 0xf; 996 } else if (mux_type & IOMUX_WIDTH_3BIT) { 997 if ((pin % 8) >= 5) 998 reg += 0x4; 999 bit = (pin % 8 % 5) * 3; 1000 mask = 0x7; 1001 } else { 1002 bit = (pin % 8) * 2; 1003 mask = 0x3; 1004 } 1005 1006 if (bank->recalced_mask & BIT(pin)) 1007 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1008 1009 if (bank->route_mask & BIT(pin)) { 1010 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1011 &route_val)) { 1012 ret = regmap_write(regmap, route_reg, route_val); 1013 if (ret) 1014 return ret; 1015 } 1016 } 1017 1018 data = (mask << (bit + 16)); 1019 data |= (mux & mask) << bit; 1020 ret = regmap_write(regmap, reg, data); 1021 1022 return ret; 1023 } 1024 1025 #define PX30_PULL_PMU_OFFSET 0x10 1026 #define PX30_PULL_GRF_OFFSET 0x60 1027 #define PX30_PULL_BITS_PER_PIN 2 1028 #define PX30_PULL_PINS_PER_REG 8 1029 #define PX30_PULL_BANK_STRIDE 16 1030 1031 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1032 int pin_num, struct regmap **regmap, 1033 int *reg, u8 *bit) 1034 { 1035 struct rockchip_pinctrl_priv *priv = bank->priv; 1036 1037 /* The first 32 pins of the first bank are located in PMU */ 1038 if (bank->bank_num == 0) { 1039 *regmap = priv->regmap_pmu; 1040 *reg = PX30_PULL_PMU_OFFSET; 1041 } else { 1042 *regmap = priv->regmap_base; 1043 *reg = PX30_PULL_GRF_OFFSET; 1044 1045 /* correct the offset, as we're starting with the 2nd bank */ 1046 *reg -= 0x10; 1047 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1048 } 1049 1050 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1051 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1052 *bit *= PX30_PULL_BITS_PER_PIN; 1053 } 1054 1055 #define PX30_DRV_PMU_OFFSET 0x20 1056 #define PX30_DRV_GRF_OFFSET 0xf0 1057 #define PX30_DRV_BITS_PER_PIN 2 1058 #define PX30_DRV_PINS_PER_REG 8 1059 #define PX30_DRV_BANK_STRIDE 16 1060 1061 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1062 int pin_num, struct regmap **regmap, 1063 int *reg, u8 *bit) 1064 { 1065 struct rockchip_pinctrl_priv *priv = bank->priv; 1066 1067 /* The first 32 pins of the first bank are located in PMU */ 1068 if (bank->bank_num == 0) { 1069 *regmap = priv->regmap_pmu; 1070 *reg = PX30_DRV_PMU_OFFSET; 1071 } else { 1072 *regmap = priv->regmap_base; 1073 *reg = PX30_DRV_GRF_OFFSET; 1074 1075 /* correct the offset, as we're starting with the 2nd bank */ 1076 *reg -= 0x10; 1077 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1078 } 1079 1080 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1081 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1082 *bit *= PX30_DRV_BITS_PER_PIN; 1083 } 1084 1085 #define PX30_SCHMITT_PMU_OFFSET 0x38 1086 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1087 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1088 #define PX30_SCHMITT_BANK_STRIDE 16 1089 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1090 1091 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1092 int pin_num, 1093 struct regmap **regmap, 1094 int *reg, u8 *bit) 1095 { 1096 struct rockchip_pinctrl_priv *priv = bank->priv; 1097 int pins_per_reg; 1098 1099 if (bank->bank_num == 0) { 1100 *regmap = priv->regmap_pmu; 1101 *reg = PX30_SCHMITT_PMU_OFFSET; 1102 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1103 } else { 1104 *regmap = priv->regmap_base; 1105 *reg = PX30_SCHMITT_GRF_OFFSET; 1106 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1107 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1108 } 1109 *reg += ((pin_num / pins_per_reg) * 4); 1110 *bit = pin_num % pins_per_reg; 1111 1112 return 0; 1113 } 1114 1115 #define RV1108_PULL_PMU_OFFSET 0x10 1116 #define RV1108_PULL_OFFSET 0x110 1117 #define RV1108_PULL_PINS_PER_REG 8 1118 #define RV1108_PULL_BITS_PER_PIN 2 1119 #define RV1108_PULL_BANK_STRIDE 16 1120 1121 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1122 int pin_num, struct regmap **regmap, 1123 int *reg, u8 *bit) 1124 { 1125 struct rockchip_pinctrl_priv *priv = bank->priv; 1126 1127 /* The first 24 pins of the first bank are located in PMU */ 1128 if (bank->bank_num == 0) { 1129 *regmap = priv->regmap_pmu; 1130 *reg = RV1108_PULL_PMU_OFFSET; 1131 } else { 1132 *reg = RV1108_PULL_OFFSET; 1133 *regmap = priv->regmap_base; 1134 /* correct the offset, as we're starting with the 2nd bank */ 1135 *reg -= 0x10; 1136 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1137 } 1138 1139 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1140 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1141 *bit *= RV1108_PULL_BITS_PER_PIN; 1142 } 1143 1144 #define RV1108_DRV_PMU_OFFSET 0x20 1145 #define RV1108_DRV_GRF_OFFSET 0x210 1146 #define RV1108_DRV_BITS_PER_PIN 2 1147 #define RV1108_DRV_PINS_PER_REG 8 1148 #define RV1108_DRV_BANK_STRIDE 16 1149 1150 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1151 int pin_num, struct regmap **regmap, 1152 int *reg, u8 *bit) 1153 { 1154 struct rockchip_pinctrl_priv *priv = bank->priv; 1155 1156 /* The first 24 pins of the first bank are located in PMU */ 1157 if (bank->bank_num == 0) { 1158 *regmap = priv->regmap_pmu; 1159 *reg = RV1108_DRV_PMU_OFFSET; 1160 } else { 1161 *regmap = priv->regmap_base; 1162 *reg = RV1108_DRV_GRF_OFFSET; 1163 1164 /* correct the offset, as we're starting with the 2nd bank */ 1165 *reg -= 0x10; 1166 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1167 } 1168 1169 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1170 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1171 *bit *= RV1108_DRV_BITS_PER_PIN; 1172 } 1173 1174 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1175 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1176 #define RV1108_SCHMITT_BANK_STRIDE 8 1177 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1178 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1179 1180 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1181 int pin_num, 1182 struct regmap **regmap, 1183 int *reg, u8 *bit) 1184 { 1185 struct rockchip_pinctrl_priv *priv = bank->priv; 1186 int pins_per_reg; 1187 1188 if (bank->bank_num == 0) { 1189 *regmap = priv->regmap_pmu; 1190 *reg = RV1108_SCHMITT_PMU_OFFSET; 1191 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1192 } else { 1193 *regmap = priv->regmap_base; 1194 *reg = RV1108_SCHMITT_GRF_OFFSET; 1195 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1196 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1197 } 1198 *reg += ((pin_num / pins_per_reg) * 4); 1199 *bit = pin_num % pins_per_reg; 1200 1201 return 0; 1202 } 1203 1204 #define RK2928_PULL_OFFSET 0x118 1205 #define RK2928_PULL_PINS_PER_REG 16 1206 #define RK2928_PULL_BANK_STRIDE 8 1207 1208 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1209 int pin_num, struct regmap **regmap, 1210 int *reg, u8 *bit) 1211 { 1212 struct rockchip_pinctrl_priv *priv = bank->priv; 1213 1214 *regmap = priv->regmap_base; 1215 *reg = RK2928_PULL_OFFSET; 1216 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1217 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1218 1219 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1220 }; 1221 1222 #define RK3128_PULL_OFFSET 0x118 1223 1224 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1225 int pin_num, struct regmap **regmap, 1226 int *reg, u8 *bit) 1227 { 1228 struct rockchip_pinctrl_priv *priv = bank->priv; 1229 1230 *regmap = priv->regmap_base; 1231 *reg = RK3128_PULL_OFFSET; 1232 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1233 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1234 1235 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1236 } 1237 1238 #define RK3188_PULL_OFFSET 0x164 1239 #define RK3188_PULL_BITS_PER_PIN 2 1240 #define RK3188_PULL_PINS_PER_REG 8 1241 #define RK3188_PULL_BANK_STRIDE 16 1242 #define RK3188_PULL_PMU_OFFSET 0x64 1243 1244 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1245 int pin_num, struct regmap **regmap, 1246 int *reg, u8 *bit) 1247 { 1248 struct rockchip_pinctrl_priv *priv = bank->priv; 1249 1250 /* The first 12 pins of the first bank are located elsewhere */ 1251 if (bank->bank_num == 0 && pin_num < 12) { 1252 *regmap = priv->regmap_pmu; 1253 *reg = RK3188_PULL_PMU_OFFSET; 1254 1255 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1256 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1257 *bit *= RK3188_PULL_BITS_PER_PIN; 1258 } else { 1259 *regmap = priv->regmap_base; 1260 *reg = RK3188_PULL_OFFSET; 1261 1262 /* correct the offset, as it is the 2nd pull register */ 1263 *reg -= 4; 1264 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1265 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1266 1267 /* 1268 * The bits in these registers have an inverse ordering 1269 * with the lowest pin being in bits 15:14 and the highest 1270 * pin in bits 1:0 1271 */ 1272 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1273 *bit *= RK3188_PULL_BITS_PER_PIN; 1274 } 1275 } 1276 1277 #define RK3288_PULL_OFFSET 0x140 1278 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1279 int pin_num, struct regmap **regmap, 1280 int *reg, u8 *bit) 1281 { 1282 struct rockchip_pinctrl_priv *priv = bank->priv; 1283 1284 /* The first 24 pins of the first bank are located in PMU */ 1285 if (bank->bank_num == 0) { 1286 *regmap = priv->regmap_pmu; 1287 *reg = RK3188_PULL_PMU_OFFSET; 1288 1289 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1290 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1291 *bit *= RK3188_PULL_BITS_PER_PIN; 1292 } else { 1293 *regmap = priv->regmap_base; 1294 *reg = RK3288_PULL_OFFSET; 1295 1296 /* correct the offset, as we're starting with the 2nd bank */ 1297 *reg -= 0x10; 1298 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1299 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1300 1301 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1302 *bit *= RK3188_PULL_BITS_PER_PIN; 1303 } 1304 } 1305 1306 #define RK3288_DRV_PMU_OFFSET 0x70 1307 #define RK3288_DRV_GRF_OFFSET 0x1c0 1308 #define RK3288_DRV_BITS_PER_PIN 2 1309 #define RK3288_DRV_PINS_PER_REG 8 1310 #define RK3288_DRV_BANK_STRIDE 16 1311 1312 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1313 int pin_num, struct regmap **regmap, 1314 int *reg, u8 *bit) 1315 { 1316 struct rockchip_pinctrl_priv *priv = bank->priv; 1317 1318 /* The first 24 pins of the first bank are located in PMU */ 1319 if (bank->bank_num == 0) { 1320 *regmap = priv->regmap_pmu; 1321 *reg = RK3288_DRV_PMU_OFFSET; 1322 1323 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1324 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1325 *bit *= RK3288_DRV_BITS_PER_PIN; 1326 } else { 1327 *regmap = priv->regmap_base; 1328 *reg = RK3288_DRV_GRF_OFFSET; 1329 1330 /* correct the offset, as we're starting with the 2nd bank */ 1331 *reg -= 0x10; 1332 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1333 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1334 1335 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1336 *bit *= RK3288_DRV_BITS_PER_PIN; 1337 } 1338 } 1339 1340 #define RK3228_PULL_OFFSET 0x100 1341 1342 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1343 int pin_num, struct regmap **regmap, 1344 int *reg, u8 *bit) 1345 { 1346 struct rockchip_pinctrl_priv *priv = bank->priv; 1347 1348 *regmap = priv->regmap_base; 1349 *reg = RK3228_PULL_OFFSET; 1350 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1351 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1352 1353 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1354 *bit *= RK3188_PULL_BITS_PER_PIN; 1355 } 1356 1357 #define RK3228_DRV_GRF_OFFSET 0x200 1358 1359 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1360 int pin_num, struct regmap **regmap, 1361 int *reg, u8 *bit) 1362 { 1363 struct rockchip_pinctrl_priv *priv = bank->priv; 1364 1365 *regmap = priv->regmap_base; 1366 *reg = RK3228_DRV_GRF_OFFSET; 1367 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1368 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1369 1370 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1371 *bit *= RK3288_DRV_BITS_PER_PIN; 1372 } 1373 1374 #define RK3368_PULL_GRF_OFFSET 0x100 1375 #define RK3368_PULL_PMU_OFFSET 0x10 1376 1377 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1378 int pin_num, struct regmap **regmap, 1379 int *reg, u8 *bit) 1380 { 1381 struct rockchip_pinctrl_priv *priv = bank->priv; 1382 1383 /* The first 32 pins of the first bank are located in PMU */ 1384 if (bank->bank_num == 0) { 1385 *regmap = priv->regmap_pmu; 1386 *reg = RK3368_PULL_PMU_OFFSET; 1387 1388 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1389 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1390 *bit *= RK3188_PULL_BITS_PER_PIN; 1391 } else { 1392 *regmap = priv->regmap_base; 1393 *reg = RK3368_PULL_GRF_OFFSET; 1394 1395 /* correct the offset, as we're starting with the 2nd bank */ 1396 *reg -= 0x10; 1397 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1398 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1399 1400 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1401 *bit *= RK3188_PULL_BITS_PER_PIN; 1402 } 1403 } 1404 1405 #define RK3368_DRV_PMU_OFFSET 0x20 1406 #define RK3368_DRV_GRF_OFFSET 0x200 1407 1408 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1409 int pin_num, struct regmap **regmap, 1410 int *reg, u8 *bit) 1411 { 1412 struct rockchip_pinctrl_priv *priv = bank->priv; 1413 1414 /* The first 32 pins of the first bank are located in PMU */ 1415 if (bank->bank_num == 0) { 1416 *regmap = priv->regmap_pmu; 1417 *reg = RK3368_DRV_PMU_OFFSET; 1418 1419 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1420 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1421 *bit *= RK3288_DRV_BITS_PER_PIN; 1422 } else { 1423 *regmap = priv->regmap_base; 1424 *reg = RK3368_DRV_GRF_OFFSET; 1425 1426 /* correct the offset, as we're starting with the 2nd bank */ 1427 *reg -= 0x10; 1428 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1429 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1430 1431 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1432 *bit *= RK3288_DRV_BITS_PER_PIN; 1433 } 1434 } 1435 1436 #define RK3399_PULL_GRF_OFFSET 0xe040 1437 #define RK3399_PULL_PMU_OFFSET 0x40 1438 #define RK3399_DRV_3BITS_PER_PIN 3 1439 1440 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1441 int pin_num, struct regmap **regmap, 1442 int *reg, u8 *bit) 1443 { 1444 struct rockchip_pinctrl_priv *priv = bank->priv; 1445 1446 /* The bank0:16 and bank1:32 pins are located in PMU */ 1447 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1448 *regmap = priv->regmap_pmu; 1449 *reg = RK3399_PULL_PMU_OFFSET; 1450 1451 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1452 1453 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1454 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1455 *bit *= RK3188_PULL_BITS_PER_PIN; 1456 } else { 1457 *regmap = priv->regmap_base; 1458 *reg = RK3399_PULL_GRF_OFFSET; 1459 1460 /* correct the offset, as we're starting with the 3rd bank */ 1461 *reg -= 0x20; 1462 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1463 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1464 1465 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1466 *bit *= RK3188_PULL_BITS_PER_PIN; 1467 } 1468 } 1469 1470 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1471 int pin_num, struct regmap **regmap, 1472 int *reg, u8 *bit) 1473 { 1474 struct rockchip_pinctrl_priv *priv = bank->priv; 1475 int drv_num = (pin_num / 8); 1476 1477 /* The bank0:16 and bank1:32 pins are located in PMU */ 1478 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1479 *regmap = priv->regmap_pmu; 1480 else 1481 *regmap = priv->regmap_base; 1482 1483 *reg = bank->drv[drv_num].offset; 1484 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1485 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1486 *bit = (pin_num % 8) * 3; 1487 else 1488 *bit = (pin_num % 8) * 2; 1489 } 1490 1491 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1492 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1493 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1494 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1495 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1496 { 4, 7, 10, 13, 16, 19, 22, 26 } 1497 }; 1498 1499 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1500 int pin_num, int strength) 1501 { 1502 struct rockchip_pinctrl_priv *priv = bank->priv; 1503 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1504 struct regmap *regmap; 1505 int reg, ret, i; 1506 u32 data, rmask_bits, temp; 1507 u8 bit; 1508 int drv_type = bank->drv[pin_num / 8].drv_type; 1509 1510 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 1511 pin_num, strength); 1512 1513 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1514 1515 ret = -EINVAL; 1516 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1517 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1518 ret = i; 1519 break; 1520 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1521 ret = rockchip_perpin_drv_list[drv_type][i]; 1522 break; 1523 } 1524 } 1525 1526 if (ret < 0) { 1527 debug("unsupported driver strength %d\n", strength); 1528 return ret; 1529 } 1530 1531 switch (drv_type) { 1532 case DRV_TYPE_IO_1V8_3V0_AUTO: 1533 case DRV_TYPE_IO_3V3_ONLY: 1534 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1535 switch (bit) { 1536 case 0 ... 12: 1537 /* regular case, nothing to do */ 1538 break; 1539 case 15: 1540 /* 1541 * drive-strength offset is special, as it is spread 1542 * over 2 registers, the bit data[15] contains bit 0 1543 * of the value while temp[1:0] contains bits 2 and 1 1544 */ 1545 data = (ret & 0x1) << 15; 1546 temp = (ret >> 0x1) & 0x3; 1547 1548 data |= BIT(31); 1549 ret = regmap_write(regmap, reg, data); 1550 if (ret) 1551 return ret; 1552 1553 temp |= (0x3 << 16); 1554 reg += 0x4; 1555 ret = regmap_write(regmap, reg, temp); 1556 1557 return ret; 1558 case 18 ... 21: 1559 /* setting fully enclosed in the second register */ 1560 reg += 4; 1561 bit -= 16; 1562 break; 1563 default: 1564 debug("unsupported bit: %d for pinctrl drive type: %d\n", 1565 bit, drv_type); 1566 return -EINVAL; 1567 } 1568 break; 1569 case DRV_TYPE_IO_DEFAULT: 1570 case DRV_TYPE_IO_1V8_OR_3V0: 1571 case DRV_TYPE_IO_1V8_ONLY: 1572 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1573 break; 1574 default: 1575 debug("unsupported pinctrl drive type: %d\n", 1576 drv_type); 1577 return -EINVAL; 1578 } 1579 1580 /* enable the write to the equivalent lower bits */ 1581 data = ((1 << rmask_bits) - 1) << (bit + 16); 1582 data |= (ret << bit); 1583 1584 ret = regmap_write(regmap, reg, data); 1585 return ret; 1586 } 1587 1588 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1589 { 1590 PIN_CONFIG_BIAS_DISABLE, 1591 PIN_CONFIG_BIAS_PULL_UP, 1592 PIN_CONFIG_BIAS_PULL_DOWN, 1593 PIN_CONFIG_BIAS_BUS_HOLD 1594 }, 1595 { 1596 PIN_CONFIG_BIAS_DISABLE, 1597 PIN_CONFIG_BIAS_PULL_DOWN, 1598 PIN_CONFIG_BIAS_DISABLE, 1599 PIN_CONFIG_BIAS_PULL_UP 1600 }, 1601 }; 1602 1603 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1604 int pin_num, int pull) 1605 { 1606 struct rockchip_pinctrl_priv *priv = bank->priv; 1607 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1608 struct regmap *regmap; 1609 int reg, ret, i, pull_type; 1610 u8 bit; 1611 u32 data; 1612 1613 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 1614 pin_num, pull); 1615 1616 /* rk3066b does support any pulls */ 1617 if (ctrl->type == RK3066B) 1618 return pull ? -EINVAL : 0; 1619 1620 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1621 1622 switch (ctrl->type) { 1623 case RK2928: 1624 case RK3128: 1625 data = BIT(bit + 16); 1626 if (pull == PIN_CONFIG_BIAS_DISABLE) 1627 data |= BIT(bit); 1628 ret = regmap_write(regmap, reg, data); 1629 break; 1630 case PX30: 1631 case RV1108: 1632 case RK3188: 1633 case RK3288: 1634 case RK3368: 1635 case RK3399: 1636 pull_type = bank->pull_type[pin_num / 8]; 1637 ret = -EINVAL; 1638 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 1639 i++) { 1640 if (rockchip_pull_list[pull_type][i] == pull) { 1641 ret = i; 1642 break; 1643 } 1644 } 1645 1646 if (ret < 0) { 1647 debug("unsupported pull setting %d\n", pull); 1648 return ret; 1649 } 1650 1651 /* enable the write to the equivalent lower bits */ 1652 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1653 data |= (ret << bit); 1654 1655 ret = regmap_write(regmap, reg, data); 1656 break; 1657 default: 1658 debug("unsupported pinctrl type\n"); 1659 return -EINVAL; 1660 } 1661 1662 return ret; 1663 } 1664 1665 #define RK3328_SCHMITT_BITS_PER_PIN 1 1666 #define RK3328_SCHMITT_PINS_PER_REG 16 1667 #define RK3328_SCHMITT_BANK_STRIDE 8 1668 #define RK3328_SCHMITT_GRF_OFFSET 0x380 1669 1670 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1671 int pin_num, 1672 struct regmap **regmap, 1673 int *reg, u8 *bit) 1674 { 1675 struct rockchip_pinctrl_priv *priv = bank->priv; 1676 1677 *regmap = priv->regmap_base; 1678 *reg = RK3328_SCHMITT_GRF_OFFSET; 1679 1680 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 1681 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 1682 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 1683 1684 return 0; 1685 } 1686 1687 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 1688 int pin_num, int enable) 1689 { 1690 struct rockchip_pinctrl_priv *priv = bank->priv; 1691 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1692 struct regmap *regmap; 1693 int reg, ret; 1694 u8 bit; 1695 u32 data; 1696 1697 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 1698 pin_num, enable); 1699 1700 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1701 if (ret) 1702 return ret; 1703 1704 /* enable the write to the equivalent lower bits */ 1705 data = BIT(bit + 16) | (enable << bit); 1706 1707 return regmap_write(regmap, reg, data); 1708 } 1709 1710 /* 1711 * Pinconf_ops handling 1712 */ 1713 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 1714 unsigned int pull) 1715 { 1716 switch (ctrl->type) { 1717 case RK2928: 1718 case RK3128: 1719 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 1720 pull == PIN_CONFIG_BIAS_DISABLE); 1721 case RK3066B: 1722 return pull ? false : true; 1723 case PX30: 1724 case RV1108: 1725 case RK3188: 1726 case RK3288: 1727 case RK3368: 1728 case RK3399: 1729 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 1730 } 1731 1732 return false; 1733 } 1734 1735 /* set the pin config settings for a specified pin */ 1736 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 1737 u32 pin, u32 param, u32 arg) 1738 { 1739 struct rockchip_pinctrl_priv *priv = bank->priv; 1740 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1741 int rc; 1742 1743 switch (param) { 1744 case PIN_CONFIG_BIAS_DISABLE: 1745 rc = rockchip_set_pull(bank, pin, param); 1746 if (rc) 1747 return rc; 1748 break; 1749 1750 case PIN_CONFIG_BIAS_PULL_UP: 1751 case PIN_CONFIG_BIAS_PULL_DOWN: 1752 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1753 case PIN_CONFIG_BIAS_BUS_HOLD: 1754 if (!rockchip_pinconf_pull_valid(ctrl, param)) 1755 return -ENOTSUPP; 1756 1757 if (!arg) 1758 return -EINVAL; 1759 1760 rc = rockchip_set_pull(bank, pin, param); 1761 if (rc) 1762 return rc; 1763 break; 1764 1765 case PIN_CONFIG_DRIVE_STRENGTH: 1766 if (!ctrl->drv_calc_reg) 1767 return -ENOTSUPP; 1768 1769 rc = rockchip_set_drive_perpin(bank, pin, arg); 1770 if (rc < 0) 1771 return rc; 1772 break; 1773 1774 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1775 if (!ctrl->schmitt_calc_reg) 1776 return -ENOTSUPP; 1777 1778 rc = rockchip_set_schmitt(bank, pin, arg); 1779 if (rc < 0) 1780 return rc; 1781 break; 1782 1783 default: 1784 break; 1785 } 1786 1787 return 0; 1788 } 1789 1790 static const struct pinconf_param rockchip_conf_params[] = { 1791 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 1792 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 1793 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 1794 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 1795 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 1796 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 1797 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 1798 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 1799 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 1800 }; 1801 1802 static int rockchip_pinconf_prop_name_to_param(const char *property, 1803 u32 *default_value) 1804 { 1805 const struct pinconf_param *p, *end; 1806 1807 p = rockchip_conf_params; 1808 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 1809 1810 /* See if this pctldev supports this parameter */ 1811 for (; p < end; p++) { 1812 if (!strcmp(property, p->property)) { 1813 *default_value = p->default_value; 1814 return p->param; 1815 } 1816 } 1817 1818 *default_value = 0; 1819 return -EPERM; 1820 } 1821 1822 static int rockchip_pinctrl_set_state(struct udevice *dev, 1823 struct udevice *config) 1824 { 1825 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1826 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1827 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 1828 u32 bank, pin, mux, conf, arg, default_val; 1829 int ret, count, i; 1830 const char *prop_name; 1831 const void *value; 1832 int prop_len, param; 1833 const u32 *data; 1834 ofnode node; 1835 #ifdef CONFIG_OF_LIVE 1836 const struct device_node *np; 1837 struct property *pp; 1838 #else 1839 int property_offset, pcfg_node; 1840 const void *blob = gd->fdt_blob; 1841 #endif 1842 data = dev_read_prop(config, "rockchip,pins", &count); 1843 if (count < 0) { 1844 debug("%s: bad array size %d\n", __func__, count); 1845 return -EINVAL; 1846 } 1847 1848 count /= sizeof(u32); 1849 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 1850 debug("%s: unsupported pins array count %d\n", 1851 __func__, count); 1852 return -EINVAL; 1853 } 1854 1855 for (i = 0; i < count; i++) 1856 cells[i] = fdt32_to_cpu(data[i]); 1857 1858 for (i = 0; i < (count >> 2); i++) { 1859 bank = cells[4 * i + 0]; 1860 pin = cells[4 * i + 1]; 1861 mux = cells[4 * i + 2]; 1862 conf = cells[4 * i + 3]; 1863 1864 ret = rockchip_verify_config(dev, bank, pin); 1865 if (ret) 1866 return ret; 1867 1868 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 1869 if (ret) 1870 return ret; 1871 1872 node = ofnode_get_by_phandle(conf); 1873 if (!ofnode_valid(node)) 1874 return -ENODEV; 1875 #ifdef CONFIG_OF_LIVE 1876 np = ofnode_to_np(node); 1877 for (pp = np->properties; pp; pp = pp->next) { 1878 prop_name = pp->name; 1879 prop_len = pp->length; 1880 value = pp->value; 1881 #else 1882 pcfg_node = ofnode_to_offset(node); 1883 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 1884 value = fdt_getprop_by_offset(blob, property_offset, 1885 &prop_name, &prop_len); 1886 if (!value) 1887 return -ENOENT; 1888 #endif 1889 param = rockchip_pinconf_prop_name_to_param(prop_name, 1890 &default_val); 1891 if (param < 0) 1892 break; 1893 1894 if (prop_len >= sizeof(fdt32_t)) 1895 arg = fdt32_to_cpu(*(fdt32_t *)value); 1896 else 1897 arg = default_val; 1898 1899 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 1900 param, arg); 1901 if (ret) { 1902 debug("%s: rockchip_pinconf_set fail: %d\n", 1903 __func__, ret); 1904 return ret; 1905 } 1906 } 1907 } 1908 1909 return 0; 1910 } 1911 1912 static struct pinctrl_ops rockchip_pinctrl_ops = { 1913 .set_state = rockchip_pinctrl_set_state, 1914 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 1915 }; 1916 1917 /* retrieve the soc specific data */ 1918 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 1919 { 1920 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1921 struct rockchip_pin_ctrl *ctrl = 1922 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 1923 struct rockchip_pin_bank *bank; 1924 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 1925 1926 grf_offs = ctrl->grf_mux_offset; 1927 pmu_offs = ctrl->pmu_mux_offset; 1928 drv_pmu_offs = ctrl->pmu_drv_offset; 1929 drv_grf_offs = ctrl->grf_drv_offset; 1930 bank = ctrl->pin_banks; 1931 1932 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1933 int bank_pins = 0; 1934 1935 bank->priv = priv; 1936 bank->pin_base = ctrl->nr_pins; 1937 ctrl->nr_pins += bank->nr_pins; 1938 1939 /* calculate iomux and drv offsets */ 1940 for (j = 0; j < 4; j++) { 1941 struct rockchip_iomux *iom = &bank->iomux[j]; 1942 struct rockchip_drv *drv = &bank->drv[j]; 1943 int inc; 1944 1945 if (bank_pins >= bank->nr_pins) 1946 break; 1947 1948 /* preset iomux offset value, set new start value */ 1949 if (iom->offset >= 0) { 1950 if (iom->type & IOMUX_SOURCE_PMU) 1951 pmu_offs = iom->offset; 1952 else 1953 grf_offs = iom->offset; 1954 } else { /* set current iomux offset */ 1955 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 1956 pmu_offs : grf_offs; 1957 } 1958 1959 /* preset drv offset value, set new start value */ 1960 if (drv->offset >= 0) { 1961 if (iom->type & IOMUX_SOURCE_PMU) 1962 drv_pmu_offs = drv->offset; 1963 else 1964 drv_grf_offs = drv->offset; 1965 } else { /* set current drv offset */ 1966 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 1967 drv_pmu_offs : drv_grf_offs; 1968 } 1969 1970 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 1971 i, j, iom->offset, drv->offset); 1972 1973 /* 1974 * Increase offset according to iomux width. 1975 * 4bit iomux'es are spread over two registers. 1976 */ 1977 inc = (iom->type & (IOMUX_WIDTH_4BIT | 1978 IOMUX_WIDTH_3BIT)) ? 8 : 4; 1979 if (iom->type & IOMUX_SOURCE_PMU) 1980 pmu_offs += inc; 1981 else 1982 grf_offs += inc; 1983 1984 /* 1985 * Increase offset according to drv width. 1986 * 3bit drive-strenth'es are spread over two registers. 1987 */ 1988 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1989 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 1990 inc = 8; 1991 else 1992 inc = 4; 1993 1994 if (iom->type & IOMUX_SOURCE_PMU) 1995 drv_pmu_offs += inc; 1996 else 1997 drv_grf_offs += inc; 1998 1999 bank_pins += 8; 2000 } 2001 2002 /* calculate the per-bank recalced_mask */ 2003 for (j = 0; j < ctrl->niomux_recalced; j++) { 2004 int pin = 0; 2005 2006 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2007 pin = ctrl->iomux_recalced[j].pin; 2008 bank->recalced_mask |= BIT(pin); 2009 } 2010 } 2011 2012 /* calculate the per-bank route_mask */ 2013 for (j = 0; j < ctrl->niomux_routes; j++) { 2014 int pin = 0; 2015 2016 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2017 pin = ctrl->iomux_routes[j].pin; 2018 bank->route_mask |= BIT(pin); 2019 } 2020 } 2021 } 2022 2023 return ctrl; 2024 } 2025 2026 static int rockchip_pinctrl_probe(struct udevice *dev) 2027 { 2028 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2029 struct rockchip_pin_ctrl *ctrl; 2030 struct udevice *syscon; 2031 struct regmap *regmap; 2032 int ret = 0; 2033 2034 /* get rockchip grf syscon phandle */ 2035 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2036 &syscon); 2037 if (ret) { 2038 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 2039 return ret; 2040 } 2041 2042 /* get grf-reg base address */ 2043 regmap = syscon_get_regmap(syscon); 2044 if (!regmap) { 2045 debug("unable to find rockchip grf regmap\n"); 2046 return -ENODEV; 2047 } 2048 priv->regmap_base = regmap; 2049 2050 /* option: get pmu-reg base address */ 2051 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 2052 &syscon); 2053 if (!ret) { 2054 /* get pmugrf-reg base address */ 2055 regmap = syscon_get_regmap(syscon); 2056 if (!regmap) { 2057 debug("unable to find rockchip pmu regmap\n"); 2058 return -ENODEV; 2059 } 2060 priv->regmap_pmu = regmap; 2061 } 2062 2063 ctrl = rockchip_pinctrl_get_soc_data(dev); 2064 if (!ctrl) { 2065 debug("driver data not available\n"); 2066 return -EINVAL; 2067 } 2068 2069 priv->ctrl = ctrl; 2070 return 0; 2071 } 2072 2073 static struct rockchip_pin_bank px30_pin_banks[] = { 2074 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2075 IOMUX_SOURCE_PMU, 2076 IOMUX_SOURCE_PMU, 2077 IOMUX_SOURCE_PMU 2078 ), 2079 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2080 IOMUX_WIDTH_4BIT, 2081 IOMUX_WIDTH_4BIT, 2082 IOMUX_WIDTH_4BIT 2083 ), 2084 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2085 IOMUX_WIDTH_4BIT, 2086 IOMUX_WIDTH_4BIT, 2087 IOMUX_WIDTH_4BIT 2088 ), 2089 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2090 IOMUX_WIDTH_4BIT, 2091 IOMUX_WIDTH_4BIT, 2092 IOMUX_WIDTH_4BIT 2093 ), 2094 }; 2095 2096 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2097 .pin_banks = px30_pin_banks, 2098 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2099 .label = "PX30-GPIO", 2100 .type = PX30, 2101 .grf_mux_offset = 0x0, 2102 .pmu_mux_offset = 0x0, 2103 .iomux_routes = px30_mux_route_data, 2104 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2105 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2106 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2107 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2108 }; 2109 2110 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2111 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2112 IOMUX_SOURCE_PMU, 2113 IOMUX_SOURCE_PMU, 2114 IOMUX_SOURCE_PMU), 2115 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2116 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2117 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2118 }; 2119 2120 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2121 .pin_banks = rv1108_pin_banks, 2122 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2123 .label = "RV1108-GPIO", 2124 .type = RV1108, 2125 .grf_mux_offset = 0x10, 2126 .pmu_mux_offset = 0x0, 2127 .iomux_recalced = rv1108_mux_recalced_data, 2128 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2129 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2130 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2131 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2132 }; 2133 2134 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2135 PIN_BANK(0, 32, "gpio0"), 2136 PIN_BANK(1, 32, "gpio1"), 2137 PIN_BANK(2, 32, "gpio2"), 2138 PIN_BANK(3, 32, "gpio3"), 2139 }; 2140 2141 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2142 .pin_banks = rk2928_pin_banks, 2143 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2144 .label = "RK2928-GPIO", 2145 .type = RK2928, 2146 .grf_mux_offset = 0xa8, 2147 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2148 }; 2149 2150 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2151 PIN_BANK(0, 32, "gpio0"), 2152 PIN_BANK(1, 32, "gpio1"), 2153 PIN_BANK(2, 32, "gpio2"), 2154 }; 2155 2156 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2157 .pin_banks = rk3036_pin_banks, 2158 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2159 .label = "RK3036-GPIO", 2160 .type = RK2928, 2161 .grf_mux_offset = 0xa8, 2162 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2163 }; 2164 2165 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2166 PIN_BANK(0, 32, "gpio0"), 2167 PIN_BANK(1, 32, "gpio1"), 2168 PIN_BANK(2, 32, "gpio2"), 2169 PIN_BANK(3, 32, "gpio3"), 2170 PIN_BANK(4, 32, "gpio4"), 2171 PIN_BANK(6, 16, "gpio6"), 2172 }; 2173 2174 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2175 .pin_banks = rk3066a_pin_banks, 2176 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2177 .label = "RK3066a-GPIO", 2178 .type = RK2928, 2179 .grf_mux_offset = 0xa8, 2180 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2181 }; 2182 2183 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2184 PIN_BANK(0, 32, "gpio0"), 2185 PIN_BANK(1, 32, "gpio1"), 2186 PIN_BANK(2, 32, "gpio2"), 2187 PIN_BANK(3, 32, "gpio3"), 2188 }; 2189 2190 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2191 .pin_banks = rk3066b_pin_banks, 2192 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2193 .label = "RK3066b-GPIO", 2194 .type = RK3066B, 2195 .grf_mux_offset = 0x60, 2196 }; 2197 2198 static struct rockchip_pin_bank rk3128_pin_banks[] = { 2199 PIN_BANK(0, 32, "gpio0"), 2200 PIN_BANK(1, 32, "gpio1"), 2201 PIN_BANK(2, 32, "gpio2"), 2202 PIN_BANK(3, 32, "gpio3"), 2203 }; 2204 2205 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 2206 .pin_banks = rk3128_pin_banks, 2207 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 2208 .label = "RK3128-GPIO", 2209 .type = RK3128, 2210 .grf_mux_offset = 0xa8, 2211 .iomux_recalced = rk3128_mux_recalced_data, 2212 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 2213 .iomux_routes = rk3128_mux_route_data, 2214 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 2215 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 2216 }; 2217 2218 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2219 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2220 PIN_BANK(1, 32, "gpio1"), 2221 PIN_BANK(2, 32, "gpio2"), 2222 PIN_BANK(3, 32, "gpio3"), 2223 }; 2224 2225 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2226 .pin_banks = rk3188_pin_banks, 2227 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2228 .label = "RK3188-GPIO", 2229 .type = RK3188, 2230 .grf_mux_offset = 0x60, 2231 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2232 }; 2233 2234 static struct rockchip_pin_bank rk3228_pin_banks[] = { 2235 PIN_BANK(0, 32, "gpio0"), 2236 PIN_BANK(1, 32, "gpio1"), 2237 PIN_BANK(2, 32, "gpio2"), 2238 PIN_BANK(3, 32, "gpio3"), 2239 }; 2240 2241 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 2242 .pin_banks = rk3228_pin_banks, 2243 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 2244 .label = "RK3228-GPIO", 2245 .type = RK3288, 2246 .grf_mux_offset = 0x0, 2247 .iomux_routes = rk3228_mux_route_data, 2248 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 2249 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2250 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2251 }; 2252 2253 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2254 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 2255 IOMUX_SOURCE_PMU, 2256 IOMUX_SOURCE_PMU, 2257 IOMUX_UNROUTED 2258 ), 2259 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2260 IOMUX_UNROUTED, 2261 IOMUX_UNROUTED, 2262 0 2263 ), 2264 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2265 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2266 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2267 IOMUX_WIDTH_4BIT, 2268 0, 2269 0 2270 ), 2271 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2272 0, 2273 0, 2274 IOMUX_UNROUTED 2275 ), 2276 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2277 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2278 0, 2279 IOMUX_WIDTH_4BIT, 2280 IOMUX_UNROUTED 2281 ), 2282 PIN_BANK(8, 16, "gpio8"), 2283 }; 2284 2285 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2286 .pin_banks = rk3288_pin_banks, 2287 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2288 .label = "RK3288-GPIO", 2289 .type = RK3288, 2290 .grf_mux_offset = 0x0, 2291 .pmu_mux_offset = 0x84, 2292 .iomux_routes = rk3288_mux_route_data, 2293 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 2294 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2295 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2296 }; 2297 2298 static struct rockchip_pin_bank rk3328_pin_banks[] = { 2299 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 2300 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2301 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 2302 IOMUX_WIDTH_3BIT, 2303 IOMUX_WIDTH_3BIT, 2304 0), 2305 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2306 IOMUX_WIDTH_3BIT, 2307 IOMUX_WIDTH_3BIT, 2308 0, 2309 0), 2310 }; 2311 2312 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 2313 .pin_banks = rk3328_pin_banks, 2314 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 2315 .label = "RK3328-GPIO", 2316 .type = RK3288, 2317 .grf_mux_offset = 0x0, 2318 .iomux_recalced = rk3328_mux_recalced_data, 2319 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 2320 .iomux_routes = rk3328_mux_route_data, 2321 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 2322 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2323 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2324 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 2325 }; 2326 2327 static struct rockchip_pin_bank rk3368_pin_banks[] = { 2328 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2329 IOMUX_SOURCE_PMU, 2330 IOMUX_SOURCE_PMU, 2331 IOMUX_SOURCE_PMU 2332 ), 2333 PIN_BANK(1, 32, "gpio1"), 2334 PIN_BANK(2, 32, "gpio2"), 2335 PIN_BANK(3, 32, "gpio3"), 2336 }; 2337 2338 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 2339 .pin_banks = rk3368_pin_banks, 2340 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 2341 .label = "RK3368-GPIO", 2342 .type = RK3368, 2343 .grf_mux_offset = 0x0, 2344 .pmu_mux_offset = 0x0, 2345 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 2346 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 2347 }; 2348 2349 static struct rockchip_pin_bank rk3399_pin_banks[] = { 2350 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 2351 IOMUX_SOURCE_PMU, 2352 IOMUX_SOURCE_PMU, 2353 IOMUX_SOURCE_PMU, 2354 IOMUX_SOURCE_PMU, 2355 DRV_TYPE_IO_1V8_ONLY, 2356 DRV_TYPE_IO_1V8_ONLY, 2357 DRV_TYPE_IO_DEFAULT, 2358 DRV_TYPE_IO_DEFAULT, 2359 0x80, 2360 0x88, 2361 -1, 2362 -1, 2363 PULL_TYPE_IO_1V8_ONLY, 2364 PULL_TYPE_IO_1V8_ONLY, 2365 PULL_TYPE_IO_DEFAULT, 2366 PULL_TYPE_IO_DEFAULT 2367 ), 2368 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 2369 IOMUX_SOURCE_PMU, 2370 IOMUX_SOURCE_PMU, 2371 IOMUX_SOURCE_PMU, 2372 DRV_TYPE_IO_1V8_OR_3V0, 2373 DRV_TYPE_IO_1V8_OR_3V0, 2374 DRV_TYPE_IO_1V8_OR_3V0, 2375 DRV_TYPE_IO_1V8_OR_3V0, 2376 0xa0, 2377 0xa8, 2378 0xb0, 2379 0xb8 2380 ), 2381 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 2382 DRV_TYPE_IO_1V8_OR_3V0, 2383 DRV_TYPE_IO_1V8_ONLY, 2384 DRV_TYPE_IO_1V8_ONLY, 2385 PULL_TYPE_IO_DEFAULT, 2386 PULL_TYPE_IO_DEFAULT, 2387 PULL_TYPE_IO_1V8_ONLY, 2388 PULL_TYPE_IO_1V8_ONLY 2389 ), 2390 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 2391 DRV_TYPE_IO_3V3_ONLY, 2392 DRV_TYPE_IO_3V3_ONLY, 2393 DRV_TYPE_IO_1V8_OR_3V0 2394 ), 2395 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 2396 DRV_TYPE_IO_1V8_3V0_AUTO, 2397 DRV_TYPE_IO_1V8_OR_3V0, 2398 DRV_TYPE_IO_1V8_OR_3V0 2399 ), 2400 }; 2401 2402 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 2403 .pin_banks = rk3399_pin_banks, 2404 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 2405 .label = "RK3399-GPIO", 2406 .type = RK3399, 2407 .grf_mux_offset = 0xe000, 2408 .pmu_mux_offset = 0x0, 2409 .grf_drv_offset = 0xe100, 2410 .pmu_drv_offset = 0x80, 2411 .iomux_routes = rk3399_mux_route_data, 2412 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 2413 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 2414 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 2415 }; 2416 2417 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 2418 { .compatible = "rockchip,px30-pinctrl", 2419 .data = (ulong)&px30_pin_ctrl }, 2420 { .compatible = "rockchip,rv1108-pinctrl", 2421 .data = (ulong)&rv1108_pin_ctrl }, 2422 { .compatible = "rockchip,rk2928-pinctrl", 2423 .data = (ulong)&rk2928_pin_ctrl }, 2424 { .compatible = "rockchip,rk3036-pinctrl", 2425 .data = (ulong)&rk3036_pin_ctrl }, 2426 { .compatible = "rockchip,rk3066a-pinctrl", 2427 .data = (ulong)&rk3066a_pin_ctrl }, 2428 { .compatible = "rockchip,rk3066b-pinctrl", 2429 .data = (ulong)&rk3066b_pin_ctrl }, 2430 { .compatible = "rockchip,rk3128-pinctrl", 2431 .data = (ulong)&rk3128_pin_ctrl }, 2432 { .compatible = "rockchip,rk3188-pinctrl", 2433 .data = (ulong)&rk3188_pin_ctrl }, 2434 { .compatible = "rockchip,rk3228-pinctrl", 2435 .data = (ulong)&rk3228_pin_ctrl }, 2436 { .compatible = "rockchip,rk3288-pinctrl", 2437 .data = (ulong)&rk3288_pin_ctrl }, 2438 { .compatible = "rockchip,rk3328-pinctrl", 2439 .data = (ulong)&rk3328_pin_ctrl }, 2440 { .compatible = "rockchip,rk3368-pinctrl", 2441 .data = (ulong)&rk3368_pin_ctrl }, 2442 { .compatible = "rockchip,rk3399-pinctrl", 2443 .data = (ulong)&rk3399_pin_ctrl }, 2444 {}, 2445 }; 2446 2447 U_BOOT_DRIVER(pinctrl_rockchip) = { 2448 .name = "rockchip_pinctrl", 2449 .id = UCLASS_PINCTRL, 2450 .of_match = rockchip_pinctrl_dt_match, 2451 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 2452 .ops = &rockchip_pinctrl_ops, 2453 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 2454 .bind = dm_scan_fdt_dev, 2455 #endif 2456 .probe = rockchip_pinctrl_probe, 2457 }; 2458