1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <regmap.h> 11 #include <syscon.h> 12 13 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 14 #define RK_FUNC_GPIO 0 15 #define MAX_ROCKCHIP_PINS_ENTRIES 20 16 17 enum rockchip_pinctrl_type { 18 PX30, 19 RV1108, 20 RK2928, 21 RK3066B, 22 RK3128, 23 RK3188, 24 RK3288, 25 RK3368, 26 RK3399, 27 }; 28 29 /** 30 * Encode variants of iomux registers into a type variable 31 */ 32 #define IOMUX_GPIO_ONLY BIT(0) 33 #define IOMUX_WIDTH_4BIT BIT(1) 34 #define IOMUX_SOURCE_PMU BIT(2) 35 #define IOMUX_UNROUTED BIT(3) 36 #define IOMUX_WIDTH_3BIT BIT(4) 37 38 /** 39 * @type: iomux variant using IOMUX_* constants 40 * @offset: if initialized to -1 it will be autocalculated, by specifying 41 * an initial offset value the relevant source offset can be reset 42 * to a new value for autocalculating the following iomux registers. 43 */ 44 struct rockchip_iomux { 45 int type; 46 int offset; 47 }; 48 49 /** 50 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 51 */ 52 enum rockchip_pin_drv_type { 53 DRV_TYPE_IO_DEFAULT = 0, 54 DRV_TYPE_IO_1V8_OR_3V0, 55 DRV_TYPE_IO_1V8_ONLY, 56 DRV_TYPE_IO_1V8_3V0_AUTO, 57 DRV_TYPE_IO_3V3_ONLY, 58 DRV_TYPE_MAX 59 }; 60 61 /** 62 * enum type index corresponding to rockchip_pull_list arrays index. 63 */ 64 enum rockchip_pin_pull_type { 65 PULL_TYPE_IO_DEFAULT = 0, 66 PULL_TYPE_IO_1V8_ONLY, 67 PULL_TYPE_MAX 68 }; 69 70 /** 71 * @drv_type: drive strength variant using rockchip_perpin_drv_type 72 * @offset: if initialized to -1 it will be autocalculated, by specifying 73 * an initial offset value the relevant source offset can be reset 74 * to a new value for autocalculating the following drive strength 75 * registers. if used chips own cal_drv func instead to calculate 76 * registers offset, the variant could be ignored. 77 */ 78 struct rockchip_drv { 79 enum rockchip_pin_drv_type drv_type; 80 int offset; 81 }; 82 83 /** 84 * @priv: common pinctrl private basedata 85 * @pin_base: first pin number 86 * @nr_pins: number of pins in this bank 87 * @name: name of the bank 88 * @bank_num: number of the bank, to account for holes 89 * @iomux: array describing the 4 iomux sources of the bank 90 * @drv: array describing the 4 drive strength sources of the bank 91 * @pull_type: array describing the 4 pull type sources of the bank 92 * @recalced_mask: bits describing the mux recalced pins of per bank 93 * @route_mask: bits describing the routing pins of per bank 94 */ 95 struct rockchip_pin_bank { 96 struct rockchip_pinctrl_priv *priv; 97 u32 pin_base; 98 u8 nr_pins; 99 char *name; 100 u8 bank_num; 101 struct rockchip_iomux iomux[4]; 102 struct rockchip_drv drv[4]; 103 enum rockchip_pin_pull_type pull_type[4]; 104 u32 recalced_mask; 105 u32 route_mask; 106 }; 107 108 #define PIN_BANK(id, pins, label) \ 109 { \ 110 .bank_num = id, \ 111 .nr_pins = pins, \ 112 .name = label, \ 113 .iomux = { \ 114 { .offset = -1 }, \ 115 { .offset = -1 }, \ 116 { .offset = -1 }, \ 117 { .offset = -1 }, \ 118 }, \ 119 } 120 121 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 122 { \ 123 .bank_num = id, \ 124 .nr_pins = pins, \ 125 .name = label, \ 126 .iomux = { \ 127 { .type = iom0, .offset = -1 }, \ 128 { .type = iom1, .offset = -1 }, \ 129 { .type = iom2, .offset = -1 }, \ 130 { .type = iom3, .offset = -1 }, \ 131 }, \ 132 } 133 134 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 135 { \ 136 .bank_num = id, \ 137 .nr_pins = pins, \ 138 .name = label, \ 139 .iomux = { \ 140 { .offset = -1 }, \ 141 { .offset = -1 }, \ 142 { .offset = -1 }, \ 143 { .offset = -1 }, \ 144 }, \ 145 .drv = { \ 146 { .drv_type = type0, .offset = -1 }, \ 147 { .drv_type = type1, .offset = -1 }, \ 148 { .drv_type = type2, .offset = -1 }, \ 149 { .drv_type = type3, .offset = -1 }, \ 150 }, \ 151 } 152 153 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 154 drv2, drv3, pull0, pull1, \ 155 pull2, pull3) \ 156 { \ 157 .bank_num = id, \ 158 .nr_pins = pins, \ 159 .name = label, \ 160 .iomux = { \ 161 { .offset = -1 }, \ 162 { .offset = -1 }, \ 163 { .offset = -1 }, \ 164 { .offset = -1 }, \ 165 }, \ 166 .drv = { \ 167 { .drv_type = drv0, .offset = -1 }, \ 168 { .drv_type = drv1, .offset = -1 }, \ 169 { .drv_type = drv2, .offset = -1 }, \ 170 { .drv_type = drv3, .offset = -1 }, \ 171 }, \ 172 .pull_type[0] = pull0, \ 173 .pull_type[1] = pull1, \ 174 .pull_type[2] = pull2, \ 175 .pull_type[3] = pull3, \ 176 } 177 178 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 179 iom2, iom3, drv0, drv1, drv2, \ 180 drv3, offset0, offset1, \ 181 offset2, offset3) \ 182 { \ 183 .bank_num = id, \ 184 .nr_pins = pins, \ 185 .name = label, \ 186 .iomux = { \ 187 { .type = iom0, .offset = -1 }, \ 188 { .type = iom1, .offset = -1 }, \ 189 { .type = iom2, .offset = -1 }, \ 190 { .type = iom3, .offset = -1 }, \ 191 }, \ 192 .drv = { \ 193 { .drv_type = drv0, .offset = offset0 }, \ 194 { .drv_type = drv1, .offset = offset1 }, \ 195 { .drv_type = drv2, .offset = offset2 }, \ 196 { .drv_type = drv3, .offset = offset3 }, \ 197 }, \ 198 } 199 200 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 201 label, iom0, iom1, iom2, \ 202 iom3, drv0, drv1, drv2, \ 203 drv3, offset0, offset1, \ 204 offset2, offset3, pull0, \ 205 pull1, pull2, pull3) \ 206 { \ 207 .bank_num = id, \ 208 .nr_pins = pins, \ 209 .name = label, \ 210 .iomux = { \ 211 { .type = iom0, .offset = -1 }, \ 212 { .type = iom1, .offset = -1 }, \ 213 { .type = iom2, .offset = -1 }, \ 214 { .type = iom3, .offset = -1 }, \ 215 }, \ 216 .drv = { \ 217 { .drv_type = drv0, .offset = offset0 }, \ 218 { .drv_type = drv1, .offset = offset1 }, \ 219 { .drv_type = drv2, .offset = offset2 }, \ 220 { .drv_type = drv3, .offset = offset3 }, \ 221 }, \ 222 .pull_type[0] = pull0, \ 223 .pull_type[1] = pull1, \ 224 .pull_type[2] = pull2, \ 225 .pull_type[3] = pull3, \ 226 } 227 228 /** 229 * struct rockchip_mux_recalced_data: represent a pin iomux data. 230 * @num: bank number. 231 * @pin: pin number. 232 * @bit: index at register. 233 * @reg: register offset. 234 * @mask: mask bit 235 */ 236 struct rockchip_mux_recalced_data { 237 u8 num; 238 u8 pin; 239 u32 reg; 240 u8 bit; 241 u8 mask; 242 }; 243 244 /** 245 * struct rockchip_mux_recalced_data: represent a pin iomux data. 246 * @bank_num: bank number. 247 * @pin: index at register or used to calc index. 248 * @func: the min pin. 249 * @route_offset: the max pin. 250 * @route_val: the register offset. 251 */ 252 struct rockchip_mux_route_data { 253 u8 bank_num; 254 u8 pin; 255 u8 func; 256 u32 route_offset; 257 u32 route_val; 258 }; 259 260 /** 261 */ 262 struct rockchip_pin_ctrl { 263 struct rockchip_pin_bank *pin_banks; 264 u32 nr_banks; 265 u32 nr_pins; 266 char *label; 267 enum rockchip_pinctrl_type type; 268 int grf_mux_offset; 269 int pmu_mux_offset; 270 int grf_drv_offset; 271 int pmu_drv_offset; 272 struct rockchip_mux_recalced_data *iomux_recalced; 273 u32 niomux_recalced; 274 struct rockchip_mux_route_data *iomux_routes; 275 u32 niomux_routes; 276 277 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 278 int pin_num, struct regmap **regmap, 279 int *reg, u8 *bit); 280 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 281 int pin_num, struct regmap **regmap, 282 int *reg, u8 *bit); 283 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 284 int pin_num, struct regmap **regmap, 285 int *reg, u8 *bit); 286 }; 287 288 /** 289 */ 290 struct rockchip_pinctrl_priv { 291 struct rockchip_pin_ctrl *ctrl; 292 struct regmap *regmap_base; 293 struct regmap *regmap_pmu; 294 295 }; 296 297 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 298 { 299 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 300 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 301 302 if (bank >= ctrl->nr_banks) { 303 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 304 return -EINVAL; 305 } 306 307 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 308 debug("pin conf pin %d >= %d\n", pin, 309 MAX_ROCKCHIP_GPIO_PER_BANK); 310 return -EINVAL; 311 } 312 313 return 0; 314 } 315 316 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 317 { 318 .num = 1, 319 .pin = 0, 320 .reg = 0x418, 321 .bit = 0, 322 .mask = 0x3 323 }, { 324 .num = 1, 325 .pin = 1, 326 .reg = 0x418, 327 .bit = 2, 328 .mask = 0x3 329 }, { 330 .num = 1, 331 .pin = 2, 332 .reg = 0x418, 333 .bit = 4, 334 .mask = 0x3 335 }, { 336 .num = 1, 337 .pin = 3, 338 .reg = 0x418, 339 .bit = 6, 340 .mask = 0x3 341 }, { 342 .num = 1, 343 .pin = 4, 344 .reg = 0x418, 345 .bit = 8, 346 .mask = 0x3 347 }, { 348 .num = 1, 349 .pin = 5, 350 .reg = 0x418, 351 .bit = 10, 352 .mask = 0x3 353 }, { 354 .num = 1, 355 .pin = 6, 356 .reg = 0x418, 357 .bit = 12, 358 .mask = 0x3 359 }, { 360 .num = 1, 361 .pin = 7, 362 .reg = 0x418, 363 .bit = 14, 364 .mask = 0x3 365 }, { 366 .num = 1, 367 .pin = 8, 368 .reg = 0x41c, 369 .bit = 0, 370 .mask = 0x3 371 }, { 372 .num = 1, 373 .pin = 9, 374 .reg = 0x41c, 375 .bit = 2, 376 .mask = 0x3 377 }, 378 }; 379 380 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 381 { 382 .num = 2, 383 .pin = 20, 384 .reg = 0xe8, 385 .bit = 0, 386 .mask = 0x7 387 }, { 388 .num = 2, 389 .pin = 21, 390 .reg = 0xe8, 391 .bit = 4, 392 .mask = 0x7 393 }, { 394 .num = 2, 395 .pin = 22, 396 .reg = 0xe8, 397 .bit = 8, 398 .mask = 0x7 399 }, { 400 .num = 2, 401 .pin = 23, 402 .reg = 0xe8, 403 .bit = 12, 404 .mask = 0x7 405 }, { 406 .num = 2, 407 .pin = 24, 408 .reg = 0xd4, 409 .bit = 12, 410 .mask = 0x7 411 }, 412 }; 413 414 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 415 { 416 .num = 2, 417 .pin = 12, 418 .reg = 0x24, 419 .bit = 8, 420 .mask = 0x3 421 }, { 422 .num = 2, 423 .pin = 15, 424 .reg = 0x28, 425 .bit = 0, 426 .mask = 0x7 427 }, { 428 .num = 2, 429 .pin = 23, 430 .reg = 0x30, 431 .bit = 14, 432 .mask = 0x3 433 }, 434 }; 435 436 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 437 int *reg, u8 *bit, int *mask) 438 { 439 struct rockchip_pinctrl_priv *priv = bank->priv; 440 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 441 struct rockchip_mux_recalced_data *data; 442 int i; 443 444 for (i = 0; i < ctrl->niomux_recalced; i++) { 445 data = &ctrl->iomux_recalced[i]; 446 if (data->num == bank->bank_num && 447 data->pin == pin) 448 break; 449 } 450 451 if (i >= ctrl->niomux_recalced) 452 return; 453 454 *reg = data->reg; 455 *mask = data->mask; 456 *bit = data->bit; 457 } 458 459 static struct rockchip_mux_route_data px30_mux_route_data[] = { 460 { 461 /* cif-d2m0 */ 462 .bank_num = 2, 463 .pin = 0, 464 .func = 1, 465 .route_offset = 0x184, 466 .route_val = BIT(16 + 7), 467 }, { 468 /* cif-d2m1 */ 469 .bank_num = 3, 470 .pin = 3, 471 .func = 3, 472 .route_offset = 0x184, 473 .route_val = BIT(16 + 7) | BIT(7), 474 }, { 475 /* pdm-m0 */ 476 .bank_num = 3, 477 .pin = 22, 478 .func = 2, 479 .route_offset = 0x184, 480 .route_val = BIT(16 + 8), 481 }, { 482 /* pdm-m1 */ 483 .bank_num = 2, 484 .pin = 22, 485 .func = 1, 486 .route_offset = 0x184, 487 .route_val = BIT(16 + 8) | BIT(8), 488 }, { 489 /* uart2-rxm0 */ 490 .bank_num = 1, 491 .pin = 26, 492 .func = 2, 493 .route_offset = 0x184, 494 .route_val = BIT(16 + 9), 495 }, { 496 /* uart2-rxm1 */ 497 .bank_num = 2, 498 .pin = 14, 499 .func = 2, 500 .route_offset = 0x184, 501 .route_val = BIT(16 + 9) | BIT(9), 502 }, { 503 /* uart3-rxm0 */ 504 .bank_num = 0, 505 .pin = 17, 506 .func = 2, 507 .route_offset = 0x184, 508 .route_val = BIT(16 + 10), 509 }, { 510 /* uart3-rxm1 */ 511 .bank_num = 1, 512 .pin = 13, 513 .func = 2, 514 .route_offset = 0x184, 515 .route_val = BIT(16 + 10) | BIT(10), 516 }, 517 }; 518 519 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 520 { 521 /* spi-0 */ 522 .bank_num = 1, 523 .pin = 10, 524 .func = 1, 525 .route_offset = 0x144, 526 .route_val = BIT(16 + 3) | BIT(16 + 4), 527 }, { 528 /* spi-1 */ 529 .bank_num = 1, 530 .pin = 27, 531 .func = 3, 532 .route_offset = 0x144, 533 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 534 }, { 535 /* spi-2 */ 536 .bank_num = 0, 537 .pin = 13, 538 .func = 2, 539 .route_offset = 0x144, 540 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 541 }, { 542 /* i2s-0 */ 543 .bank_num = 1, 544 .pin = 5, 545 .func = 1, 546 .route_offset = 0x144, 547 .route_val = BIT(16 + 5), 548 }, { 549 /* i2s-1 */ 550 .bank_num = 0, 551 .pin = 14, 552 .func = 1, 553 .route_offset = 0x144, 554 .route_val = BIT(16 + 5) | BIT(5), 555 }, { 556 /* emmc-0 */ 557 .bank_num = 1, 558 .pin = 22, 559 .func = 2, 560 .route_offset = 0x144, 561 .route_val = BIT(16 + 6), 562 }, { 563 /* emmc-1 */ 564 .bank_num = 2, 565 .pin = 4, 566 .func = 2, 567 .route_offset = 0x144, 568 .route_val = BIT(16 + 6) | BIT(6), 569 }, 570 }; 571 572 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 573 { 574 /* pwm0-0 */ 575 .bank_num = 0, 576 .pin = 26, 577 .func = 1, 578 .route_offset = 0x50, 579 .route_val = BIT(16), 580 }, { 581 /* pwm0-1 */ 582 .bank_num = 3, 583 .pin = 21, 584 .func = 1, 585 .route_offset = 0x50, 586 .route_val = BIT(16) | BIT(0), 587 }, { 588 /* pwm1-0 */ 589 .bank_num = 0, 590 .pin = 27, 591 .func = 1, 592 .route_offset = 0x50, 593 .route_val = BIT(16 + 1), 594 }, { 595 /* pwm1-1 */ 596 .bank_num = 0, 597 .pin = 30, 598 .func = 2, 599 .route_offset = 0x50, 600 .route_val = BIT(16 + 1) | BIT(1), 601 }, { 602 /* pwm2-0 */ 603 .bank_num = 0, 604 .pin = 28, 605 .func = 1, 606 .route_offset = 0x50, 607 .route_val = BIT(16 + 2), 608 }, { 609 /* pwm2-1 */ 610 .bank_num = 1, 611 .pin = 12, 612 .func = 2, 613 .route_offset = 0x50, 614 .route_val = BIT(16 + 2) | BIT(2), 615 }, { 616 /* pwm3-0 */ 617 .bank_num = 3, 618 .pin = 26, 619 .func = 1, 620 .route_offset = 0x50, 621 .route_val = BIT(16 + 3), 622 }, { 623 /* pwm3-1 */ 624 .bank_num = 1, 625 .pin = 11, 626 .func = 2, 627 .route_offset = 0x50, 628 .route_val = BIT(16 + 3) | BIT(3), 629 }, { 630 /* sdio-0_d0 */ 631 .bank_num = 1, 632 .pin = 1, 633 .func = 1, 634 .route_offset = 0x50, 635 .route_val = BIT(16 + 4), 636 }, { 637 /* sdio-1_d0 */ 638 .bank_num = 3, 639 .pin = 2, 640 .func = 1, 641 .route_offset = 0x50, 642 .route_val = BIT(16 + 4) | BIT(4), 643 }, { 644 /* spi-0_rx */ 645 .bank_num = 0, 646 .pin = 13, 647 .func = 2, 648 .route_offset = 0x50, 649 .route_val = BIT(16 + 5), 650 }, { 651 /* spi-1_rx */ 652 .bank_num = 2, 653 .pin = 0, 654 .func = 2, 655 .route_offset = 0x50, 656 .route_val = BIT(16 + 5) | BIT(5), 657 }, { 658 /* emmc-0_cmd */ 659 .bank_num = 1, 660 .pin = 22, 661 .func = 2, 662 .route_offset = 0x50, 663 .route_val = BIT(16 + 7), 664 }, { 665 /* emmc-1_cmd */ 666 .bank_num = 2, 667 .pin = 4, 668 .func = 2, 669 .route_offset = 0x50, 670 .route_val = BIT(16 + 7) | BIT(7), 671 }, { 672 /* uart2-0_rx */ 673 .bank_num = 1, 674 .pin = 19, 675 .func = 2, 676 .route_offset = 0x50, 677 .route_val = BIT(16 + 8), 678 }, { 679 /* uart2-1_rx */ 680 .bank_num = 1, 681 .pin = 10, 682 .func = 2, 683 .route_offset = 0x50, 684 .route_val = BIT(16 + 8) | BIT(8), 685 }, { 686 /* uart1-0_rx */ 687 .bank_num = 1, 688 .pin = 10, 689 .func = 1, 690 .route_offset = 0x50, 691 .route_val = BIT(16 + 11), 692 }, { 693 /* uart1-1_rx */ 694 .bank_num = 3, 695 .pin = 13, 696 .func = 1, 697 .route_offset = 0x50, 698 .route_val = BIT(16 + 11) | BIT(11), 699 }, 700 }; 701 702 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 703 { 704 /* edphdmi_cecinoutt1 */ 705 .bank_num = 7, 706 .pin = 16, 707 .func = 2, 708 .route_offset = 0x264, 709 .route_val = BIT(16 + 12) | BIT(12), 710 }, { 711 /* edphdmi_cecinout */ 712 .bank_num = 7, 713 .pin = 23, 714 .func = 4, 715 .route_offset = 0x264, 716 .route_val = BIT(16 + 12), 717 }, 718 }; 719 720 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 721 { 722 /* uart2dbg_rxm0 */ 723 .bank_num = 1, 724 .pin = 1, 725 .func = 2, 726 .route_offset = 0x50, 727 .route_val = BIT(16) | BIT(16 + 1), 728 }, { 729 /* uart2dbg_rxm1 */ 730 .bank_num = 2, 731 .pin = 1, 732 .func = 1, 733 .route_offset = 0x50, 734 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 735 }, { 736 /* gmac-m1_rxd0 */ 737 .bank_num = 1, 738 .pin = 11, 739 .func = 2, 740 .route_offset = 0x50, 741 .route_val = BIT(16 + 2) | BIT(2), 742 }, { 743 /* gmac-m1-optimized_rxd3 */ 744 .bank_num = 1, 745 .pin = 14, 746 .func = 2, 747 .route_offset = 0x50, 748 .route_val = BIT(16 + 10) | BIT(10), 749 }, { 750 /* pdm_sdi0m0 */ 751 .bank_num = 2, 752 .pin = 19, 753 .func = 2, 754 .route_offset = 0x50, 755 .route_val = BIT(16 + 3), 756 }, { 757 /* pdm_sdi0m1 */ 758 .bank_num = 1, 759 .pin = 23, 760 .func = 3, 761 .route_offset = 0x50, 762 .route_val = BIT(16 + 3) | BIT(3), 763 }, { 764 /* spi_rxdm2 */ 765 .bank_num = 3, 766 .pin = 2, 767 .func = 4, 768 .route_offset = 0x50, 769 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 770 }, { 771 /* i2s2_sdim0 */ 772 .bank_num = 1, 773 .pin = 24, 774 .func = 1, 775 .route_offset = 0x50, 776 .route_val = BIT(16 + 6), 777 }, { 778 /* i2s2_sdim1 */ 779 .bank_num = 3, 780 .pin = 2, 781 .func = 6, 782 .route_offset = 0x50, 783 .route_val = BIT(16 + 6) | BIT(6), 784 }, { 785 /* card_iom1 */ 786 .bank_num = 2, 787 .pin = 22, 788 .func = 3, 789 .route_offset = 0x50, 790 .route_val = BIT(16 + 7) | BIT(7), 791 }, { 792 /* tsp_d5m1 */ 793 .bank_num = 2, 794 .pin = 16, 795 .func = 3, 796 .route_offset = 0x50, 797 .route_val = BIT(16 + 8) | BIT(8), 798 }, { 799 /* cif_data5m1 */ 800 .bank_num = 2, 801 .pin = 16, 802 .func = 4, 803 .route_offset = 0x50, 804 .route_val = BIT(16 + 9) | BIT(9), 805 }, 806 }; 807 808 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 809 { 810 /* uart2dbga_rx */ 811 .bank_num = 4, 812 .pin = 8, 813 .func = 2, 814 .route_offset = 0xe21c, 815 .route_val = BIT(16 + 10) | BIT(16 + 11), 816 }, { 817 /* uart2dbgb_rx */ 818 .bank_num = 4, 819 .pin = 16, 820 .func = 2, 821 .route_offset = 0xe21c, 822 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 823 }, { 824 /* uart2dbgc_rx */ 825 .bank_num = 4, 826 .pin = 19, 827 .func = 1, 828 .route_offset = 0xe21c, 829 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 830 }, { 831 /* pcie_clkreqn */ 832 .bank_num = 2, 833 .pin = 26, 834 .func = 2, 835 .route_offset = 0xe21c, 836 .route_val = BIT(16 + 14), 837 }, { 838 /* pcie_clkreqnb */ 839 .bank_num = 4, 840 .pin = 24, 841 .func = 1, 842 .route_offset = 0xe21c, 843 .route_val = BIT(16 + 14) | BIT(14), 844 }, 845 }; 846 847 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 848 int mux, u32 *reg, u32 *value) 849 { 850 struct rockchip_pinctrl_priv *priv = bank->priv; 851 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 852 struct rockchip_mux_route_data *data; 853 int i; 854 855 for (i = 0; i < ctrl->niomux_routes; i++) { 856 data = &ctrl->iomux_routes[i]; 857 if ((data->bank_num == bank->bank_num) && 858 (data->pin == pin) && (data->func == mux)) 859 break; 860 } 861 862 if (i >= ctrl->niomux_routes) 863 return false; 864 865 *reg = data->route_offset; 866 *value = data->route_val; 867 868 return true; 869 } 870 871 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 872 { 873 struct rockchip_pinctrl_priv *priv = bank->priv; 874 int iomux_num = (pin / 8); 875 struct regmap *regmap; 876 unsigned int val; 877 int reg, ret, mask, mux_type; 878 u8 bit; 879 880 if (iomux_num > 3) 881 return -EINVAL; 882 883 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 884 debug("pin %d is unrouted\n", pin); 885 return -EINVAL; 886 } 887 888 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 889 return RK_FUNC_GPIO; 890 891 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 892 ? priv->regmap_pmu : priv->regmap_base; 893 894 /* get basic quadrupel of mux registers and the correct reg inside */ 895 mux_type = bank->iomux[iomux_num].type; 896 reg = bank->iomux[iomux_num].offset; 897 if (mux_type & IOMUX_WIDTH_4BIT) { 898 if ((pin % 8) >= 4) 899 reg += 0x4; 900 bit = (pin % 4) * 4; 901 mask = 0xf; 902 } else if (mux_type & IOMUX_WIDTH_3BIT) { 903 if ((pin % 8) >= 5) 904 reg += 0x4; 905 bit = (pin % 8 % 5) * 3; 906 mask = 0x7; 907 } else { 908 bit = (pin % 8) * 2; 909 mask = 0x3; 910 } 911 912 if (bank->recalced_mask & BIT(pin)) 913 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 914 915 ret = regmap_read(regmap, reg, &val); 916 if (ret) 917 return ret; 918 919 return ((val >> bit) & mask); 920 } 921 922 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 923 int index) 924 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 925 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 926 927 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 928 } 929 930 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 931 int pin, int mux) 932 { 933 int iomux_num = (pin / 8); 934 935 if (iomux_num > 3) 936 return -EINVAL; 937 938 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 939 debug("pin %d is unrouted\n", pin); 940 return -EINVAL; 941 } 942 943 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 944 if (mux != IOMUX_GPIO_ONLY) { 945 debug("pin %d only supports a gpio mux\n", pin); 946 return -ENOTSUPP; 947 } 948 } 949 950 return 0; 951 } 952 953 /* 954 * Set a new mux function for a pin. 955 * 956 * The register is divided into the upper and lower 16 bit. When changing 957 * a value, the previous register value is not read and changed. Instead 958 * it seems the changed bits are marked in the upper 16 bit, while the 959 * changed value gets set in the same offset in the lower 16 bit. 960 * All pin settings seem to be 2 bit wide in both the upper and lower 961 * parts. 962 * @bank: pin bank to change 963 * @pin: pin to change 964 * @mux: new mux function to set 965 */ 966 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 967 { 968 struct rockchip_pinctrl_priv *priv = bank->priv; 969 int iomux_num = (pin / 8); 970 struct regmap *regmap; 971 int reg, ret, mask, mux_type; 972 u8 bit; 973 u32 data, route_reg, route_val; 974 975 ret = rockchip_verify_mux(bank, pin, mux); 976 if (ret < 0) 977 return ret; 978 979 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 980 return 0; 981 982 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 983 984 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 985 ? priv->regmap_pmu : priv->regmap_base; 986 987 /* get basic quadrupel of mux registers and the correct reg inside */ 988 mux_type = bank->iomux[iomux_num].type; 989 reg = bank->iomux[iomux_num].offset; 990 if (mux_type & IOMUX_WIDTH_4BIT) { 991 if ((pin % 8) >= 4) 992 reg += 0x4; 993 bit = (pin % 4) * 4; 994 mask = 0xf; 995 } else if (mux_type & IOMUX_WIDTH_3BIT) { 996 if ((pin % 8) >= 5) 997 reg += 0x4; 998 bit = (pin % 8 % 5) * 3; 999 mask = 0x7; 1000 } else { 1001 bit = (pin % 8) * 2; 1002 mask = 0x3; 1003 } 1004 1005 if (bank->recalced_mask & BIT(pin)) 1006 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1007 1008 if (bank->route_mask & BIT(pin)) { 1009 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1010 &route_val)) { 1011 ret = regmap_write(regmap, route_reg, route_val); 1012 if (ret) 1013 return ret; 1014 } 1015 } 1016 1017 data = (mask << (bit + 16)); 1018 data |= (mux & mask) << bit; 1019 ret = regmap_write(regmap, reg, data); 1020 1021 return ret; 1022 } 1023 1024 #define PX30_PULL_PMU_OFFSET 0x10 1025 #define PX30_PULL_GRF_OFFSET 0x60 1026 #define PX30_PULL_BITS_PER_PIN 2 1027 #define PX30_PULL_PINS_PER_REG 8 1028 #define PX30_PULL_BANK_STRIDE 16 1029 1030 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1031 int pin_num, struct regmap **regmap, 1032 int *reg, u8 *bit) 1033 { 1034 struct rockchip_pinctrl_priv *priv = bank->priv; 1035 1036 /* The first 32 pins of the first bank are located in PMU */ 1037 if (bank->bank_num == 0) { 1038 *regmap = priv->regmap_pmu; 1039 *reg = PX30_PULL_PMU_OFFSET; 1040 } else { 1041 *regmap = priv->regmap_base; 1042 *reg = PX30_PULL_GRF_OFFSET; 1043 1044 /* correct the offset, as we're starting with the 2nd bank */ 1045 *reg -= 0x10; 1046 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1047 } 1048 1049 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1050 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1051 *bit *= PX30_PULL_BITS_PER_PIN; 1052 } 1053 1054 #define PX30_DRV_PMU_OFFSET 0x20 1055 #define PX30_DRV_GRF_OFFSET 0xf0 1056 #define PX30_DRV_BITS_PER_PIN 2 1057 #define PX30_DRV_PINS_PER_REG 8 1058 #define PX30_DRV_BANK_STRIDE 16 1059 1060 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1061 int pin_num, struct regmap **regmap, 1062 int *reg, u8 *bit) 1063 { 1064 struct rockchip_pinctrl_priv *priv = bank->priv; 1065 1066 /* The first 32 pins of the first bank are located in PMU */ 1067 if (bank->bank_num == 0) { 1068 *regmap = priv->regmap_pmu; 1069 *reg = PX30_DRV_PMU_OFFSET; 1070 } else { 1071 *regmap = priv->regmap_base; 1072 *reg = PX30_DRV_GRF_OFFSET; 1073 1074 /* correct the offset, as we're starting with the 2nd bank */ 1075 *reg -= 0x10; 1076 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1077 } 1078 1079 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1080 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1081 *bit *= PX30_DRV_BITS_PER_PIN; 1082 } 1083 1084 #define PX30_SCHMITT_PMU_OFFSET 0x38 1085 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1086 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1087 #define PX30_SCHMITT_BANK_STRIDE 16 1088 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1089 1090 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1091 int pin_num, 1092 struct regmap **regmap, 1093 int *reg, u8 *bit) 1094 { 1095 struct rockchip_pinctrl_priv *priv = bank->priv; 1096 int pins_per_reg; 1097 1098 if (bank->bank_num == 0) { 1099 *regmap = priv->regmap_pmu; 1100 *reg = PX30_SCHMITT_PMU_OFFSET; 1101 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1102 } else { 1103 *regmap = priv->regmap_base; 1104 *reg = PX30_SCHMITT_GRF_OFFSET; 1105 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1106 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1107 } 1108 *reg += ((pin_num / pins_per_reg) * 4); 1109 *bit = pin_num % pins_per_reg; 1110 1111 return 0; 1112 } 1113 1114 #define RV1108_PULL_PMU_OFFSET 0x10 1115 #define RV1108_PULL_OFFSET 0x110 1116 #define RV1108_PULL_PINS_PER_REG 8 1117 #define RV1108_PULL_BITS_PER_PIN 2 1118 #define RV1108_PULL_BANK_STRIDE 16 1119 1120 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1121 int pin_num, struct regmap **regmap, 1122 int *reg, u8 *bit) 1123 { 1124 struct rockchip_pinctrl_priv *priv = bank->priv; 1125 1126 /* The first 24 pins of the first bank are located in PMU */ 1127 if (bank->bank_num == 0) { 1128 *regmap = priv->regmap_pmu; 1129 *reg = RV1108_PULL_PMU_OFFSET; 1130 } else { 1131 *reg = RV1108_PULL_OFFSET; 1132 *regmap = priv->regmap_base; 1133 /* correct the offset, as we're starting with the 2nd bank */ 1134 *reg -= 0x10; 1135 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1136 } 1137 1138 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1139 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1140 *bit *= RV1108_PULL_BITS_PER_PIN; 1141 } 1142 1143 #define RV1108_DRV_PMU_OFFSET 0x20 1144 #define RV1108_DRV_GRF_OFFSET 0x210 1145 #define RV1108_DRV_BITS_PER_PIN 2 1146 #define RV1108_DRV_PINS_PER_REG 8 1147 #define RV1108_DRV_BANK_STRIDE 16 1148 1149 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1150 int pin_num, struct regmap **regmap, 1151 int *reg, u8 *bit) 1152 { 1153 struct rockchip_pinctrl_priv *priv = bank->priv; 1154 1155 /* The first 24 pins of the first bank are located in PMU */ 1156 if (bank->bank_num == 0) { 1157 *regmap = priv->regmap_pmu; 1158 *reg = RV1108_DRV_PMU_OFFSET; 1159 } else { 1160 *regmap = priv->regmap_base; 1161 *reg = RV1108_DRV_GRF_OFFSET; 1162 1163 /* correct the offset, as we're starting with the 2nd bank */ 1164 *reg -= 0x10; 1165 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1166 } 1167 1168 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1169 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1170 *bit *= RV1108_DRV_BITS_PER_PIN; 1171 } 1172 1173 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1174 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1175 #define RV1108_SCHMITT_BANK_STRIDE 8 1176 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1177 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1178 1179 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1180 int pin_num, 1181 struct regmap **regmap, 1182 int *reg, u8 *bit) 1183 { 1184 struct rockchip_pinctrl_priv *priv = bank->priv; 1185 int pins_per_reg; 1186 1187 if (bank->bank_num == 0) { 1188 *regmap = priv->regmap_pmu; 1189 *reg = RV1108_SCHMITT_PMU_OFFSET; 1190 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1191 } else { 1192 *regmap = priv->regmap_base; 1193 *reg = RV1108_SCHMITT_GRF_OFFSET; 1194 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1195 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1196 } 1197 *reg += ((pin_num / pins_per_reg) * 4); 1198 *bit = pin_num % pins_per_reg; 1199 1200 return 0; 1201 } 1202 1203 #define RK2928_PULL_OFFSET 0x118 1204 #define RK2928_PULL_PINS_PER_REG 16 1205 #define RK2928_PULL_BANK_STRIDE 8 1206 1207 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1208 int pin_num, struct regmap **regmap, 1209 int *reg, u8 *bit) 1210 { 1211 struct rockchip_pinctrl_priv *priv = bank->priv; 1212 1213 *regmap = priv->regmap_base; 1214 *reg = RK2928_PULL_OFFSET; 1215 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1216 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1217 1218 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1219 }; 1220 1221 #define RK3128_PULL_OFFSET 0x118 1222 1223 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1224 int pin_num, struct regmap **regmap, 1225 int *reg, u8 *bit) 1226 { 1227 struct rockchip_pinctrl_priv *priv = bank->priv; 1228 1229 *regmap = priv->regmap_base; 1230 *reg = RK3128_PULL_OFFSET; 1231 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1232 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1233 1234 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1235 } 1236 1237 #define RK3188_PULL_OFFSET 0x164 1238 #define RK3188_PULL_BITS_PER_PIN 2 1239 #define RK3188_PULL_PINS_PER_REG 8 1240 #define RK3188_PULL_BANK_STRIDE 16 1241 #define RK3188_PULL_PMU_OFFSET 0x64 1242 1243 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1244 int pin_num, struct regmap **regmap, 1245 int *reg, u8 *bit) 1246 { 1247 struct rockchip_pinctrl_priv *priv = bank->priv; 1248 1249 /* The first 12 pins of the first bank are located elsewhere */ 1250 if (bank->bank_num == 0 && pin_num < 12) { 1251 *regmap = priv->regmap_pmu; 1252 *reg = RK3188_PULL_PMU_OFFSET; 1253 1254 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1255 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1256 *bit *= RK3188_PULL_BITS_PER_PIN; 1257 } else { 1258 *regmap = priv->regmap_base; 1259 *reg = RK3188_PULL_OFFSET; 1260 1261 /* correct the offset, as it is the 2nd pull register */ 1262 *reg -= 4; 1263 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1264 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1265 1266 /* 1267 * The bits in these registers have an inverse ordering 1268 * with the lowest pin being in bits 15:14 and the highest 1269 * pin in bits 1:0 1270 */ 1271 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1272 *bit *= RK3188_PULL_BITS_PER_PIN; 1273 } 1274 } 1275 1276 #define RK3288_PULL_OFFSET 0x140 1277 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1278 int pin_num, struct regmap **regmap, 1279 int *reg, u8 *bit) 1280 { 1281 struct rockchip_pinctrl_priv *priv = bank->priv; 1282 1283 /* The first 24 pins of the first bank are located in PMU */ 1284 if (bank->bank_num == 0) { 1285 *regmap = priv->regmap_pmu; 1286 *reg = RK3188_PULL_PMU_OFFSET; 1287 1288 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1289 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1290 *bit *= RK3188_PULL_BITS_PER_PIN; 1291 } else { 1292 *regmap = priv->regmap_base; 1293 *reg = RK3288_PULL_OFFSET; 1294 1295 /* correct the offset, as we're starting with the 2nd bank */ 1296 *reg -= 0x10; 1297 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1298 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1299 1300 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1301 *bit *= RK3188_PULL_BITS_PER_PIN; 1302 } 1303 } 1304 1305 #define RK3288_DRV_PMU_OFFSET 0x70 1306 #define RK3288_DRV_GRF_OFFSET 0x1c0 1307 #define RK3288_DRV_BITS_PER_PIN 2 1308 #define RK3288_DRV_PINS_PER_REG 8 1309 #define RK3288_DRV_BANK_STRIDE 16 1310 1311 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1312 int pin_num, struct regmap **regmap, 1313 int *reg, u8 *bit) 1314 { 1315 struct rockchip_pinctrl_priv *priv = bank->priv; 1316 1317 /* The first 24 pins of the first bank are located in PMU */ 1318 if (bank->bank_num == 0) { 1319 *regmap = priv->regmap_pmu; 1320 *reg = RK3288_DRV_PMU_OFFSET; 1321 1322 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1323 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1324 *bit *= RK3288_DRV_BITS_PER_PIN; 1325 } else { 1326 *regmap = priv->regmap_base; 1327 *reg = RK3288_DRV_GRF_OFFSET; 1328 1329 /* correct the offset, as we're starting with the 2nd bank */ 1330 *reg -= 0x10; 1331 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1332 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1333 1334 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1335 *bit *= RK3288_DRV_BITS_PER_PIN; 1336 } 1337 } 1338 1339 #define RK3228_PULL_OFFSET 0x100 1340 1341 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1342 int pin_num, struct regmap **regmap, 1343 int *reg, u8 *bit) 1344 { 1345 struct rockchip_pinctrl_priv *priv = bank->priv; 1346 1347 *regmap = priv->regmap_base; 1348 *reg = RK3228_PULL_OFFSET; 1349 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1350 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1351 1352 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1353 *bit *= RK3188_PULL_BITS_PER_PIN; 1354 } 1355 1356 #define RK3228_DRV_GRF_OFFSET 0x200 1357 1358 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1359 int pin_num, struct regmap **regmap, 1360 int *reg, u8 *bit) 1361 { 1362 struct rockchip_pinctrl_priv *priv = bank->priv; 1363 1364 *regmap = priv->regmap_base; 1365 *reg = RK3228_DRV_GRF_OFFSET; 1366 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1367 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1368 1369 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1370 *bit *= RK3288_DRV_BITS_PER_PIN; 1371 } 1372 1373 #define RK3368_PULL_GRF_OFFSET 0x100 1374 #define RK3368_PULL_PMU_OFFSET 0x10 1375 1376 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1377 int pin_num, struct regmap **regmap, 1378 int *reg, u8 *bit) 1379 { 1380 struct rockchip_pinctrl_priv *priv = bank->priv; 1381 1382 /* The first 32 pins of the first bank are located in PMU */ 1383 if (bank->bank_num == 0) { 1384 *regmap = priv->regmap_pmu; 1385 *reg = RK3368_PULL_PMU_OFFSET; 1386 1387 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1388 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1389 *bit *= RK3188_PULL_BITS_PER_PIN; 1390 } else { 1391 *regmap = priv->regmap_base; 1392 *reg = RK3368_PULL_GRF_OFFSET; 1393 1394 /* correct the offset, as we're starting with the 2nd bank */ 1395 *reg -= 0x10; 1396 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1397 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1398 1399 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1400 *bit *= RK3188_PULL_BITS_PER_PIN; 1401 } 1402 } 1403 1404 #define RK3368_DRV_PMU_OFFSET 0x20 1405 #define RK3368_DRV_GRF_OFFSET 0x200 1406 1407 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1408 int pin_num, struct regmap **regmap, 1409 int *reg, u8 *bit) 1410 { 1411 struct rockchip_pinctrl_priv *priv = bank->priv; 1412 1413 /* The first 32 pins of the first bank are located in PMU */ 1414 if (bank->bank_num == 0) { 1415 *regmap = priv->regmap_pmu; 1416 *reg = RK3368_DRV_PMU_OFFSET; 1417 1418 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1419 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1420 *bit *= RK3288_DRV_BITS_PER_PIN; 1421 } else { 1422 *regmap = priv->regmap_base; 1423 *reg = RK3368_DRV_GRF_OFFSET; 1424 1425 /* correct the offset, as we're starting with the 2nd bank */ 1426 *reg -= 0x10; 1427 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1428 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1429 1430 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1431 *bit *= RK3288_DRV_BITS_PER_PIN; 1432 } 1433 } 1434 1435 #define RK3399_PULL_GRF_OFFSET 0xe040 1436 #define RK3399_PULL_PMU_OFFSET 0x40 1437 #define RK3399_DRV_3BITS_PER_PIN 3 1438 1439 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1440 int pin_num, struct regmap **regmap, 1441 int *reg, u8 *bit) 1442 { 1443 struct rockchip_pinctrl_priv *priv = bank->priv; 1444 1445 /* The bank0:16 and bank1:32 pins are located in PMU */ 1446 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1447 *regmap = priv->regmap_pmu; 1448 *reg = RK3399_PULL_PMU_OFFSET; 1449 1450 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1451 1452 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1453 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1454 *bit *= RK3188_PULL_BITS_PER_PIN; 1455 } else { 1456 *regmap = priv->regmap_base; 1457 *reg = RK3399_PULL_GRF_OFFSET; 1458 1459 /* correct the offset, as we're starting with the 3rd bank */ 1460 *reg -= 0x20; 1461 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1462 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1463 1464 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1465 *bit *= RK3188_PULL_BITS_PER_PIN; 1466 } 1467 } 1468 1469 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1470 int pin_num, struct regmap **regmap, 1471 int *reg, u8 *bit) 1472 { 1473 struct rockchip_pinctrl_priv *priv = bank->priv; 1474 int drv_num = (pin_num / 8); 1475 1476 /* The bank0:16 and bank1:32 pins are located in PMU */ 1477 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1478 *regmap = priv->regmap_pmu; 1479 else 1480 *regmap = priv->regmap_base; 1481 1482 *reg = bank->drv[drv_num].offset; 1483 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1484 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1485 *bit = (pin_num % 8) * 3; 1486 else 1487 *bit = (pin_num % 8) * 2; 1488 } 1489 1490 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1491 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1492 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1493 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1494 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1495 { 4, 7, 10, 13, 16, 19, 22, 26 } 1496 }; 1497 1498 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1499 int pin_num, int strength) 1500 { 1501 struct rockchip_pinctrl_priv *priv = bank->priv; 1502 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1503 struct regmap *regmap; 1504 int reg, ret, i; 1505 u32 data, rmask_bits, temp; 1506 u8 bit; 1507 int drv_type = bank->drv[pin_num / 8].drv_type; 1508 1509 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 1510 pin_num, strength); 1511 1512 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1513 1514 ret = -EINVAL; 1515 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1516 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1517 ret = i; 1518 break; 1519 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1520 ret = rockchip_perpin_drv_list[drv_type][i]; 1521 break; 1522 } 1523 } 1524 1525 if (ret < 0) { 1526 debug("unsupported driver strength %d\n", strength); 1527 return ret; 1528 } 1529 1530 switch (drv_type) { 1531 case DRV_TYPE_IO_1V8_3V0_AUTO: 1532 case DRV_TYPE_IO_3V3_ONLY: 1533 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1534 switch (bit) { 1535 case 0 ... 12: 1536 /* regular case, nothing to do */ 1537 break; 1538 case 15: 1539 /* 1540 * drive-strength offset is special, as it is spread 1541 * over 2 registers, the bit data[15] contains bit 0 1542 * of the value while temp[1:0] contains bits 2 and 1 1543 */ 1544 data = (ret & 0x1) << 15; 1545 temp = (ret >> 0x1) & 0x3; 1546 1547 data |= BIT(31); 1548 ret = regmap_write(regmap, reg, data); 1549 if (ret) 1550 return ret; 1551 1552 temp |= (0x3 << 16); 1553 reg += 0x4; 1554 ret = regmap_write(regmap, reg, temp); 1555 1556 return ret; 1557 case 18 ... 21: 1558 /* setting fully enclosed in the second register */ 1559 reg += 4; 1560 bit -= 16; 1561 break; 1562 default: 1563 debug("unsupported bit: %d for pinctrl drive type: %d\n", 1564 bit, drv_type); 1565 return -EINVAL; 1566 } 1567 break; 1568 case DRV_TYPE_IO_DEFAULT: 1569 case DRV_TYPE_IO_1V8_OR_3V0: 1570 case DRV_TYPE_IO_1V8_ONLY: 1571 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1572 break; 1573 default: 1574 debug("unsupported pinctrl drive type: %d\n", 1575 drv_type); 1576 return -EINVAL; 1577 } 1578 1579 /* enable the write to the equivalent lower bits */ 1580 data = ((1 << rmask_bits) - 1) << (bit + 16); 1581 data |= (ret << bit); 1582 1583 ret = regmap_write(regmap, reg, data); 1584 return ret; 1585 } 1586 1587 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1588 { 1589 PIN_CONFIG_BIAS_DISABLE, 1590 PIN_CONFIG_BIAS_PULL_UP, 1591 PIN_CONFIG_BIAS_PULL_DOWN, 1592 PIN_CONFIG_BIAS_BUS_HOLD 1593 }, 1594 { 1595 PIN_CONFIG_BIAS_DISABLE, 1596 PIN_CONFIG_BIAS_PULL_DOWN, 1597 PIN_CONFIG_BIAS_DISABLE, 1598 PIN_CONFIG_BIAS_PULL_UP 1599 }, 1600 }; 1601 1602 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1603 int pin_num, int pull) 1604 { 1605 struct rockchip_pinctrl_priv *priv = bank->priv; 1606 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1607 struct regmap *regmap; 1608 int reg, ret, i, pull_type; 1609 u8 bit; 1610 u32 data; 1611 1612 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 1613 pin_num, pull); 1614 1615 /* rk3066b does support any pulls */ 1616 if (ctrl->type == RK3066B) 1617 return pull ? -EINVAL : 0; 1618 1619 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1620 1621 switch (ctrl->type) { 1622 case RK2928: 1623 case RK3128: 1624 data = BIT(bit + 16); 1625 if (pull == PIN_CONFIG_BIAS_DISABLE) 1626 data |= BIT(bit); 1627 ret = regmap_write(regmap, reg, data); 1628 break; 1629 case PX30: 1630 case RV1108: 1631 case RK3188: 1632 case RK3288: 1633 case RK3368: 1634 case RK3399: 1635 pull_type = bank->pull_type[pin_num / 8]; 1636 ret = -EINVAL; 1637 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 1638 i++) { 1639 if (rockchip_pull_list[pull_type][i] == pull) { 1640 ret = i; 1641 break; 1642 } 1643 } 1644 1645 if (ret < 0) { 1646 debug("unsupported pull setting %d\n", pull); 1647 return ret; 1648 } 1649 1650 /* enable the write to the equivalent lower bits */ 1651 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1652 data |= (ret << bit); 1653 1654 ret = regmap_write(regmap, reg, data); 1655 break; 1656 default: 1657 debug("unsupported pinctrl type\n"); 1658 return -EINVAL; 1659 } 1660 1661 return ret; 1662 } 1663 1664 #define RK3328_SCHMITT_BITS_PER_PIN 1 1665 #define RK3328_SCHMITT_PINS_PER_REG 16 1666 #define RK3328_SCHMITT_BANK_STRIDE 8 1667 #define RK3328_SCHMITT_GRF_OFFSET 0x380 1668 1669 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1670 int pin_num, 1671 struct regmap **regmap, 1672 int *reg, u8 *bit) 1673 { 1674 struct rockchip_pinctrl_priv *priv = bank->priv; 1675 1676 *regmap = priv->regmap_base; 1677 *reg = RK3328_SCHMITT_GRF_OFFSET; 1678 1679 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 1680 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 1681 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 1682 1683 return 0; 1684 } 1685 1686 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 1687 int pin_num, int enable) 1688 { 1689 struct rockchip_pinctrl_priv *priv = bank->priv; 1690 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1691 struct regmap *regmap; 1692 int reg, ret; 1693 u8 bit; 1694 u32 data; 1695 1696 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 1697 pin_num, enable); 1698 1699 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1700 if (ret) 1701 return ret; 1702 1703 /* enable the write to the equivalent lower bits */ 1704 data = BIT(bit + 16) | (enable << bit); 1705 1706 return regmap_write(regmap, reg, data); 1707 } 1708 1709 /* 1710 * Pinconf_ops handling 1711 */ 1712 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 1713 unsigned int pull) 1714 { 1715 switch (ctrl->type) { 1716 case RK2928: 1717 case RK3128: 1718 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 1719 pull == PIN_CONFIG_BIAS_DISABLE); 1720 case RK3066B: 1721 return pull ? false : true; 1722 case PX30: 1723 case RV1108: 1724 case RK3188: 1725 case RK3288: 1726 case RK3368: 1727 case RK3399: 1728 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 1729 } 1730 1731 return false; 1732 } 1733 1734 /* set the pin config settings for a specified pin */ 1735 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 1736 u32 pin, u32 param, u32 arg) 1737 { 1738 struct rockchip_pinctrl_priv *priv = bank->priv; 1739 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1740 int rc; 1741 1742 switch (param) { 1743 case PIN_CONFIG_BIAS_DISABLE: 1744 rc = rockchip_set_pull(bank, pin, param); 1745 if (rc) 1746 return rc; 1747 break; 1748 1749 case PIN_CONFIG_BIAS_PULL_UP: 1750 case PIN_CONFIG_BIAS_PULL_DOWN: 1751 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1752 case PIN_CONFIG_BIAS_BUS_HOLD: 1753 if (!rockchip_pinconf_pull_valid(ctrl, param)) 1754 return -ENOTSUPP; 1755 1756 if (!arg) 1757 return -EINVAL; 1758 1759 rc = rockchip_set_pull(bank, pin, param); 1760 if (rc) 1761 return rc; 1762 break; 1763 1764 case PIN_CONFIG_DRIVE_STRENGTH: 1765 if (!ctrl->drv_calc_reg) 1766 return -ENOTSUPP; 1767 1768 rc = rockchip_set_drive_perpin(bank, pin, arg); 1769 if (rc < 0) 1770 return rc; 1771 break; 1772 1773 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1774 if (!ctrl->schmitt_calc_reg) 1775 return -ENOTSUPP; 1776 1777 rc = rockchip_set_schmitt(bank, pin, arg); 1778 if (rc < 0) 1779 return rc; 1780 break; 1781 1782 default: 1783 break; 1784 } 1785 1786 return 0; 1787 } 1788 1789 static const struct pinconf_param rockchip_conf_params[] = { 1790 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 1791 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 1792 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 1793 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 1794 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 1795 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 1796 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 1797 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 1798 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 1799 }; 1800 1801 static int rockchip_pinconf_prop_name_to_param(const char *property, 1802 u32 *default_value) 1803 { 1804 const struct pinconf_param *p, *end; 1805 1806 p = rockchip_conf_params; 1807 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 1808 1809 /* See if this pctldev supports this parameter */ 1810 for (; p < end; p++) { 1811 if (!strcmp(property, p->property)) { 1812 *default_value = p->default_value; 1813 return p->param; 1814 } 1815 } 1816 1817 *default_value = 0; 1818 return -EPERM; 1819 } 1820 1821 static int rockchip_pinctrl_set_state(struct udevice *dev, 1822 struct udevice *config) 1823 { 1824 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1825 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1826 const void *blob = gd->fdt_blob; 1827 int node = dev_of_offset(config); 1828 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 1829 u32 bank, pin, mux, conf, arg, default_val; 1830 int ret, count, i; 1831 const char *prop_name; 1832 int pcfg_node, property_offset, prop_len, param; 1833 const void *value; 1834 1835 count = fdtdec_get_int_array_count(blob, node, "rockchip,pins", 1836 cells, ARRAY_SIZE(cells)); 1837 if (count < 0) { 1838 debug("%s: bad array %d\n", __func__, count); 1839 return -EINVAL; 1840 } 1841 1842 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 1843 debug("%s: unsupported pins array count %d\n", 1844 __func__, count); 1845 return -EINVAL; 1846 } 1847 1848 for (i = 0; i < (count >> 2); i++) { 1849 bank = cells[4 * i + 0]; 1850 pin = cells[4 * i + 1]; 1851 mux = cells[4 * i + 2]; 1852 conf = cells[4 * i + 3]; 1853 1854 ret = rockchip_verify_config(dev, bank, pin); 1855 if (ret) 1856 return ret; 1857 1858 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 1859 if (ret) 1860 return ret; 1861 1862 pcfg_node = fdt_node_offset_by_phandle(blob, conf); 1863 if (pcfg_node < 0) 1864 return -ENODEV; 1865 1866 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 1867 value = fdt_getprop_by_offset(blob, property_offset, 1868 &prop_name, &prop_len); 1869 if (!value) 1870 return -ENOENT; 1871 1872 param = rockchip_pinconf_prop_name_to_param(prop_name, 1873 &default_val); 1874 if (param < 0) 1875 break; 1876 1877 if (prop_len >= sizeof(fdt32_t)) 1878 arg = fdt32_to_cpu(*(fdt32_t *)value); 1879 else 1880 arg = default_val; 1881 1882 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 1883 param, arg); 1884 if (ret) { 1885 debug("%s: rockchip_pinconf_set fail: %d\n", 1886 __func__, ret); 1887 return ret; 1888 } 1889 } 1890 } 1891 1892 return 0; 1893 } 1894 1895 static struct pinctrl_ops rockchip_pinctrl_ops = { 1896 .set_state = rockchip_pinctrl_set_state, 1897 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 1898 }; 1899 1900 /* retrieve the soc specific data */ 1901 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 1902 { 1903 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1904 struct rockchip_pin_ctrl *ctrl = 1905 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 1906 struct rockchip_pin_bank *bank; 1907 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 1908 1909 grf_offs = ctrl->grf_mux_offset; 1910 pmu_offs = ctrl->pmu_mux_offset; 1911 drv_pmu_offs = ctrl->pmu_drv_offset; 1912 drv_grf_offs = ctrl->grf_drv_offset; 1913 bank = ctrl->pin_banks; 1914 1915 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1916 int bank_pins = 0; 1917 1918 bank->priv = priv; 1919 bank->pin_base = ctrl->nr_pins; 1920 ctrl->nr_pins += bank->nr_pins; 1921 1922 /* calculate iomux and drv offsets */ 1923 for (j = 0; j < 4; j++) { 1924 struct rockchip_iomux *iom = &bank->iomux[j]; 1925 struct rockchip_drv *drv = &bank->drv[j]; 1926 int inc; 1927 1928 if (bank_pins >= bank->nr_pins) 1929 break; 1930 1931 /* preset iomux offset value, set new start value */ 1932 if (iom->offset >= 0) { 1933 if (iom->type & IOMUX_SOURCE_PMU) 1934 pmu_offs = iom->offset; 1935 else 1936 grf_offs = iom->offset; 1937 } else { /* set current iomux offset */ 1938 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 1939 pmu_offs : grf_offs; 1940 } 1941 1942 /* preset drv offset value, set new start value */ 1943 if (drv->offset >= 0) { 1944 if (iom->type & IOMUX_SOURCE_PMU) 1945 drv_pmu_offs = drv->offset; 1946 else 1947 drv_grf_offs = drv->offset; 1948 } else { /* set current drv offset */ 1949 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 1950 drv_pmu_offs : drv_grf_offs; 1951 } 1952 1953 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 1954 i, j, iom->offset, drv->offset); 1955 1956 /* 1957 * Increase offset according to iomux width. 1958 * 4bit iomux'es are spread over two registers. 1959 */ 1960 inc = (iom->type & (IOMUX_WIDTH_4BIT | 1961 IOMUX_WIDTH_3BIT)) ? 8 : 4; 1962 if (iom->type & IOMUX_SOURCE_PMU) 1963 pmu_offs += inc; 1964 else 1965 grf_offs += inc; 1966 1967 /* 1968 * Increase offset according to drv width. 1969 * 3bit drive-strenth'es are spread over two registers. 1970 */ 1971 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1972 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 1973 inc = 8; 1974 else 1975 inc = 4; 1976 1977 if (iom->type & IOMUX_SOURCE_PMU) 1978 drv_pmu_offs += inc; 1979 else 1980 drv_grf_offs += inc; 1981 1982 bank_pins += 8; 1983 } 1984 1985 /* calculate the per-bank recalced_mask */ 1986 for (j = 0; j < ctrl->niomux_recalced; j++) { 1987 int pin = 0; 1988 1989 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 1990 pin = ctrl->iomux_recalced[j].pin; 1991 bank->recalced_mask |= BIT(pin); 1992 } 1993 } 1994 1995 /* calculate the per-bank route_mask */ 1996 for (j = 0; j < ctrl->niomux_routes; j++) { 1997 int pin = 0; 1998 1999 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2000 pin = ctrl->iomux_routes[j].pin; 2001 bank->route_mask |= BIT(pin); 2002 } 2003 } 2004 } 2005 2006 return ctrl; 2007 } 2008 2009 static int rockchip_pinctrl_probe(struct udevice *dev) 2010 { 2011 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2012 struct rockchip_pin_ctrl *ctrl; 2013 struct udevice *syscon; 2014 struct regmap *regmap; 2015 int ret = 0; 2016 2017 /* get rockchip grf syscon phandle */ 2018 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2019 &syscon); 2020 if (ret) { 2021 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 2022 return ret; 2023 } 2024 2025 /* get grf-reg base address */ 2026 regmap = syscon_get_regmap(syscon); 2027 if (!regmap) { 2028 debug("unable to find rockchip grf regmap\n"); 2029 return -ENODEV; 2030 } 2031 priv->regmap_base = regmap; 2032 2033 /* option: get pmu-reg base address */ 2034 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 2035 &syscon); 2036 if (!ret) { 2037 /* get pmugrf-reg base address */ 2038 regmap = syscon_get_regmap(syscon); 2039 if (!regmap) { 2040 debug("unable to find rockchip pmu regmap\n"); 2041 return -ENODEV; 2042 } 2043 priv->regmap_pmu = regmap; 2044 } 2045 2046 ctrl = rockchip_pinctrl_get_soc_data(dev); 2047 if (!ctrl) { 2048 debug("driver data not available\n"); 2049 return -EINVAL; 2050 } 2051 2052 priv->ctrl = ctrl; 2053 return 0; 2054 } 2055 2056 static struct rockchip_pin_bank px30_pin_banks[] = { 2057 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2058 IOMUX_SOURCE_PMU, 2059 IOMUX_SOURCE_PMU, 2060 IOMUX_SOURCE_PMU 2061 ), 2062 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2063 IOMUX_WIDTH_4BIT, 2064 IOMUX_WIDTH_4BIT, 2065 IOMUX_WIDTH_4BIT 2066 ), 2067 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2068 IOMUX_WIDTH_4BIT, 2069 IOMUX_WIDTH_4BIT, 2070 IOMUX_WIDTH_4BIT 2071 ), 2072 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2073 IOMUX_WIDTH_4BIT, 2074 IOMUX_WIDTH_4BIT, 2075 IOMUX_WIDTH_4BIT 2076 ), 2077 }; 2078 2079 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2080 .pin_banks = px30_pin_banks, 2081 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2082 .label = "PX30-GPIO", 2083 .type = PX30, 2084 .grf_mux_offset = 0x0, 2085 .pmu_mux_offset = 0x0, 2086 .iomux_routes = px30_mux_route_data, 2087 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2088 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2089 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2090 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2091 }; 2092 2093 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2094 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2095 IOMUX_SOURCE_PMU, 2096 IOMUX_SOURCE_PMU, 2097 IOMUX_SOURCE_PMU), 2098 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2099 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2100 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2101 }; 2102 2103 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2104 .pin_banks = rv1108_pin_banks, 2105 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2106 .label = "RV1108-GPIO", 2107 .type = RV1108, 2108 .grf_mux_offset = 0x10, 2109 .pmu_mux_offset = 0x0, 2110 .iomux_recalced = rv1108_mux_recalced_data, 2111 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2112 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2113 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2114 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2115 }; 2116 2117 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2118 PIN_BANK(0, 32, "gpio0"), 2119 PIN_BANK(1, 32, "gpio1"), 2120 PIN_BANK(2, 32, "gpio2"), 2121 PIN_BANK(3, 32, "gpio3"), 2122 }; 2123 2124 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2125 .pin_banks = rk2928_pin_banks, 2126 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2127 .label = "RK2928-GPIO", 2128 .type = RK2928, 2129 .grf_mux_offset = 0xa8, 2130 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2131 }; 2132 2133 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2134 PIN_BANK(0, 32, "gpio0"), 2135 PIN_BANK(1, 32, "gpio1"), 2136 PIN_BANK(2, 32, "gpio2"), 2137 }; 2138 2139 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2140 .pin_banks = rk3036_pin_banks, 2141 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2142 .label = "RK3036-GPIO", 2143 .type = RK2928, 2144 .grf_mux_offset = 0xa8, 2145 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2146 }; 2147 2148 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2149 PIN_BANK(0, 32, "gpio0"), 2150 PIN_BANK(1, 32, "gpio1"), 2151 PIN_BANK(2, 32, "gpio2"), 2152 PIN_BANK(3, 32, "gpio3"), 2153 PIN_BANK(4, 32, "gpio4"), 2154 PIN_BANK(6, 16, "gpio6"), 2155 }; 2156 2157 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2158 .pin_banks = rk3066a_pin_banks, 2159 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2160 .label = "RK3066a-GPIO", 2161 .type = RK2928, 2162 .grf_mux_offset = 0xa8, 2163 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2164 }; 2165 2166 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2167 PIN_BANK(0, 32, "gpio0"), 2168 PIN_BANK(1, 32, "gpio1"), 2169 PIN_BANK(2, 32, "gpio2"), 2170 PIN_BANK(3, 32, "gpio3"), 2171 }; 2172 2173 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2174 .pin_banks = rk3066b_pin_banks, 2175 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2176 .label = "RK3066b-GPIO", 2177 .type = RK3066B, 2178 .grf_mux_offset = 0x60, 2179 }; 2180 2181 static struct rockchip_pin_bank rk3128_pin_banks[] = { 2182 PIN_BANK(0, 32, "gpio0"), 2183 PIN_BANK(1, 32, "gpio1"), 2184 PIN_BANK(2, 32, "gpio2"), 2185 PIN_BANK(3, 32, "gpio3"), 2186 }; 2187 2188 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 2189 .pin_banks = rk3128_pin_banks, 2190 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 2191 .label = "RK3128-GPIO", 2192 .type = RK3128, 2193 .grf_mux_offset = 0xa8, 2194 .iomux_recalced = rk3128_mux_recalced_data, 2195 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 2196 .iomux_routes = rk3128_mux_route_data, 2197 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 2198 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 2199 }; 2200 2201 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2202 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2203 PIN_BANK(1, 32, "gpio1"), 2204 PIN_BANK(2, 32, "gpio2"), 2205 PIN_BANK(3, 32, "gpio3"), 2206 }; 2207 2208 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2209 .pin_banks = rk3188_pin_banks, 2210 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2211 .label = "RK3188-GPIO", 2212 .type = RK3188, 2213 .grf_mux_offset = 0x60, 2214 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2215 }; 2216 2217 static struct rockchip_pin_bank rk3228_pin_banks[] = { 2218 PIN_BANK(0, 32, "gpio0"), 2219 PIN_BANK(1, 32, "gpio1"), 2220 PIN_BANK(2, 32, "gpio2"), 2221 PIN_BANK(3, 32, "gpio3"), 2222 }; 2223 2224 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 2225 .pin_banks = rk3228_pin_banks, 2226 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 2227 .label = "RK3228-GPIO", 2228 .type = RK3288, 2229 .grf_mux_offset = 0x0, 2230 .iomux_routes = rk3228_mux_route_data, 2231 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 2232 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2233 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2234 }; 2235 2236 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2237 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 2238 IOMUX_SOURCE_PMU, 2239 IOMUX_SOURCE_PMU, 2240 IOMUX_UNROUTED 2241 ), 2242 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2243 IOMUX_UNROUTED, 2244 IOMUX_UNROUTED, 2245 0 2246 ), 2247 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2248 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2249 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2250 IOMUX_WIDTH_4BIT, 2251 0, 2252 0 2253 ), 2254 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2255 0, 2256 0, 2257 IOMUX_UNROUTED 2258 ), 2259 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2260 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2261 0, 2262 IOMUX_WIDTH_4BIT, 2263 IOMUX_UNROUTED 2264 ), 2265 PIN_BANK(8, 16, "gpio8"), 2266 }; 2267 2268 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2269 .pin_banks = rk3288_pin_banks, 2270 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2271 .label = "RK3288-GPIO", 2272 .type = RK3288, 2273 .grf_mux_offset = 0x0, 2274 .pmu_mux_offset = 0x84, 2275 .iomux_routes = rk3288_mux_route_data, 2276 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 2277 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2278 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2279 }; 2280 2281 static struct rockchip_pin_bank rk3328_pin_banks[] = { 2282 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 2283 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2284 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 2285 IOMUX_WIDTH_3BIT, 2286 IOMUX_WIDTH_3BIT, 2287 0), 2288 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2289 IOMUX_WIDTH_3BIT, 2290 IOMUX_WIDTH_3BIT, 2291 0, 2292 0), 2293 }; 2294 2295 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 2296 .pin_banks = rk3328_pin_banks, 2297 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 2298 .label = "RK3328-GPIO", 2299 .type = RK3288, 2300 .grf_mux_offset = 0x0, 2301 .iomux_recalced = rk3328_mux_recalced_data, 2302 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 2303 .iomux_routes = rk3328_mux_route_data, 2304 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 2305 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2306 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2307 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 2308 }; 2309 2310 static struct rockchip_pin_bank rk3368_pin_banks[] = { 2311 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2312 IOMUX_SOURCE_PMU, 2313 IOMUX_SOURCE_PMU, 2314 IOMUX_SOURCE_PMU 2315 ), 2316 PIN_BANK(1, 32, "gpio1"), 2317 PIN_BANK(2, 32, "gpio2"), 2318 PIN_BANK(3, 32, "gpio3"), 2319 }; 2320 2321 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 2322 .pin_banks = rk3368_pin_banks, 2323 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 2324 .label = "RK3368-GPIO", 2325 .type = RK3368, 2326 .grf_mux_offset = 0x0, 2327 .pmu_mux_offset = 0x0, 2328 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 2329 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 2330 }; 2331 2332 static struct rockchip_pin_bank rk3399_pin_banks[] = { 2333 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 2334 IOMUX_SOURCE_PMU, 2335 IOMUX_SOURCE_PMU, 2336 IOMUX_SOURCE_PMU, 2337 IOMUX_SOURCE_PMU, 2338 DRV_TYPE_IO_1V8_ONLY, 2339 DRV_TYPE_IO_1V8_ONLY, 2340 DRV_TYPE_IO_DEFAULT, 2341 DRV_TYPE_IO_DEFAULT, 2342 0x80, 2343 0x88, 2344 -1, 2345 -1, 2346 PULL_TYPE_IO_1V8_ONLY, 2347 PULL_TYPE_IO_1V8_ONLY, 2348 PULL_TYPE_IO_DEFAULT, 2349 PULL_TYPE_IO_DEFAULT 2350 ), 2351 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 2352 IOMUX_SOURCE_PMU, 2353 IOMUX_SOURCE_PMU, 2354 IOMUX_SOURCE_PMU, 2355 DRV_TYPE_IO_1V8_OR_3V0, 2356 DRV_TYPE_IO_1V8_OR_3V0, 2357 DRV_TYPE_IO_1V8_OR_3V0, 2358 DRV_TYPE_IO_1V8_OR_3V0, 2359 0xa0, 2360 0xa8, 2361 0xb0, 2362 0xb8 2363 ), 2364 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 2365 DRV_TYPE_IO_1V8_OR_3V0, 2366 DRV_TYPE_IO_1V8_ONLY, 2367 DRV_TYPE_IO_1V8_ONLY, 2368 PULL_TYPE_IO_DEFAULT, 2369 PULL_TYPE_IO_DEFAULT, 2370 PULL_TYPE_IO_1V8_ONLY, 2371 PULL_TYPE_IO_1V8_ONLY 2372 ), 2373 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 2374 DRV_TYPE_IO_3V3_ONLY, 2375 DRV_TYPE_IO_3V3_ONLY, 2376 DRV_TYPE_IO_1V8_OR_3V0 2377 ), 2378 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 2379 DRV_TYPE_IO_1V8_3V0_AUTO, 2380 DRV_TYPE_IO_1V8_OR_3V0, 2381 DRV_TYPE_IO_1V8_OR_3V0 2382 ), 2383 }; 2384 2385 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 2386 .pin_banks = rk3399_pin_banks, 2387 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 2388 .label = "RK3399-GPIO", 2389 .type = RK3399, 2390 .grf_mux_offset = 0xe000, 2391 .pmu_mux_offset = 0x0, 2392 .grf_drv_offset = 0xe100, 2393 .pmu_drv_offset = 0x80, 2394 .iomux_routes = rk3399_mux_route_data, 2395 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 2396 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 2397 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 2398 }; 2399 2400 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 2401 { .compatible = "rockchip,px30-pinctrl", 2402 .data = (ulong)&px30_pin_ctrl }, 2403 { .compatible = "rockchip,rv1108-pinctrl", 2404 .data = (ulong)&rv1108_pin_ctrl }, 2405 { .compatible = "rockchip,rk2928-pinctrl", 2406 .data = (ulong)&rk2928_pin_ctrl }, 2407 { .compatible = "rockchip,rk3036-pinctrl", 2408 .data = (ulong)&rk3036_pin_ctrl }, 2409 { .compatible = "rockchip,rk3066a-pinctrl", 2410 .data = (ulong)&rk3066a_pin_ctrl }, 2411 { .compatible = "rockchip,rk3066b-pinctrl", 2412 .data = (ulong)&rk3066b_pin_ctrl }, 2413 { .compatible = "rockchip,rk3128-pinctrl", 2414 .data = (ulong)&rk3128_pin_ctrl }, 2415 { .compatible = "rockchip,rk3188-pinctrl", 2416 .data = (ulong)&rk3188_pin_ctrl }, 2417 { .compatible = "rockchip,rk3228-pinctrl", 2418 .data = (ulong)&rk3228_pin_ctrl }, 2419 { .compatible = "rockchip,rk3288-pinctrl", 2420 .data = (ulong)&rk3288_pin_ctrl }, 2421 { .compatible = "rockchip,rk3328-pinctrl", 2422 .data = (ulong)&rk3328_pin_ctrl }, 2423 { .compatible = "rockchip,rk3368-pinctrl", 2424 .data = (ulong)&rk3368_pin_ctrl }, 2425 { .compatible = "rockchip,rk3399-pinctrl", 2426 .data = (ulong)&rk3399_pin_ctrl }, 2427 {}, 2428 }; 2429 2430 U_BOOT_DRIVER(pinctrl_rockchip) = { 2431 .name = "rockchip_pinctrl", 2432 .id = UCLASS_PINCTRL, 2433 .of_match = rockchip_pinctrl_dt_match, 2434 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 2435 .ops = &rockchip_pinctrl_ops, 2436 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 2437 .bind = dm_scan_fdt_dev, 2438 #endif 2439 .probe = rockchip_pinctrl_probe, 2440 }; 2441