1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 #include <asm/arch/cpu.h> 14 15 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 16 #define RK_FUNC_GPIO 0 17 #define MAX_ROCKCHIP_PINS_ENTRIES 30 18 19 enum rockchip_pinctrl_type { 20 PX30, 21 RV1108, 22 RK1808, 23 RK2928, 24 RK3066B, 25 RK3128, 26 RK3188, 27 RK3288, 28 RK3308, 29 RK3368, 30 RK3399, 31 }; 32 33 /** 34 * Encode variants of iomux registers into a type variable 35 */ 36 #define IOMUX_GPIO_ONLY BIT(0) 37 #define IOMUX_WIDTH_4BIT BIT(1) 38 #define IOMUX_SOURCE_PMU BIT(2) 39 #define IOMUX_UNROUTED BIT(3) 40 #define IOMUX_WIDTH_3BIT BIT(4) 41 #define IOMUX_8WIDTH_2BIT BIT(5) 42 #define IOMUX_WRITABLE_32BIT BIT(6) 43 44 /** 45 * @type: iomux variant using IOMUX_* constants 46 * @offset: if initialized to -1 it will be autocalculated, by specifying 47 * an initial offset value the relevant source offset can be reset 48 * to a new value for autocalculating the following iomux registers. 49 */ 50 struct rockchip_iomux { 51 int type; 52 int offset; 53 }; 54 55 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 56 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 57 58 /** 59 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 60 */ 61 enum rockchip_pin_drv_type { 62 DRV_TYPE_IO_DEFAULT = 0, 63 DRV_TYPE_IO_1V8_OR_3V0, 64 DRV_TYPE_IO_1V8_ONLY, 65 DRV_TYPE_IO_1V8_3V0_AUTO, 66 DRV_TYPE_IO_3V3_ONLY, 67 DRV_TYPE_MAX 68 }; 69 70 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 71 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 72 73 /** 74 * enum type index corresponding to rockchip_pull_list arrays index. 75 */ 76 enum rockchip_pin_pull_type { 77 PULL_TYPE_IO_DEFAULT = 0, 78 PULL_TYPE_IO_1V8_ONLY, 79 PULL_TYPE_MAX 80 }; 81 82 /** 83 * @drv_type: drive strength variant using rockchip_perpin_drv_type 84 * @offset: if initialized to -1 it will be autocalculated, by specifying 85 * an initial offset value the relevant source offset can be reset 86 * to a new value for autocalculating the following drive strength 87 * registers. if used chips own cal_drv func instead to calculate 88 * registers offset, the variant could be ignored. 89 */ 90 struct rockchip_drv { 91 enum rockchip_pin_drv_type drv_type; 92 int offset; 93 }; 94 95 /** 96 * @priv: common pinctrl private basedata 97 * @pin_base: first pin number 98 * @nr_pins: number of pins in this bank 99 * @name: name of the bank 100 * @bank_num: number of the bank, to account for holes 101 * @iomux: array describing the 4 iomux sources of the bank 102 * @drv: array describing the 4 drive strength sources of the bank 103 * @pull_type: array describing the 4 pull type sources of the bank 104 * @recalced_mask: bits describing the mux recalced pins of per bank 105 * @route_mask: bits describing the routing pins of per bank 106 */ 107 struct rockchip_pin_bank { 108 struct rockchip_pinctrl_priv *priv; 109 u32 pin_base; 110 u8 nr_pins; 111 char *name; 112 u8 bank_num; 113 struct rockchip_iomux iomux[4]; 114 struct rockchip_drv drv[4]; 115 enum rockchip_pin_pull_type pull_type[4]; 116 u32 recalced_mask; 117 u32 route_mask; 118 }; 119 120 #define PIN_BANK(id, pins, label) \ 121 { \ 122 .bank_num = id, \ 123 .nr_pins = pins, \ 124 .name = label, \ 125 .iomux = { \ 126 { .offset = -1 }, \ 127 { .offset = -1 }, \ 128 { .offset = -1 }, \ 129 { .offset = -1 }, \ 130 }, \ 131 } 132 133 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 134 { \ 135 .bank_num = id, \ 136 .nr_pins = pins, \ 137 .name = label, \ 138 .iomux = { \ 139 { .type = iom0, .offset = -1 }, \ 140 { .type = iom1, .offset = -1 }, \ 141 { .type = iom2, .offset = -1 }, \ 142 { .type = iom3, .offset = -1 }, \ 143 }, \ 144 } 145 146 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 147 { \ 148 .bank_num = id, \ 149 .nr_pins = pins, \ 150 .name = label, \ 151 .iomux = { \ 152 { .offset = -1 }, \ 153 { .offset = -1 }, \ 154 { .offset = -1 }, \ 155 { .offset = -1 }, \ 156 }, \ 157 .drv = { \ 158 { .drv_type = type0, .offset = -1 }, \ 159 { .drv_type = type1, .offset = -1 }, \ 160 { .drv_type = type2, .offset = -1 }, \ 161 { .drv_type = type3, .offset = -1 }, \ 162 }, \ 163 } 164 165 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 166 drv2, drv3, pull0, pull1, \ 167 pull2, pull3) \ 168 { \ 169 .bank_num = id, \ 170 .nr_pins = pins, \ 171 .name = label, \ 172 .iomux = { \ 173 { .offset = -1 }, \ 174 { .offset = -1 }, \ 175 { .offset = -1 }, \ 176 { .offset = -1 }, \ 177 }, \ 178 .drv = { \ 179 { .drv_type = drv0, .offset = -1 }, \ 180 { .drv_type = drv1, .offset = -1 }, \ 181 { .drv_type = drv2, .offset = -1 }, \ 182 { .drv_type = drv3, .offset = -1 }, \ 183 }, \ 184 .pull_type[0] = pull0, \ 185 .pull_type[1] = pull1, \ 186 .pull_type[2] = pull2, \ 187 .pull_type[3] = pull3, \ 188 } 189 190 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 191 iom2, iom3, drv0, drv1, drv2, \ 192 drv3, offset0, offset1, \ 193 offset2, offset3) \ 194 { \ 195 .bank_num = id, \ 196 .nr_pins = pins, \ 197 .name = label, \ 198 .iomux = { \ 199 { .type = iom0, .offset = -1 }, \ 200 { .type = iom1, .offset = -1 }, \ 201 { .type = iom2, .offset = -1 }, \ 202 { .type = iom3, .offset = -1 }, \ 203 }, \ 204 .drv = { \ 205 { .drv_type = drv0, .offset = offset0 }, \ 206 { .drv_type = drv1, .offset = offset1 }, \ 207 { .drv_type = drv2, .offset = offset2 }, \ 208 { .drv_type = drv3, .offset = offset3 }, \ 209 }, \ 210 } 211 212 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 213 iom2, iom3, drv0, drv1, drv2, \ 214 drv3, pull0, pull1, pull2, \ 215 pull3) \ 216 { \ 217 .bank_num = id, \ 218 .nr_pins = pins, \ 219 .name = label, \ 220 .iomux = { \ 221 { .type = iom0, .offset = -1 }, \ 222 { .type = iom1, .offset = -1 }, \ 223 { .type = iom2, .offset = -1 }, \ 224 { .type = iom3, .offset = -1 }, \ 225 }, \ 226 .drv = { \ 227 { .drv_type = drv0, .offset = -1 }, \ 228 { .drv_type = drv1, .offset = -1 }, \ 229 { .drv_type = drv2, .offset = -1 }, \ 230 { .drv_type = drv3, .offset = -1 }, \ 231 }, \ 232 .pull_type[0] = pull0, \ 233 .pull_type[1] = pull1, \ 234 .pull_type[2] = pull2, \ 235 .pull_type[3] = pull3, \ 236 } 237 238 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 239 label, iom0, iom1, iom2, \ 240 iom3, drv0, drv1, drv2, \ 241 drv3, offset0, offset1, \ 242 offset2, offset3, pull0, \ 243 pull1, pull2, pull3) \ 244 { \ 245 .bank_num = id, \ 246 .nr_pins = pins, \ 247 .name = label, \ 248 .iomux = { \ 249 { .type = iom0, .offset = -1 }, \ 250 { .type = iom1, .offset = -1 }, \ 251 { .type = iom2, .offset = -1 }, \ 252 { .type = iom3, .offset = -1 }, \ 253 }, \ 254 .drv = { \ 255 { .drv_type = drv0, .offset = offset0 }, \ 256 { .drv_type = drv1, .offset = offset1 }, \ 257 { .drv_type = drv2, .offset = offset2 }, \ 258 { .drv_type = drv3, .offset = offset3 }, \ 259 }, \ 260 .pull_type[0] = pull0, \ 261 .pull_type[1] = pull1, \ 262 .pull_type[2] = pull2, \ 263 .pull_type[3] = pull3, \ 264 } 265 266 /** 267 * struct rockchip_mux_recalced_data: represent a pin iomux data. 268 * @num: bank number. 269 * @pin: pin number. 270 * @bit: index at register. 271 * @reg: register offset. 272 * @mask: mask bit 273 */ 274 struct rockchip_mux_recalced_data { 275 u8 num; 276 u8 pin; 277 u32 reg; 278 u8 bit; 279 u8 mask; 280 }; 281 282 /** 283 * struct rockchip_mux_recalced_data: represent a pin iomux data. 284 * @bank_num: bank number. 285 * @pin: index at register or used to calc index. 286 * @func: the min pin. 287 * @route_offset: the max pin. 288 * @route_val: the register offset. 289 */ 290 struct rockchip_mux_route_data { 291 u8 bank_num; 292 u8 pin; 293 u8 func; 294 u32 route_offset; 295 u32 route_val; 296 }; 297 298 /** 299 */ 300 struct rockchip_pin_ctrl { 301 struct rockchip_pin_bank *pin_banks; 302 u32 nr_banks; 303 u32 nr_pins; 304 char *label; 305 enum rockchip_pinctrl_type type; 306 int grf_mux_offset; 307 int pmu_mux_offset; 308 int grf_drv_offset; 309 int pmu_drv_offset; 310 struct rockchip_mux_recalced_data *iomux_recalced; 311 u32 niomux_recalced; 312 struct rockchip_mux_route_data *iomux_routes; 313 u32 niomux_routes; 314 315 int (*ctrl_data_re_init)(struct rockchip_pin_ctrl *ctrl); 316 317 int (*soc_data_init)(struct rockchip_pinctrl_priv *info); 318 319 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 320 int pin_num, struct regmap **regmap, 321 int *reg, u8 *bit); 322 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 323 int pin_num, struct regmap **regmap, 324 int *reg, u8 *bit); 325 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 326 int pin_num, struct regmap **regmap, 327 int *reg, u8 *bit); 328 }; 329 330 /** 331 */ 332 struct rockchip_pinctrl_priv { 333 struct rockchip_pin_ctrl *ctrl; 334 struct regmap *regmap_base; 335 struct regmap *regmap_pmu; 336 337 }; 338 339 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 340 { 341 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 342 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 343 344 if (bank >= ctrl->nr_banks) { 345 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 346 return -EINVAL; 347 } 348 349 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 350 debug("pin conf pin %d >= %d\n", pin, 351 MAX_ROCKCHIP_GPIO_PER_BANK); 352 return -EINVAL; 353 } 354 355 return 0; 356 } 357 358 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 359 { 360 .num = 1, 361 .pin = 0, 362 .reg = 0x418, 363 .bit = 0, 364 .mask = 0x3 365 }, { 366 .num = 1, 367 .pin = 1, 368 .reg = 0x418, 369 .bit = 2, 370 .mask = 0x3 371 }, { 372 .num = 1, 373 .pin = 2, 374 .reg = 0x418, 375 .bit = 4, 376 .mask = 0x3 377 }, { 378 .num = 1, 379 .pin = 3, 380 .reg = 0x418, 381 .bit = 6, 382 .mask = 0x3 383 }, { 384 .num = 1, 385 .pin = 4, 386 .reg = 0x418, 387 .bit = 8, 388 .mask = 0x3 389 }, { 390 .num = 1, 391 .pin = 5, 392 .reg = 0x418, 393 .bit = 10, 394 .mask = 0x3 395 }, { 396 .num = 1, 397 .pin = 6, 398 .reg = 0x418, 399 .bit = 12, 400 .mask = 0x3 401 }, { 402 .num = 1, 403 .pin = 7, 404 .reg = 0x418, 405 .bit = 14, 406 .mask = 0x3 407 }, { 408 .num = 1, 409 .pin = 8, 410 .reg = 0x41c, 411 .bit = 0, 412 .mask = 0x3 413 }, { 414 .num = 1, 415 .pin = 9, 416 .reg = 0x41c, 417 .bit = 2, 418 .mask = 0x3 419 }, 420 }; 421 422 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 423 { 424 .num = 2, 425 .pin = 20, 426 .reg = 0xe8, 427 .bit = 0, 428 .mask = 0x7 429 }, { 430 .num = 2, 431 .pin = 21, 432 .reg = 0xe8, 433 .bit = 4, 434 .mask = 0x7 435 }, { 436 .num = 2, 437 .pin = 22, 438 .reg = 0xe8, 439 .bit = 8, 440 .mask = 0x7 441 }, { 442 .num = 2, 443 .pin = 23, 444 .reg = 0xe8, 445 .bit = 12, 446 .mask = 0x7 447 }, { 448 .num = 2, 449 .pin = 24, 450 .reg = 0xd4, 451 .bit = 12, 452 .mask = 0x7 453 }, 454 }; 455 456 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 457 { 458 .num = 1, 459 .pin = 14, 460 .reg = 0x28, 461 .bit = 12, 462 .mask = 0x7 463 }, { 464 .num = 1, 465 .pin = 15, 466 .reg = 0x2c, 467 .bit = 0, 468 .mask = 0x3 469 }, { 470 .num = 1, 471 .pin = 18, 472 .reg = 0x30, 473 .bit = 4, 474 .mask = 0x7 475 }, { 476 .num = 1, 477 .pin = 19, 478 .reg = 0x30, 479 .bit = 8, 480 .mask = 0x7 481 }, { 482 .num = 1, 483 .pin = 20, 484 .reg = 0x30, 485 .bit = 12, 486 .mask = 0x7 487 }, { 488 .num = 1, 489 .pin = 21, 490 .reg = 0x34, 491 .bit = 0, 492 .mask = 0x7 493 }, { 494 .num = 1, 495 .pin = 22, 496 .reg = 0x34, 497 .bit = 4, 498 .mask = 0x7 499 }, { 500 .num = 1, 501 .pin = 23, 502 .reg = 0x34, 503 .bit = 8, 504 .mask = 0x7 505 }, { 506 .num = 3, 507 .pin = 12, 508 .reg = 0x68, 509 .bit = 8, 510 .mask = 0x7 511 }, { 512 .num = 3, 513 .pin = 13, 514 .reg = 0x68, 515 .bit = 12, 516 .mask = 0x7 517 }, 518 }; 519 520 static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { 521 { 522 .num = 1, 523 .pin = 14, 524 .reg = 0x28, 525 .bit = 12, 526 .mask = 0xf 527 }, { 528 .num = 1, 529 .pin = 15, 530 .reg = 0x2c, 531 .bit = 0, 532 .mask = 0x3 533 }, { 534 .num = 1, 535 .pin = 18, 536 .reg = 0x30, 537 .bit = 4, 538 .mask = 0xf 539 }, { 540 .num = 1, 541 .pin = 19, 542 .reg = 0x30, 543 .bit = 8, 544 .mask = 0xf 545 }, { 546 .num = 1, 547 .pin = 20, 548 .reg = 0x30, 549 .bit = 12, 550 .mask = 0xf 551 }, { 552 .num = 1, 553 .pin = 21, 554 .reg = 0x34, 555 .bit = 0, 556 .mask = 0xf 557 }, { 558 .num = 1, 559 .pin = 22, 560 .reg = 0x34, 561 .bit = 4, 562 .mask = 0xf 563 }, { 564 .num = 1, 565 .pin = 23, 566 .reg = 0x34, 567 .bit = 8, 568 .mask = 0xf 569 }, { 570 .num = 3, 571 .pin = 13, 572 .reg = 0x68, 573 .bit = 12, 574 .mask = 0xf 575 }, { 576 .num = 2, 577 .pin = 2, 578 .reg = 0x608, 579 .bit = 0, 580 .mask = 0x7 581 }, { 582 .num = 2, 583 .pin = 3, 584 .reg = 0x608, 585 .bit = 4, 586 .mask = 0x7 587 }, { 588 .num = 2, 589 .pin = 16, 590 .reg = 0x610, 591 .bit = 8, 592 .mask = 0x7 593 }, { 594 .num = 3, 595 .pin = 10, 596 .reg = 0x610, 597 .bit = 0, 598 .mask = 0x7 599 }, { 600 .num = 3, 601 .pin = 11, 602 .reg = 0x610, 603 .bit = 4, 604 .mask = 0x7 605 }, 606 }; 607 608 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 609 { 610 .num = 2, 611 .pin = 12, 612 .reg = 0x24, 613 .bit = 8, 614 .mask = 0x3 615 }, { 616 .num = 2, 617 .pin = 15, 618 .reg = 0x28, 619 .bit = 0, 620 .mask = 0x7 621 }, { 622 .num = 2, 623 .pin = 23, 624 .reg = 0x30, 625 .bit = 14, 626 .mask = 0x3 627 }, 628 }; 629 630 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 631 int *reg, u8 *bit, int *mask) 632 { 633 struct rockchip_pinctrl_priv *priv = bank->priv; 634 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 635 struct rockchip_mux_recalced_data *data; 636 int i; 637 638 for (i = 0; i < ctrl->niomux_recalced; i++) { 639 data = &ctrl->iomux_recalced[i]; 640 if (data->num == bank->bank_num && 641 data->pin == pin) 642 break; 643 } 644 645 if (i >= ctrl->niomux_recalced) 646 return; 647 648 *reg = data->reg; 649 *mask = data->mask; 650 *bit = data->bit; 651 } 652 653 static struct rockchip_mux_route_data px30_mux_route_data[] = { 654 { 655 /* cif-d2m0 */ 656 .bank_num = 2, 657 .pin = 0, 658 .func = 1, 659 .route_offset = 0x184, 660 .route_val = BIT(16 + 7), 661 }, { 662 /* cif-d2m1 */ 663 .bank_num = 3, 664 .pin = 3, 665 .func = 3, 666 .route_offset = 0x184, 667 .route_val = BIT(16 + 7) | BIT(7), 668 }, { 669 /* pdm-m0 */ 670 .bank_num = 3, 671 .pin = 22, 672 .func = 2, 673 .route_offset = 0x184, 674 .route_val = BIT(16 + 8), 675 }, { 676 /* pdm-m1 */ 677 .bank_num = 2, 678 .pin = 22, 679 .func = 1, 680 .route_offset = 0x184, 681 .route_val = BIT(16 + 8) | BIT(8), 682 }, { 683 /* uart2-rxm0 */ 684 .bank_num = 1, 685 .pin = 27, 686 .func = 2, 687 .route_offset = 0x184, 688 .route_val = BIT(16 + 10), 689 }, { 690 /* uart2-rxm1 */ 691 .bank_num = 2, 692 .pin = 14, 693 .func = 2, 694 .route_offset = 0x184, 695 .route_val = BIT(16 + 10) | BIT(10), 696 }, { 697 /* uart3-rxm0 */ 698 .bank_num = 0, 699 .pin = 17, 700 .func = 2, 701 .route_offset = 0x184, 702 .route_val = BIT(16 + 9), 703 }, { 704 /* uart3-rxm1 */ 705 .bank_num = 1, 706 .pin = 15, 707 .func = 2, 708 .route_offset = 0x184, 709 .route_val = BIT(16 + 9) | BIT(9), 710 }, 711 }; 712 713 static struct rockchip_mux_route_data rk1808_mux_route_data[] = { 714 { 715 /* i2c2m0_sda */ 716 .bank_num = 3, 717 .pin = 12, 718 .func = 2, 719 .route_offset = 0x190, 720 .route_val = BIT(16 + 3), 721 }, { 722 /* i2c2m1_sda */ 723 .bank_num = 1, 724 .pin = 13, 725 .func = 2, 726 .route_offset = 0x190, 727 .route_val = BIT(16 + 3) | BIT(3), 728 }, { 729 /* uart2_rxm0 */ 730 .bank_num = 4, 731 .pin = 3, 732 .func = 2, 733 .route_offset = 0x190, 734 .route_val = BIT(16 + 14) | BIT(16 + 15), 735 }, { 736 /* uart2_rxm1 */ 737 .bank_num = 2, 738 .pin = 25, 739 .func = 2, 740 .route_offset = 0x190, 741 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15), 742 }, { 743 /* uart2_rxm2 */ 744 .bank_num = 3, 745 .pin = 4, 746 .func = 2, 747 .route_offset = 0x190, 748 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15), 749 }, 750 }; 751 752 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 753 { 754 /* spi-0 */ 755 .bank_num = 1, 756 .pin = 10, 757 .func = 1, 758 .route_offset = 0x144, 759 .route_val = BIT(16 + 3) | BIT(16 + 4), 760 }, { 761 /* spi-1 */ 762 .bank_num = 1, 763 .pin = 27, 764 .func = 3, 765 .route_offset = 0x144, 766 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 767 }, { 768 /* spi-2 */ 769 .bank_num = 0, 770 .pin = 13, 771 .func = 2, 772 .route_offset = 0x144, 773 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 774 }, { 775 /* i2s-0 */ 776 .bank_num = 1, 777 .pin = 5, 778 .func = 1, 779 .route_offset = 0x144, 780 .route_val = BIT(16 + 5), 781 }, { 782 /* i2s-1 */ 783 .bank_num = 0, 784 .pin = 14, 785 .func = 1, 786 .route_offset = 0x144, 787 .route_val = BIT(16 + 5) | BIT(5), 788 }, { 789 /* emmc-0 */ 790 .bank_num = 1, 791 .pin = 22, 792 .func = 2, 793 .route_offset = 0x144, 794 .route_val = BIT(16 + 6), 795 }, { 796 /* emmc-1 */ 797 .bank_num = 2, 798 .pin = 4, 799 .func = 2, 800 .route_offset = 0x144, 801 .route_val = BIT(16 + 6) | BIT(6), 802 }, 803 }; 804 805 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 806 { 807 /* pwm0-0 */ 808 .bank_num = 0, 809 .pin = 26, 810 .func = 1, 811 .route_offset = 0x50, 812 .route_val = BIT(16), 813 }, { 814 /* pwm0-1 */ 815 .bank_num = 3, 816 .pin = 21, 817 .func = 1, 818 .route_offset = 0x50, 819 .route_val = BIT(16) | BIT(0), 820 }, { 821 /* pwm1-0 */ 822 .bank_num = 0, 823 .pin = 27, 824 .func = 1, 825 .route_offset = 0x50, 826 .route_val = BIT(16 + 1), 827 }, { 828 /* pwm1-1 */ 829 .bank_num = 0, 830 .pin = 30, 831 .func = 2, 832 .route_offset = 0x50, 833 .route_val = BIT(16 + 1) | BIT(1), 834 }, { 835 /* pwm2-0 */ 836 .bank_num = 0, 837 .pin = 28, 838 .func = 1, 839 .route_offset = 0x50, 840 .route_val = BIT(16 + 2), 841 }, { 842 /* pwm2-1 */ 843 .bank_num = 1, 844 .pin = 12, 845 .func = 2, 846 .route_offset = 0x50, 847 .route_val = BIT(16 + 2) | BIT(2), 848 }, { 849 /* pwm3-0 */ 850 .bank_num = 3, 851 .pin = 26, 852 .func = 1, 853 .route_offset = 0x50, 854 .route_val = BIT(16 + 3), 855 }, { 856 /* pwm3-1 */ 857 .bank_num = 1, 858 .pin = 11, 859 .func = 2, 860 .route_offset = 0x50, 861 .route_val = BIT(16 + 3) | BIT(3), 862 }, { 863 /* sdio-0_d0 */ 864 .bank_num = 1, 865 .pin = 1, 866 .func = 1, 867 .route_offset = 0x50, 868 .route_val = BIT(16 + 4), 869 }, { 870 /* sdio-1_d0 */ 871 .bank_num = 3, 872 .pin = 2, 873 .func = 1, 874 .route_offset = 0x50, 875 .route_val = BIT(16 + 4) | BIT(4), 876 }, { 877 /* spi-0_rx */ 878 .bank_num = 0, 879 .pin = 13, 880 .func = 2, 881 .route_offset = 0x50, 882 .route_val = BIT(16 + 5), 883 }, { 884 /* spi-1_rx */ 885 .bank_num = 2, 886 .pin = 0, 887 .func = 2, 888 .route_offset = 0x50, 889 .route_val = BIT(16 + 5) | BIT(5), 890 }, { 891 /* emmc-0_cmd */ 892 .bank_num = 1, 893 .pin = 22, 894 .func = 2, 895 .route_offset = 0x50, 896 .route_val = BIT(16 + 7), 897 }, { 898 /* emmc-1_cmd */ 899 .bank_num = 2, 900 .pin = 4, 901 .func = 2, 902 .route_offset = 0x50, 903 .route_val = BIT(16 + 7) | BIT(7), 904 }, { 905 /* uart2-0_rx */ 906 .bank_num = 1, 907 .pin = 19, 908 .func = 2, 909 .route_offset = 0x50, 910 .route_val = BIT(16 + 8), 911 }, { 912 /* uart2-1_rx */ 913 .bank_num = 1, 914 .pin = 10, 915 .func = 2, 916 .route_offset = 0x50, 917 .route_val = BIT(16 + 8) | BIT(8), 918 }, { 919 /* uart1-0_rx */ 920 .bank_num = 1, 921 .pin = 10, 922 .func = 1, 923 .route_offset = 0x50, 924 .route_val = BIT(16 + 11), 925 }, { 926 /* uart1-1_rx */ 927 .bank_num = 3, 928 .pin = 13, 929 .func = 1, 930 .route_offset = 0x50, 931 .route_val = BIT(16 + 11) | BIT(11), 932 }, 933 }; 934 935 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 936 { 937 /* edphdmi_cecinoutt1 */ 938 .bank_num = 7, 939 .pin = 16, 940 .func = 2, 941 .route_offset = 0x264, 942 .route_val = BIT(16 + 12) | BIT(12), 943 }, { 944 /* edphdmi_cecinout */ 945 .bank_num = 7, 946 .pin = 23, 947 .func = 4, 948 .route_offset = 0x264, 949 .route_val = BIT(16 + 12), 950 }, 951 }; 952 953 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 954 { 955 /* rtc_clk */ 956 .bank_num = 0, 957 .pin = 19, 958 .func = 1, 959 .route_offset = 0x314, 960 .route_val = BIT(16 + 0) | BIT(0), 961 }, { 962 /* uart2_rxm0 */ 963 .bank_num = 1, 964 .pin = 22, 965 .func = 2, 966 .route_offset = 0x314, 967 .route_val = BIT(16 + 2) | BIT(16 + 3), 968 }, { 969 /* uart2_rxm1 */ 970 .bank_num = 4, 971 .pin = 26, 972 .func = 2, 973 .route_offset = 0x314, 974 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 975 }, { 976 /* i2c3_sdam0 */ 977 .bank_num = 0, 978 .pin = 23, 979 .func = 2, 980 .route_offset = 0x314, 981 .route_val = BIT(16 + 4), 982 }, { 983 /* i2c3_sdam1 */ 984 .bank_num = 3, 985 .pin = 12, 986 .func = 2, 987 .route_offset = 0x314, 988 .route_val = BIT(16 + 4) | BIT(4), 989 }, { 990 /* i2s-8ch-1-sclktxm0 */ 991 .bank_num = 1, 992 .pin = 3, 993 .func = 2, 994 .route_offset = 0x308, 995 .route_val = BIT(16 + 3), 996 }, { 997 /* i2s-8ch-1-sclkrxm0 */ 998 .bank_num = 1, 999 .pin = 4, 1000 .func = 2, 1001 .route_offset = 0x308, 1002 .route_val = BIT(16 + 3), 1003 }, { 1004 /* i2s-8ch-1-sclktxm1 */ 1005 .bank_num = 1, 1006 .pin = 13, 1007 .func = 2, 1008 .route_offset = 0x308, 1009 .route_val = BIT(16 + 3) | BIT(3), 1010 }, { 1011 /* i2s-8ch-1-sclkrxm1 */ 1012 .bank_num = 1, 1013 .pin = 14, 1014 .func = 2, 1015 .route_offset = 0x308, 1016 .route_val = BIT(16 + 3) | BIT(3), 1017 }, { 1018 /* pdm-clkm0 */ 1019 .bank_num = 1, 1020 .pin = 4, 1021 .func = 3, 1022 .route_offset = 0x308, 1023 .route_val = BIT(16 + 12) | BIT(16 + 13), 1024 }, { 1025 /* pdm-clkm1 */ 1026 .bank_num = 1, 1027 .pin = 14, 1028 .func = 4, 1029 .route_offset = 0x308, 1030 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1031 }, { 1032 /* pdm-clkm2 */ 1033 .bank_num = 2, 1034 .pin = 6, 1035 .func = 2, 1036 .route_offset = 0x308, 1037 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1038 }, { 1039 /* pdm-clkm-m2 */ 1040 .bank_num = 2, 1041 .pin = 4, 1042 .func = 3, 1043 .route_offset = 0x600, 1044 .route_val = BIT(16 + 2) | BIT(2), 1045 }, 1046 }; 1047 1048 static struct rockchip_mux_route_data rk3308b_mux_route_data[] = { 1049 { 1050 /* rtc_clk */ 1051 .bank_num = 0, 1052 .pin = 19, 1053 .func = 1, 1054 .route_offset = 0x314, 1055 .route_val = BIT(16 + 0) | BIT(0), 1056 }, { 1057 /* uart2_rxm0 */ 1058 .bank_num = 1, 1059 .pin = 22, 1060 .func = 2, 1061 .route_offset = 0x314, 1062 .route_val = BIT(16 + 2) | BIT(16 + 3), 1063 }, { 1064 /* uart2_rxm1 */ 1065 .bank_num = 4, 1066 .pin = 26, 1067 .func = 2, 1068 .route_offset = 0x314, 1069 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1070 }, { 1071 /* i2c3_sdam0 */ 1072 .bank_num = 0, 1073 .pin = 15, 1074 .func = 2, 1075 .route_offset = 0x608, 1076 .route_val = BIT(16 + 8) | BIT(16 + 9), 1077 }, { 1078 /* i2c3_sdam1 */ 1079 .bank_num = 3, 1080 .pin = 12, 1081 .func = 2, 1082 .route_offset = 0x608, 1083 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 1084 }, { 1085 /* i2c3_sdam2 */ 1086 .bank_num = 2, 1087 .pin = 0, 1088 .func = 3, 1089 .route_offset = 0x608, 1090 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 1091 }, { 1092 /* i2s-8ch-1-sclktxm0 */ 1093 .bank_num = 1, 1094 .pin = 3, 1095 .func = 2, 1096 .route_offset = 0x308, 1097 .route_val = BIT(16 + 3), 1098 }, { 1099 /* i2s-8ch-1-sclkrxm0 */ 1100 .bank_num = 1, 1101 .pin = 4, 1102 .func = 2, 1103 .route_offset = 0x308, 1104 .route_val = BIT(16 + 3), 1105 }, { 1106 /* i2s-8ch-1-sclktxm1 */ 1107 .bank_num = 1, 1108 .pin = 13, 1109 .func = 2, 1110 .route_offset = 0x308, 1111 .route_val = BIT(16 + 3) | BIT(3), 1112 }, { 1113 /* i2s-8ch-1-sclkrxm1 */ 1114 .bank_num = 1, 1115 .pin = 14, 1116 .func = 2, 1117 .route_offset = 0x308, 1118 .route_val = BIT(16 + 3) | BIT(3), 1119 }, { 1120 /* pdm-clkm0 */ 1121 .bank_num = 1, 1122 .pin = 4, 1123 .func = 3, 1124 .route_offset = 0x308, 1125 .route_val = BIT(16 + 12) | BIT(16 + 13), 1126 }, { 1127 /* pdm-clkm1 */ 1128 .bank_num = 1, 1129 .pin = 14, 1130 .func = 4, 1131 .route_offset = 0x308, 1132 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1133 }, { 1134 /* pdm-clkm2 */ 1135 .bank_num = 2, 1136 .pin = 6, 1137 .func = 2, 1138 .route_offset = 0x308, 1139 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1140 }, { 1141 /* pdm-clkm-m2 */ 1142 .bank_num = 2, 1143 .pin = 4, 1144 .func = 3, 1145 .route_offset = 0x600, 1146 .route_val = BIT(16 + 2) | BIT(2), 1147 }, { 1148 /* spi1_miso */ 1149 .bank_num = 3, 1150 .pin = 10, 1151 .func = 3, 1152 .route_offset = 0x314, 1153 .route_val = BIT(16 + 9), 1154 }, { 1155 /* spi1_miso_m1 */ 1156 .bank_num = 2, 1157 .pin = 4, 1158 .func = 2, 1159 .route_offset = 0x314, 1160 .route_val = BIT(16 + 9) | BIT(9), 1161 }, { 1162 /* owire_m0 */ 1163 .bank_num = 0, 1164 .pin = 11, 1165 .func = 3, 1166 .route_offset = 0x314, 1167 .route_val = BIT(16 + 10) | BIT(16 + 11), 1168 }, { 1169 /* owire_m1 */ 1170 .bank_num = 1, 1171 .pin = 22, 1172 .func = 7, 1173 .route_offset = 0x314, 1174 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1175 }, { 1176 /* owire_m2 */ 1177 .bank_num = 2, 1178 .pin = 2, 1179 .func = 5, 1180 .route_offset = 0x314, 1181 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1182 }, { 1183 /* can_rxd_m0 */ 1184 .bank_num = 0, 1185 .pin = 11, 1186 .func = 2, 1187 .route_offset = 0x314, 1188 .route_val = BIT(16 + 12) | BIT(16 + 13), 1189 }, { 1190 /* can_rxd_m1 */ 1191 .bank_num = 1, 1192 .pin = 22, 1193 .func = 5, 1194 .route_offset = 0x314, 1195 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1196 }, { 1197 /* can_rxd_m2 */ 1198 .bank_num = 2, 1199 .pin = 2, 1200 .func = 4, 1201 .route_offset = 0x314, 1202 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1203 }, { 1204 /* mac_rxd0_m0 */ 1205 .bank_num = 1, 1206 .pin = 20, 1207 .func = 3, 1208 .route_offset = 0x314, 1209 .route_val = BIT(16 + 14), 1210 }, { 1211 /* mac_rxd0_m1 */ 1212 .bank_num = 4, 1213 .pin = 2, 1214 .func = 2, 1215 .route_offset = 0x314, 1216 .route_val = BIT(16 + 14) | BIT(14), 1217 }, { 1218 /* uart3_rx */ 1219 .bank_num = 3, 1220 .pin = 12, 1221 .func = 4, 1222 .route_offset = 0x314, 1223 .route_val = BIT(16 + 15), 1224 }, { 1225 /* uart3_rx_m1 */ 1226 .bank_num = 0, 1227 .pin = 17, 1228 .func = 3, 1229 .route_offset = 0x314, 1230 .route_val = BIT(16 + 15) | BIT(15), 1231 }, 1232 }; 1233 1234 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1235 { 1236 /* uart2dbg_rxm0 */ 1237 .bank_num = 1, 1238 .pin = 1, 1239 .func = 2, 1240 .route_offset = 0x50, 1241 .route_val = BIT(16) | BIT(16 + 1), 1242 }, { 1243 /* uart2dbg_rxm1 */ 1244 .bank_num = 2, 1245 .pin = 1, 1246 .func = 1, 1247 .route_offset = 0x50, 1248 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1249 }, { 1250 /* gmac-m1_rxd0 */ 1251 .bank_num = 1, 1252 .pin = 11, 1253 .func = 2, 1254 .route_offset = 0x50, 1255 .route_val = BIT(16 + 2) | BIT(2), 1256 }, { 1257 /* gmac-m1-optimized_rxd3 */ 1258 .bank_num = 1, 1259 .pin = 14, 1260 .func = 2, 1261 .route_offset = 0x50, 1262 .route_val = BIT(16 + 10) | BIT(10), 1263 }, { 1264 /* pdm_sdi0m0 */ 1265 .bank_num = 2, 1266 .pin = 19, 1267 .func = 2, 1268 .route_offset = 0x50, 1269 .route_val = BIT(16 + 3), 1270 }, { 1271 /* pdm_sdi0m1 */ 1272 .bank_num = 1, 1273 .pin = 23, 1274 .func = 3, 1275 .route_offset = 0x50, 1276 .route_val = BIT(16 + 3) | BIT(3), 1277 }, { 1278 /* spi_rxdm2 */ 1279 .bank_num = 3, 1280 .pin = 2, 1281 .func = 4, 1282 .route_offset = 0x50, 1283 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1284 }, { 1285 /* i2s2_sdim0 */ 1286 .bank_num = 1, 1287 .pin = 24, 1288 .func = 1, 1289 .route_offset = 0x50, 1290 .route_val = BIT(16 + 6), 1291 }, { 1292 /* i2s2_sdim1 */ 1293 .bank_num = 3, 1294 .pin = 2, 1295 .func = 6, 1296 .route_offset = 0x50, 1297 .route_val = BIT(16 + 6) | BIT(6), 1298 }, { 1299 /* card_iom1 */ 1300 .bank_num = 2, 1301 .pin = 22, 1302 .func = 3, 1303 .route_offset = 0x50, 1304 .route_val = BIT(16 + 7) | BIT(7), 1305 }, { 1306 /* tsp_d5m1 */ 1307 .bank_num = 2, 1308 .pin = 16, 1309 .func = 3, 1310 .route_offset = 0x50, 1311 .route_val = BIT(16 + 8) | BIT(8), 1312 }, { 1313 /* cif_data5m1 */ 1314 .bank_num = 2, 1315 .pin = 16, 1316 .func = 4, 1317 .route_offset = 0x50, 1318 .route_val = BIT(16 + 9) | BIT(9), 1319 }, 1320 }; 1321 1322 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1323 { 1324 /* uart2dbga_rx */ 1325 .bank_num = 4, 1326 .pin = 8, 1327 .func = 2, 1328 .route_offset = 0xe21c, 1329 .route_val = BIT(16 + 10) | BIT(16 + 11), 1330 }, { 1331 /* uart2dbgb_rx */ 1332 .bank_num = 4, 1333 .pin = 16, 1334 .func = 2, 1335 .route_offset = 0xe21c, 1336 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1337 }, { 1338 /* uart2dbgc_rx */ 1339 .bank_num = 4, 1340 .pin = 19, 1341 .func = 1, 1342 .route_offset = 0xe21c, 1343 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1344 }, { 1345 /* pcie_clkreqn */ 1346 .bank_num = 2, 1347 .pin = 26, 1348 .func = 2, 1349 .route_offset = 0xe21c, 1350 .route_val = BIT(16 + 14), 1351 }, { 1352 /* pcie_clkreqnb */ 1353 .bank_num = 4, 1354 .pin = 24, 1355 .func = 1, 1356 .route_offset = 0xe21c, 1357 .route_val = BIT(16 + 14) | BIT(14), 1358 }, 1359 }; 1360 1361 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1362 int mux, u32 *reg, u32 *value) 1363 { 1364 struct rockchip_pinctrl_priv *priv = bank->priv; 1365 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1366 struct rockchip_mux_route_data *data; 1367 int i; 1368 1369 for (i = 0; i < ctrl->niomux_routes; i++) { 1370 data = &ctrl->iomux_routes[i]; 1371 if ((data->bank_num == bank->bank_num) && 1372 (data->pin == pin) && (data->func == mux)) 1373 break; 1374 } 1375 1376 if (i >= ctrl->niomux_routes) 1377 return false; 1378 1379 *reg = data->route_offset; 1380 *value = data->route_val; 1381 1382 return true; 1383 } 1384 1385 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1386 { 1387 struct rockchip_pinctrl_priv *priv = bank->priv; 1388 int iomux_num = (pin / 8); 1389 struct regmap *regmap; 1390 unsigned int val; 1391 int reg, ret, mask, mux_type; 1392 u8 bit; 1393 1394 if (iomux_num > 3) 1395 return -EINVAL; 1396 1397 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1398 debug("pin %d is unrouted\n", pin); 1399 return -EINVAL; 1400 } 1401 1402 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1403 return RK_FUNC_GPIO; 1404 1405 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1406 ? priv->regmap_pmu : priv->regmap_base; 1407 1408 /* get basic quadrupel of mux registers and the correct reg inside */ 1409 mux_type = bank->iomux[iomux_num].type; 1410 reg = bank->iomux[iomux_num].offset; 1411 if (mux_type & IOMUX_WIDTH_4BIT) { 1412 if ((pin % 8) >= 4) 1413 reg += 0x4; 1414 bit = (pin % 4) * 4; 1415 mask = 0xf; 1416 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1417 if ((pin % 8) >= 5) 1418 reg += 0x4; 1419 bit = (pin % 8 % 5) * 3; 1420 mask = 0x7; 1421 } else { 1422 bit = (pin % 8) * 2; 1423 mask = 0x3; 1424 } 1425 1426 if (bank->recalced_mask & BIT(pin)) 1427 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1428 1429 ret = regmap_read(regmap, reg, &val); 1430 if (ret) 1431 return ret; 1432 1433 return ((val >> bit) & mask); 1434 } 1435 1436 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1437 int index) 1438 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1439 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1440 1441 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1442 } 1443 1444 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1445 int pin, int mux) 1446 { 1447 int iomux_num = (pin / 8); 1448 1449 if (iomux_num > 3) 1450 return -EINVAL; 1451 1452 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1453 debug("pin %d is unrouted\n", pin); 1454 return -EINVAL; 1455 } 1456 1457 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1458 if (mux != IOMUX_GPIO_ONLY) { 1459 debug("pin %d only supports a gpio mux\n", pin); 1460 return -ENOTSUPP; 1461 } 1462 } 1463 1464 return 0; 1465 } 1466 1467 /* 1468 * Set a new mux function for a pin. 1469 * 1470 * The register is divided into the upper and lower 16 bit. When changing 1471 * a value, the previous register value is not read and changed. Instead 1472 * it seems the changed bits are marked in the upper 16 bit, while the 1473 * changed value gets set in the same offset in the lower 16 bit. 1474 * All pin settings seem to be 2 bit wide in both the upper and lower 1475 * parts. 1476 * @bank: pin bank to change 1477 * @pin: pin to change 1478 * @mux: new mux function to set 1479 */ 1480 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1481 { 1482 struct rockchip_pinctrl_priv *priv = bank->priv; 1483 int iomux_num = (pin / 8); 1484 struct regmap *regmap; 1485 int reg, ret, mask, mux_type; 1486 u8 bit; 1487 u32 data, route_reg, route_val; 1488 1489 ret = rockchip_verify_mux(bank, pin, mux); 1490 if (ret < 0) 1491 return ret; 1492 1493 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1494 return 0; 1495 1496 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1497 1498 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1499 ? priv->regmap_pmu : priv->regmap_base; 1500 1501 /* get basic quadrupel of mux registers and the correct reg inside */ 1502 mux_type = bank->iomux[iomux_num].type; 1503 reg = bank->iomux[iomux_num].offset; 1504 if (mux_type & IOMUX_WIDTH_4BIT) { 1505 if ((pin % 8) >= 4) 1506 reg += 0x4; 1507 bit = (pin % 4) * 4; 1508 mask = 0xf; 1509 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1510 if ((pin % 8) >= 5) 1511 reg += 0x4; 1512 bit = (pin % 8 % 5) * 3; 1513 mask = 0x7; 1514 } else { 1515 bit = (pin % 8) * 2; 1516 mask = 0x3; 1517 } 1518 1519 if (bank->recalced_mask & BIT(pin)) 1520 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1521 1522 if (bank->route_mask & BIT(pin)) { 1523 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1524 &route_val)) { 1525 ret = regmap_write(regmap, route_reg, route_val); 1526 if (ret) 1527 return ret; 1528 } 1529 } 1530 1531 if (mux_type & IOMUX_WRITABLE_32BIT) { 1532 regmap_read(regmap, reg, &data); 1533 data &= ~(mask << bit); 1534 } else { 1535 data = (mask << (bit + 16)); 1536 } 1537 1538 data |= (mux & mask) << bit; 1539 ret = regmap_write(regmap, reg, data); 1540 1541 return ret; 1542 } 1543 1544 #define PX30_PULL_PMU_OFFSET 0x10 1545 #define PX30_PULL_GRF_OFFSET 0x60 1546 #define PX30_PULL_BITS_PER_PIN 2 1547 #define PX30_PULL_PINS_PER_REG 8 1548 #define PX30_PULL_BANK_STRIDE 16 1549 1550 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1551 int pin_num, struct regmap **regmap, 1552 int *reg, u8 *bit) 1553 { 1554 struct rockchip_pinctrl_priv *priv = bank->priv; 1555 1556 /* The first 32 pins of the first bank are located in PMU */ 1557 if (bank->bank_num == 0) { 1558 *regmap = priv->regmap_pmu; 1559 *reg = PX30_PULL_PMU_OFFSET; 1560 } else { 1561 *regmap = priv->regmap_base; 1562 *reg = PX30_PULL_GRF_OFFSET; 1563 1564 /* correct the offset, as we're starting with the 2nd bank */ 1565 *reg -= 0x10; 1566 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1567 } 1568 1569 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1570 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1571 *bit *= PX30_PULL_BITS_PER_PIN; 1572 } 1573 1574 #define PX30_DRV_PMU_OFFSET 0x20 1575 #define PX30_DRV_GRF_OFFSET 0xf0 1576 #define PX30_DRV_BITS_PER_PIN 2 1577 #define PX30_DRV_PINS_PER_REG 8 1578 #define PX30_DRV_BANK_STRIDE 16 1579 1580 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1581 int pin_num, struct regmap **regmap, 1582 int *reg, u8 *bit) 1583 { 1584 struct rockchip_pinctrl_priv *priv = bank->priv; 1585 1586 /* The first 32 pins of the first bank are located in PMU */ 1587 if (bank->bank_num == 0) { 1588 *regmap = priv->regmap_pmu; 1589 *reg = PX30_DRV_PMU_OFFSET; 1590 } else { 1591 *regmap = priv->regmap_base; 1592 *reg = PX30_DRV_GRF_OFFSET; 1593 1594 /* correct the offset, as we're starting with the 2nd bank */ 1595 *reg -= 0x10; 1596 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1597 } 1598 1599 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1600 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1601 *bit *= PX30_DRV_BITS_PER_PIN; 1602 } 1603 1604 #define PX30_SCHMITT_PMU_OFFSET 0x38 1605 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1606 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1607 #define PX30_SCHMITT_BANK_STRIDE 16 1608 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1609 1610 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1611 int pin_num, 1612 struct regmap **regmap, 1613 int *reg, u8 *bit) 1614 { 1615 struct rockchip_pinctrl_priv *priv = bank->priv; 1616 int pins_per_reg; 1617 1618 if (bank->bank_num == 0) { 1619 *regmap = priv->regmap_pmu; 1620 *reg = PX30_SCHMITT_PMU_OFFSET; 1621 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1622 } else { 1623 *regmap = priv->regmap_base; 1624 *reg = PX30_SCHMITT_GRF_OFFSET; 1625 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1626 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1627 } 1628 *reg += ((pin_num / pins_per_reg) * 4); 1629 *bit = pin_num % pins_per_reg; 1630 1631 return 0; 1632 } 1633 1634 #define RV1108_PULL_PMU_OFFSET 0x10 1635 #define RV1108_PULL_OFFSET 0x110 1636 #define RV1108_PULL_PINS_PER_REG 8 1637 #define RV1108_PULL_BITS_PER_PIN 2 1638 #define RV1108_PULL_BANK_STRIDE 16 1639 1640 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1641 int pin_num, struct regmap **regmap, 1642 int *reg, u8 *bit) 1643 { 1644 struct rockchip_pinctrl_priv *priv = bank->priv; 1645 1646 /* The first 24 pins of the first bank are located in PMU */ 1647 if (bank->bank_num == 0) { 1648 *regmap = priv->regmap_pmu; 1649 *reg = RV1108_PULL_PMU_OFFSET; 1650 } else { 1651 *reg = RV1108_PULL_OFFSET; 1652 *regmap = priv->regmap_base; 1653 /* correct the offset, as we're starting with the 2nd bank */ 1654 *reg -= 0x10; 1655 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1656 } 1657 1658 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1659 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1660 *bit *= RV1108_PULL_BITS_PER_PIN; 1661 } 1662 1663 #define RV1108_DRV_PMU_OFFSET 0x20 1664 #define RV1108_DRV_GRF_OFFSET 0x210 1665 #define RV1108_DRV_BITS_PER_PIN 2 1666 #define RV1108_DRV_PINS_PER_REG 8 1667 #define RV1108_DRV_BANK_STRIDE 16 1668 1669 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1670 int pin_num, struct regmap **regmap, 1671 int *reg, u8 *bit) 1672 { 1673 struct rockchip_pinctrl_priv *priv = bank->priv; 1674 1675 /* The first 24 pins of the first bank are located in PMU */ 1676 if (bank->bank_num == 0) { 1677 *regmap = priv->regmap_pmu; 1678 *reg = RV1108_DRV_PMU_OFFSET; 1679 } else { 1680 *regmap = priv->regmap_base; 1681 *reg = RV1108_DRV_GRF_OFFSET; 1682 1683 /* correct the offset, as we're starting with the 2nd bank */ 1684 *reg -= 0x10; 1685 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1686 } 1687 1688 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1689 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1690 *bit *= RV1108_DRV_BITS_PER_PIN; 1691 } 1692 1693 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1694 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1695 #define RV1108_SCHMITT_BANK_STRIDE 8 1696 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1697 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1698 1699 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1700 int pin_num, 1701 struct regmap **regmap, 1702 int *reg, u8 *bit) 1703 { 1704 struct rockchip_pinctrl_priv *priv = bank->priv; 1705 int pins_per_reg; 1706 1707 if (bank->bank_num == 0) { 1708 *regmap = priv->regmap_pmu; 1709 *reg = RV1108_SCHMITT_PMU_OFFSET; 1710 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1711 } else { 1712 *regmap = priv->regmap_base; 1713 *reg = RV1108_SCHMITT_GRF_OFFSET; 1714 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1715 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1716 } 1717 *reg += ((pin_num / pins_per_reg) * 4); 1718 *bit = pin_num % pins_per_reg; 1719 1720 return 0; 1721 } 1722 1723 #define RK1808_PULL_PMU_OFFSET 0x10 1724 #define RK1808_PULL_GRF_OFFSET 0x80 1725 #define RK1808_PULL_PINS_PER_REG 8 1726 #define RK1808_PULL_BITS_PER_PIN 2 1727 #define RK1808_PULL_BANK_STRIDE 16 1728 1729 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1730 int pin_num, 1731 struct regmap **regmap, 1732 int *reg, u8 *bit) 1733 { 1734 struct rockchip_pinctrl_priv *priv = bank->priv; 1735 1736 if (bank->bank_num == 0) { 1737 *regmap = priv->regmap_pmu; 1738 *reg = RK1808_PULL_PMU_OFFSET; 1739 } else { 1740 *reg = RK1808_PULL_GRF_OFFSET; 1741 *regmap = priv->regmap_base; 1742 } 1743 1744 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4); 1745 *bit = (pin_num % RK1808_PULL_PINS_PER_REG); 1746 *bit *= RK1808_PULL_BITS_PER_PIN; 1747 } 1748 1749 #define RK1808_DRV_PMU_OFFSET 0x20 1750 #define RK1808_DRV_GRF_OFFSET 0x140 1751 #define RK1808_DRV_BITS_PER_PIN 2 1752 #define RK1808_DRV_PINS_PER_REG 8 1753 #define RK1808_DRV_BANK_STRIDE 16 1754 1755 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1756 int pin_num, 1757 struct regmap **regmap, 1758 int *reg, u8 *bit) 1759 { 1760 struct rockchip_pinctrl_priv *priv = bank->priv; 1761 1762 if (bank->bank_num == 0) { 1763 *regmap = priv->regmap_pmu; 1764 *reg = RK1808_DRV_PMU_OFFSET; 1765 } else { 1766 *regmap = priv->regmap_base; 1767 *reg = RK1808_DRV_GRF_OFFSET; 1768 } 1769 1770 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4); 1771 *bit = pin_num % RK1808_DRV_PINS_PER_REG; 1772 *bit *= RK1808_DRV_BITS_PER_PIN; 1773 } 1774 1775 #define RK1808_SCHMITT_PMU_OFFSET 0x0040 1776 #define RK1808_SCHMITT_GRF_OFFSET 0x0100 1777 #define RK1808_SCHMITT_BANK_STRIDE 16 1778 #define RK1808_SCHMITT_PINS_PER_REG 8 1779 1780 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1781 int pin_num, 1782 struct regmap **regmap, 1783 int *reg, u8 *bit) 1784 { 1785 struct rockchip_pinctrl_priv *priv = bank->priv; 1786 1787 if (bank->bank_num == 0) { 1788 *regmap = priv->regmap_pmu; 1789 *reg = RK1808_SCHMITT_PMU_OFFSET; 1790 } else { 1791 *regmap = priv->regmap_base; 1792 *reg = RK1808_SCHMITT_GRF_OFFSET; 1793 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE; 1794 } 1795 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4); 1796 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG; 1797 1798 return 0; 1799 } 1800 1801 #define RK2928_PULL_OFFSET 0x118 1802 #define RK2928_PULL_PINS_PER_REG 16 1803 #define RK2928_PULL_BANK_STRIDE 8 1804 1805 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1806 int pin_num, struct regmap **regmap, 1807 int *reg, u8 *bit) 1808 { 1809 struct rockchip_pinctrl_priv *priv = bank->priv; 1810 1811 *regmap = priv->regmap_base; 1812 *reg = RK2928_PULL_OFFSET; 1813 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1814 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1815 1816 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1817 }; 1818 1819 #define RK3128_PULL_OFFSET 0x118 1820 1821 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1822 int pin_num, struct regmap **regmap, 1823 int *reg, u8 *bit) 1824 { 1825 struct rockchip_pinctrl_priv *priv = bank->priv; 1826 1827 *regmap = priv->regmap_base; 1828 *reg = RK3128_PULL_OFFSET; 1829 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1830 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1831 1832 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1833 } 1834 1835 #define RK3188_PULL_OFFSET 0x164 1836 #define RK3188_PULL_BITS_PER_PIN 2 1837 #define RK3188_PULL_PINS_PER_REG 8 1838 #define RK3188_PULL_BANK_STRIDE 16 1839 #define RK3188_PULL_PMU_OFFSET 0x64 1840 1841 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1842 int pin_num, struct regmap **regmap, 1843 int *reg, u8 *bit) 1844 { 1845 struct rockchip_pinctrl_priv *priv = bank->priv; 1846 1847 /* The first 12 pins of the first bank are located elsewhere */ 1848 if (bank->bank_num == 0 && pin_num < 12) { 1849 *regmap = priv->regmap_pmu; 1850 *reg = RK3188_PULL_PMU_OFFSET; 1851 1852 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1853 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1854 *bit *= RK3188_PULL_BITS_PER_PIN; 1855 } else { 1856 *regmap = priv->regmap_base; 1857 *reg = RK3188_PULL_OFFSET; 1858 1859 /* correct the offset, as it is the 2nd pull register */ 1860 *reg -= 4; 1861 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1862 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1863 1864 /* 1865 * The bits in these registers have an inverse ordering 1866 * with the lowest pin being in bits 15:14 and the highest 1867 * pin in bits 1:0 1868 */ 1869 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1870 *bit *= RK3188_PULL_BITS_PER_PIN; 1871 } 1872 } 1873 1874 #define RK3288_PULL_OFFSET 0x140 1875 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1876 int pin_num, struct regmap **regmap, 1877 int *reg, u8 *bit) 1878 { 1879 struct rockchip_pinctrl_priv *priv = bank->priv; 1880 1881 /* The first 24 pins of the first bank are located in PMU */ 1882 if (bank->bank_num == 0) { 1883 *regmap = priv->regmap_pmu; 1884 *reg = RK3188_PULL_PMU_OFFSET; 1885 1886 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1887 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1888 *bit *= RK3188_PULL_BITS_PER_PIN; 1889 } else { 1890 *regmap = priv->regmap_base; 1891 *reg = RK3288_PULL_OFFSET; 1892 1893 /* correct the offset, as we're starting with the 2nd bank */ 1894 *reg -= 0x10; 1895 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1896 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1897 1898 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1899 *bit *= RK3188_PULL_BITS_PER_PIN; 1900 } 1901 } 1902 1903 #define RK3288_DRV_PMU_OFFSET 0x70 1904 #define RK3288_DRV_GRF_OFFSET 0x1c0 1905 #define RK3288_DRV_BITS_PER_PIN 2 1906 #define RK3288_DRV_PINS_PER_REG 8 1907 #define RK3288_DRV_BANK_STRIDE 16 1908 1909 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1910 int pin_num, struct regmap **regmap, 1911 int *reg, u8 *bit) 1912 { 1913 struct rockchip_pinctrl_priv *priv = bank->priv; 1914 1915 /* The first 24 pins of the first bank are located in PMU */ 1916 if (bank->bank_num == 0) { 1917 *regmap = priv->regmap_pmu; 1918 *reg = RK3288_DRV_PMU_OFFSET; 1919 1920 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1921 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1922 *bit *= RK3288_DRV_BITS_PER_PIN; 1923 } else { 1924 *regmap = priv->regmap_base; 1925 *reg = RK3288_DRV_GRF_OFFSET; 1926 1927 /* correct the offset, as we're starting with the 2nd bank */ 1928 *reg -= 0x10; 1929 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1930 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1931 1932 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1933 *bit *= RK3288_DRV_BITS_PER_PIN; 1934 } 1935 } 1936 1937 #define RK3228_PULL_OFFSET 0x100 1938 1939 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1940 int pin_num, struct regmap **regmap, 1941 int *reg, u8 *bit) 1942 { 1943 struct rockchip_pinctrl_priv *priv = bank->priv; 1944 1945 *regmap = priv->regmap_base; 1946 *reg = RK3228_PULL_OFFSET; 1947 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1948 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1949 1950 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1951 *bit *= RK3188_PULL_BITS_PER_PIN; 1952 } 1953 1954 #define RK3228_DRV_GRF_OFFSET 0x200 1955 1956 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1957 int pin_num, struct regmap **regmap, 1958 int *reg, u8 *bit) 1959 { 1960 struct rockchip_pinctrl_priv *priv = bank->priv; 1961 1962 *regmap = priv->regmap_base; 1963 *reg = RK3228_DRV_GRF_OFFSET; 1964 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1965 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1966 1967 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1968 *bit *= RK3288_DRV_BITS_PER_PIN; 1969 } 1970 1971 #define RK3308_PULL_OFFSET 0xa0 1972 1973 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1974 int pin_num, struct regmap **regmap, 1975 int *reg, u8 *bit) 1976 { 1977 struct rockchip_pinctrl_priv *priv = bank->priv; 1978 1979 *regmap = priv->regmap_base; 1980 *reg = RK3308_PULL_OFFSET; 1981 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1982 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1983 1984 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1985 *bit *= RK3188_PULL_BITS_PER_PIN; 1986 } 1987 1988 #define RK3308_DRV_GRF_OFFSET 0x100 1989 1990 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1991 int pin_num, struct regmap **regmap, 1992 int *reg, u8 *bit) 1993 { 1994 struct rockchip_pinctrl_priv *priv = bank->priv; 1995 1996 *regmap = priv->regmap_base; 1997 *reg = RK3308_DRV_GRF_OFFSET; 1998 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1999 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2000 2001 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2002 *bit *= RK3288_DRV_BITS_PER_PIN; 2003 } 2004 2005 #define RK3308_SCHMITT_PINS_PER_REG 8 2006 #define RK3308_SCHMITT_BANK_STRIDE 16 2007 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 2008 2009 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2010 int pin_num, 2011 struct regmap **regmap, 2012 int *reg, u8 *bit) 2013 { 2014 struct rockchip_pinctrl_priv *priv = bank->priv; 2015 2016 *regmap = priv->regmap_base; 2017 *reg = RK3308_SCHMITT_GRF_OFFSET; 2018 2019 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 2020 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 2021 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 2022 2023 return 0; 2024 } 2025 2026 #define RK3368_PULL_GRF_OFFSET 0x100 2027 #define RK3368_PULL_PMU_OFFSET 0x10 2028 2029 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2030 int pin_num, struct regmap **regmap, 2031 int *reg, u8 *bit) 2032 { 2033 struct rockchip_pinctrl_priv *priv = bank->priv; 2034 2035 /* The first 32 pins of the first bank are located in PMU */ 2036 if (bank->bank_num == 0) { 2037 *regmap = priv->regmap_pmu; 2038 *reg = RK3368_PULL_PMU_OFFSET; 2039 2040 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2041 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2042 *bit *= RK3188_PULL_BITS_PER_PIN; 2043 } else { 2044 *regmap = priv->regmap_base; 2045 *reg = RK3368_PULL_GRF_OFFSET; 2046 2047 /* correct the offset, as we're starting with the 2nd bank */ 2048 *reg -= 0x10; 2049 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2050 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2051 2052 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2053 *bit *= RK3188_PULL_BITS_PER_PIN; 2054 } 2055 } 2056 2057 #define RK3368_DRV_PMU_OFFSET 0x20 2058 #define RK3368_DRV_GRF_OFFSET 0x200 2059 2060 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2061 int pin_num, struct regmap **regmap, 2062 int *reg, u8 *bit) 2063 { 2064 struct rockchip_pinctrl_priv *priv = bank->priv; 2065 2066 /* The first 32 pins of the first bank are located in PMU */ 2067 if (bank->bank_num == 0) { 2068 *regmap = priv->regmap_pmu; 2069 *reg = RK3368_DRV_PMU_OFFSET; 2070 2071 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2072 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2073 *bit *= RK3288_DRV_BITS_PER_PIN; 2074 } else { 2075 *regmap = priv->regmap_base; 2076 *reg = RK3368_DRV_GRF_OFFSET; 2077 2078 /* correct the offset, as we're starting with the 2nd bank */ 2079 *reg -= 0x10; 2080 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2081 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2082 2083 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2084 *bit *= RK3288_DRV_BITS_PER_PIN; 2085 } 2086 } 2087 2088 #define RK3399_PULL_GRF_OFFSET 0xe040 2089 #define RK3399_PULL_PMU_OFFSET 0x40 2090 #define RK3399_DRV_3BITS_PER_PIN 3 2091 2092 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2093 int pin_num, struct regmap **regmap, 2094 int *reg, u8 *bit) 2095 { 2096 struct rockchip_pinctrl_priv *priv = bank->priv; 2097 2098 /* The bank0:16 and bank1:32 pins are located in PMU */ 2099 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2100 *regmap = priv->regmap_pmu; 2101 *reg = RK3399_PULL_PMU_OFFSET; 2102 2103 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2104 2105 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2106 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2107 *bit *= RK3188_PULL_BITS_PER_PIN; 2108 } else { 2109 *regmap = priv->regmap_base; 2110 *reg = RK3399_PULL_GRF_OFFSET; 2111 2112 /* correct the offset, as we're starting with the 3rd bank */ 2113 *reg -= 0x20; 2114 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2115 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2116 2117 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2118 *bit *= RK3188_PULL_BITS_PER_PIN; 2119 } 2120 } 2121 2122 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2123 int pin_num, struct regmap **regmap, 2124 int *reg, u8 *bit) 2125 { 2126 struct rockchip_pinctrl_priv *priv = bank->priv; 2127 int drv_num = (pin_num / 8); 2128 2129 /* The bank0:16 and bank1:32 pins are located in PMU */ 2130 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2131 *regmap = priv->regmap_pmu; 2132 else 2133 *regmap = priv->regmap_base; 2134 2135 *reg = bank->drv[drv_num].offset; 2136 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2137 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2138 *bit = (pin_num % 8) * 3; 2139 else 2140 *bit = (pin_num % 8) * 2; 2141 } 2142 2143 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2144 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2145 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2146 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2147 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2148 { 4, 7, 10, 13, 16, 19, 22, 26 } 2149 }; 2150 2151 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2152 int pin_num, int strength) 2153 { 2154 struct rockchip_pinctrl_priv *priv = bank->priv; 2155 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2156 struct regmap *regmap; 2157 int reg, ret, i; 2158 u32 data, rmask_bits, temp; 2159 u8 bit; 2160 /* Where need to clean the special mask for rockchip_perpin_drv_list */ 2161 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); 2162 2163 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 2164 pin_num, strength); 2165 2166 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2167 2168 ret = -EINVAL; 2169 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2170 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2171 ret = i; 2172 break; 2173 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2174 ret = rockchip_perpin_drv_list[drv_type][i]; 2175 break; 2176 } 2177 } 2178 2179 if (ret < 0) { 2180 debug("unsupported driver strength %d\n", strength); 2181 return ret; 2182 } 2183 2184 switch (drv_type) { 2185 case DRV_TYPE_IO_1V8_3V0_AUTO: 2186 case DRV_TYPE_IO_3V3_ONLY: 2187 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2188 switch (bit) { 2189 case 0 ... 12: 2190 /* regular case, nothing to do */ 2191 break; 2192 case 15: 2193 /* 2194 * drive-strength offset is special, as it is spread 2195 * over 2 registers, the bit data[15] contains bit 0 2196 * of the value while temp[1:0] contains bits 2 and 1 2197 */ 2198 data = (ret & 0x1) << 15; 2199 temp = (ret >> 0x1) & 0x3; 2200 2201 data |= BIT(31); 2202 ret = regmap_write(regmap, reg, data); 2203 if (ret) 2204 return ret; 2205 2206 temp |= (0x3 << 16); 2207 reg += 0x4; 2208 ret = regmap_write(regmap, reg, temp); 2209 2210 return ret; 2211 case 18 ... 21: 2212 /* setting fully enclosed in the second register */ 2213 reg += 4; 2214 bit -= 16; 2215 break; 2216 default: 2217 debug("unsupported bit: %d for pinctrl drive type: %d\n", 2218 bit, drv_type); 2219 return -EINVAL; 2220 } 2221 break; 2222 case DRV_TYPE_IO_DEFAULT: 2223 case DRV_TYPE_IO_1V8_OR_3V0: 2224 case DRV_TYPE_IO_1V8_ONLY: 2225 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2226 break; 2227 default: 2228 debug("unsupported pinctrl drive type: %d\n", 2229 drv_type); 2230 return -EINVAL; 2231 } 2232 2233 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 2234 regmap_read(regmap, reg, &data); 2235 data &= ~(((1 << rmask_bits) - 1) << bit); 2236 } else { 2237 /* enable the write to the equivalent lower bits */ 2238 data = ((1 << rmask_bits) - 1) << (bit + 16); 2239 } 2240 2241 data |= (ret << bit); 2242 ret = regmap_write(regmap, reg, data); 2243 return ret; 2244 } 2245 2246 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2247 { 2248 PIN_CONFIG_BIAS_DISABLE, 2249 PIN_CONFIG_BIAS_PULL_UP, 2250 PIN_CONFIG_BIAS_PULL_DOWN, 2251 PIN_CONFIG_BIAS_BUS_HOLD 2252 }, 2253 { 2254 PIN_CONFIG_BIAS_DISABLE, 2255 PIN_CONFIG_BIAS_PULL_DOWN, 2256 PIN_CONFIG_BIAS_DISABLE, 2257 PIN_CONFIG_BIAS_PULL_UP 2258 }, 2259 }; 2260 2261 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2262 int pin_num, int pull) 2263 { 2264 struct rockchip_pinctrl_priv *priv = bank->priv; 2265 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2266 struct regmap *regmap; 2267 int reg, ret, i, pull_type; 2268 u8 bit; 2269 u32 data; 2270 2271 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 2272 pin_num, pull); 2273 2274 /* rk3066b does support any pulls */ 2275 if (ctrl->type == RK3066B) 2276 return pull ? -EINVAL : 0; 2277 2278 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2279 2280 switch (ctrl->type) { 2281 case RK2928: 2282 case RK3128: 2283 data = BIT(bit + 16); 2284 if (pull == PIN_CONFIG_BIAS_DISABLE) 2285 data |= BIT(bit); 2286 ret = regmap_write(regmap, reg, data); 2287 break; 2288 case PX30: 2289 case RV1108: 2290 case RK1808: 2291 case RK3188: 2292 case RK3288: 2293 case RK3308: 2294 case RK3368: 2295 case RK3399: 2296 /* 2297 * Where need to clean the special mask for 2298 * rockchip_pull_list. 2299 */ 2300 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); 2301 ret = -EINVAL; 2302 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2303 i++) { 2304 if (rockchip_pull_list[pull_type][i] == pull) { 2305 ret = i; 2306 break; 2307 } 2308 } 2309 2310 if (ret < 0) { 2311 debug("unsupported pull setting %d\n", pull); 2312 return ret; 2313 } 2314 2315 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 2316 regmap_read(regmap, reg, &data); 2317 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); 2318 } else { 2319 /* enable the write to the equivalent lower bits */ 2320 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2321 } 2322 2323 data |= (ret << bit); 2324 ret = regmap_write(regmap, reg, data); 2325 break; 2326 default: 2327 debug("unsupported pinctrl type\n"); 2328 return -EINVAL; 2329 } 2330 2331 return ret; 2332 } 2333 2334 #define RK3328_SCHMITT_BITS_PER_PIN 1 2335 #define RK3328_SCHMITT_PINS_PER_REG 16 2336 #define RK3328_SCHMITT_BANK_STRIDE 8 2337 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2338 2339 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2340 int pin_num, 2341 struct regmap **regmap, 2342 int *reg, u8 *bit) 2343 { 2344 struct rockchip_pinctrl_priv *priv = bank->priv; 2345 2346 *regmap = priv->regmap_base; 2347 *reg = RK3328_SCHMITT_GRF_OFFSET; 2348 2349 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2350 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2351 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2352 2353 return 0; 2354 } 2355 2356 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2357 int pin_num, int enable) 2358 { 2359 struct rockchip_pinctrl_priv *priv = bank->priv; 2360 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2361 struct regmap *regmap; 2362 int reg, ret; 2363 u8 bit; 2364 u32 data; 2365 2366 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 2367 pin_num, enable); 2368 2369 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2370 if (ret) 2371 return ret; 2372 2373 /* enable the write to the equivalent lower bits */ 2374 data = BIT(bit + 16) | (enable << bit); 2375 2376 return regmap_write(regmap, reg, data); 2377 } 2378 2379 /* 2380 * Pinconf_ops handling 2381 */ 2382 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2383 unsigned int pull) 2384 { 2385 switch (ctrl->type) { 2386 case RK2928: 2387 case RK3128: 2388 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2389 pull == PIN_CONFIG_BIAS_DISABLE); 2390 case RK3066B: 2391 return pull ? false : true; 2392 case PX30: 2393 case RV1108: 2394 case RK1808: 2395 case RK3188: 2396 case RK3288: 2397 case RK3308: 2398 case RK3368: 2399 case RK3399: 2400 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2401 } 2402 2403 return false; 2404 } 2405 2406 /* set the pin config settings for a specified pin */ 2407 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 2408 u32 pin, u32 param, u32 arg) 2409 { 2410 struct rockchip_pinctrl_priv *priv = bank->priv; 2411 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2412 int rc; 2413 2414 switch (param) { 2415 case PIN_CONFIG_BIAS_DISABLE: 2416 rc = rockchip_set_pull(bank, pin, param); 2417 if (rc) 2418 return rc; 2419 break; 2420 2421 case PIN_CONFIG_BIAS_PULL_UP: 2422 case PIN_CONFIG_BIAS_PULL_DOWN: 2423 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2424 case PIN_CONFIG_BIAS_BUS_HOLD: 2425 if (!rockchip_pinconf_pull_valid(ctrl, param)) 2426 return -ENOTSUPP; 2427 2428 if (!arg) 2429 return -EINVAL; 2430 2431 rc = rockchip_set_pull(bank, pin, param); 2432 if (rc) 2433 return rc; 2434 break; 2435 2436 case PIN_CONFIG_DRIVE_STRENGTH: 2437 if (!ctrl->drv_calc_reg) 2438 return -ENOTSUPP; 2439 2440 rc = rockchip_set_drive_perpin(bank, pin, arg); 2441 if (rc < 0) 2442 return rc; 2443 break; 2444 2445 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2446 if (!ctrl->schmitt_calc_reg) 2447 return -ENOTSUPP; 2448 2449 rc = rockchip_set_schmitt(bank, pin, arg); 2450 if (rc < 0) 2451 return rc; 2452 break; 2453 2454 default: 2455 break; 2456 } 2457 2458 return 0; 2459 } 2460 2461 static const struct pinconf_param rockchip_conf_params[] = { 2462 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 2463 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 2464 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 2465 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 2466 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 2467 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 2468 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 2469 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 2470 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 2471 }; 2472 2473 static int rockchip_pinconf_prop_name_to_param(const char *property, 2474 u32 *default_value) 2475 { 2476 const struct pinconf_param *p, *end; 2477 2478 p = rockchip_conf_params; 2479 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 2480 2481 /* See if this pctldev supports this parameter */ 2482 for (; p < end; p++) { 2483 if (!strcmp(property, p->property)) { 2484 *default_value = p->default_value; 2485 return p->param; 2486 } 2487 } 2488 2489 *default_value = 0; 2490 return -EPERM; 2491 } 2492 2493 static int rockchip_pinctrl_set_state(struct udevice *dev, 2494 struct udevice *config) 2495 { 2496 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2497 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2498 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 2499 u32 bank, pin, mux, conf, arg, default_val; 2500 int ret, count, i; 2501 const char *prop_name; 2502 const void *value; 2503 int prop_len, param; 2504 const u32 *data; 2505 ofnode node; 2506 #ifdef CONFIG_OF_LIVE 2507 const struct device_node *np; 2508 struct property *pp; 2509 #else 2510 int property_offset, pcfg_node; 2511 const void *blob = gd->fdt_blob; 2512 #endif 2513 data = dev_read_prop(config, "rockchip,pins", &count); 2514 if (count < 0) { 2515 debug("%s: bad array size %d\n", __func__, count); 2516 return -EINVAL; 2517 } 2518 2519 count /= sizeof(u32); 2520 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2521 debug("%s: unsupported pins array count %d\n", 2522 __func__, count); 2523 return -EINVAL; 2524 } 2525 2526 for (i = 0; i < count; i++) 2527 cells[i] = fdt32_to_cpu(data[i]); 2528 2529 for (i = 0; i < (count >> 2); i++) { 2530 bank = cells[4 * i + 0]; 2531 pin = cells[4 * i + 1]; 2532 mux = cells[4 * i + 2]; 2533 conf = cells[4 * i + 3]; 2534 2535 ret = rockchip_verify_config(dev, bank, pin); 2536 if (ret) 2537 return ret; 2538 2539 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2540 if (ret) 2541 return ret; 2542 2543 node = ofnode_get_by_phandle(conf); 2544 if (!ofnode_valid(node)) 2545 return -ENODEV; 2546 #ifdef CONFIG_OF_LIVE 2547 np = ofnode_to_np(node); 2548 for (pp = np->properties; pp; pp = pp->next) { 2549 prop_name = pp->name; 2550 prop_len = pp->length; 2551 value = pp->value; 2552 #else 2553 pcfg_node = ofnode_to_offset(node); 2554 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2555 value = fdt_getprop_by_offset(blob, property_offset, 2556 &prop_name, &prop_len); 2557 if (!value) 2558 return -ENOENT; 2559 #endif 2560 param = rockchip_pinconf_prop_name_to_param(prop_name, 2561 &default_val); 2562 if (param < 0) 2563 break; 2564 2565 if (prop_len >= sizeof(fdt32_t)) 2566 arg = fdt32_to_cpu(*(fdt32_t *)value); 2567 else 2568 arg = default_val; 2569 2570 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2571 param, arg); 2572 if (ret) { 2573 debug("%s: rockchip_pinconf_set fail: %d\n", 2574 __func__, ret); 2575 return ret; 2576 } 2577 } 2578 } 2579 2580 return 0; 2581 } 2582 2583 static struct pinctrl_ops rockchip_pinctrl_ops = { 2584 .set_state = rockchip_pinctrl_set_state, 2585 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2586 }; 2587 2588 /* Ctrl data specially handle */ 2589 static int rk3308b_ctrl_data_re_init(struct rockchip_pin_ctrl *ctrl) 2590 { 2591 /* 2592 * Special for rk3308b, where we need to replace the recalced 2593 * and routed arrays. 2594 */ 2595 if (soc_is_rk3308b()) { 2596 ctrl->iomux_recalced = rk3308b_mux_recalced_data; 2597 ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data); 2598 ctrl->iomux_routes = rk3308b_mux_route_data; 2599 ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data); 2600 } 2601 2602 return 0; 2603 } 2604 2605 /* retrieve the soc specific data */ 2606 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 2607 { 2608 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2609 struct rockchip_pin_ctrl *ctrl = 2610 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 2611 struct rockchip_pin_bank *bank; 2612 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2613 2614 grf_offs = ctrl->grf_mux_offset; 2615 pmu_offs = ctrl->pmu_mux_offset; 2616 drv_pmu_offs = ctrl->pmu_drv_offset; 2617 drv_grf_offs = ctrl->grf_drv_offset; 2618 bank = ctrl->pin_banks; 2619 2620 /* Ctrl data re-initialize for some Socs */ 2621 if (ctrl->ctrl_data_re_init) { 2622 if (ctrl->ctrl_data_re_init(ctrl)) 2623 return NULL; 2624 } 2625 2626 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2627 int bank_pins = 0; 2628 2629 bank->priv = priv; 2630 bank->pin_base = ctrl->nr_pins; 2631 ctrl->nr_pins += bank->nr_pins; 2632 2633 /* calculate iomux and drv offsets */ 2634 for (j = 0; j < 4; j++) { 2635 struct rockchip_iomux *iom = &bank->iomux[j]; 2636 struct rockchip_drv *drv = &bank->drv[j]; 2637 int inc; 2638 2639 if (bank_pins >= bank->nr_pins) 2640 break; 2641 2642 /* preset iomux offset value, set new start value */ 2643 if (iom->offset >= 0) { 2644 if (iom->type & IOMUX_SOURCE_PMU) 2645 pmu_offs = iom->offset; 2646 else 2647 grf_offs = iom->offset; 2648 } else { /* set current iomux offset */ 2649 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2650 pmu_offs : grf_offs; 2651 } 2652 2653 /* preset drv offset value, set new start value */ 2654 if (drv->offset >= 0) { 2655 if (iom->type & IOMUX_SOURCE_PMU) 2656 drv_pmu_offs = drv->offset; 2657 else 2658 drv_grf_offs = drv->offset; 2659 } else { /* set current drv offset */ 2660 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2661 drv_pmu_offs : drv_grf_offs; 2662 } 2663 2664 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2665 i, j, iom->offset, drv->offset); 2666 2667 /* 2668 * Increase offset according to iomux width. 2669 * 4bit iomux'es are spread over two registers. 2670 */ 2671 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2672 IOMUX_WIDTH_3BIT | 2673 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 2674 if (iom->type & IOMUX_SOURCE_PMU) 2675 pmu_offs += inc; 2676 else 2677 grf_offs += inc; 2678 2679 /* 2680 * Increase offset according to drv width. 2681 * 3bit drive-strenth'es are spread over two registers. 2682 */ 2683 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2684 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2685 inc = 8; 2686 else 2687 inc = 4; 2688 2689 if (iom->type & IOMUX_SOURCE_PMU) 2690 drv_pmu_offs += inc; 2691 else 2692 drv_grf_offs += inc; 2693 2694 bank_pins += 8; 2695 } 2696 2697 /* calculate the per-bank recalced_mask */ 2698 for (j = 0; j < ctrl->niomux_recalced; j++) { 2699 int pin = 0; 2700 2701 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2702 pin = ctrl->iomux_recalced[j].pin; 2703 bank->recalced_mask |= BIT(pin); 2704 } 2705 } 2706 2707 /* calculate the per-bank route_mask */ 2708 for (j = 0; j < ctrl->niomux_routes; j++) { 2709 int pin = 0; 2710 2711 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2712 pin = ctrl->iomux_routes[j].pin; 2713 bank->route_mask |= BIT(pin); 2714 } 2715 } 2716 } 2717 2718 return ctrl; 2719 } 2720 2721 /* SoC data specially handle */ 2722 2723 /* rk3308b SoC data initialize */ 2724 #define RK3308B_GRF_SOC_CON13 0x608 2725 #define RK3308B_GRF_SOC_CON15 0x610 2726 2727 /* RK3308B_GRF_SOC_CON13 */ 2728 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) 2729 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 2730 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 2731 2732 /* RK3308B_GRF_SOC_CON15 */ 2733 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) 2734 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 2735 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 2736 2737 static int rk3308b_soc_data_init(struct rockchip_pinctrl_priv *priv) 2738 { 2739 int ret; 2740 2741 /* 2742 * Enable the special ctrl of selected sources. 2743 */ 2744 if (soc_is_rk3308b()) { 2745 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13, 2746 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | 2747 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | 2748 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); 2749 if (ret) 2750 return ret; 2751 2752 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15, 2753 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | 2754 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | 2755 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); 2756 if (ret) 2757 return ret; 2758 } 2759 2760 return 0; 2761 } 2762 2763 static int rockchip_pinctrl_probe(struct udevice *dev) 2764 { 2765 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2766 struct rockchip_pin_ctrl *ctrl; 2767 struct udevice *syscon; 2768 struct regmap *regmap; 2769 int ret = 0; 2770 2771 /* get rockchip grf syscon phandle */ 2772 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2773 &syscon); 2774 if (ret) { 2775 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 2776 return ret; 2777 } 2778 2779 /* get grf-reg base address */ 2780 regmap = syscon_get_regmap(syscon); 2781 if (!regmap) { 2782 debug("unable to find rockchip grf regmap\n"); 2783 return -ENODEV; 2784 } 2785 priv->regmap_base = regmap; 2786 2787 /* option: get pmu-reg base address */ 2788 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 2789 &syscon); 2790 if (!ret) { 2791 /* get pmugrf-reg base address */ 2792 regmap = syscon_get_regmap(syscon); 2793 if (!regmap) { 2794 debug("unable to find rockchip pmu regmap\n"); 2795 return -ENODEV; 2796 } 2797 priv->regmap_pmu = regmap; 2798 } 2799 2800 ctrl = rockchip_pinctrl_get_soc_data(dev); 2801 if (!ctrl) { 2802 debug("driver data not available\n"); 2803 return -EINVAL; 2804 } 2805 2806 /* Special handle for some Socs */ 2807 if (ctrl->soc_data_init) { 2808 ret = ctrl->soc_data_init(priv); 2809 if (ret) 2810 return ret; 2811 } 2812 2813 priv->ctrl = ctrl; 2814 return 0; 2815 } 2816 2817 static struct rockchip_pin_bank px30_pin_banks[] = { 2818 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2819 IOMUX_SOURCE_PMU, 2820 IOMUX_SOURCE_PMU, 2821 IOMUX_SOURCE_PMU 2822 ), 2823 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2824 IOMUX_WIDTH_4BIT, 2825 IOMUX_WIDTH_4BIT, 2826 IOMUX_WIDTH_4BIT 2827 ), 2828 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2829 IOMUX_WIDTH_4BIT, 2830 IOMUX_WIDTH_4BIT, 2831 IOMUX_WIDTH_4BIT 2832 ), 2833 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2834 IOMUX_WIDTH_4BIT, 2835 IOMUX_WIDTH_4BIT, 2836 IOMUX_WIDTH_4BIT 2837 ), 2838 }; 2839 2840 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2841 .pin_banks = px30_pin_banks, 2842 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2843 .label = "PX30-GPIO", 2844 .type = PX30, 2845 .grf_mux_offset = 0x0, 2846 .pmu_mux_offset = 0x0, 2847 .iomux_routes = px30_mux_route_data, 2848 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2849 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2850 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2851 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2852 }; 2853 2854 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2855 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2856 IOMUX_SOURCE_PMU, 2857 IOMUX_SOURCE_PMU, 2858 IOMUX_SOURCE_PMU), 2859 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2860 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2861 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2862 }; 2863 2864 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2865 .pin_banks = rv1108_pin_banks, 2866 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2867 .label = "RV1108-GPIO", 2868 .type = RV1108, 2869 .grf_mux_offset = 0x10, 2870 .pmu_mux_offset = 0x0, 2871 .iomux_recalced = rv1108_mux_recalced_data, 2872 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2873 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2874 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2875 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2876 }; 2877 2878 static struct rockchip_pin_bank rk1808_pin_banks[] = { 2879 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 2880 IOMUX_SOURCE_PMU, 2881 IOMUX_SOURCE_PMU, 2882 IOMUX_SOURCE_PMU, 2883 IOMUX_SOURCE_PMU), 2884 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 2885 IOMUX_WIDTH_4BIT, 2886 IOMUX_WIDTH_4BIT, 2887 IOMUX_WIDTH_4BIT, 2888 IOMUX_WIDTH_4BIT), 2889 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 2890 IOMUX_WIDTH_4BIT, 2891 IOMUX_WIDTH_4BIT, 2892 IOMUX_WIDTH_4BIT, 2893 IOMUX_WIDTH_4BIT), 2894 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2895 IOMUX_WIDTH_4BIT, 2896 IOMUX_WIDTH_4BIT, 2897 IOMUX_WIDTH_4BIT, 2898 IOMUX_WIDTH_4BIT), 2899 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", 2900 IOMUX_WIDTH_4BIT, 2901 IOMUX_WIDTH_4BIT, 2902 IOMUX_WIDTH_4BIT, 2903 IOMUX_WIDTH_4BIT), 2904 }; 2905 2906 static struct rockchip_pin_ctrl rk1808_pin_ctrl = { 2907 .pin_banks = rk1808_pin_banks, 2908 .nr_banks = ARRAY_SIZE(rk1808_pin_banks), 2909 .label = "RK1808-GPIO", 2910 .type = RK1808, 2911 .iomux_routes = rk1808_mux_route_data, 2912 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data), 2913 .grf_mux_offset = 0x0, 2914 .pmu_mux_offset = 0x0, 2915 .pull_calc_reg = rk1808_calc_pull_reg_and_bit, 2916 .drv_calc_reg = rk1808_calc_drv_reg_and_bit, 2917 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit, 2918 }; 2919 2920 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2921 PIN_BANK(0, 32, "gpio0"), 2922 PIN_BANK(1, 32, "gpio1"), 2923 PIN_BANK(2, 32, "gpio2"), 2924 PIN_BANK(3, 32, "gpio3"), 2925 }; 2926 2927 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2928 .pin_banks = rk2928_pin_banks, 2929 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2930 .label = "RK2928-GPIO", 2931 .type = RK2928, 2932 .grf_mux_offset = 0xa8, 2933 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2934 }; 2935 2936 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2937 PIN_BANK(0, 32, "gpio0"), 2938 PIN_BANK(1, 32, "gpio1"), 2939 PIN_BANK(2, 32, "gpio2"), 2940 }; 2941 2942 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2943 .pin_banks = rk3036_pin_banks, 2944 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2945 .label = "RK3036-GPIO", 2946 .type = RK2928, 2947 .grf_mux_offset = 0xa8, 2948 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2949 }; 2950 2951 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2952 PIN_BANK(0, 32, "gpio0"), 2953 PIN_BANK(1, 32, "gpio1"), 2954 PIN_BANK(2, 32, "gpio2"), 2955 PIN_BANK(3, 32, "gpio3"), 2956 PIN_BANK(4, 32, "gpio4"), 2957 PIN_BANK(6, 16, "gpio6"), 2958 }; 2959 2960 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2961 .pin_banks = rk3066a_pin_banks, 2962 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2963 .label = "RK3066a-GPIO", 2964 .type = RK2928, 2965 .grf_mux_offset = 0xa8, 2966 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2967 }; 2968 2969 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2970 PIN_BANK(0, 32, "gpio0"), 2971 PIN_BANK(1, 32, "gpio1"), 2972 PIN_BANK(2, 32, "gpio2"), 2973 PIN_BANK(3, 32, "gpio3"), 2974 }; 2975 2976 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2977 .pin_banks = rk3066b_pin_banks, 2978 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2979 .label = "RK3066b-GPIO", 2980 .type = RK3066B, 2981 .grf_mux_offset = 0x60, 2982 }; 2983 2984 static struct rockchip_pin_bank rk3128_pin_banks[] = { 2985 PIN_BANK(0, 32, "gpio0"), 2986 PIN_BANK(1, 32, "gpio1"), 2987 PIN_BANK(2, 32, "gpio2"), 2988 PIN_BANK(3, 32, "gpio3"), 2989 }; 2990 2991 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 2992 .pin_banks = rk3128_pin_banks, 2993 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 2994 .label = "RK3128-GPIO", 2995 .type = RK3128, 2996 .grf_mux_offset = 0xa8, 2997 .iomux_recalced = rk3128_mux_recalced_data, 2998 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 2999 .iomux_routes = rk3128_mux_route_data, 3000 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3001 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3002 }; 3003 3004 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3005 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3006 PIN_BANK(1, 32, "gpio1"), 3007 PIN_BANK(2, 32, "gpio2"), 3008 PIN_BANK(3, 32, "gpio3"), 3009 }; 3010 3011 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3012 .pin_banks = rk3188_pin_banks, 3013 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3014 .label = "RK3188-GPIO", 3015 .type = RK3188, 3016 .grf_mux_offset = 0x60, 3017 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3018 }; 3019 3020 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3021 PIN_BANK(0, 32, "gpio0"), 3022 PIN_BANK(1, 32, "gpio1"), 3023 PIN_BANK(2, 32, "gpio2"), 3024 PIN_BANK(3, 32, "gpio3"), 3025 }; 3026 3027 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3028 .pin_banks = rk3228_pin_banks, 3029 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3030 .label = "RK3228-GPIO", 3031 .type = RK3288, 3032 .grf_mux_offset = 0x0, 3033 .iomux_routes = rk3228_mux_route_data, 3034 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3035 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3036 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3037 }; 3038 3039 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3040 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 3041 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3042 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3043 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3044 IOMUX_UNROUTED, 3045 DRV_TYPE_WRITABLE_32BIT, 3046 DRV_TYPE_WRITABLE_32BIT, 3047 DRV_TYPE_WRITABLE_32BIT, 3048 0, 3049 PULL_TYPE_WRITABLE_32BIT, 3050 PULL_TYPE_WRITABLE_32BIT, 3051 PULL_TYPE_WRITABLE_32BIT, 3052 0 3053 ), 3054 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3055 IOMUX_UNROUTED, 3056 IOMUX_UNROUTED, 3057 0 3058 ), 3059 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3060 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3061 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3062 IOMUX_WIDTH_4BIT, 3063 0, 3064 0 3065 ), 3066 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3067 0, 3068 0, 3069 IOMUX_UNROUTED 3070 ), 3071 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3072 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3073 0, 3074 IOMUX_WIDTH_4BIT, 3075 IOMUX_UNROUTED 3076 ), 3077 PIN_BANK(8, 16, "gpio8"), 3078 }; 3079 3080 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3081 .pin_banks = rk3288_pin_banks, 3082 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3083 .label = "RK3288-GPIO", 3084 .type = RK3288, 3085 .grf_mux_offset = 0x0, 3086 .pmu_mux_offset = 0x84, 3087 .iomux_routes = rk3288_mux_route_data, 3088 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3089 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3090 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3091 }; 3092 3093 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3094 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 3095 IOMUX_8WIDTH_2BIT, 3096 IOMUX_8WIDTH_2BIT, 3097 IOMUX_8WIDTH_2BIT), 3098 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 3099 IOMUX_8WIDTH_2BIT, 3100 IOMUX_8WIDTH_2BIT, 3101 IOMUX_8WIDTH_2BIT), 3102 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 3103 IOMUX_8WIDTH_2BIT, 3104 IOMUX_8WIDTH_2BIT, 3105 IOMUX_8WIDTH_2BIT), 3106 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 3107 IOMUX_8WIDTH_2BIT, 3108 IOMUX_8WIDTH_2BIT, 3109 IOMUX_8WIDTH_2BIT), 3110 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 3111 IOMUX_8WIDTH_2BIT, 3112 IOMUX_8WIDTH_2BIT, 3113 IOMUX_8WIDTH_2BIT), 3114 }; 3115 3116 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3117 .pin_banks = rk3308_pin_banks, 3118 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3119 .label = "RK3308-GPIO", 3120 .type = RK3308, 3121 .grf_mux_offset = 0x0, 3122 .iomux_recalced = rk3308_mux_recalced_data, 3123 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3124 .iomux_routes = rk3308_mux_route_data, 3125 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3126 .ctrl_data_re_init = rk3308b_ctrl_data_re_init, 3127 .soc_data_init = rk3308b_soc_data_init, 3128 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3129 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3130 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3131 }; 3132 3133 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3134 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3135 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3136 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3137 IOMUX_WIDTH_3BIT, 3138 IOMUX_WIDTH_3BIT, 3139 0), 3140 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3141 IOMUX_WIDTH_3BIT, 3142 IOMUX_WIDTH_3BIT, 3143 0, 3144 0), 3145 }; 3146 3147 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3148 .pin_banks = rk3328_pin_banks, 3149 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3150 .label = "RK3328-GPIO", 3151 .type = RK3288, 3152 .grf_mux_offset = 0x0, 3153 .iomux_recalced = rk3328_mux_recalced_data, 3154 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3155 .iomux_routes = rk3328_mux_route_data, 3156 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3157 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3158 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3159 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3160 }; 3161 3162 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3163 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3164 IOMUX_SOURCE_PMU, 3165 IOMUX_SOURCE_PMU, 3166 IOMUX_SOURCE_PMU 3167 ), 3168 PIN_BANK(1, 32, "gpio1"), 3169 PIN_BANK(2, 32, "gpio2"), 3170 PIN_BANK(3, 32, "gpio3"), 3171 }; 3172 3173 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3174 .pin_banks = rk3368_pin_banks, 3175 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3176 .label = "RK3368-GPIO", 3177 .type = RK3368, 3178 .grf_mux_offset = 0x0, 3179 .pmu_mux_offset = 0x0, 3180 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3181 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3182 }; 3183 3184 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3185 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3186 IOMUX_SOURCE_PMU, 3187 IOMUX_SOURCE_PMU, 3188 IOMUX_SOURCE_PMU, 3189 IOMUX_SOURCE_PMU, 3190 DRV_TYPE_IO_1V8_ONLY, 3191 DRV_TYPE_IO_1V8_ONLY, 3192 DRV_TYPE_IO_DEFAULT, 3193 DRV_TYPE_IO_DEFAULT, 3194 0x80, 3195 0x88, 3196 -1, 3197 -1, 3198 PULL_TYPE_IO_1V8_ONLY, 3199 PULL_TYPE_IO_1V8_ONLY, 3200 PULL_TYPE_IO_DEFAULT, 3201 PULL_TYPE_IO_DEFAULT 3202 ), 3203 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3204 IOMUX_SOURCE_PMU, 3205 IOMUX_SOURCE_PMU, 3206 IOMUX_SOURCE_PMU, 3207 DRV_TYPE_IO_1V8_OR_3V0, 3208 DRV_TYPE_IO_1V8_OR_3V0, 3209 DRV_TYPE_IO_1V8_OR_3V0, 3210 DRV_TYPE_IO_1V8_OR_3V0, 3211 0xa0, 3212 0xa8, 3213 0xb0, 3214 0xb8 3215 ), 3216 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3217 DRV_TYPE_IO_1V8_OR_3V0, 3218 DRV_TYPE_IO_1V8_ONLY, 3219 DRV_TYPE_IO_1V8_ONLY, 3220 PULL_TYPE_IO_DEFAULT, 3221 PULL_TYPE_IO_DEFAULT, 3222 PULL_TYPE_IO_1V8_ONLY, 3223 PULL_TYPE_IO_1V8_ONLY 3224 ), 3225 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3226 DRV_TYPE_IO_3V3_ONLY, 3227 DRV_TYPE_IO_3V3_ONLY, 3228 DRV_TYPE_IO_1V8_OR_3V0 3229 ), 3230 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3231 DRV_TYPE_IO_1V8_3V0_AUTO, 3232 DRV_TYPE_IO_1V8_OR_3V0, 3233 DRV_TYPE_IO_1V8_OR_3V0 3234 ), 3235 }; 3236 3237 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3238 .pin_banks = rk3399_pin_banks, 3239 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3240 .label = "RK3399-GPIO", 3241 .type = RK3399, 3242 .grf_mux_offset = 0xe000, 3243 .pmu_mux_offset = 0x0, 3244 .grf_drv_offset = 0xe100, 3245 .pmu_drv_offset = 0x80, 3246 .iomux_routes = rk3399_mux_route_data, 3247 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3248 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3249 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3250 }; 3251 3252 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 3253 { .compatible = "rockchip,px30-pinctrl", 3254 .data = (ulong)&px30_pin_ctrl }, 3255 { .compatible = "rockchip,rv1108-pinctrl", 3256 .data = (ulong)&rv1108_pin_ctrl }, 3257 { .compatible = "rockchip,rk1808-pinctrl", 3258 .data = (ulong)&rk1808_pin_ctrl }, 3259 { .compatible = "rockchip,rk2928-pinctrl", 3260 .data = (ulong)&rk2928_pin_ctrl }, 3261 { .compatible = "rockchip,rk3036-pinctrl", 3262 .data = (ulong)&rk3036_pin_ctrl }, 3263 { .compatible = "rockchip,rk3066a-pinctrl", 3264 .data = (ulong)&rk3066a_pin_ctrl }, 3265 { .compatible = "rockchip,rk3066b-pinctrl", 3266 .data = (ulong)&rk3066b_pin_ctrl }, 3267 { .compatible = "rockchip,rk3128-pinctrl", 3268 .data = (ulong)&rk3128_pin_ctrl }, 3269 { .compatible = "rockchip,rk3188-pinctrl", 3270 .data = (ulong)&rk3188_pin_ctrl }, 3271 { .compatible = "rockchip,rk3228-pinctrl", 3272 .data = (ulong)&rk3228_pin_ctrl }, 3273 { .compatible = "rockchip,rk3288-pinctrl", 3274 .data = (ulong)&rk3288_pin_ctrl }, 3275 { .compatible = "rockchip,rk3308-pinctrl", 3276 .data = (ulong)&rk3308_pin_ctrl }, 3277 { .compatible = "rockchip,rk3328-pinctrl", 3278 .data = (ulong)&rk3328_pin_ctrl }, 3279 { .compatible = "rockchip,rk3368-pinctrl", 3280 .data = (ulong)&rk3368_pin_ctrl }, 3281 { .compatible = "rockchip,rk3399-pinctrl", 3282 .data = (ulong)&rk3399_pin_ctrl }, 3283 {}, 3284 }; 3285 3286 U_BOOT_DRIVER(pinctrl_rockchip) = { 3287 .name = "rockchip_pinctrl", 3288 .id = UCLASS_PINCTRL, 3289 .of_match = rockchip_pinctrl_dt_match, 3290 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 3291 .ops = &rockchip_pinctrl_ops, 3292 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 3293 .bind = dm_scan_fdt_dev, 3294 #endif 3295 .probe = rockchip_pinctrl_probe, 3296 }; 3297