1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 14 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 15 #define RK_FUNC_GPIO 0 16 #define MAX_ROCKCHIP_PINS_ENTRIES 30 17 18 enum rockchip_pinctrl_type { 19 PX30, 20 RV1108, 21 RK1808, 22 RK2928, 23 RK3066B, 24 RK3128, 25 RK3188, 26 RK3288, 27 RK3308, 28 RK3368, 29 RK3399, 30 }; 31 32 /** 33 * Encode variants of iomux registers into a type variable 34 */ 35 #define IOMUX_GPIO_ONLY BIT(0) 36 #define IOMUX_WIDTH_4BIT BIT(1) 37 #define IOMUX_SOURCE_PMU BIT(2) 38 #define IOMUX_UNROUTED BIT(3) 39 #define IOMUX_WIDTH_3BIT BIT(4) 40 #define IOMUX_8WIDTH_2BIT BIT(5) 41 #define IOMUX_WRITABLE_32BIT BIT(6) 42 43 /** 44 * @type: iomux variant using IOMUX_* constants 45 * @offset: if initialized to -1 it will be autocalculated, by specifying 46 * an initial offset value the relevant source offset can be reset 47 * to a new value for autocalculating the following iomux registers. 48 */ 49 struct rockchip_iomux { 50 int type; 51 int offset; 52 }; 53 54 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 55 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 56 57 /** 58 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 59 */ 60 enum rockchip_pin_drv_type { 61 DRV_TYPE_IO_DEFAULT = 0, 62 DRV_TYPE_IO_1V8_OR_3V0, 63 DRV_TYPE_IO_1V8_ONLY, 64 DRV_TYPE_IO_1V8_3V0_AUTO, 65 DRV_TYPE_IO_3V3_ONLY, 66 DRV_TYPE_MAX 67 }; 68 69 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 70 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 71 72 /** 73 * enum type index corresponding to rockchip_pull_list arrays index. 74 */ 75 enum rockchip_pin_pull_type { 76 PULL_TYPE_IO_DEFAULT = 0, 77 PULL_TYPE_IO_1V8_ONLY, 78 PULL_TYPE_MAX 79 }; 80 81 /** 82 * @drv_type: drive strength variant using rockchip_perpin_drv_type 83 * @offset: if initialized to -1 it will be autocalculated, by specifying 84 * an initial offset value the relevant source offset can be reset 85 * to a new value for autocalculating the following drive strength 86 * registers. if used chips own cal_drv func instead to calculate 87 * registers offset, the variant could be ignored. 88 */ 89 struct rockchip_drv { 90 enum rockchip_pin_drv_type drv_type; 91 int offset; 92 }; 93 94 /** 95 * @priv: common pinctrl private basedata 96 * @pin_base: first pin number 97 * @nr_pins: number of pins in this bank 98 * @name: name of the bank 99 * @bank_num: number of the bank, to account for holes 100 * @iomux: array describing the 4 iomux sources of the bank 101 * @drv: array describing the 4 drive strength sources of the bank 102 * @pull_type: array describing the 4 pull type sources of the bank 103 * @recalced_mask: bits describing the mux recalced pins of per bank 104 * @route_mask: bits describing the routing pins of per bank 105 */ 106 struct rockchip_pin_bank { 107 struct rockchip_pinctrl_priv *priv; 108 u32 pin_base; 109 u8 nr_pins; 110 char *name; 111 u8 bank_num; 112 struct rockchip_iomux iomux[4]; 113 struct rockchip_drv drv[4]; 114 enum rockchip_pin_pull_type pull_type[4]; 115 u32 recalced_mask; 116 u32 route_mask; 117 }; 118 119 #define PIN_BANK(id, pins, label) \ 120 { \ 121 .bank_num = id, \ 122 .nr_pins = pins, \ 123 .name = label, \ 124 .iomux = { \ 125 { .offset = -1 }, \ 126 { .offset = -1 }, \ 127 { .offset = -1 }, \ 128 { .offset = -1 }, \ 129 }, \ 130 } 131 132 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 133 { \ 134 .bank_num = id, \ 135 .nr_pins = pins, \ 136 .name = label, \ 137 .iomux = { \ 138 { .type = iom0, .offset = -1 }, \ 139 { .type = iom1, .offset = -1 }, \ 140 { .type = iom2, .offset = -1 }, \ 141 { .type = iom3, .offset = -1 }, \ 142 }, \ 143 } 144 145 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 146 { \ 147 .bank_num = id, \ 148 .nr_pins = pins, \ 149 .name = label, \ 150 .iomux = { \ 151 { .offset = -1 }, \ 152 { .offset = -1 }, \ 153 { .offset = -1 }, \ 154 { .offset = -1 }, \ 155 }, \ 156 .drv = { \ 157 { .drv_type = type0, .offset = -1 }, \ 158 { .drv_type = type1, .offset = -1 }, \ 159 { .drv_type = type2, .offset = -1 }, \ 160 { .drv_type = type3, .offset = -1 }, \ 161 }, \ 162 } 163 164 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 165 drv2, drv3, pull0, pull1, \ 166 pull2, pull3) \ 167 { \ 168 .bank_num = id, \ 169 .nr_pins = pins, \ 170 .name = label, \ 171 .iomux = { \ 172 { .offset = -1 }, \ 173 { .offset = -1 }, \ 174 { .offset = -1 }, \ 175 { .offset = -1 }, \ 176 }, \ 177 .drv = { \ 178 { .drv_type = drv0, .offset = -1 }, \ 179 { .drv_type = drv1, .offset = -1 }, \ 180 { .drv_type = drv2, .offset = -1 }, \ 181 { .drv_type = drv3, .offset = -1 }, \ 182 }, \ 183 .pull_type[0] = pull0, \ 184 .pull_type[1] = pull1, \ 185 .pull_type[2] = pull2, \ 186 .pull_type[3] = pull3, \ 187 } 188 189 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 190 iom2, iom3, drv0, drv1, drv2, \ 191 drv3, offset0, offset1, \ 192 offset2, offset3) \ 193 { \ 194 .bank_num = id, \ 195 .nr_pins = pins, \ 196 .name = label, \ 197 .iomux = { \ 198 { .type = iom0, .offset = -1 }, \ 199 { .type = iom1, .offset = -1 }, \ 200 { .type = iom2, .offset = -1 }, \ 201 { .type = iom3, .offset = -1 }, \ 202 }, \ 203 .drv = { \ 204 { .drv_type = drv0, .offset = offset0 }, \ 205 { .drv_type = drv1, .offset = offset1 }, \ 206 { .drv_type = drv2, .offset = offset2 }, \ 207 { .drv_type = drv3, .offset = offset3 }, \ 208 }, \ 209 } 210 211 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 212 iom2, iom3, drv0, drv1, drv2, \ 213 drv3, pull0, pull1, pull2, \ 214 pull3) \ 215 { \ 216 .bank_num = id, \ 217 .nr_pins = pins, \ 218 .name = label, \ 219 .iomux = { \ 220 { .type = iom0, .offset = -1 }, \ 221 { .type = iom1, .offset = -1 }, \ 222 { .type = iom2, .offset = -1 }, \ 223 { .type = iom3, .offset = -1 }, \ 224 }, \ 225 .drv = { \ 226 { .drv_type = drv0, .offset = -1 }, \ 227 { .drv_type = drv1, .offset = -1 }, \ 228 { .drv_type = drv2, .offset = -1 }, \ 229 { .drv_type = drv3, .offset = -1 }, \ 230 }, \ 231 .pull_type[0] = pull0, \ 232 .pull_type[1] = pull1, \ 233 .pull_type[2] = pull2, \ 234 .pull_type[3] = pull3, \ 235 } 236 237 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 238 label, iom0, iom1, iom2, \ 239 iom3, drv0, drv1, drv2, \ 240 drv3, offset0, offset1, \ 241 offset2, offset3, pull0, \ 242 pull1, pull2, pull3) \ 243 { \ 244 .bank_num = id, \ 245 .nr_pins = pins, \ 246 .name = label, \ 247 .iomux = { \ 248 { .type = iom0, .offset = -1 }, \ 249 { .type = iom1, .offset = -1 }, \ 250 { .type = iom2, .offset = -1 }, \ 251 { .type = iom3, .offset = -1 }, \ 252 }, \ 253 .drv = { \ 254 { .drv_type = drv0, .offset = offset0 }, \ 255 { .drv_type = drv1, .offset = offset1 }, \ 256 { .drv_type = drv2, .offset = offset2 }, \ 257 { .drv_type = drv3, .offset = offset3 }, \ 258 }, \ 259 .pull_type[0] = pull0, \ 260 .pull_type[1] = pull1, \ 261 .pull_type[2] = pull2, \ 262 .pull_type[3] = pull3, \ 263 } 264 265 /** 266 * struct rockchip_mux_recalced_data: represent a pin iomux data. 267 * @num: bank number. 268 * @pin: pin number. 269 * @bit: index at register. 270 * @reg: register offset. 271 * @mask: mask bit 272 */ 273 struct rockchip_mux_recalced_data { 274 u8 num; 275 u8 pin; 276 u32 reg; 277 u8 bit; 278 u8 mask; 279 }; 280 281 /** 282 * struct rockchip_mux_recalced_data: represent a pin iomux data. 283 * @bank_num: bank number. 284 * @pin: index at register or used to calc index. 285 * @func: the min pin. 286 * @route_offset: the max pin. 287 * @route_val: the register offset. 288 */ 289 struct rockchip_mux_route_data { 290 u8 bank_num; 291 u8 pin; 292 u8 func; 293 u32 route_offset; 294 u32 route_val; 295 }; 296 297 /** 298 */ 299 struct rockchip_pin_ctrl { 300 struct rockchip_pin_bank *pin_banks; 301 u32 nr_banks; 302 u32 nr_pins; 303 char *label; 304 enum rockchip_pinctrl_type type; 305 int grf_mux_offset; 306 int pmu_mux_offset; 307 int grf_drv_offset; 308 int pmu_drv_offset; 309 struct rockchip_mux_recalced_data *iomux_recalced; 310 u32 niomux_recalced; 311 struct rockchip_mux_route_data *iomux_routes; 312 u32 niomux_routes; 313 314 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 315 int pin_num, struct regmap **regmap, 316 int *reg, u8 *bit); 317 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 318 int pin_num, struct regmap **regmap, 319 int *reg, u8 *bit); 320 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 321 int pin_num, struct regmap **regmap, 322 int *reg, u8 *bit); 323 }; 324 325 /** 326 */ 327 struct rockchip_pinctrl_priv { 328 struct rockchip_pin_ctrl *ctrl; 329 struct regmap *regmap_base; 330 struct regmap *regmap_pmu; 331 332 }; 333 334 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 335 { 336 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 337 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 338 339 if (bank >= ctrl->nr_banks) { 340 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 341 return -EINVAL; 342 } 343 344 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 345 debug("pin conf pin %d >= %d\n", pin, 346 MAX_ROCKCHIP_GPIO_PER_BANK); 347 return -EINVAL; 348 } 349 350 return 0; 351 } 352 353 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 354 { 355 .num = 1, 356 .pin = 0, 357 .reg = 0x418, 358 .bit = 0, 359 .mask = 0x3 360 }, { 361 .num = 1, 362 .pin = 1, 363 .reg = 0x418, 364 .bit = 2, 365 .mask = 0x3 366 }, { 367 .num = 1, 368 .pin = 2, 369 .reg = 0x418, 370 .bit = 4, 371 .mask = 0x3 372 }, { 373 .num = 1, 374 .pin = 3, 375 .reg = 0x418, 376 .bit = 6, 377 .mask = 0x3 378 }, { 379 .num = 1, 380 .pin = 4, 381 .reg = 0x418, 382 .bit = 8, 383 .mask = 0x3 384 }, { 385 .num = 1, 386 .pin = 5, 387 .reg = 0x418, 388 .bit = 10, 389 .mask = 0x3 390 }, { 391 .num = 1, 392 .pin = 6, 393 .reg = 0x418, 394 .bit = 12, 395 .mask = 0x3 396 }, { 397 .num = 1, 398 .pin = 7, 399 .reg = 0x418, 400 .bit = 14, 401 .mask = 0x3 402 }, { 403 .num = 1, 404 .pin = 8, 405 .reg = 0x41c, 406 .bit = 0, 407 .mask = 0x3 408 }, { 409 .num = 1, 410 .pin = 9, 411 .reg = 0x41c, 412 .bit = 2, 413 .mask = 0x3 414 }, 415 }; 416 417 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 418 { 419 .num = 2, 420 .pin = 20, 421 .reg = 0xe8, 422 .bit = 0, 423 .mask = 0x7 424 }, { 425 .num = 2, 426 .pin = 21, 427 .reg = 0xe8, 428 .bit = 4, 429 .mask = 0x7 430 }, { 431 .num = 2, 432 .pin = 22, 433 .reg = 0xe8, 434 .bit = 8, 435 .mask = 0x7 436 }, { 437 .num = 2, 438 .pin = 23, 439 .reg = 0xe8, 440 .bit = 12, 441 .mask = 0x7 442 }, { 443 .num = 2, 444 .pin = 24, 445 .reg = 0xd4, 446 .bit = 12, 447 .mask = 0x7 448 }, 449 }; 450 451 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 452 { 453 .num = 1, 454 .pin = 14, 455 .reg = 0x28, 456 .bit = 12, 457 .mask = 0x7 458 }, { 459 .num = 1, 460 .pin = 15, 461 .reg = 0x2c, 462 .bit = 0, 463 .mask = 0x3 464 }, { 465 .num = 1, 466 .pin = 18, 467 .reg = 0x30, 468 .bit = 4, 469 .mask = 0x7 470 }, { 471 .num = 1, 472 .pin = 19, 473 .reg = 0x30, 474 .bit = 8, 475 .mask = 0x7 476 }, { 477 .num = 1, 478 .pin = 20, 479 .reg = 0x30, 480 .bit = 12, 481 .mask = 0x7 482 }, { 483 .num = 1, 484 .pin = 21, 485 .reg = 0x34, 486 .bit = 0, 487 .mask = 0x7 488 }, { 489 .num = 1, 490 .pin = 22, 491 .reg = 0x34, 492 .bit = 4, 493 .mask = 0x7 494 }, { 495 .num = 1, 496 .pin = 23, 497 .reg = 0x34, 498 .bit = 8, 499 .mask = 0x7 500 }, { 501 .num = 3, 502 .pin = 12, 503 .reg = 0x68, 504 .bit = 8, 505 .mask = 0x7 506 }, { 507 .num = 3, 508 .pin = 13, 509 .reg = 0x68, 510 .bit = 12, 511 .mask = 0x7 512 }, 513 }; 514 515 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 516 { 517 .num = 2, 518 .pin = 12, 519 .reg = 0x24, 520 .bit = 8, 521 .mask = 0x3 522 }, { 523 .num = 2, 524 .pin = 15, 525 .reg = 0x28, 526 .bit = 0, 527 .mask = 0x7 528 }, { 529 .num = 2, 530 .pin = 23, 531 .reg = 0x30, 532 .bit = 14, 533 .mask = 0x3 534 }, 535 }; 536 537 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 538 int *reg, u8 *bit, int *mask) 539 { 540 struct rockchip_pinctrl_priv *priv = bank->priv; 541 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 542 struct rockchip_mux_recalced_data *data; 543 int i; 544 545 for (i = 0; i < ctrl->niomux_recalced; i++) { 546 data = &ctrl->iomux_recalced[i]; 547 if (data->num == bank->bank_num && 548 data->pin == pin) 549 break; 550 } 551 552 if (i >= ctrl->niomux_recalced) 553 return; 554 555 *reg = data->reg; 556 *mask = data->mask; 557 *bit = data->bit; 558 } 559 560 static struct rockchip_mux_route_data px30_mux_route_data[] = { 561 { 562 /* cif-d2m0 */ 563 .bank_num = 2, 564 .pin = 0, 565 .func = 1, 566 .route_offset = 0x184, 567 .route_val = BIT(16 + 7), 568 }, { 569 /* cif-d2m1 */ 570 .bank_num = 3, 571 .pin = 3, 572 .func = 3, 573 .route_offset = 0x184, 574 .route_val = BIT(16 + 7) | BIT(7), 575 }, { 576 /* pdm-m0 */ 577 .bank_num = 3, 578 .pin = 22, 579 .func = 2, 580 .route_offset = 0x184, 581 .route_val = BIT(16 + 8), 582 }, { 583 /* pdm-m1 */ 584 .bank_num = 2, 585 .pin = 22, 586 .func = 1, 587 .route_offset = 0x184, 588 .route_val = BIT(16 + 8) | BIT(8), 589 }, { 590 /* uart2-rxm0 */ 591 .bank_num = 1, 592 .pin = 27, 593 .func = 2, 594 .route_offset = 0x184, 595 .route_val = BIT(16 + 10), 596 }, { 597 /* uart2-rxm1 */ 598 .bank_num = 2, 599 .pin = 14, 600 .func = 2, 601 .route_offset = 0x184, 602 .route_val = BIT(16 + 10) | BIT(10), 603 }, { 604 /* uart3-rxm0 */ 605 .bank_num = 0, 606 .pin = 17, 607 .func = 2, 608 .route_offset = 0x184, 609 .route_val = BIT(16 + 9), 610 }, { 611 /* uart3-rxm1 */ 612 .bank_num = 1, 613 .pin = 15, 614 .func = 2, 615 .route_offset = 0x184, 616 .route_val = BIT(16 + 9) | BIT(9), 617 }, 618 }; 619 620 static struct rockchip_mux_route_data rk1808_mux_route_data[] = { 621 { 622 /* i2c2m0_sda */ 623 .bank_num = 3, 624 .pin = 12, 625 .func = 2, 626 .route_offset = 0x190, 627 .route_val = BIT(16 + 3), 628 }, { 629 /* i2c2m1_sda */ 630 .bank_num = 1, 631 .pin = 13, 632 .func = 2, 633 .route_offset = 0x190, 634 .route_val = BIT(16 + 3) | BIT(3), 635 }, { 636 /* uart2_rxm0 */ 637 .bank_num = 4, 638 .pin = 3, 639 .func = 2, 640 .route_offset = 0x190, 641 .route_val = BIT(16 + 14) | BIT(16 + 15), 642 }, { 643 /* uart2_rxm1 */ 644 .bank_num = 2, 645 .pin = 25, 646 .func = 2, 647 .route_offset = 0x190, 648 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15), 649 }, { 650 /* uart2_rxm2 */ 651 .bank_num = 3, 652 .pin = 4, 653 .func = 2, 654 .route_offset = 0x190, 655 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15), 656 }, 657 }; 658 659 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 660 { 661 /* spi-0 */ 662 .bank_num = 1, 663 .pin = 10, 664 .func = 1, 665 .route_offset = 0x144, 666 .route_val = BIT(16 + 3) | BIT(16 + 4), 667 }, { 668 /* spi-1 */ 669 .bank_num = 1, 670 .pin = 27, 671 .func = 3, 672 .route_offset = 0x144, 673 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 674 }, { 675 /* spi-2 */ 676 .bank_num = 0, 677 .pin = 13, 678 .func = 2, 679 .route_offset = 0x144, 680 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 681 }, { 682 /* i2s-0 */ 683 .bank_num = 1, 684 .pin = 5, 685 .func = 1, 686 .route_offset = 0x144, 687 .route_val = BIT(16 + 5), 688 }, { 689 /* i2s-1 */ 690 .bank_num = 0, 691 .pin = 14, 692 .func = 1, 693 .route_offset = 0x144, 694 .route_val = BIT(16 + 5) | BIT(5), 695 }, { 696 /* emmc-0 */ 697 .bank_num = 1, 698 .pin = 22, 699 .func = 2, 700 .route_offset = 0x144, 701 .route_val = BIT(16 + 6), 702 }, { 703 /* emmc-1 */ 704 .bank_num = 2, 705 .pin = 4, 706 .func = 2, 707 .route_offset = 0x144, 708 .route_val = BIT(16 + 6) | BIT(6), 709 }, 710 }; 711 712 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 713 { 714 /* pwm0-0 */ 715 .bank_num = 0, 716 .pin = 26, 717 .func = 1, 718 .route_offset = 0x50, 719 .route_val = BIT(16), 720 }, { 721 /* pwm0-1 */ 722 .bank_num = 3, 723 .pin = 21, 724 .func = 1, 725 .route_offset = 0x50, 726 .route_val = BIT(16) | BIT(0), 727 }, { 728 /* pwm1-0 */ 729 .bank_num = 0, 730 .pin = 27, 731 .func = 1, 732 .route_offset = 0x50, 733 .route_val = BIT(16 + 1), 734 }, { 735 /* pwm1-1 */ 736 .bank_num = 0, 737 .pin = 30, 738 .func = 2, 739 .route_offset = 0x50, 740 .route_val = BIT(16 + 1) | BIT(1), 741 }, { 742 /* pwm2-0 */ 743 .bank_num = 0, 744 .pin = 28, 745 .func = 1, 746 .route_offset = 0x50, 747 .route_val = BIT(16 + 2), 748 }, { 749 /* pwm2-1 */ 750 .bank_num = 1, 751 .pin = 12, 752 .func = 2, 753 .route_offset = 0x50, 754 .route_val = BIT(16 + 2) | BIT(2), 755 }, { 756 /* pwm3-0 */ 757 .bank_num = 3, 758 .pin = 26, 759 .func = 1, 760 .route_offset = 0x50, 761 .route_val = BIT(16 + 3), 762 }, { 763 /* pwm3-1 */ 764 .bank_num = 1, 765 .pin = 11, 766 .func = 2, 767 .route_offset = 0x50, 768 .route_val = BIT(16 + 3) | BIT(3), 769 }, { 770 /* sdio-0_d0 */ 771 .bank_num = 1, 772 .pin = 1, 773 .func = 1, 774 .route_offset = 0x50, 775 .route_val = BIT(16 + 4), 776 }, { 777 /* sdio-1_d0 */ 778 .bank_num = 3, 779 .pin = 2, 780 .func = 1, 781 .route_offset = 0x50, 782 .route_val = BIT(16 + 4) | BIT(4), 783 }, { 784 /* spi-0_rx */ 785 .bank_num = 0, 786 .pin = 13, 787 .func = 2, 788 .route_offset = 0x50, 789 .route_val = BIT(16 + 5), 790 }, { 791 /* spi-1_rx */ 792 .bank_num = 2, 793 .pin = 0, 794 .func = 2, 795 .route_offset = 0x50, 796 .route_val = BIT(16 + 5) | BIT(5), 797 }, { 798 /* emmc-0_cmd */ 799 .bank_num = 1, 800 .pin = 22, 801 .func = 2, 802 .route_offset = 0x50, 803 .route_val = BIT(16 + 7), 804 }, { 805 /* emmc-1_cmd */ 806 .bank_num = 2, 807 .pin = 4, 808 .func = 2, 809 .route_offset = 0x50, 810 .route_val = BIT(16 + 7) | BIT(7), 811 }, { 812 /* uart2-0_rx */ 813 .bank_num = 1, 814 .pin = 19, 815 .func = 2, 816 .route_offset = 0x50, 817 .route_val = BIT(16 + 8), 818 }, { 819 /* uart2-1_rx */ 820 .bank_num = 1, 821 .pin = 10, 822 .func = 2, 823 .route_offset = 0x50, 824 .route_val = BIT(16 + 8) | BIT(8), 825 }, { 826 /* uart1-0_rx */ 827 .bank_num = 1, 828 .pin = 10, 829 .func = 1, 830 .route_offset = 0x50, 831 .route_val = BIT(16 + 11), 832 }, { 833 /* uart1-1_rx */ 834 .bank_num = 3, 835 .pin = 13, 836 .func = 1, 837 .route_offset = 0x50, 838 .route_val = BIT(16 + 11) | BIT(11), 839 }, 840 }; 841 842 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 843 { 844 /* edphdmi_cecinoutt1 */ 845 .bank_num = 7, 846 .pin = 16, 847 .func = 2, 848 .route_offset = 0x264, 849 .route_val = BIT(16 + 12) | BIT(12), 850 }, { 851 /* edphdmi_cecinout */ 852 .bank_num = 7, 853 .pin = 23, 854 .func = 4, 855 .route_offset = 0x264, 856 .route_val = BIT(16 + 12), 857 }, 858 }; 859 860 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 861 { 862 /* uart2_rxm0 */ 863 .bank_num = 1, 864 .pin = 22, 865 .func = 2, 866 .route_offset = 0x314, 867 .route_val = BIT(16 + 2) | BIT(16 + 3), 868 }, { 869 /* uart2_rxm1 */ 870 .bank_num = 4, 871 .pin = 26, 872 .func = 2, 873 .route_offset = 0x314, 874 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 875 }, { 876 /* i2c3_sdam0 */ 877 .bank_num = 0, 878 .pin = 23, 879 .func = 2, 880 .route_offset = 0x314, 881 .route_val = BIT(16 + 4), 882 }, { 883 /* i2c3_sdam1 */ 884 .bank_num = 3, 885 .pin = 12, 886 .func = 2, 887 .route_offset = 0x314, 888 .route_val = BIT(16 + 4) | BIT(4), 889 }, 890 }; 891 892 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 893 { 894 /* uart2dbg_rxm0 */ 895 .bank_num = 1, 896 .pin = 1, 897 .func = 2, 898 .route_offset = 0x50, 899 .route_val = BIT(16) | BIT(16 + 1), 900 }, { 901 /* uart2dbg_rxm1 */ 902 .bank_num = 2, 903 .pin = 1, 904 .func = 1, 905 .route_offset = 0x50, 906 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 907 }, { 908 /* gmac-m1_rxd0 */ 909 .bank_num = 1, 910 .pin = 11, 911 .func = 2, 912 .route_offset = 0x50, 913 .route_val = BIT(16 + 2) | BIT(2), 914 }, { 915 /* gmac-m1-optimized_rxd3 */ 916 .bank_num = 1, 917 .pin = 14, 918 .func = 2, 919 .route_offset = 0x50, 920 .route_val = BIT(16 + 10) | BIT(10), 921 }, { 922 /* pdm_sdi0m0 */ 923 .bank_num = 2, 924 .pin = 19, 925 .func = 2, 926 .route_offset = 0x50, 927 .route_val = BIT(16 + 3), 928 }, { 929 /* pdm_sdi0m1 */ 930 .bank_num = 1, 931 .pin = 23, 932 .func = 3, 933 .route_offset = 0x50, 934 .route_val = BIT(16 + 3) | BIT(3), 935 }, { 936 /* spi_rxdm2 */ 937 .bank_num = 3, 938 .pin = 2, 939 .func = 4, 940 .route_offset = 0x50, 941 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 942 }, { 943 /* i2s2_sdim0 */ 944 .bank_num = 1, 945 .pin = 24, 946 .func = 1, 947 .route_offset = 0x50, 948 .route_val = BIT(16 + 6), 949 }, { 950 /* i2s2_sdim1 */ 951 .bank_num = 3, 952 .pin = 2, 953 .func = 6, 954 .route_offset = 0x50, 955 .route_val = BIT(16 + 6) | BIT(6), 956 }, { 957 /* card_iom1 */ 958 .bank_num = 2, 959 .pin = 22, 960 .func = 3, 961 .route_offset = 0x50, 962 .route_val = BIT(16 + 7) | BIT(7), 963 }, { 964 /* tsp_d5m1 */ 965 .bank_num = 2, 966 .pin = 16, 967 .func = 3, 968 .route_offset = 0x50, 969 .route_val = BIT(16 + 8) | BIT(8), 970 }, { 971 /* cif_data5m1 */ 972 .bank_num = 2, 973 .pin = 16, 974 .func = 4, 975 .route_offset = 0x50, 976 .route_val = BIT(16 + 9) | BIT(9), 977 }, 978 }; 979 980 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 981 { 982 /* uart2dbga_rx */ 983 .bank_num = 4, 984 .pin = 8, 985 .func = 2, 986 .route_offset = 0xe21c, 987 .route_val = BIT(16 + 10) | BIT(16 + 11), 988 }, { 989 /* uart2dbgb_rx */ 990 .bank_num = 4, 991 .pin = 16, 992 .func = 2, 993 .route_offset = 0xe21c, 994 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 995 }, { 996 /* uart2dbgc_rx */ 997 .bank_num = 4, 998 .pin = 19, 999 .func = 1, 1000 .route_offset = 0xe21c, 1001 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1002 }, { 1003 /* pcie_clkreqn */ 1004 .bank_num = 2, 1005 .pin = 26, 1006 .func = 2, 1007 .route_offset = 0xe21c, 1008 .route_val = BIT(16 + 14), 1009 }, { 1010 /* pcie_clkreqnb */ 1011 .bank_num = 4, 1012 .pin = 24, 1013 .func = 1, 1014 .route_offset = 0xe21c, 1015 .route_val = BIT(16 + 14) | BIT(14), 1016 }, 1017 }; 1018 1019 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1020 int mux, u32 *reg, u32 *value) 1021 { 1022 struct rockchip_pinctrl_priv *priv = bank->priv; 1023 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1024 struct rockchip_mux_route_data *data; 1025 int i; 1026 1027 for (i = 0; i < ctrl->niomux_routes; i++) { 1028 data = &ctrl->iomux_routes[i]; 1029 if ((data->bank_num == bank->bank_num) && 1030 (data->pin == pin) && (data->func == mux)) 1031 break; 1032 } 1033 1034 if (i >= ctrl->niomux_routes) 1035 return false; 1036 1037 *reg = data->route_offset; 1038 *value = data->route_val; 1039 1040 return true; 1041 } 1042 1043 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1044 { 1045 struct rockchip_pinctrl_priv *priv = bank->priv; 1046 int iomux_num = (pin / 8); 1047 struct regmap *regmap; 1048 unsigned int val; 1049 int reg, ret, mask, mux_type; 1050 u8 bit; 1051 1052 if (iomux_num > 3) 1053 return -EINVAL; 1054 1055 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1056 debug("pin %d is unrouted\n", pin); 1057 return -EINVAL; 1058 } 1059 1060 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1061 return RK_FUNC_GPIO; 1062 1063 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1064 ? priv->regmap_pmu : priv->regmap_base; 1065 1066 /* get basic quadrupel of mux registers and the correct reg inside */ 1067 mux_type = bank->iomux[iomux_num].type; 1068 reg = bank->iomux[iomux_num].offset; 1069 if (mux_type & IOMUX_WIDTH_4BIT) { 1070 if ((pin % 8) >= 4) 1071 reg += 0x4; 1072 bit = (pin % 4) * 4; 1073 mask = 0xf; 1074 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1075 if ((pin % 8) >= 5) 1076 reg += 0x4; 1077 bit = (pin % 8 % 5) * 3; 1078 mask = 0x7; 1079 } else { 1080 bit = (pin % 8) * 2; 1081 mask = 0x3; 1082 } 1083 1084 if (bank->recalced_mask & BIT(pin)) 1085 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1086 1087 ret = regmap_read(regmap, reg, &val); 1088 if (ret) 1089 return ret; 1090 1091 return ((val >> bit) & mask); 1092 } 1093 1094 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1095 int index) 1096 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1097 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1098 1099 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1100 } 1101 1102 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1103 int pin, int mux) 1104 { 1105 int iomux_num = (pin / 8); 1106 1107 if (iomux_num > 3) 1108 return -EINVAL; 1109 1110 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1111 debug("pin %d is unrouted\n", pin); 1112 return -EINVAL; 1113 } 1114 1115 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1116 if (mux != IOMUX_GPIO_ONLY) { 1117 debug("pin %d only supports a gpio mux\n", pin); 1118 return -ENOTSUPP; 1119 } 1120 } 1121 1122 return 0; 1123 } 1124 1125 /* 1126 * Set a new mux function for a pin. 1127 * 1128 * The register is divided into the upper and lower 16 bit. When changing 1129 * a value, the previous register value is not read and changed. Instead 1130 * it seems the changed bits are marked in the upper 16 bit, while the 1131 * changed value gets set in the same offset in the lower 16 bit. 1132 * All pin settings seem to be 2 bit wide in both the upper and lower 1133 * parts. 1134 * @bank: pin bank to change 1135 * @pin: pin to change 1136 * @mux: new mux function to set 1137 */ 1138 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1139 { 1140 struct rockchip_pinctrl_priv *priv = bank->priv; 1141 int iomux_num = (pin / 8); 1142 struct regmap *regmap; 1143 int reg, ret, mask, mux_type; 1144 u8 bit; 1145 u32 data, route_reg, route_val; 1146 1147 ret = rockchip_verify_mux(bank, pin, mux); 1148 if (ret < 0) 1149 return ret; 1150 1151 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1152 return 0; 1153 1154 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1155 1156 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1157 ? priv->regmap_pmu : priv->regmap_base; 1158 1159 /* get basic quadrupel of mux registers and the correct reg inside */ 1160 mux_type = bank->iomux[iomux_num].type; 1161 reg = bank->iomux[iomux_num].offset; 1162 if (mux_type & IOMUX_WIDTH_4BIT) { 1163 if ((pin % 8) >= 4) 1164 reg += 0x4; 1165 bit = (pin % 4) * 4; 1166 mask = 0xf; 1167 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1168 if ((pin % 8) >= 5) 1169 reg += 0x4; 1170 bit = (pin % 8 % 5) * 3; 1171 mask = 0x7; 1172 } else { 1173 bit = (pin % 8) * 2; 1174 mask = 0x3; 1175 } 1176 1177 if (bank->recalced_mask & BIT(pin)) 1178 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1179 1180 if (bank->route_mask & BIT(pin)) { 1181 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1182 &route_val)) { 1183 ret = regmap_write(regmap, route_reg, route_val); 1184 if (ret) 1185 return ret; 1186 } 1187 } 1188 1189 if (mux_type & IOMUX_WRITABLE_32BIT) { 1190 regmap_read(regmap, reg, &data); 1191 data &= ~(mask << bit); 1192 } else { 1193 data = (mask << (bit + 16)); 1194 } 1195 1196 data |= (mux & mask) << bit; 1197 ret = regmap_write(regmap, reg, data); 1198 1199 return ret; 1200 } 1201 1202 #define PX30_PULL_PMU_OFFSET 0x10 1203 #define PX30_PULL_GRF_OFFSET 0x60 1204 #define PX30_PULL_BITS_PER_PIN 2 1205 #define PX30_PULL_PINS_PER_REG 8 1206 #define PX30_PULL_BANK_STRIDE 16 1207 1208 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1209 int pin_num, struct regmap **regmap, 1210 int *reg, u8 *bit) 1211 { 1212 struct rockchip_pinctrl_priv *priv = bank->priv; 1213 1214 /* The first 32 pins of the first bank are located in PMU */ 1215 if (bank->bank_num == 0) { 1216 *regmap = priv->regmap_pmu; 1217 *reg = PX30_PULL_PMU_OFFSET; 1218 } else { 1219 *regmap = priv->regmap_base; 1220 *reg = PX30_PULL_GRF_OFFSET; 1221 1222 /* correct the offset, as we're starting with the 2nd bank */ 1223 *reg -= 0x10; 1224 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1225 } 1226 1227 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1228 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1229 *bit *= PX30_PULL_BITS_PER_PIN; 1230 } 1231 1232 #define PX30_DRV_PMU_OFFSET 0x20 1233 #define PX30_DRV_GRF_OFFSET 0xf0 1234 #define PX30_DRV_BITS_PER_PIN 2 1235 #define PX30_DRV_PINS_PER_REG 8 1236 #define PX30_DRV_BANK_STRIDE 16 1237 1238 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1239 int pin_num, struct regmap **regmap, 1240 int *reg, u8 *bit) 1241 { 1242 struct rockchip_pinctrl_priv *priv = bank->priv; 1243 1244 /* The first 32 pins of the first bank are located in PMU */ 1245 if (bank->bank_num == 0) { 1246 *regmap = priv->regmap_pmu; 1247 *reg = PX30_DRV_PMU_OFFSET; 1248 } else { 1249 *regmap = priv->regmap_base; 1250 *reg = PX30_DRV_GRF_OFFSET; 1251 1252 /* correct the offset, as we're starting with the 2nd bank */ 1253 *reg -= 0x10; 1254 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1255 } 1256 1257 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1258 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1259 *bit *= PX30_DRV_BITS_PER_PIN; 1260 } 1261 1262 #define PX30_SCHMITT_PMU_OFFSET 0x38 1263 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1264 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1265 #define PX30_SCHMITT_BANK_STRIDE 16 1266 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1267 1268 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1269 int pin_num, 1270 struct regmap **regmap, 1271 int *reg, u8 *bit) 1272 { 1273 struct rockchip_pinctrl_priv *priv = bank->priv; 1274 int pins_per_reg; 1275 1276 if (bank->bank_num == 0) { 1277 *regmap = priv->regmap_pmu; 1278 *reg = PX30_SCHMITT_PMU_OFFSET; 1279 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1280 } else { 1281 *regmap = priv->regmap_base; 1282 *reg = PX30_SCHMITT_GRF_OFFSET; 1283 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1284 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1285 } 1286 *reg += ((pin_num / pins_per_reg) * 4); 1287 *bit = pin_num % pins_per_reg; 1288 1289 return 0; 1290 } 1291 1292 #define RV1108_PULL_PMU_OFFSET 0x10 1293 #define RV1108_PULL_OFFSET 0x110 1294 #define RV1108_PULL_PINS_PER_REG 8 1295 #define RV1108_PULL_BITS_PER_PIN 2 1296 #define RV1108_PULL_BANK_STRIDE 16 1297 1298 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1299 int pin_num, struct regmap **regmap, 1300 int *reg, u8 *bit) 1301 { 1302 struct rockchip_pinctrl_priv *priv = bank->priv; 1303 1304 /* The first 24 pins of the first bank are located in PMU */ 1305 if (bank->bank_num == 0) { 1306 *regmap = priv->regmap_pmu; 1307 *reg = RV1108_PULL_PMU_OFFSET; 1308 } else { 1309 *reg = RV1108_PULL_OFFSET; 1310 *regmap = priv->regmap_base; 1311 /* correct the offset, as we're starting with the 2nd bank */ 1312 *reg -= 0x10; 1313 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1314 } 1315 1316 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1317 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1318 *bit *= RV1108_PULL_BITS_PER_PIN; 1319 } 1320 1321 #define RV1108_DRV_PMU_OFFSET 0x20 1322 #define RV1108_DRV_GRF_OFFSET 0x210 1323 #define RV1108_DRV_BITS_PER_PIN 2 1324 #define RV1108_DRV_PINS_PER_REG 8 1325 #define RV1108_DRV_BANK_STRIDE 16 1326 1327 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1328 int pin_num, struct regmap **regmap, 1329 int *reg, u8 *bit) 1330 { 1331 struct rockchip_pinctrl_priv *priv = bank->priv; 1332 1333 /* The first 24 pins of the first bank are located in PMU */ 1334 if (bank->bank_num == 0) { 1335 *regmap = priv->regmap_pmu; 1336 *reg = RV1108_DRV_PMU_OFFSET; 1337 } else { 1338 *regmap = priv->regmap_base; 1339 *reg = RV1108_DRV_GRF_OFFSET; 1340 1341 /* correct the offset, as we're starting with the 2nd bank */ 1342 *reg -= 0x10; 1343 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1344 } 1345 1346 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1347 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1348 *bit *= RV1108_DRV_BITS_PER_PIN; 1349 } 1350 1351 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1352 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1353 #define RV1108_SCHMITT_BANK_STRIDE 8 1354 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1355 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1356 1357 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1358 int pin_num, 1359 struct regmap **regmap, 1360 int *reg, u8 *bit) 1361 { 1362 struct rockchip_pinctrl_priv *priv = bank->priv; 1363 int pins_per_reg; 1364 1365 if (bank->bank_num == 0) { 1366 *regmap = priv->regmap_pmu; 1367 *reg = RV1108_SCHMITT_PMU_OFFSET; 1368 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1369 } else { 1370 *regmap = priv->regmap_base; 1371 *reg = RV1108_SCHMITT_GRF_OFFSET; 1372 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1373 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1374 } 1375 *reg += ((pin_num / pins_per_reg) * 4); 1376 *bit = pin_num % pins_per_reg; 1377 1378 return 0; 1379 } 1380 1381 #define RK1808_PULL_PMU_OFFSET 0x10 1382 #define RK1808_PULL_GRF_OFFSET 0x80 1383 #define RK1808_PULL_PINS_PER_REG 8 1384 #define RK1808_PULL_BITS_PER_PIN 2 1385 #define RK1808_PULL_BANK_STRIDE 16 1386 1387 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1388 int pin_num, 1389 struct regmap **regmap, 1390 int *reg, u8 *bit) 1391 { 1392 struct rockchip_pinctrl_priv *priv = bank->priv; 1393 1394 if (bank->bank_num == 0) { 1395 *regmap = priv->regmap_pmu; 1396 *reg = RK1808_PULL_PMU_OFFSET; 1397 } else { 1398 *reg = RK1808_PULL_GRF_OFFSET; 1399 *regmap = priv->regmap_base; 1400 } 1401 1402 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4); 1403 *bit = (pin_num % RK1808_PULL_PINS_PER_REG); 1404 *bit *= RK1808_PULL_BITS_PER_PIN; 1405 } 1406 1407 #define RK1808_DRV_PMU_OFFSET 0x20 1408 #define RK1808_DRV_GRF_OFFSET 0x140 1409 #define RK1808_DRV_BITS_PER_PIN 2 1410 #define RK1808_DRV_PINS_PER_REG 8 1411 #define RK1808_DRV_BANK_STRIDE 16 1412 1413 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1414 int pin_num, 1415 struct regmap **regmap, 1416 int *reg, u8 *bit) 1417 { 1418 struct rockchip_pinctrl_priv *priv = bank->priv; 1419 1420 if (bank->bank_num == 0) { 1421 *regmap = priv->regmap_pmu; 1422 *reg = RK1808_DRV_PMU_OFFSET; 1423 } else { 1424 *regmap = priv->regmap_base; 1425 *reg = RK1808_DRV_GRF_OFFSET; 1426 } 1427 1428 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4); 1429 *bit = pin_num % RK1808_DRV_PINS_PER_REG; 1430 *bit *= RK1808_DRV_BITS_PER_PIN; 1431 } 1432 1433 #define RK1808_SCHMITT_PMU_OFFSET 0x0040 1434 #define RK1808_SCHMITT_GRF_OFFSET 0x0100 1435 #define RK1808_SCHMITT_BANK_STRIDE 16 1436 #define RK1808_SCHMITT_PINS_PER_REG 8 1437 1438 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1439 int pin_num, 1440 struct regmap **regmap, 1441 int *reg, u8 *bit) 1442 { 1443 struct rockchip_pinctrl_priv *priv = bank->priv; 1444 1445 if (bank->bank_num == 0) { 1446 *regmap = priv->regmap_pmu; 1447 *reg = RK1808_SCHMITT_PMU_OFFSET; 1448 } else { 1449 *regmap = priv->regmap_base; 1450 *reg = RK1808_SCHMITT_GRF_OFFSET; 1451 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE; 1452 } 1453 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4); 1454 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG; 1455 1456 return 0; 1457 } 1458 1459 #define RK2928_PULL_OFFSET 0x118 1460 #define RK2928_PULL_PINS_PER_REG 16 1461 #define RK2928_PULL_BANK_STRIDE 8 1462 1463 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1464 int pin_num, struct regmap **regmap, 1465 int *reg, u8 *bit) 1466 { 1467 struct rockchip_pinctrl_priv *priv = bank->priv; 1468 1469 *regmap = priv->regmap_base; 1470 *reg = RK2928_PULL_OFFSET; 1471 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1472 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1473 1474 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1475 }; 1476 1477 #define RK3128_PULL_OFFSET 0x118 1478 1479 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1480 int pin_num, struct regmap **regmap, 1481 int *reg, u8 *bit) 1482 { 1483 struct rockchip_pinctrl_priv *priv = bank->priv; 1484 1485 *regmap = priv->regmap_base; 1486 *reg = RK3128_PULL_OFFSET; 1487 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1488 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1489 1490 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1491 } 1492 1493 #define RK3188_PULL_OFFSET 0x164 1494 #define RK3188_PULL_BITS_PER_PIN 2 1495 #define RK3188_PULL_PINS_PER_REG 8 1496 #define RK3188_PULL_BANK_STRIDE 16 1497 #define RK3188_PULL_PMU_OFFSET 0x64 1498 1499 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1500 int pin_num, struct regmap **regmap, 1501 int *reg, u8 *bit) 1502 { 1503 struct rockchip_pinctrl_priv *priv = bank->priv; 1504 1505 /* The first 12 pins of the first bank are located elsewhere */ 1506 if (bank->bank_num == 0 && pin_num < 12) { 1507 *regmap = priv->regmap_pmu; 1508 *reg = RK3188_PULL_PMU_OFFSET; 1509 1510 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1511 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1512 *bit *= RK3188_PULL_BITS_PER_PIN; 1513 } else { 1514 *regmap = priv->regmap_base; 1515 *reg = RK3188_PULL_OFFSET; 1516 1517 /* correct the offset, as it is the 2nd pull register */ 1518 *reg -= 4; 1519 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1520 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1521 1522 /* 1523 * The bits in these registers have an inverse ordering 1524 * with the lowest pin being in bits 15:14 and the highest 1525 * pin in bits 1:0 1526 */ 1527 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1528 *bit *= RK3188_PULL_BITS_PER_PIN; 1529 } 1530 } 1531 1532 #define RK3288_PULL_OFFSET 0x140 1533 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1534 int pin_num, struct regmap **regmap, 1535 int *reg, u8 *bit) 1536 { 1537 struct rockchip_pinctrl_priv *priv = bank->priv; 1538 1539 /* The first 24 pins of the first bank are located in PMU */ 1540 if (bank->bank_num == 0) { 1541 *regmap = priv->regmap_pmu; 1542 *reg = RK3188_PULL_PMU_OFFSET; 1543 1544 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1545 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1546 *bit *= RK3188_PULL_BITS_PER_PIN; 1547 } else { 1548 *regmap = priv->regmap_base; 1549 *reg = RK3288_PULL_OFFSET; 1550 1551 /* correct the offset, as we're starting with the 2nd bank */ 1552 *reg -= 0x10; 1553 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1554 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1555 1556 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1557 *bit *= RK3188_PULL_BITS_PER_PIN; 1558 } 1559 } 1560 1561 #define RK3288_DRV_PMU_OFFSET 0x70 1562 #define RK3288_DRV_GRF_OFFSET 0x1c0 1563 #define RK3288_DRV_BITS_PER_PIN 2 1564 #define RK3288_DRV_PINS_PER_REG 8 1565 #define RK3288_DRV_BANK_STRIDE 16 1566 1567 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1568 int pin_num, struct regmap **regmap, 1569 int *reg, u8 *bit) 1570 { 1571 struct rockchip_pinctrl_priv *priv = bank->priv; 1572 1573 /* The first 24 pins of the first bank are located in PMU */ 1574 if (bank->bank_num == 0) { 1575 *regmap = priv->regmap_pmu; 1576 *reg = RK3288_DRV_PMU_OFFSET; 1577 1578 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1579 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1580 *bit *= RK3288_DRV_BITS_PER_PIN; 1581 } else { 1582 *regmap = priv->regmap_base; 1583 *reg = RK3288_DRV_GRF_OFFSET; 1584 1585 /* correct the offset, as we're starting with the 2nd bank */ 1586 *reg -= 0x10; 1587 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1588 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1589 1590 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1591 *bit *= RK3288_DRV_BITS_PER_PIN; 1592 } 1593 } 1594 1595 #define RK3228_PULL_OFFSET 0x100 1596 1597 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1598 int pin_num, struct regmap **regmap, 1599 int *reg, u8 *bit) 1600 { 1601 struct rockchip_pinctrl_priv *priv = bank->priv; 1602 1603 *regmap = priv->regmap_base; 1604 *reg = RK3228_PULL_OFFSET; 1605 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1606 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1607 1608 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1609 *bit *= RK3188_PULL_BITS_PER_PIN; 1610 } 1611 1612 #define RK3228_DRV_GRF_OFFSET 0x200 1613 1614 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1615 int pin_num, struct regmap **regmap, 1616 int *reg, u8 *bit) 1617 { 1618 struct rockchip_pinctrl_priv *priv = bank->priv; 1619 1620 *regmap = priv->regmap_base; 1621 *reg = RK3228_DRV_GRF_OFFSET; 1622 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1623 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1624 1625 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1626 *bit *= RK3288_DRV_BITS_PER_PIN; 1627 } 1628 1629 #define RK3308_PULL_OFFSET 0xa0 1630 1631 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1632 int pin_num, struct regmap **regmap, 1633 int *reg, u8 *bit) 1634 { 1635 struct rockchip_pinctrl_priv *priv = bank->priv; 1636 1637 *regmap = priv->regmap_base; 1638 *reg = RK3308_PULL_OFFSET; 1639 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1640 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1641 1642 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1643 *bit *= RK3188_PULL_BITS_PER_PIN; 1644 } 1645 1646 #define RK3308_DRV_GRF_OFFSET 0x100 1647 1648 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1649 int pin_num, struct regmap **regmap, 1650 int *reg, u8 *bit) 1651 { 1652 struct rockchip_pinctrl_priv *priv = bank->priv; 1653 1654 *regmap = priv->regmap_base; 1655 *reg = RK3308_DRV_GRF_OFFSET; 1656 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1657 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1658 1659 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1660 *bit *= RK3288_DRV_BITS_PER_PIN; 1661 } 1662 1663 #define RK3308_SCHMITT_PINS_PER_REG 8 1664 #define RK3308_SCHMITT_BANK_STRIDE 16 1665 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1666 1667 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1668 int pin_num, 1669 struct regmap **regmap, 1670 int *reg, u8 *bit) 1671 { 1672 struct rockchip_pinctrl_priv *priv = bank->priv; 1673 1674 *regmap = priv->regmap_base; 1675 *reg = RK3308_SCHMITT_GRF_OFFSET; 1676 1677 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1678 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1679 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1680 1681 return 0; 1682 } 1683 1684 #define RK3368_PULL_GRF_OFFSET 0x100 1685 #define RK3368_PULL_PMU_OFFSET 0x10 1686 1687 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1688 int pin_num, struct regmap **regmap, 1689 int *reg, u8 *bit) 1690 { 1691 struct rockchip_pinctrl_priv *priv = bank->priv; 1692 1693 /* The first 32 pins of the first bank are located in PMU */ 1694 if (bank->bank_num == 0) { 1695 *regmap = priv->regmap_pmu; 1696 *reg = RK3368_PULL_PMU_OFFSET; 1697 1698 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1699 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1700 *bit *= RK3188_PULL_BITS_PER_PIN; 1701 } else { 1702 *regmap = priv->regmap_base; 1703 *reg = RK3368_PULL_GRF_OFFSET; 1704 1705 /* correct the offset, as we're starting with the 2nd bank */ 1706 *reg -= 0x10; 1707 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1708 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1709 1710 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1711 *bit *= RK3188_PULL_BITS_PER_PIN; 1712 } 1713 } 1714 1715 #define RK3368_DRV_PMU_OFFSET 0x20 1716 #define RK3368_DRV_GRF_OFFSET 0x200 1717 1718 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1719 int pin_num, struct regmap **regmap, 1720 int *reg, u8 *bit) 1721 { 1722 struct rockchip_pinctrl_priv *priv = bank->priv; 1723 1724 /* The first 32 pins of the first bank are located in PMU */ 1725 if (bank->bank_num == 0) { 1726 *regmap = priv->regmap_pmu; 1727 *reg = RK3368_DRV_PMU_OFFSET; 1728 1729 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1730 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1731 *bit *= RK3288_DRV_BITS_PER_PIN; 1732 } else { 1733 *regmap = priv->regmap_base; 1734 *reg = RK3368_DRV_GRF_OFFSET; 1735 1736 /* correct the offset, as we're starting with the 2nd bank */ 1737 *reg -= 0x10; 1738 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1739 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1740 1741 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1742 *bit *= RK3288_DRV_BITS_PER_PIN; 1743 } 1744 } 1745 1746 #define RK3399_PULL_GRF_OFFSET 0xe040 1747 #define RK3399_PULL_PMU_OFFSET 0x40 1748 #define RK3399_DRV_3BITS_PER_PIN 3 1749 1750 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1751 int pin_num, struct regmap **regmap, 1752 int *reg, u8 *bit) 1753 { 1754 struct rockchip_pinctrl_priv *priv = bank->priv; 1755 1756 /* The bank0:16 and bank1:32 pins are located in PMU */ 1757 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1758 *regmap = priv->regmap_pmu; 1759 *reg = RK3399_PULL_PMU_OFFSET; 1760 1761 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1762 1763 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1764 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1765 *bit *= RK3188_PULL_BITS_PER_PIN; 1766 } else { 1767 *regmap = priv->regmap_base; 1768 *reg = RK3399_PULL_GRF_OFFSET; 1769 1770 /* correct the offset, as we're starting with the 3rd bank */ 1771 *reg -= 0x20; 1772 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1773 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1774 1775 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1776 *bit *= RK3188_PULL_BITS_PER_PIN; 1777 } 1778 } 1779 1780 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1781 int pin_num, struct regmap **regmap, 1782 int *reg, u8 *bit) 1783 { 1784 struct rockchip_pinctrl_priv *priv = bank->priv; 1785 int drv_num = (pin_num / 8); 1786 1787 /* The bank0:16 and bank1:32 pins are located in PMU */ 1788 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1789 *regmap = priv->regmap_pmu; 1790 else 1791 *regmap = priv->regmap_base; 1792 1793 *reg = bank->drv[drv_num].offset; 1794 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1795 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1796 *bit = (pin_num % 8) * 3; 1797 else 1798 *bit = (pin_num % 8) * 2; 1799 } 1800 1801 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1802 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1803 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1804 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1805 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1806 { 4, 7, 10, 13, 16, 19, 22, 26 } 1807 }; 1808 1809 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1810 int pin_num, int strength) 1811 { 1812 struct rockchip_pinctrl_priv *priv = bank->priv; 1813 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1814 struct regmap *regmap; 1815 int reg, ret, i; 1816 u32 data, rmask_bits, temp; 1817 u8 bit; 1818 int drv_type = bank->drv[pin_num / 8].drv_type & DRV_TYPE_IO_MASK; 1819 1820 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 1821 pin_num, strength); 1822 1823 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1824 1825 ret = -EINVAL; 1826 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1827 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1828 ret = i; 1829 break; 1830 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1831 ret = rockchip_perpin_drv_list[drv_type][i]; 1832 break; 1833 } 1834 } 1835 1836 if (ret < 0) { 1837 debug("unsupported driver strength %d\n", strength); 1838 return ret; 1839 } 1840 1841 switch (drv_type) { 1842 case DRV_TYPE_IO_1V8_3V0_AUTO: 1843 case DRV_TYPE_IO_3V3_ONLY: 1844 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1845 switch (bit) { 1846 case 0 ... 12: 1847 /* regular case, nothing to do */ 1848 break; 1849 case 15: 1850 /* 1851 * drive-strength offset is special, as it is spread 1852 * over 2 registers, the bit data[15] contains bit 0 1853 * of the value while temp[1:0] contains bits 2 and 1 1854 */ 1855 data = (ret & 0x1) << 15; 1856 temp = (ret >> 0x1) & 0x3; 1857 1858 data |= BIT(31); 1859 ret = regmap_write(regmap, reg, data); 1860 if (ret) 1861 return ret; 1862 1863 temp |= (0x3 << 16); 1864 reg += 0x4; 1865 ret = regmap_write(regmap, reg, temp); 1866 1867 return ret; 1868 case 18 ... 21: 1869 /* setting fully enclosed in the second register */ 1870 reg += 4; 1871 bit -= 16; 1872 break; 1873 default: 1874 debug("unsupported bit: %d for pinctrl drive type: %d\n", 1875 bit, drv_type); 1876 return -EINVAL; 1877 } 1878 break; 1879 case DRV_TYPE_IO_DEFAULT: 1880 case DRV_TYPE_IO_1V8_OR_3V0: 1881 case DRV_TYPE_IO_1V8_ONLY: 1882 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1883 break; 1884 default: 1885 debug("unsupported pinctrl drive type: %d\n", 1886 drv_type); 1887 return -EINVAL; 1888 } 1889 1890 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 1891 regmap_read(regmap, reg, &data); 1892 data &= ~(((1 << rmask_bits) - 1) << bit); 1893 } else { 1894 /* enable the write to the equivalent lower bits */ 1895 data = ((1 << rmask_bits) - 1) << (bit + 16); 1896 } 1897 1898 data |= (ret << bit); 1899 ret = regmap_write(regmap, reg, data); 1900 return ret; 1901 } 1902 1903 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1904 { 1905 PIN_CONFIG_BIAS_DISABLE, 1906 PIN_CONFIG_BIAS_PULL_UP, 1907 PIN_CONFIG_BIAS_PULL_DOWN, 1908 PIN_CONFIG_BIAS_BUS_HOLD 1909 }, 1910 { 1911 PIN_CONFIG_BIAS_DISABLE, 1912 PIN_CONFIG_BIAS_PULL_DOWN, 1913 PIN_CONFIG_BIAS_DISABLE, 1914 PIN_CONFIG_BIAS_PULL_UP 1915 }, 1916 }; 1917 1918 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1919 int pin_num, int pull) 1920 { 1921 struct rockchip_pinctrl_priv *priv = bank->priv; 1922 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1923 struct regmap *regmap; 1924 int reg, ret, i, pull_type; 1925 u8 bit; 1926 u32 data; 1927 1928 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 1929 pin_num, pull); 1930 1931 /* rk3066b does support any pulls */ 1932 if (ctrl->type == RK3066B) 1933 return pull ? -EINVAL : 0; 1934 1935 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1936 1937 switch (ctrl->type) { 1938 case RK2928: 1939 case RK3128: 1940 data = BIT(bit + 16); 1941 if (pull == PIN_CONFIG_BIAS_DISABLE) 1942 data |= BIT(bit); 1943 ret = regmap_write(regmap, reg, data); 1944 break; 1945 case PX30: 1946 case RV1108: 1947 case RK1808: 1948 case RK3188: 1949 case RK3288: 1950 case RK3308: 1951 case RK3368: 1952 case RK3399: 1953 pull_type = bank->pull_type[pin_num / 8] & PULL_TYPE_IO_MASK; 1954 ret = -EINVAL; 1955 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 1956 i++) { 1957 if (rockchip_pull_list[pull_type][i] == pull) { 1958 ret = i; 1959 break; 1960 } 1961 } 1962 1963 if (ret < 0) { 1964 debug("unsupported pull setting %d\n", pull); 1965 return ret; 1966 } 1967 1968 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 1969 regmap_read(regmap, reg, &data); 1970 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); 1971 } else { 1972 /* enable the write to the equivalent lower bits */ 1973 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1974 } 1975 1976 data |= (ret << bit); 1977 ret = regmap_write(regmap, reg, data); 1978 break; 1979 default: 1980 debug("unsupported pinctrl type\n"); 1981 return -EINVAL; 1982 } 1983 1984 return ret; 1985 } 1986 1987 #define RK3328_SCHMITT_BITS_PER_PIN 1 1988 #define RK3328_SCHMITT_PINS_PER_REG 16 1989 #define RK3328_SCHMITT_BANK_STRIDE 8 1990 #define RK3328_SCHMITT_GRF_OFFSET 0x380 1991 1992 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1993 int pin_num, 1994 struct regmap **regmap, 1995 int *reg, u8 *bit) 1996 { 1997 struct rockchip_pinctrl_priv *priv = bank->priv; 1998 1999 *regmap = priv->regmap_base; 2000 *reg = RK3328_SCHMITT_GRF_OFFSET; 2001 2002 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2003 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2004 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2005 2006 return 0; 2007 } 2008 2009 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2010 int pin_num, int enable) 2011 { 2012 struct rockchip_pinctrl_priv *priv = bank->priv; 2013 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2014 struct regmap *regmap; 2015 int reg, ret; 2016 u8 bit; 2017 u32 data; 2018 2019 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 2020 pin_num, enable); 2021 2022 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2023 if (ret) 2024 return ret; 2025 2026 /* enable the write to the equivalent lower bits */ 2027 data = BIT(bit + 16) | (enable << bit); 2028 2029 return regmap_write(regmap, reg, data); 2030 } 2031 2032 /* 2033 * Pinconf_ops handling 2034 */ 2035 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2036 unsigned int pull) 2037 { 2038 switch (ctrl->type) { 2039 case RK2928: 2040 case RK3128: 2041 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2042 pull == PIN_CONFIG_BIAS_DISABLE); 2043 case RK3066B: 2044 return pull ? false : true; 2045 case PX30: 2046 case RV1108: 2047 case RK1808: 2048 case RK3188: 2049 case RK3288: 2050 case RK3308: 2051 case RK3368: 2052 case RK3399: 2053 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2054 } 2055 2056 return false; 2057 } 2058 2059 /* set the pin config settings for a specified pin */ 2060 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 2061 u32 pin, u32 param, u32 arg) 2062 { 2063 struct rockchip_pinctrl_priv *priv = bank->priv; 2064 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2065 int rc; 2066 2067 switch (param) { 2068 case PIN_CONFIG_BIAS_DISABLE: 2069 rc = rockchip_set_pull(bank, pin, param); 2070 if (rc) 2071 return rc; 2072 break; 2073 2074 case PIN_CONFIG_BIAS_PULL_UP: 2075 case PIN_CONFIG_BIAS_PULL_DOWN: 2076 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2077 case PIN_CONFIG_BIAS_BUS_HOLD: 2078 if (!rockchip_pinconf_pull_valid(ctrl, param)) 2079 return -ENOTSUPP; 2080 2081 if (!arg) 2082 return -EINVAL; 2083 2084 rc = rockchip_set_pull(bank, pin, param); 2085 if (rc) 2086 return rc; 2087 break; 2088 2089 case PIN_CONFIG_DRIVE_STRENGTH: 2090 if (!ctrl->drv_calc_reg) 2091 return -ENOTSUPP; 2092 2093 rc = rockchip_set_drive_perpin(bank, pin, arg); 2094 if (rc < 0) 2095 return rc; 2096 break; 2097 2098 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2099 if (!ctrl->schmitt_calc_reg) 2100 return -ENOTSUPP; 2101 2102 rc = rockchip_set_schmitt(bank, pin, arg); 2103 if (rc < 0) 2104 return rc; 2105 break; 2106 2107 default: 2108 break; 2109 } 2110 2111 return 0; 2112 } 2113 2114 static const struct pinconf_param rockchip_conf_params[] = { 2115 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 2116 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 2117 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 2118 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 2119 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 2120 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 2121 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 2122 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 2123 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 2124 }; 2125 2126 static int rockchip_pinconf_prop_name_to_param(const char *property, 2127 u32 *default_value) 2128 { 2129 const struct pinconf_param *p, *end; 2130 2131 p = rockchip_conf_params; 2132 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 2133 2134 /* See if this pctldev supports this parameter */ 2135 for (; p < end; p++) { 2136 if (!strcmp(property, p->property)) { 2137 *default_value = p->default_value; 2138 return p->param; 2139 } 2140 } 2141 2142 *default_value = 0; 2143 return -EPERM; 2144 } 2145 2146 static int rockchip_pinctrl_set_state(struct udevice *dev, 2147 struct udevice *config) 2148 { 2149 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2150 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2151 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 2152 u32 bank, pin, mux, conf, arg, default_val; 2153 int ret, count, i; 2154 const char *prop_name; 2155 const void *value; 2156 int prop_len, param; 2157 const u32 *data; 2158 ofnode node; 2159 #ifdef CONFIG_OF_LIVE 2160 const struct device_node *np; 2161 struct property *pp; 2162 #else 2163 int property_offset, pcfg_node; 2164 const void *blob = gd->fdt_blob; 2165 #endif 2166 data = dev_read_prop(config, "rockchip,pins", &count); 2167 if (count < 0) { 2168 debug("%s: bad array size %d\n", __func__, count); 2169 return -EINVAL; 2170 } 2171 2172 count /= sizeof(u32); 2173 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2174 debug("%s: unsupported pins array count %d\n", 2175 __func__, count); 2176 return -EINVAL; 2177 } 2178 2179 for (i = 0; i < count; i++) 2180 cells[i] = fdt32_to_cpu(data[i]); 2181 2182 for (i = 0; i < (count >> 2); i++) { 2183 bank = cells[4 * i + 0]; 2184 pin = cells[4 * i + 1]; 2185 mux = cells[4 * i + 2]; 2186 conf = cells[4 * i + 3]; 2187 2188 ret = rockchip_verify_config(dev, bank, pin); 2189 if (ret) 2190 return ret; 2191 2192 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2193 if (ret) 2194 return ret; 2195 2196 node = ofnode_get_by_phandle(conf); 2197 if (!ofnode_valid(node)) 2198 return -ENODEV; 2199 #ifdef CONFIG_OF_LIVE 2200 np = ofnode_to_np(node); 2201 for (pp = np->properties; pp; pp = pp->next) { 2202 prop_name = pp->name; 2203 prop_len = pp->length; 2204 value = pp->value; 2205 #else 2206 pcfg_node = ofnode_to_offset(node); 2207 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2208 value = fdt_getprop_by_offset(blob, property_offset, 2209 &prop_name, &prop_len); 2210 if (!value) 2211 return -ENOENT; 2212 #endif 2213 param = rockchip_pinconf_prop_name_to_param(prop_name, 2214 &default_val); 2215 if (param < 0) 2216 break; 2217 2218 if (prop_len >= sizeof(fdt32_t)) 2219 arg = fdt32_to_cpu(*(fdt32_t *)value); 2220 else 2221 arg = default_val; 2222 2223 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2224 param, arg); 2225 if (ret) { 2226 debug("%s: rockchip_pinconf_set fail: %d\n", 2227 __func__, ret); 2228 return ret; 2229 } 2230 } 2231 } 2232 2233 return 0; 2234 } 2235 2236 static struct pinctrl_ops rockchip_pinctrl_ops = { 2237 .set_state = rockchip_pinctrl_set_state, 2238 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2239 }; 2240 2241 /* retrieve the soc specific data */ 2242 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 2243 { 2244 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2245 struct rockchip_pin_ctrl *ctrl = 2246 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 2247 struct rockchip_pin_bank *bank; 2248 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2249 2250 grf_offs = ctrl->grf_mux_offset; 2251 pmu_offs = ctrl->pmu_mux_offset; 2252 drv_pmu_offs = ctrl->pmu_drv_offset; 2253 drv_grf_offs = ctrl->grf_drv_offset; 2254 bank = ctrl->pin_banks; 2255 2256 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2257 int bank_pins = 0; 2258 2259 bank->priv = priv; 2260 bank->pin_base = ctrl->nr_pins; 2261 ctrl->nr_pins += bank->nr_pins; 2262 2263 /* calculate iomux and drv offsets */ 2264 for (j = 0; j < 4; j++) { 2265 struct rockchip_iomux *iom = &bank->iomux[j]; 2266 struct rockchip_drv *drv = &bank->drv[j]; 2267 int inc; 2268 2269 if (bank_pins >= bank->nr_pins) 2270 break; 2271 2272 /* preset iomux offset value, set new start value */ 2273 if (iom->offset >= 0) { 2274 if (iom->type & IOMUX_SOURCE_PMU) 2275 pmu_offs = iom->offset; 2276 else 2277 grf_offs = iom->offset; 2278 } else { /* set current iomux offset */ 2279 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2280 pmu_offs : grf_offs; 2281 } 2282 2283 /* preset drv offset value, set new start value */ 2284 if (drv->offset >= 0) { 2285 if (iom->type & IOMUX_SOURCE_PMU) 2286 drv_pmu_offs = drv->offset; 2287 else 2288 drv_grf_offs = drv->offset; 2289 } else { /* set current drv offset */ 2290 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2291 drv_pmu_offs : drv_grf_offs; 2292 } 2293 2294 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2295 i, j, iom->offset, drv->offset); 2296 2297 /* 2298 * Increase offset according to iomux width. 2299 * 4bit iomux'es are spread over two registers. 2300 */ 2301 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2302 IOMUX_WIDTH_3BIT | 2303 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 2304 if (iom->type & IOMUX_SOURCE_PMU) 2305 pmu_offs += inc; 2306 else 2307 grf_offs += inc; 2308 2309 /* 2310 * Increase offset according to drv width. 2311 * 3bit drive-strenth'es are spread over two registers. 2312 */ 2313 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2314 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2315 inc = 8; 2316 else 2317 inc = 4; 2318 2319 if (iom->type & IOMUX_SOURCE_PMU) 2320 drv_pmu_offs += inc; 2321 else 2322 drv_grf_offs += inc; 2323 2324 bank_pins += 8; 2325 } 2326 2327 /* calculate the per-bank recalced_mask */ 2328 for (j = 0; j < ctrl->niomux_recalced; j++) { 2329 int pin = 0; 2330 2331 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2332 pin = ctrl->iomux_recalced[j].pin; 2333 bank->recalced_mask |= BIT(pin); 2334 } 2335 } 2336 2337 /* calculate the per-bank route_mask */ 2338 for (j = 0; j < ctrl->niomux_routes; j++) { 2339 int pin = 0; 2340 2341 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2342 pin = ctrl->iomux_routes[j].pin; 2343 bank->route_mask |= BIT(pin); 2344 } 2345 } 2346 } 2347 2348 return ctrl; 2349 } 2350 2351 static int rockchip_pinctrl_probe(struct udevice *dev) 2352 { 2353 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2354 struct rockchip_pin_ctrl *ctrl; 2355 struct udevice *syscon; 2356 struct regmap *regmap; 2357 int ret = 0; 2358 2359 /* get rockchip grf syscon phandle */ 2360 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2361 &syscon); 2362 if (ret) { 2363 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 2364 return ret; 2365 } 2366 2367 /* get grf-reg base address */ 2368 regmap = syscon_get_regmap(syscon); 2369 if (!regmap) { 2370 debug("unable to find rockchip grf regmap\n"); 2371 return -ENODEV; 2372 } 2373 priv->regmap_base = regmap; 2374 2375 /* option: get pmu-reg base address */ 2376 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 2377 &syscon); 2378 if (!ret) { 2379 /* get pmugrf-reg base address */ 2380 regmap = syscon_get_regmap(syscon); 2381 if (!regmap) { 2382 debug("unable to find rockchip pmu regmap\n"); 2383 return -ENODEV; 2384 } 2385 priv->regmap_pmu = regmap; 2386 } 2387 2388 ctrl = rockchip_pinctrl_get_soc_data(dev); 2389 if (!ctrl) { 2390 debug("driver data not available\n"); 2391 return -EINVAL; 2392 } 2393 2394 priv->ctrl = ctrl; 2395 return 0; 2396 } 2397 2398 static struct rockchip_pin_bank px30_pin_banks[] = { 2399 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2400 IOMUX_SOURCE_PMU, 2401 IOMUX_SOURCE_PMU, 2402 IOMUX_SOURCE_PMU 2403 ), 2404 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2405 IOMUX_WIDTH_4BIT, 2406 IOMUX_WIDTH_4BIT, 2407 IOMUX_WIDTH_4BIT 2408 ), 2409 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2410 IOMUX_WIDTH_4BIT, 2411 IOMUX_WIDTH_4BIT, 2412 IOMUX_WIDTH_4BIT 2413 ), 2414 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2415 IOMUX_WIDTH_4BIT, 2416 IOMUX_WIDTH_4BIT, 2417 IOMUX_WIDTH_4BIT 2418 ), 2419 }; 2420 2421 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2422 .pin_banks = px30_pin_banks, 2423 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2424 .label = "PX30-GPIO", 2425 .type = PX30, 2426 .grf_mux_offset = 0x0, 2427 .pmu_mux_offset = 0x0, 2428 .iomux_routes = px30_mux_route_data, 2429 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2430 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2431 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2432 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2433 }; 2434 2435 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2436 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2437 IOMUX_SOURCE_PMU, 2438 IOMUX_SOURCE_PMU, 2439 IOMUX_SOURCE_PMU), 2440 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2441 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2442 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2443 }; 2444 2445 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2446 .pin_banks = rv1108_pin_banks, 2447 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2448 .label = "RV1108-GPIO", 2449 .type = RV1108, 2450 .grf_mux_offset = 0x10, 2451 .pmu_mux_offset = 0x0, 2452 .iomux_recalced = rv1108_mux_recalced_data, 2453 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2454 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2455 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2456 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2457 }; 2458 2459 static struct rockchip_pin_bank rk1808_pin_banks[] = { 2460 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 2461 IOMUX_SOURCE_PMU, 2462 IOMUX_SOURCE_PMU, 2463 IOMUX_SOURCE_PMU, 2464 IOMUX_SOURCE_PMU), 2465 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 2466 IOMUX_WIDTH_4BIT, 2467 IOMUX_WIDTH_4BIT, 2468 IOMUX_WIDTH_4BIT, 2469 IOMUX_WIDTH_4BIT), 2470 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 2471 IOMUX_WIDTH_4BIT, 2472 IOMUX_WIDTH_4BIT, 2473 IOMUX_WIDTH_4BIT, 2474 IOMUX_WIDTH_4BIT), 2475 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2476 IOMUX_WIDTH_4BIT, 2477 IOMUX_WIDTH_4BIT, 2478 IOMUX_WIDTH_4BIT, 2479 IOMUX_WIDTH_4BIT), 2480 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", 2481 IOMUX_WIDTH_4BIT, 2482 IOMUX_WIDTH_4BIT, 2483 IOMUX_WIDTH_4BIT, 2484 IOMUX_WIDTH_4BIT), 2485 }; 2486 2487 static struct rockchip_pin_ctrl rk1808_pin_ctrl = { 2488 .pin_banks = rk1808_pin_banks, 2489 .nr_banks = ARRAY_SIZE(rk1808_pin_banks), 2490 .label = "RK1808-GPIO", 2491 .type = RK1808, 2492 .iomux_routes = rk1808_mux_route_data, 2493 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data), 2494 .grf_mux_offset = 0x0, 2495 .pmu_mux_offset = 0x0, 2496 .pull_calc_reg = rk1808_calc_pull_reg_and_bit, 2497 .drv_calc_reg = rk1808_calc_drv_reg_and_bit, 2498 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit, 2499 }; 2500 2501 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2502 PIN_BANK(0, 32, "gpio0"), 2503 PIN_BANK(1, 32, "gpio1"), 2504 PIN_BANK(2, 32, "gpio2"), 2505 PIN_BANK(3, 32, "gpio3"), 2506 }; 2507 2508 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2509 .pin_banks = rk2928_pin_banks, 2510 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2511 .label = "RK2928-GPIO", 2512 .type = RK2928, 2513 .grf_mux_offset = 0xa8, 2514 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2515 }; 2516 2517 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2518 PIN_BANK(0, 32, "gpio0"), 2519 PIN_BANK(1, 32, "gpio1"), 2520 PIN_BANK(2, 32, "gpio2"), 2521 }; 2522 2523 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2524 .pin_banks = rk3036_pin_banks, 2525 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2526 .label = "RK3036-GPIO", 2527 .type = RK2928, 2528 .grf_mux_offset = 0xa8, 2529 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2530 }; 2531 2532 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2533 PIN_BANK(0, 32, "gpio0"), 2534 PIN_BANK(1, 32, "gpio1"), 2535 PIN_BANK(2, 32, "gpio2"), 2536 PIN_BANK(3, 32, "gpio3"), 2537 PIN_BANK(4, 32, "gpio4"), 2538 PIN_BANK(6, 16, "gpio6"), 2539 }; 2540 2541 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2542 .pin_banks = rk3066a_pin_banks, 2543 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2544 .label = "RK3066a-GPIO", 2545 .type = RK2928, 2546 .grf_mux_offset = 0xa8, 2547 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2548 }; 2549 2550 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2551 PIN_BANK(0, 32, "gpio0"), 2552 PIN_BANK(1, 32, "gpio1"), 2553 PIN_BANK(2, 32, "gpio2"), 2554 PIN_BANK(3, 32, "gpio3"), 2555 }; 2556 2557 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2558 .pin_banks = rk3066b_pin_banks, 2559 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2560 .label = "RK3066b-GPIO", 2561 .type = RK3066B, 2562 .grf_mux_offset = 0x60, 2563 }; 2564 2565 static struct rockchip_pin_bank rk3128_pin_banks[] = { 2566 PIN_BANK(0, 32, "gpio0"), 2567 PIN_BANK(1, 32, "gpio1"), 2568 PIN_BANK(2, 32, "gpio2"), 2569 PIN_BANK(3, 32, "gpio3"), 2570 }; 2571 2572 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 2573 .pin_banks = rk3128_pin_banks, 2574 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 2575 .label = "RK3128-GPIO", 2576 .type = RK3128, 2577 .grf_mux_offset = 0xa8, 2578 .iomux_recalced = rk3128_mux_recalced_data, 2579 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 2580 .iomux_routes = rk3128_mux_route_data, 2581 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 2582 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 2583 }; 2584 2585 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2586 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2587 PIN_BANK(1, 32, "gpio1"), 2588 PIN_BANK(2, 32, "gpio2"), 2589 PIN_BANK(3, 32, "gpio3"), 2590 }; 2591 2592 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2593 .pin_banks = rk3188_pin_banks, 2594 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2595 .label = "RK3188-GPIO", 2596 .type = RK3188, 2597 .grf_mux_offset = 0x60, 2598 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2599 }; 2600 2601 static struct rockchip_pin_bank rk3228_pin_banks[] = { 2602 PIN_BANK(0, 32, "gpio0"), 2603 PIN_BANK(1, 32, "gpio1"), 2604 PIN_BANK(2, 32, "gpio2"), 2605 PIN_BANK(3, 32, "gpio3"), 2606 }; 2607 2608 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 2609 .pin_banks = rk3228_pin_banks, 2610 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 2611 .label = "RK3228-GPIO", 2612 .type = RK3288, 2613 .grf_mux_offset = 0x0, 2614 .iomux_routes = rk3228_mux_route_data, 2615 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 2616 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2617 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2618 }; 2619 2620 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2621 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 2622 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 2623 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 2624 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 2625 IOMUX_UNROUTED, 2626 DRV_TYPE_WRITABLE_32BIT, 2627 DRV_TYPE_WRITABLE_32BIT, 2628 DRV_TYPE_WRITABLE_32BIT, 2629 0, 2630 PULL_TYPE_WRITABLE_32BIT, 2631 PULL_TYPE_WRITABLE_32BIT, 2632 PULL_TYPE_WRITABLE_32BIT, 2633 0 2634 ), 2635 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2636 IOMUX_UNROUTED, 2637 IOMUX_UNROUTED, 2638 0 2639 ), 2640 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2641 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2642 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2643 IOMUX_WIDTH_4BIT, 2644 0, 2645 0 2646 ), 2647 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2648 0, 2649 0, 2650 IOMUX_UNROUTED 2651 ), 2652 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2653 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2654 0, 2655 IOMUX_WIDTH_4BIT, 2656 IOMUX_UNROUTED 2657 ), 2658 PIN_BANK(8, 16, "gpio8"), 2659 }; 2660 2661 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2662 .pin_banks = rk3288_pin_banks, 2663 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2664 .label = "RK3288-GPIO", 2665 .type = RK3288, 2666 .grf_mux_offset = 0x0, 2667 .pmu_mux_offset = 0x84, 2668 .iomux_routes = rk3288_mux_route_data, 2669 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 2670 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2671 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2672 }; 2673 2674 static struct rockchip_pin_bank rk3308_pin_banks[] = { 2675 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 2676 IOMUX_8WIDTH_2BIT, 2677 IOMUX_8WIDTH_2BIT, 2678 IOMUX_8WIDTH_2BIT), 2679 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 2680 IOMUX_8WIDTH_2BIT, 2681 IOMUX_8WIDTH_2BIT, 2682 IOMUX_8WIDTH_2BIT), 2683 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 2684 IOMUX_8WIDTH_2BIT, 2685 IOMUX_8WIDTH_2BIT, 2686 IOMUX_8WIDTH_2BIT), 2687 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 2688 IOMUX_8WIDTH_2BIT, 2689 IOMUX_8WIDTH_2BIT, 2690 IOMUX_8WIDTH_2BIT), 2691 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 2692 IOMUX_8WIDTH_2BIT, 2693 IOMUX_8WIDTH_2BIT, 2694 IOMUX_8WIDTH_2BIT), 2695 }; 2696 2697 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 2698 .pin_banks = rk3308_pin_banks, 2699 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 2700 .label = "RK3308-GPIO", 2701 .type = RK3308, 2702 .grf_mux_offset = 0x0, 2703 .iomux_recalced = rk3308_mux_recalced_data, 2704 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 2705 .iomux_routes = rk3308_mux_route_data, 2706 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 2707 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 2708 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 2709 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 2710 }; 2711 2712 static struct rockchip_pin_bank rk3328_pin_banks[] = { 2713 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 2714 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2715 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 2716 IOMUX_WIDTH_3BIT, 2717 IOMUX_WIDTH_3BIT, 2718 0), 2719 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2720 IOMUX_WIDTH_3BIT, 2721 IOMUX_WIDTH_3BIT, 2722 0, 2723 0), 2724 }; 2725 2726 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 2727 .pin_banks = rk3328_pin_banks, 2728 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 2729 .label = "RK3328-GPIO", 2730 .type = RK3288, 2731 .grf_mux_offset = 0x0, 2732 .iomux_recalced = rk3328_mux_recalced_data, 2733 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 2734 .iomux_routes = rk3328_mux_route_data, 2735 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 2736 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2737 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2738 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 2739 }; 2740 2741 static struct rockchip_pin_bank rk3368_pin_banks[] = { 2742 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2743 IOMUX_SOURCE_PMU, 2744 IOMUX_SOURCE_PMU, 2745 IOMUX_SOURCE_PMU 2746 ), 2747 PIN_BANK(1, 32, "gpio1"), 2748 PIN_BANK(2, 32, "gpio2"), 2749 PIN_BANK(3, 32, "gpio3"), 2750 }; 2751 2752 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 2753 .pin_banks = rk3368_pin_banks, 2754 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 2755 .label = "RK3368-GPIO", 2756 .type = RK3368, 2757 .grf_mux_offset = 0x0, 2758 .pmu_mux_offset = 0x0, 2759 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 2760 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 2761 }; 2762 2763 static struct rockchip_pin_bank rk3399_pin_banks[] = { 2764 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 2765 IOMUX_SOURCE_PMU, 2766 IOMUX_SOURCE_PMU, 2767 IOMUX_SOURCE_PMU, 2768 IOMUX_SOURCE_PMU, 2769 DRV_TYPE_IO_1V8_ONLY, 2770 DRV_TYPE_IO_1V8_ONLY, 2771 DRV_TYPE_IO_DEFAULT, 2772 DRV_TYPE_IO_DEFAULT, 2773 0x80, 2774 0x88, 2775 -1, 2776 -1, 2777 PULL_TYPE_IO_1V8_ONLY, 2778 PULL_TYPE_IO_1V8_ONLY, 2779 PULL_TYPE_IO_DEFAULT, 2780 PULL_TYPE_IO_DEFAULT 2781 ), 2782 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 2783 IOMUX_SOURCE_PMU, 2784 IOMUX_SOURCE_PMU, 2785 IOMUX_SOURCE_PMU, 2786 DRV_TYPE_IO_1V8_OR_3V0, 2787 DRV_TYPE_IO_1V8_OR_3V0, 2788 DRV_TYPE_IO_1V8_OR_3V0, 2789 DRV_TYPE_IO_1V8_OR_3V0, 2790 0xa0, 2791 0xa8, 2792 0xb0, 2793 0xb8 2794 ), 2795 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 2796 DRV_TYPE_IO_1V8_OR_3V0, 2797 DRV_TYPE_IO_1V8_ONLY, 2798 DRV_TYPE_IO_1V8_ONLY, 2799 PULL_TYPE_IO_DEFAULT, 2800 PULL_TYPE_IO_DEFAULT, 2801 PULL_TYPE_IO_1V8_ONLY, 2802 PULL_TYPE_IO_1V8_ONLY 2803 ), 2804 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 2805 DRV_TYPE_IO_3V3_ONLY, 2806 DRV_TYPE_IO_3V3_ONLY, 2807 DRV_TYPE_IO_1V8_OR_3V0 2808 ), 2809 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 2810 DRV_TYPE_IO_1V8_3V0_AUTO, 2811 DRV_TYPE_IO_1V8_OR_3V0, 2812 DRV_TYPE_IO_1V8_OR_3V0 2813 ), 2814 }; 2815 2816 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 2817 .pin_banks = rk3399_pin_banks, 2818 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 2819 .label = "RK3399-GPIO", 2820 .type = RK3399, 2821 .grf_mux_offset = 0xe000, 2822 .pmu_mux_offset = 0x0, 2823 .grf_drv_offset = 0xe100, 2824 .pmu_drv_offset = 0x80, 2825 .iomux_routes = rk3399_mux_route_data, 2826 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 2827 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 2828 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 2829 }; 2830 2831 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 2832 { .compatible = "rockchip,px30-pinctrl", 2833 .data = (ulong)&px30_pin_ctrl }, 2834 { .compatible = "rockchip,rv1108-pinctrl", 2835 .data = (ulong)&rv1108_pin_ctrl }, 2836 { .compatible = "rockchip,rk1808-pinctrl", 2837 .data = (ulong)&rk1808_pin_ctrl }, 2838 { .compatible = "rockchip,rk2928-pinctrl", 2839 .data = (ulong)&rk2928_pin_ctrl }, 2840 { .compatible = "rockchip,rk3036-pinctrl", 2841 .data = (ulong)&rk3036_pin_ctrl }, 2842 { .compatible = "rockchip,rk3066a-pinctrl", 2843 .data = (ulong)&rk3066a_pin_ctrl }, 2844 { .compatible = "rockchip,rk3066b-pinctrl", 2845 .data = (ulong)&rk3066b_pin_ctrl }, 2846 { .compatible = "rockchip,rk3128-pinctrl", 2847 .data = (ulong)&rk3128_pin_ctrl }, 2848 { .compatible = "rockchip,rk3188-pinctrl", 2849 .data = (ulong)&rk3188_pin_ctrl }, 2850 { .compatible = "rockchip,rk3228-pinctrl", 2851 .data = (ulong)&rk3228_pin_ctrl }, 2852 { .compatible = "rockchip,rk3288-pinctrl", 2853 .data = (ulong)&rk3288_pin_ctrl }, 2854 { .compatible = "rockchip,rk3308-pinctrl", 2855 .data = (ulong)&rk3308_pin_ctrl }, 2856 { .compatible = "rockchip,rk3328-pinctrl", 2857 .data = (ulong)&rk3328_pin_ctrl }, 2858 { .compatible = "rockchip,rk3368-pinctrl", 2859 .data = (ulong)&rk3368_pin_ctrl }, 2860 { .compatible = "rockchip,rk3399-pinctrl", 2861 .data = (ulong)&rk3399_pin_ctrl }, 2862 {}, 2863 }; 2864 2865 U_BOOT_DRIVER(pinctrl_rockchip) = { 2866 .name = "rockchip_pinctrl", 2867 .id = UCLASS_PINCTRL, 2868 .of_match = rockchip_pinctrl_dt_match, 2869 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 2870 .ops = &rockchip_pinctrl_ops, 2871 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 2872 .bind = dm_scan_fdt_dev, 2873 #endif 2874 .probe = rockchip_pinctrl_probe, 2875 }; 2876