1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <linux/bitops.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/arch/cpu.h> 15 #include <dt-bindings/pinctrl/rockchip.h> 16 17 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 18 #define RK_FUNC_GPIO 0 19 #define MAX_ROCKCHIP_PINS_ENTRIES 30 20 21 enum rockchip_pinctrl_type { 22 PX30, 23 RV1108, 24 RV1126, 25 RK1808, 26 RK2928, 27 RK3066B, 28 RK3128, 29 RK3188, 30 RK3288, 31 RK3308, 32 RK3368, 33 RK3399, 34 }; 35 36 #define RK_GENMASK_VAL(h, l, v) \ 37 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 38 39 /** 40 * Encode variants of iomux registers into a type variable 41 */ 42 #define IOMUX_GPIO_ONLY BIT(0) 43 #define IOMUX_WIDTH_4BIT BIT(1) 44 #define IOMUX_SOURCE_PMU BIT(2) 45 #define IOMUX_UNROUTED BIT(3) 46 #define IOMUX_WIDTH_3BIT BIT(4) 47 #define IOMUX_8WIDTH_2BIT BIT(5) 48 #define IOMUX_WRITABLE_32BIT BIT(6) 49 #define IOMUX_L_SOURCE_PMU BIT(7) 50 51 /** 52 * @type: iomux variant using IOMUX_* constants 53 * @offset: if initialized to -1 it will be autocalculated, by specifying 54 * an initial offset value the relevant source offset can be reset 55 * to a new value for autocalculating the following iomux registers. 56 */ 57 struct rockchip_iomux { 58 int type; 59 int offset; 60 }; 61 62 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 63 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 64 65 /** 66 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 67 */ 68 enum rockchip_pin_drv_type { 69 DRV_TYPE_IO_DEFAULT = 0, 70 DRV_TYPE_IO_1V8_OR_3V0, 71 DRV_TYPE_IO_1V8_ONLY, 72 DRV_TYPE_IO_1V8_3V0_AUTO, 73 DRV_TYPE_IO_3V3_ONLY, 74 DRV_TYPE_IO_SMIC, 75 DRV_TYPE_MAX 76 }; 77 78 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 79 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 80 81 /** 82 * enum type index corresponding to rockchip_pull_list arrays index. 83 */ 84 enum rockchip_pin_pull_type { 85 PULL_TYPE_IO_DEFAULT = 0, 86 PULL_TYPE_IO_1V8_ONLY, 87 PULL_TYPE_MAX 88 }; 89 90 /** 91 * enum mux route register type, should be invalid/default/topgrf/pmugrf. 92 * INVALID: means do not need to set mux route 93 * DEFAULT: means same regmap as pin iomux 94 * TOPGRF: means mux route setting in topgrf 95 * PMUGRF: means mux route setting in pmugrf 96 */ 97 enum rockchip_pin_route_type { 98 ROUTE_TYPE_DEFAULT = 0, 99 ROUTE_TYPE_TOPGRF = 1, 100 ROUTE_TYPE_PMUGRF = 2, 101 102 ROUTE_TYPE_INVALID = -1, 103 }; 104 105 /** 106 * @drv_type: drive strength variant using rockchip_perpin_drv_type 107 * @offset: if initialized to -1 it will be autocalculated, by specifying 108 * an initial offset value the relevant source offset can be reset 109 * to a new value for autocalculating the following drive strength 110 * registers. if used chips own cal_drv func instead to calculate 111 * registers offset, the variant could be ignored. 112 */ 113 struct rockchip_drv { 114 enum rockchip_pin_drv_type drv_type; 115 int offset; 116 }; 117 118 /** 119 * @priv: common pinctrl private basedata 120 * @pin_base: first pin number 121 * @nr_pins: number of pins in this bank 122 * @name: name of the bank 123 * @bank_num: number of the bank, to account for holes 124 * @iomux: array describing the 4 iomux sources of the bank 125 * @drv: array describing the 4 drive strength sources of the bank 126 * @pull_type: array describing the 4 pull type sources of the bank 127 * @recalced_mask: bits describing the mux recalced pins of per bank 128 * @route_mask: bits describing the routing pins of per bank 129 */ 130 struct rockchip_pin_bank { 131 struct rockchip_pinctrl_priv *priv; 132 u32 pin_base; 133 u8 nr_pins; 134 char *name; 135 u8 bank_num; 136 struct rockchip_iomux iomux[4]; 137 struct rockchip_drv drv[4]; 138 enum rockchip_pin_pull_type pull_type[4]; 139 u32 recalced_mask; 140 u32 route_mask; 141 }; 142 143 #define PIN_BANK(id, pins, label) \ 144 { \ 145 .bank_num = id, \ 146 .nr_pins = pins, \ 147 .name = label, \ 148 .iomux = { \ 149 { .offset = -1 }, \ 150 { .offset = -1 }, \ 151 { .offset = -1 }, \ 152 { .offset = -1 }, \ 153 }, \ 154 } 155 156 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 157 { \ 158 .bank_num = id, \ 159 .nr_pins = pins, \ 160 .name = label, \ 161 .iomux = { \ 162 { .type = iom0, .offset = -1 }, \ 163 { .type = iom1, .offset = -1 }, \ 164 { .type = iom2, .offset = -1 }, \ 165 { .type = iom3, .offset = -1 }, \ 166 }, \ 167 } 168 169 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ 170 iom3, offset0, offset1, offset2, \ 171 offset3) \ 172 { \ 173 .bank_num = id, \ 174 .nr_pins = pins, \ 175 .name = label, \ 176 .iomux = { \ 177 { .type = iom0, .offset = offset0 }, \ 178 { .type = iom1, .offset = offset1 }, \ 179 { .type = iom2, .offset = offset2 }, \ 180 { .type = iom3, .offset = offset3 }, \ 181 }, \ 182 } 183 184 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 185 { \ 186 .bank_num = id, \ 187 .nr_pins = pins, \ 188 .name = label, \ 189 .iomux = { \ 190 { .offset = -1 }, \ 191 { .offset = -1 }, \ 192 { .offset = -1 }, \ 193 { .offset = -1 }, \ 194 }, \ 195 .drv = { \ 196 { .drv_type = type0, .offset = -1 }, \ 197 { .drv_type = type1, .offset = -1 }, \ 198 { .drv_type = type2, .offset = -1 }, \ 199 { .drv_type = type3, .offset = -1 }, \ 200 }, \ 201 } 202 203 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 204 drv2, drv3, pull0, pull1, \ 205 pull2, pull3) \ 206 { \ 207 .bank_num = id, \ 208 .nr_pins = pins, \ 209 .name = label, \ 210 .iomux = { \ 211 { .offset = -1 }, \ 212 { .offset = -1 }, \ 213 { .offset = -1 }, \ 214 { .offset = -1 }, \ 215 }, \ 216 .drv = { \ 217 { .drv_type = drv0, .offset = -1 }, \ 218 { .drv_type = drv1, .offset = -1 }, \ 219 { .drv_type = drv2, .offset = -1 }, \ 220 { .drv_type = drv3, .offset = -1 }, \ 221 }, \ 222 .pull_type[0] = pull0, \ 223 .pull_type[1] = pull1, \ 224 .pull_type[2] = pull2, \ 225 .pull_type[3] = pull3, \ 226 } 227 228 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 229 iom2, iom3, drv0, drv1, drv2, \ 230 drv3, offset0, offset1, \ 231 offset2, offset3) \ 232 { \ 233 .bank_num = id, \ 234 .nr_pins = pins, \ 235 .name = label, \ 236 .iomux = { \ 237 { .type = iom0, .offset = -1 }, \ 238 { .type = iom1, .offset = -1 }, \ 239 { .type = iom2, .offset = -1 }, \ 240 { .type = iom3, .offset = -1 }, \ 241 }, \ 242 .drv = { \ 243 { .drv_type = drv0, .offset = offset0 }, \ 244 { .drv_type = drv1, .offset = offset1 }, \ 245 { .drv_type = drv2, .offset = offset2 }, \ 246 { .drv_type = drv3, .offset = offset3 }, \ 247 }, \ 248 } 249 250 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 251 iom2, iom3, drv0, drv1, drv2, \ 252 drv3, pull0, pull1, pull2, \ 253 pull3) \ 254 { \ 255 .bank_num = id, \ 256 .nr_pins = pins, \ 257 .name = label, \ 258 .iomux = { \ 259 { .type = iom0, .offset = -1 }, \ 260 { .type = iom1, .offset = -1 }, \ 261 { .type = iom2, .offset = -1 }, \ 262 { .type = iom3, .offset = -1 }, \ 263 }, \ 264 .drv = { \ 265 { .drv_type = drv0, .offset = -1 }, \ 266 { .drv_type = drv1, .offset = -1 }, \ 267 { .drv_type = drv2, .offset = -1 }, \ 268 { .drv_type = drv3, .offset = -1 }, \ 269 }, \ 270 .pull_type[0] = pull0, \ 271 .pull_type[1] = pull1, \ 272 .pull_type[2] = pull2, \ 273 .pull_type[3] = pull3, \ 274 } 275 276 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 277 label, iom0, iom1, iom2, \ 278 iom3, drv0, drv1, drv2, \ 279 drv3, offset0, offset1, \ 280 offset2, offset3, pull0, \ 281 pull1, pull2, pull3) \ 282 { \ 283 .bank_num = id, \ 284 .nr_pins = pins, \ 285 .name = label, \ 286 .iomux = { \ 287 { .type = iom0, .offset = -1 }, \ 288 { .type = iom1, .offset = -1 }, \ 289 { .type = iom2, .offset = -1 }, \ 290 { .type = iom3, .offset = -1 }, \ 291 }, \ 292 .drv = { \ 293 { .drv_type = drv0, .offset = offset0 }, \ 294 { .drv_type = drv1, .offset = offset1 }, \ 295 { .drv_type = drv2, .offset = offset2 }, \ 296 { .drv_type = drv3, .offset = offset3 }, \ 297 }, \ 298 .pull_type[0] = pull0, \ 299 .pull_type[1] = pull1, \ 300 .pull_type[2] = pull2, \ 301 .pull_type[3] = pull3, \ 302 } 303 304 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 305 { \ 306 .bank_num = ID, \ 307 .pin = PIN, \ 308 .func = FUNC, \ 309 .route_offset = REG, \ 310 .route_val = VAL, \ 311 .route_type = FLAG, \ 312 } 313 314 #define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ 315 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT) 316 317 #define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ 318 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF) 319 320 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ 321 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF) 322 323 /** 324 * struct rockchip_mux_recalced_data: represent a pin iomux data. 325 * @num: bank number. 326 * @pin: pin number. 327 * @bit: index at register. 328 * @reg: register offset. 329 * @mask: mask bit 330 */ 331 struct rockchip_mux_recalced_data { 332 u8 num; 333 u8 pin; 334 u32 reg; 335 u8 bit; 336 u8 mask; 337 }; 338 339 /** 340 * struct rockchip_mux_recalced_data: represent a pin iomux data. 341 * @bank_num: bank number. 342 * @pin: index at register or used to calc index. 343 * @func: the min pin. 344 * @route_type: the register type. 345 * @route_offset: the max pin. 346 * @route_val: the register offset. 347 */ 348 struct rockchip_mux_route_data { 349 u8 bank_num; 350 u8 pin; 351 u8 func; 352 enum rockchip_pin_route_type route_type : 8; 353 u32 route_offset; 354 u32 route_val; 355 }; 356 357 /** 358 */ 359 struct rockchip_pin_ctrl { 360 struct rockchip_pin_bank *pin_banks; 361 u32 nr_banks; 362 u32 nr_pins; 363 char *label; 364 enum rockchip_pinctrl_type type; 365 int grf_mux_offset; 366 int pmu_mux_offset; 367 int grf_drv_offset; 368 int pmu_drv_offset; 369 struct rockchip_mux_recalced_data *iomux_recalced; 370 u32 niomux_recalced; 371 struct rockchip_mux_route_data *iomux_routes; 372 u32 niomux_routes; 373 374 int (*ctrl_data_re_init)(const struct rockchip_pin_ctrl *ctrl); 375 376 int (*soc_data_init)(struct rockchip_pinctrl_priv *info); 377 378 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 379 int pin_num, struct regmap **regmap, 380 int *reg, u8 *bit); 381 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 382 int pin_num, struct regmap **regmap, 383 int *reg, u8 *bit); 384 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 385 int pin_num, struct regmap **regmap, 386 int *reg, u8 *bit); 387 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank, 388 int pin_num, struct regmap **regmap, 389 int *reg, u8 *bit); 390 }; 391 392 /** 393 */ 394 struct rockchip_pinctrl_priv { 395 struct rockchip_pin_ctrl *ctrl; 396 struct regmap *regmap_base; 397 struct regmap *regmap_pmu; 398 399 }; 400 401 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 402 { 403 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 404 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 405 406 if (bank >= ctrl->nr_banks) { 407 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 408 return -EINVAL; 409 } 410 411 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 412 debug("pin conf pin %d >= %d\n", pin, 413 MAX_ROCKCHIP_GPIO_PER_BANK); 414 return -EINVAL; 415 } 416 417 return 0; 418 } 419 420 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 421 { 422 .num = 1, 423 .pin = 0, 424 .reg = 0x418, 425 .bit = 0, 426 .mask = 0x3 427 }, { 428 .num = 1, 429 .pin = 1, 430 .reg = 0x418, 431 .bit = 2, 432 .mask = 0x3 433 }, { 434 .num = 1, 435 .pin = 2, 436 .reg = 0x418, 437 .bit = 4, 438 .mask = 0x3 439 }, { 440 .num = 1, 441 .pin = 3, 442 .reg = 0x418, 443 .bit = 6, 444 .mask = 0x3 445 }, { 446 .num = 1, 447 .pin = 4, 448 .reg = 0x418, 449 .bit = 8, 450 .mask = 0x3 451 }, { 452 .num = 1, 453 .pin = 5, 454 .reg = 0x418, 455 .bit = 10, 456 .mask = 0x3 457 }, { 458 .num = 1, 459 .pin = 6, 460 .reg = 0x418, 461 .bit = 12, 462 .mask = 0x3 463 }, { 464 .num = 1, 465 .pin = 7, 466 .reg = 0x418, 467 .bit = 14, 468 .mask = 0x3 469 }, { 470 .num = 1, 471 .pin = 8, 472 .reg = 0x41c, 473 .bit = 0, 474 .mask = 0x3 475 }, { 476 .num = 1, 477 .pin = 9, 478 .reg = 0x41c, 479 .bit = 2, 480 .mask = 0x3 481 }, 482 }; 483 484 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 485 { 486 .num = 0, 487 .pin = 20, 488 .reg = 0x10000, 489 .bit = 0, 490 .mask = 0xf 491 }, 492 { 493 .num = 0, 494 .pin = 21, 495 .reg = 0x10000, 496 .bit = 4, 497 .mask = 0xf 498 }, 499 { 500 .num = 0, 501 .pin = 22, 502 .reg = 0x10000, 503 .bit = 8, 504 .mask = 0xf 505 }, 506 { 507 .num = 0, 508 .pin = 23, 509 .reg = 0x10000, 510 .bit = 12, 511 .mask = 0xf 512 }, 513 }; 514 515 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 516 { 517 .num = 2, 518 .pin = 20, 519 .reg = 0xe8, 520 .bit = 0, 521 .mask = 0x7 522 }, { 523 .num = 2, 524 .pin = 21, 525 .reg = 0xe8, 526 .bit = 4, 527 .mask = 0x7 528 }, { 529 .num = 2, 530 .pin = 22, 531 .reg = 0xe8, 532 .bit = 8, 533 .mask = 0x7 534 }, { 535 .num = 2, 536 .pin = 23, 537 .reg = 0xe8, 538 .bit = 12, 539 .mask = 0x7 540 }, { 541 .num = 2, 542 .pin = 24, 543 .reg = 0xd4, 544 .bit = 12, 545 .mask = 0x7 546 }, 547 }; 548 549 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 550 { 551 .num = 1, 552 .pin = 14, 553 .reg = 0x28, 554 .bit = 12, 555 .mask = 0x7 556 }, { 557 .num = 1, 558 .pin = 15, 559 .reg = 0x2c, 560 .bit = 0, 561 .mask = 0x3 562 }, { 563 .num = 1, 564 .pin = 18, 565 .reg = 0x30, 566 .bit = 4, 567 .mask = 0x7 568 }, { 569 .num = 1, 570 .pin = 19, 571 .reg = 0x30, 572 .bit = 8, 573 .mask = 0x7 574 }, { 575 .num = 1, 576 .pin = 20, 577 .reg = 0x30, 578 .bit = 12, 579 .mask = 0x7 580 }, { 581 .num = 1, 582 .pin = 21, 583 .reg = 0x34, 584 .bit = 0, 585 .mask = 0x7 586 }, { 587 .num = 1, 588 .pin = 22, 589 .reg = 0x34, 590 .bit = 4, 591 .mask = 0x7 592 }, { 593 .num = 1, 594 .pin = 23, 595 .reg = 0x34, 596 .bit = 8, 597 .mask = 0x7 598 }, { 599 .num = 3, 600 .pin = 12, 601 .reg = 0x68, 602 .bit = 8, 603 .mask = 0x7 604 }, { 605 .num = 3, 606 .pin = 13, 607 .reg = 0x68, 608 .bit = 12, 609 .mask = 0x7 610 }, 611 }; 612 613 static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { 614 { 615 .num = 1, 616 .pin = 14, 617 .reg = 0x28, 618 .bit = 12, 619 .mask = 0xf 620 }, { 621 .num = 1, 622 .pin = 15, 623 .reg = 0x2c, 624 .bit = 0, 625 .mask = 0x3 626 }, { 627 .num = 1, 628 .pin = 18, 629 .reg = 0x30, 630 .bit = 4, 631 .mask = 0xf 632 }, { 633 .num = 1, 634 .pin = 19, 635 .reg = 0x30, 636 .bit = 8, 637 .mask = 0xf 638 }, { 639 .num = 1, 640 .pin = 20, 641 .reg = 0x30, 642 .bit = 12, 643 .mask = 0xf 644 }, { 645 .num = 1, 646 .pin = 21, 647 .reg = 0x34, 648 .bit = 0, 649 .mask = 0xf 650 }, { 651 .num = 1, 652 .pin = 22, 653 .reg = 0x34, 654 .bit = 4, 655 .mask = 0xf 656 }, { 657 .num = 1, 658 .pin = 23, 659 .reg = 0x34, 660 .bit = 8, 661 .mask = 0xf 662 }, { 663 .num = 3, 664 .pin = 12, 665 .reg = 0x68, 666 .bit = 8, 667 .mask = 0xf 668 }, { 669 .num = 3, 670 .pin = 13, 671 .reg = 0x68, 672 .bit = 12, 673 .mask = 0xf 674 }, { 675 .num = 2, 676 .pin = 2, 677 .reg = 0x608, 678 .bit = 0, 679 .mask = 0x7 680 }, { 681 .num = 2, 682 .pin = 3, 683 .reg = 0x608, 684 .bit = 4, 685 .mask = 0x7 686 }, { 687 .num = 2, 688 .pin = 16, 689 .reg = 0x610, 690 .bit = 8, 691 .mask = 0x7 692 }, { 693 .num = 3, 694 .pin = 10, 695 .reg = 0x610, 696 .bit = 0, 697 .mask = 0x7 698 }, { 699 .num = 3, 700 .pin = 11, 701 .reg = 0x610, 702 .bit = 4, 703 .mask = 0x7 704 }, 705 }; 706 707 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 708 { 709 /* gpio2_b7_sel */ 710 .num = 2, 711 .pin = 15, 712 .reg = 0x28, 713 .bit = 0, 714 .mask = 0x7 715 }, { 716 /* gpio2_c7_sel */ 717 .num = 2, 718 .pin = 23, 719 .reg = 0x30, 720 .bit = 14, 721 .mask = 0x3 722 }, { 723 /* gpio3_b1_sel */ 724 .num = 3, 725 .pin = 9, 726 .reg = 0x44, 727 .bit = 2, 728 .mask = 0x3 729 }, { 730 /* gpio3_b2_sel */ 731 .num = 3, 732 .pin = 10, 733 .reg = 0x44, 734 .bit = 4, 735 .mask = 0x3 736 }, { 737 /* gpio3_b3_sel */ 738 .num = 3, 739 .pin = 11, 740 .reg = 0x44, 741 .bit = 6, 742 .mask = 0x3 743 }, { 744 /* gpio3_b4_sel */ 745 .num = 3, 746 .pin = 12, 747 .reg = 0x44, 748 .bit = 8, 749 .mask = 0x3 750 }, { 751 /* gpio3_b5_sel */ 752 .num = 3, 753 .pin = 13, 754 .reg = 0x44, 755 .bit = 10, 756 .mask = 0x3 757 }, { 758 /* gpio3_b6_sel */ 759 .num = 3, 760 .pin = 14, 761 .reg = 0x44, 762 .bit = 12, 763 .mask = 0x3 764 }, { 765 /* gpio3_b7_sel */ 766 .num = 3, 767 .pin = 15, 768 .reg = 0x44, 769 .bit = 14, 770 .mask = 0x3 771 }, 772 }; 773 774 static struct rockchip_mux_route_data rv1126_mux_route_data[] = { 775 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ 776 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ 777 778 MR_TOPGRF(RK_GPIO0, RK_PD4, RK_FUNC_4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ 779 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ 780 MR_TOPGRF(RK_GPIO2, RK_PC7, RK_FUNC_6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ 781 782 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ 783 MR_TOPGRF(RK_GPIO2, RK_PB3, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ 784 785 MR_TOPGRF(RK_GPIO3, RK_PD4, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ 786 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ 787 788 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ 789 MR_TOPGRF(RK_GPIO2, RK_PD1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ 790 791 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ 792 MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ 793 MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ 794 795 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ 796 MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ 797 798 MR_TOPGRF(RK_GPIO2, RK_PA5, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ 799 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ 800 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ 801 802 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ 803 MR_TOPGRF(RK_GPIO1, RK_PC6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ 804 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ 805 806 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ 807 MR_TOPGRF(RK_GPIO2, RK_PB7, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ 808 809 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ 810 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ 811 812 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */ 813 MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */ 814 815 MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */ 816 MR_TOPGRF(RK_GPIO2, RK_PD6, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */ 817 818 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */ 819 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */ 820 821 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ 822 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ 823 824 MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ 825 MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ 826 827 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ 828 MR_TOPGRF(RK_GPIO1, RK_PA7, RK_FUNC_2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ 829 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ 830 831 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ 832 MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ 833 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ 834 835 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ 836 MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ 837 MR_TOPGRF(RK_GPIO2, RK_PA0, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ 838 839 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */ 840 MR_PMUGRF(RK_GPIO2, RK_PB3, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */ 841 842 MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */ 843 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */ 844 845 MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */ 846 MR_PMUGRF(RK_GPIO2, RK_PB1, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */ 847 848 MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ 849 MR_PMUGRF(RK_GPIO2, RK_PB0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ 850 851 MR_PMUGRF(RK_GPIO0, RK_PC2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */ 852 MR_PMUGRF(RK_GPIO2, RK_PA7, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */ 853 854 MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */ 855 MR_PMUGRF(RK_GPIO2, RK_PA6, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */ 856 857 MR_PMUGRF(RK_GPIO0, RK_PB2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */ 858 MR_PMUGRF(RK_GPIO2, RK_PD4, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */ 859 860 MR_PMUGRF(RK_GPIO0, RK_PB1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ 861 MR_PMUGRF(RK_GPIO3, RK_PA0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ 862 863 MR_PMUGRF(RK_GPIO0, RK_PB0, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ 864 MR_PMUGRF(RK_GPIO2, RK_PA1, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ 865 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ 866 867 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ 868 MR_PMUGRF(RK_GPIO1, RK_PD0, RK_FUNC_5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ 869 MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */ 870 }; 871 872 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 873 int *reg, u8 *bit, int *mask) 874 { 875 struct rockchip_pinctrl_priv *priv = bank->priv; 876 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 877 struct rockchip_mux_recalced_data *data; 878 int i; 879 880 for (i = 0; i < ctrl->niomux_recalced; i++) { 881 data = &ctrl->iomux_recalced[i]; 882 if (data->num == bank->bank_num && 883 data->pin == pin) 884 break; 885 } 886 887 if (i >= ctrl->niomux_recalced) 888 return; 889 890 *reg = data->reg; 891 *mask = data->mask; 892 *bit = data->bit; 893 } 894 895 static struct rockchip_mux_route_data px30_mux_route_data[] = { 896 { 897 /* cif-d2m0 */ 898 .bank_num = 2, 899 .pin = 0, 900 .func = 1, 901 .route_offset = 0x184, 902 .route_val = BIT(16 + 7), 903 }, { 904 /* cif-d2m1 */ 905 .bank_num = 3, 906 .pin = 3, 907 .func = 3, 908 .route_offset = 0x184, 909 .route_val = BIT(16 + 7) | BIT(7), 910 }, { 911 /* pdm-m0 */ 912 .bank_num = 3, 913 .pin = 22, 914 .func = 2, 915 .route_offset = 0x184, 916 .route_val = BIT(16 + 8), 917 }, { 918 /* pdm-m1 */ 919 .bank_num = 2, 920 .pin = 22, 921 .func = 1, 922 .route_offset = 0x184, 923 .route_val = BIT(16 + 8) | BIT(8), 924 }, { 925 /* uart2-rxm0 */ 926 .bank_num = 1, 927 .pin = 27, 928 .func = 2, 929 .route_offset = 0x184, 930 .route_val = BIT(16 + 10), 931 }, { 932 /* uart2-rxm1 */ 933 .bank_num = 2, 934 .pin = 14, 935 .func = 2, 936 .route_offset = 0x184, 937 .route_val = BIT(16 + 10) | BIT(10), 938 }, { 939 /* uart3-rxm0 */ 940 .bank_num = 0, 941 .pin = 17, 942 .func = 2, 943 .route_offset = 0x184, 944 .route_val = BIT(16 + 9), 945 }, { 946 /* uart3-rxm1 */ 947 .bank_num = 1, 948 .pin = 15, 949 .func = 2, 950 .route_offset = 0x184, 951 .route_val = BIT(16 + 9) | BIT(9), 952 }, 953 }; 954 955 static struct rockchip_mux_route_data rk1808_mux_route_data[] = { 956 { 957 /* i2c2m0_sda */ 958 .bank_num = 3, 959 .pin = 12, 960 .func = 2, 961 .route_offset = 0x190, 962 .route_val = BIT(16 + 3), 963 }, { 964 /* i2c2m1_sda */ 965 .bank_num = 1, 966 .pin = 13, 967 .func = 2, 968 .route_offset = 0x190, 969 .route_val = BIT(16 + 3) | BIT(3), 970 }, { 971 /* uart2_rxm0 */ 972 .bank_num = 4, 973 .pin = 3, 974 .func = 2, 975 .route_offset = 0x190, 976 .route_val = BIT(16 + 14) | BIT(16 + 15), 977 }, { 978 /* uart2_rxm1 */ 979 .bank_num = 2, 980 .pin = 25, 981 .func = 2, 982 .route_offset = 0x190, 983 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15), 984 }, { 985 /* uart2_rxm2 */ 986 .bank_num = 3, 987 .pin = 4, 988 .func = 2, 989 .route_offset = 0x190, 990 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15), 991 }, 992 }; 993 994 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 995 { 996 /* spi-0 */ 997 .bank_num = 1, 998 .pin = 10, 999 .func = 1, 1000 .route_offset = 0x144, 1001 .route_val = BIT(16 + 3) | BIT(16 + 4), 1002 }, { 1003 /* spi-1 */ 1004 .bank_num = 1, 1005 .pin = 27, 1006 .func = 3, 1007 .route_offset = 0x144, 1008 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 1009 }, { 1010 /* spi-2 */ 1011 .bank_num = 0, 1012 .pin = 13, 1013 .func = 2, 1014 .route_offset = 0x144, 1015 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 1016 }, { 1017 /* i2s-0 */ 1018 .bank_num = 1, 1019 .pin = 5, 1020 .func = 1, 1021 .route_offset = 0x144, 1022 .route_val = BIT(16 + 5), 1023 }, { 1024 /* i2s-1 */ 1025 .bank_num = 0, 1026 .pin = 14, 1027 .func = 1, 1028 .route_offset = 0x144, 1029 .route_val = BIT(16 + 5) | BIT(5), 1030 }, { 1031 /* emmc-0 */ 1032 .bank_num = 1, 1033 .pin = 22, 1034 .func = 2, 1035 .route_offset = 0x144, 1036 .route_val = BIT(16 + 6), 1037 }, { 1038 /* emmc-1 */ 1039 .bank_num = 2, 1040 .pin = 4, 1041 .func = 2, 1042 .route_offset = 0x144, 1043 .route_val = BIT(16 + 6) | BIT(6), 1044 }, 1045 }; 1046 1047 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 1048 { 1049 /* pwm0-0 */ 1050 .bank_num = 0, 1051 .pin = 26, 1052 .func = 1, 1053 .route_offset = 0x50, 1054 .route_val = BIT(16), 1055 }, { 1056 /* pwm0-1 */ 1057 .bank_num = 3, 1058 .pin = 21, 1059 .func = 1, 1060 .route_offset = 0x50, 1061 .route_val = BIT(16) | BIT(0), 1062 }, { 1063 /* pwm1-0 */ 1064 .bank_num = 0, 1065 .pin = 27, 1066 .func = 1, 1067 .route_offset = 0x50, 1068 .route_val = BIT(16 + 1), 1069 }, { 1070 /* pwm1-1 */ 1071 .bank_num = 0, 1072 .pin = 30, 1073 .func = 2, 1074 .route_offset = 0x50, 1075 .route_val = BIT(16 + 1) | BIT(1), 1076 }, { 1077 /* pwm2-0 */ 1078 .bank_num = 0, 1079 .pin = 28, 1080 .func = 1, 1081 .route_offset = 0x50, 1082 .route_val = BIT(16 + 2), 1083 }, { 1084 /* pwm2-1 */ 1085 .bank_num = 1, 1086 .pin = 12, 1087 .func = 2, 1088 .route_offset = 0x50, 1089 .route_val = BIT(16 + 2) | BIT(2), 1090 }, { 1091 /* pwm3-0 */ 1092 .bank_num = 3, 1093 .pin = 26, 1094 .func = 1, 1095 .route_offset = 0x50, 1096 .route_val = BIT(16 + 3), 1097 }, { 1098 /* pwm3-1 */ 1099 .bank_num = 1, 1100 .pin = 11, 1101 .func = 2, 1102 .route_offset = 0x50, 1103 .route_val = BIT(16 + 3) | BIT(3), 1104 }, { 1105 /* sdio-0_d0 */ 1106 .bank_num = 1, 1107 .pin = 1, 1108 .func = 1, 1109 .route_offset = 0x50, 1110 .route_val = BIT(16 + 4), 1111 }, { 1112 /* sdio-1_d0 */ 1113 .bank_num = 3, 1114 .pin = 2, 1115 .func = 1, 1116 .route_offset = 0x50, 1117 .route_val = BIT(16 + 4) | BIT(4), 1118 }, { 1119 /* spi-0_rx */ 1120 .bank_num = 0, 1121 .pin = 13, 1122 .func = 2, 1123 .route_offset = 0x50, 1124 .route_val = BIT(16 + 5), 1125 }, { 1126 /* spi-1_rx */ 1127 .bank_num = 2, 1128 .pin = 0, 1129 .func = 2, 1130 .route_offset = 0x50, 1131 .route_val = BIT(16 + 5) | BIT(5), 1132 }, { 1133 /* emmc-0_cmd */ 1134 .bank_num = 1, 1135 .pin = 22, 1136 .func = 2, 1137 .route_offset = 0x50, 1138 .route_val = BIT(16 + 7), 1139 }, { 1140 /* emmc-1_cmd */ 1141 .bank_num = 2, 1142 .pin = 4, 1143 .func = 2, 1144 .route_offset = 0x50, 1145 .route_val = BIT(16 + 7) | BIT(7), 1146 }, { 1147 /* uart2-0_rx */ 1148 .bank_num = 1, 1149 .pin = 19, 1150 .func = 2, 1151 .route_offset = 0x50, 1152 .route_val = BIT(16 + 8), 1153 }, { 1154 /* uart2-1_rx */ 1155 .bank_num = 1, 1156 .pin = 10, 1157 .func = 2, 1158 .route_offset = 0x50, 1159 .route_val = BIT(16 + 8) | BIT(8), 1160 }, { 1161 /* uart1-0_rx */ 1162 .bank_num = 1, 1163 .pin = 10, 1164 .func = 1, 1165 .route_offset = 0x50, 1166 .route_val = BIT(16 + 11), 1167 }, { 1168 /* uart1-1_rx */ 1169 .bank_num = 3, 1170 .pin = 13, 1171 .func = 1, 1172 .route_offset = 0x50, 1173 .route_val = BIT(16 + 11) | BIT(11), 1174 }, 1175 }; 1176 1177 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 1178 { 1179 /* edphdmi_cecinoutt1 */ 1180 .bank_num = 7, 1181 .pin = 16, 1182 .func = 2, 1183 .route_offset = 0x264, 1184 .route_val = BIT(16 + 12) | BIT(12), 1185 }, { 1186 /* edphdmi_cecinout */ 1187 .bank_num = 7, 1188 .pin = 23, 1189 .func = 4, 1190 .route_offset = 0x264, 1191 .route_val = BIT(16 + 12), 1192 }, 1193 }; 1194 1195 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 1196 { 1197 /* rtc_clk */ 1198 .bank_num = 0, 1199 .pin = 19, 1200 .func = 1, 1201 .route_offset = 0x314, 1202 .route_val = BIT(16 + 0) | BIT(0), 1203 }, { 1204 /* uart2_rxm0 */ 1205 .bank_num = 1, 1206 .pin = 22, 1207 .func = 2, 1208 .route_offset = 0x314, 1209 .route_val = BIT(16 + 2) | BIT(16 + 3), 1210 }, { 1211 /* uart2_rxm1 */ 1212 .bank_num = 4, 1213 .pin = 26, 1214 .func = 2, 1215 .route_offset = 0x314, 1216 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1217 }, { 1218 /* i2c3_sdam0 */ 1219 .bank_num = 0, 1220 .pin = 23, 1221 .func = 2, 1222 .route_offset = 0x314, 1223 .route_val = BIT(16 + 4), 1224 }, { 1225 /* i2c3_sdam1 */ 1226 .bank_num = 3, 1227 .pin = 12, 1228 .func = 2, 1229 .route_offset = 0x314, 1230 .route_val = BIT(16 + 4) | BIT(4), 1231 }, { 1232 /* i2s-8ch-1-sclktxm0 */ 1233 .bank_num = 1, 1234 .pin = 3, 1235 .func = 2, 1236 .route_offset = 0x308, 1237 .route_val = BIT(16 + 3), 1238 }, { 1239 /* i2s-8ch-1-sclkrxm0 */ 1240 .bank_num = 1, 1241 .pin = 4, 1242 .func = 2, 1243 .route_offset = 0x308, 1244 .route_val = BIT(16 + 3), 1245 }, { 1246 /* i2s-8ch-1-sclktxm1 */ 1247 .bank_num = 1, 1248 .pin = 13, 1249 .func = 2, 1250 .route_offset = 0x308, 1251 .route_val = BIT(16 + 3) | BIT(3), 1252 }, { 1253 /* i2s-8ch-1-sclkrxm1 */ 1254 .bank_num = 1, 1255 .pin = 14, 1256 .func = 2, 1257 .route_offset = 0x308, 1258 .route_val = BIT(16 + 3) | BIT(3), 1259 }, { 1260 /* pdm-clkm0 */ 1261 .bank_num = 1, 1262 .pin = 4, 1263 .func = 3, 1264 .route_offset = 0x308, 1265 .route_val = BIT(16 + 12) | BIT(16 + 13), 1266 }, { 1267 /* pdm-clkm1 */ 1268 .bank_num = 1, 1269 .pin = 14, 1270 .func = 4, 1271 .route_offset = 0x308, 1272 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1273 }, { 1274 /* pdm-clkm2 */ 1275 .bank_num = 2, 1276 .pin = 6, 1277 .func = 2, 1278 .route_offset = 0x308, 1279 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1280 }, { 1281 /* pdm-clkm-m2 */ 1282 .bank_num = 2, 1283 .pin = 4, 1284 .func = 3, 1285 .route_offset = 0x600, 1286 .route_val = BIT(16 + 2) | BIT(2), 1287 }, 1288 }; 1289 1290 static struct rockchip_mux_route_data rk3308b_mux_route_data[] = { 1291 { 1292 /* rtc_clk */ 1293 .bank_num = 0, 1294 .pin = 19, 1295 .func = 1, 1296 .route_offset = 0x314, 1297 .route_val = BIT(16 + 0) | BIT(0), 1298 }, { 1299 /* uart2_rxm0 */ 1300 .bank_num = 1, 1301 .pin = 22, 1302 .func = 2, 1303 .route_offset = 0x314, 1304 .route_val = BIT(16 + 2) | BIT(16 + 3), 1305 }, { 1306 /* uart2_rxm1 */ 1307 .bank_num = 4, 1308 .pin = 26, 1309 .func = 2, 1310 .route_offset = 0x314, 1311 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1312 }, { 1313 /* i2c3_sdam0 */ 1314 .bank_num = 0, 1315 .pin = 15, 1316 .func = 2, 1317 .route_offset = 0x608, 1318 .route_val = BIT(16 + 8) | BIT(16 + 9), 1319 }, { 1320 /* i2c3_sdam1 */ 1321 .bank_num = 3, 1322 .pin = 12, 1323 .func = 2, 1324 .route_offset = 0x608, 1325 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 1326 }, { 1327 /* i2c3_sdam2 */ 1328 .bank_num = 2, 1329 .pin = 0, 1330 .func = 3, 1331 .route_offset = 0x608, 1332 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 1333 }, { 1334 /* i2s-8ch-1-sclktxm0 */ 1335 .bank_num = 1, 1336 .pin = 3, 1337 .func = 2, 1338 .route_offset = 0x308, 1339 .route_val = BIT(16 + 3), 1340 }, { 1341 /* i2s-8ch-1-sclkrxm0 */ 1342 .bank_num = 1, 1343 .pin = 4, 1344 .func = 2, 1345 .route_offset = 0x308, 1346 .route_val = BIT(16 + 3), 1347 }, { 1348 /* i2s-8ch-1-sclktxm1 */ 1349 .bank_num = 1, 1350 .pin = 13, 1351 .func = 2, 1352 .route_offset = 0x308, 1353 .route_val = BIT(16 + 3) | BIT(3), 1354 }, { 1355 /* i2s-8ch-1-sclkrxm1 */ 1356 .bank_num = 1, 1357 .pin = 14, 1358 .func = 2, 1359 .route_offset = 0x308, 1360 .route_val = BIT(16 + 3) | BIT(3), 1361 }, { 1362 /* pdm-clkm0 */ 1363 .bank_num = 1, 1364 .pin = 4, 1365 .func = 3, 1366 .route_offset = 0x308, 1367 .route_val = BIT(16 + 12) | BIT(16 + 13), 1368 }, { 1369 /* pdm-clkm1 */ 1370 .bank_num = 1, 1371 .pin = 14, 1372 .func = 4, 1373 .route_offset = 0x308, 1374 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1375 }, { 1376 /* pdm-clkm2 */ 1377 .bank_num = 2, 1378 .pin = 6, 1379 .func = 2, 1380 .route_offset = 0x308, 1381 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1382 }, { 1383 /* pdm-clkm-m2 */ 1384 .bank_num = 2, 1385 .pin = 4, 1386 .func = 3, 1387 .route_offset = 0x600, 1388 .route_val = BIT(16 + 2) | BIT(2), 1389 }, { 1390 /* spi1_miso */ 1391 .bank_num = 3, 1392 .pin = 10, 1393 .func = 3, 1394 .route_offset = 0x314, 1395 .route_val = BIT(16 + 9), 1396 }, { 1397 /* spi1_miso_m1 */ 1398 .bank_num = 2, 1399 .pin = 4, 1400 .func = 2, 1401 .route_offset = 0x314, 1402 .route_val = BIT(16 + 9) | BIT(9), 1403 }, { 1404 /* owire_m0 */ 1405 .bank_num = 0, 1406 .pin = 11, 1407 .func = 3, 1408 .route_offset = 0x314, 1409 .route_val = BIT(16 + 10) | BIT(16 + 11), 1410 }, { 1411 /* owire_m1 */ 1412 .bank_num = 1, 1413 .pin = 22, 1414 .func = 7, 1415 .route_offset = 0x314, 1416 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1417 }, { 1418 /* owire_m2 */ 1419 .bank_num = 2, 1420 .pin = 2, 1421 .func = 5, 1422 .route_offset = 0x314, 1423 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1424 }, { 1425 /* can_rxd_m0 */ 1426 .bank_num = 0, 1427 .pin = 11, 1428 .func = 2, 1429 .route_offset = 0x314, 1430 .route_val = BIT(16 + 12) | BIT(16 + 13), 1431 }, { 1432 /* can_rxd_m1 */ 1433 .bank_num = 1, 1434 .pin = 22, 1435 .func = 5, 1436 .route_offset = 0x314, 1437 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1438 }, { 1439 /* can_rxd_m2 */ 1440 .bank_num = 2, 1441 .pin = 2, 1442 .func = 4, 1443 .route_offset = 0x314, 1444 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1445 }, { 1446 /* mac_rxd0_m0 */ 1447 .bank_num = 1, 1448 .pin = 20, 1449 .func = 3, 1450 .route_offset = 0x314, 1451 .route_val = BIT(16 + 14), 1452 }, { 1453 /* mac_rxd0_m1 */ 1454 .bank_num = 4, 1455 .pin = 2, 1456 .func = 2, 1457 .route_offset = 0x314, 1458 .route_val = BIT(16 + 14) | BIT(14), 1459 }, { 1460 /* uart3_rx */ 1461 .bank_num = 3, 1462 .pin = 12, 1463 .func = 4, 1464 .route_offset = 0x314, 1465 .route_val = BIT(16 + 15), 1466 }, { 1467 /* uart3_rx_m1 */ 1468 .bank_num = 0, 1469 .pin = 17, 1470 .func = 3, 1471 .route_offset = 0x314, 1472 .route_val = BIT(16 + 15) | BIT(15), 1473 }, 1474 }; 1475 1476 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1477 { 1478 /* uart2dbg_rxm0 */ 1479 .bank_num = 1, 1480 .pin = 1, 1481 .func = 2, 1482 .route_offset = 0x50, 1483 .route_val = BIT(16) | BIT(16 + 1), 1484 }, { 1485 /* uart2dbg_rxm1 */ 1486 .bank_num = 2, 1487 .pin = 1, 1488 .func = 1, 1489 .route_offset = 0x50, 1490 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1491 }, { 1492 /* gmac-m1_rxd0 */ 1493 .bank_num = 1, 1494 .pin = 11, 1495 .func = 2, 1496 .route_offset = 0x50, 1497 .route_val = BIT(16 + 2) | BIT(2), 1498 }, { 1499 /* gmac-m1-optimized_rxd3 */ 1500 .bank_num = 1, 1501 .pin = 14, 1502 .func = 2, 1503 .route_offset = 0x50, 1504 .route_val = BIT(16 + 10) | BIT(10), 1505 }, { 1506 /* pdm_sdi0m0 */ 1507 .bank_num = 2, 1508 .pin = 19, 1509 .func = 2, 1510 .route_offset = 0x50, 1511 .route_val = BIT(16 + 3), 1512 }, { 1513 /* pdm_sdi0m1 */ 1514 .bank_num = 1, 1515 .pin = 23, 1516 .func = 3, 1517 .route_offset = 0x50, 1518 .route_val = BIT(16 + 3) | BIT(3), 1519 }, { 1520 /* spi_rxdm2 */ 1521 .bank_num = 3, 1522 .pin = 2, 1523 .func = 4, 1524 .route_offset = 0x50, 1525 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1526 }, { 1527 /* i2s2_sdim0 */ 1528 .bank_num = 1, 1529 .pin = 24, 1530 .func = 1, 1531 .route_offset = 0x50, 1532 .route_val = BIT(16 + 6), 1533 }, { 1534 /* i2s2_sdim1 */ 1535 .bank_num = 3, 1536 .pin = 2, 1537 .func = 6, 1538 .route_offset = 0x50, 1539 .route_val = BIT(16 + 6) | BIT(6), 1540 }, { 1541 /* card_iom1 */ 1542 .bank_num = 2, 1543 .pin = 22, 1544 .func = 3, 1545 .route_offset = 0x50, 1546 .route_val = BIT(16 + 7) | BIT(7), 1547 }, { 1548 /* tsp_d5m1 */ 1549 .bank_num = 2, 1550 .pin = 16, 1551 .func = 3, 1552 .route_offset = 0x50, 1553 .route_val = BIT(16 + 8) | BIT(8), 1554 }, { 1555 /* cif_data5m1 */ 1556 .bank_num = 2, 1557 .pin = 16, 1558 .func = 4, 1559 .route_offset = 0x50, 1560 .route_val = BIT(16 + 9) | BIT(9), 1561 }, 1562 }; 1563 1564 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1565 { 1566 /* uart2dbga_rx */ 1567 .bank_num = 4, 1568 .pin = 8, 1569 .func = 2, 1570 .route_offset = 0xe21c, 1571 .route_val = BIT(16 + 10) | BIT(16 + 11), 1572 }, { 1573 /* uart2dbgb_rx */ 1574 .bank_num = 4, 1575 .pin = 16, 1576 .func = 2, 1577 .route_offset = 0xe21c, 1578 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1579 }, { 1580 /* uart2dbgc_rx */ 1581 .bank_num = 4, 1582 .pin = 19, 1583 .func = 1, 1584 .route_offset = 0xe21c, 1585 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1586 }, { 1587 /* pcie_clkreqn */ 1588 .bank_num = 2, 1589 .pin = 26, 1590 .func = 2, 1591 .route_offset = 0xe21c, 1592 .route_val = BIT(16 + 14), 1593 }, { 1594 /* pcie_clkreqnb */ 1595 .bank_num = 4, 1596 .pin = 24, 1597 .func = 1, 1598 .route_offset = 0xe21c, 1599 .route_val = BIT(16 + 14) | BIT(14), 1600 }, 1601 }; 1602 1603 static enum rockchip_pin_route_type 1604 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1605 int mux, u32 *reg, u32 *value) 1606 { 1607 struct rockchip_pinctrl_priv *priv = bank->priv; 1608 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1609 struct rockchip_mux_route_data *data; 1610 int i; 1611 1612 for (i = 0; i < ctrl->niomux_routes; i++) { 1613 data = &ctrl->iomux_routes[i]; 1614 if ((data->bank_num == bank->bank_num) && 1615 (data->pin == pin) && (data->func == mux)) 1616 break; 1617 } 1618 1619 if (i >= ctrl->niomux_routes) 1620 return ROUTE_TYPE_INVALID; 1621 1622 *reg = data->route_offset; 1623 *value = data->route_val; 1624 1625 return data->route_type; 1626 } 1627 1628 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1629 { 1630 struct rockchip_pinctrl_priv *priv = bank->priv; 1631 int iomux_num = (pin / 8); 1632 struct regmap *regmap; 1633 unsigned int val; 1634 int reg, ret, mask, mux_type; 1635 u8 bit; 1636 1637 if (iomux_num > 3) 1638 return -EINVAL; 1639 1640 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1641 debug("pin %d is unrouted\n", pin); 1642 return -EINVAL; 1643 } 1644 1645 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1646 return RK_FUNC_GPIO; 1647 1648 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1649 regmap = priv->regmap_pmu; 1650 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1651 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 1652 else 1653 regmap = priv->regmap_base; 1654 1655 /* get basic quadrupel of mux registers and the correct reg inside */ 1656 mux_type = bank->iomux[iomux_num].type; 1657 reg = bank->iomux[iomux_num].offset; 1658 if (mux_type & IOMUX_WIDTH_4BIT) { 1659 if ((pin % 8) >= 4) 1660 reg += 0x4; 1661 bit = (pin % 4) * 4; 1662 mask = 0xf; 1663 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1664 if ((pin % 8) >= 5) 1665 reg += 0x4; 1666 bit = (pin % 8 % 5) * 3; 1667 mask = 0x7; 1668 } else { 1669 bit = (pin % 8) * 2; 1670 mask = 0x3; 1671 } 1672 1673 if (bank->recalced_mask & BIT(pin)) 1674 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1675 1676 ret = regmap_read(regmap, reg, &val); 1677 if (ret) 1678 return ret; 1679 1680 return ((val >> bit) & mask); 1681 } 1682 1683 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1684 int index) 1685 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1686 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1687 1688 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1689 } 1690 1691 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1692 int pin, int mux) 1693 { 1694 int iomux_num = (pin / 8); 1695 1696 if (iomux_num > 3) 1697 return -EINVAL; 1698 1699 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1700 debug("pin %d is unrouted\n", pin); 1701 return -EINVAL; 1702 } 1703 1704 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1705 if (mux != IOMUX_GPIO_ONLY) { 1706 debug("pin %d only supports a gpio mux\n", pin); 1707 return -ENOTSUPP; 1708 } 1709 } 1710 1711 return 0; 1712 } 1713 1714 /* 1715 * Set a new mux function for a pin. 1716 * 1717 * The register is divided into the upper and lower 16 bit. When changing 1718 * a value, the previous register value is not read and changed. Instead 1719 * it seems the changed bits are marked in the upper 16 bit, while the 1720 * changed value gets set in the same offset in the lower 16 bit. 1721 * All pin settings seem to be 2 bit wide in both the upper and lower 1722 * parts. 1723 * @bank: pin bank to change 1724 * @pin: pin to change 1725 * @mux: new mux function to set 1726 */ 1727 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1728 { 1729 struct rockchip_pinctrl_priv *priv = bank->priv; 1730 int iomux_num = (pin / 8); 1731 struct regmap *regmap; 1732 int reg, ret, mask, mux_type; 1733 u8 bit; 1734 u32 data; 1735 1736 ret = rockchip_verify_mux(bank, pin, mux); 1737 if (ret < 0) 1738 return ret; 1739 1740 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1741 return 0; 1742 1743 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1744 1745 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1746 regmap = priv->regmap_pmu; 1747 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1748 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 1749 else 1750 regmap = priv->regmap_base; 1751 1752 /* get basic quadrupel of mux registers and the correct reg inside */ 1753 mux_type = bank->iomux[iomux_num].type; 1754 reg = bank->iomux[iomux_num].offset; 1755 if (mux_type & IOMUX_WIDTH_4BIT) { 1756 if ((pin % 8) >= 4) 1757 reg += 0x4; 1758 bit = (pin % 4) * 4; 1759 mask = 0xf; 1760 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1761 if ((pin % 8) >= 5) 1762 reg += 0x4; 1763 bit = (pin % 8 % 5) * 3; 1764 mask = 0x7; 1765 } else { 1766 bit = (pin % 8) * 2; 1767 mask = 0x3; 1768 } 1769 1770 if (bank->recalced_mask & BIT(pin)) 1771 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1772 1773 if (bank->route_mask & BIT(pin)) { 1774 u32 route_reg = 0, route_val = 0; 1775 1776 ret = rockchip_get_mux_route(bank, pin, mux, 1777 &route_reg, &route_val); 1778 switch (ret) { 1779 case ROUTE_TYPE_DEFAULT: 1780 regmap_write(regmap, route_reg, route_val); 1781 break; 1782 case ROUTE_TYPE_TOPGRF: 1783 regmap_write(priv->regmap_base, route_reg, route_val); 1784 break; 1785 case ROUTE_TYPE_PMUGRF: 1786 regmap_write(priv->regmap_pmu, route_reg, route_val); 1787 break; 1788 case ROUTE_TYPE_INVALID: /* Fall through */ 1789 default: 1790 break; 1791 } 1792 } 1793 1794 if (mux_type & IOMUX_WRITABLE_32BIT) { 1795 regmap_read(regmap, reg, &data); 1796 data &= ~(mask << bit); 1797 } else { 1798 data = (mask << (bit + 16)); 1799 } 1800 1801 data |= (mux & mask) << bit; 1802 ret = regmap_write(regmap, reg, data); 1803 1804 return ret; 1805 } 1806 1807 #define PX30_PULL_PMU_OFFSET 0x10 1808 #define PX30_PULL_GRF_OFFSET 0x60 1809 #define PX30_PULL_BITS_PER_PIN 2 1810 #define PX30_PULL_PINS_PER_REG 8 1811 #define PX30_PULL_BANK_STRIDE 16 1812 1813 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1814 int pin_num, struct regmap **regmap, 1815 int *reg, u8 *bit) 1816 { 1817 struct rockchip_pinctrl_priv *priv = bank->priv; 1818 1819 /* The first 32 pins of the first bank are located in PMU */ 1820 if (bank->bank_num == 0) { 1821 *regmap = priv->regmap_pmu; 1822 *reg = PX30_PULL_PMU_OFFSET; 1823 } else { 1824 *regmap = priv->regmap_base; 1825 *reg = PX30_PULL_GRF_OFFSET; 1826 1827 /* correct the offset, as we're starting with the 2nd bank */ 1828 *reg -= 0x10; 1829 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1830 } 1831 1832 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1833 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1834 *bit *= PX30_PULL_BITS_PER_PIN; 1835 } 1836 1837 #define PX30_DRV_PMU_OFFSET 0x20 1838 #define PX30_DRV_GRF_OFFSET 0xf0 1839 #define PX30_DRV_BITS_PER_PIN 2 1840 #define PX30_DRV_PINS_PER_REG 8 1841 #define PX30_DRV_BANK_STRIDE 16 1842 1843 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1844 int pin_num, struct regmap **regmap, 1845 int *reg, u8 *bit) 1846 { 1847 struct rockchip_pinctrl_priv *priv = bank->priv; 1848 1849 /* The first 32 pins of the first bank are located in PMU */ 1850 if (bank->bank_num == 0) { 1851 *regmap = priv->regmap_pmu; 1852 *reg = PX30_DRV_PMU_OFFSET; 1853 } else { 1854 *regmap = priv->regmap_base; 1855 *reg = PX30_DRV_GRF_OFFSET; 1856 1857 /* correct the offset, as we're starting with the 2nd bank */ 1858 *reg -= 0x10; 1859 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1860 } 1861 1862 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1863 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1864 *bit *= PX30_DRV_BITS_PER_PIN; 1865 } 1866 1867 #define PX30_SCHMITT_PMU_OFFSET 0x38 1868 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1869 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1870 #define PX30_SCHMITT_BANK_STRIDE 16 1871 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1872 1873 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1874 int pin_num, 1875 struct regmap **regmap, 1876 int *reg, u8 *bit) 1877 { 1878 struct rockchip_pinctrl_priv *priv = bank->priv; 1879 int pins_per_reg; 1880 1881 if (bank->bank_num == 0) { 1882 *regmap = priv->regmap_pmu; 1883 *reg = PX30_SCHMITT_PMU_OFFSET; 1884 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1885 } else { 1886 *regmap = priv->regmap_base; 1887 *reg = PX30_SCHMITT_GRF_OFFSET; 1888 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1889 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1890 } 1891 *reg += ((pin_num / pins_per_reg) * 4); 1892 *bit = pin_num % pins_per_reg; 1893 1894 return 0; 1895 } 1896 1897 #define RV1108_PULL_PMU_OFFSET 0x10 1898 #define RV1108_PULL_OFFSET 0x110 1899 #define RV1108_PULL_PINS_PER_REG 8 1900 #define RV1108_PULL_BITS_PER_PIN 2 1901 #define RV1108_PULL_BANK_STRIDE 16 1902 1903 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1904 int pin_num, struct regmap **regmap, 1905 int *reg, u8 *bit) 1906 { 1907 struct rockchip_pinctrl_priv *priv = bank->priv; 1908 1909 /* The first 24 pins of the first bank are located in PMU */ 1910 if (bank->bank_num == 0) { 1911 *regmap = priv->regmap_pmu; 1912 *reg = RV1108_PULL_PMU_OFFSET; 1913 } else { 1914 *reg = RV1108_PULL_OFFSET; 1915 *regmap = priv->regmap_base; 1916 /* correct the offset, as we're starting with the 2nd bank */ 1917 *reg -= 0x10; 1918 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1919 } 1920 1921 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1922 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1923 *bit *= RV1108_PULL_BITS_PER_PIN; 1924 } 1925 1926 #define RV1108_DRV_PMU_OFFSET 0x20 1927 #define RV1108_DRV_GRF_OFFSET 0x210 1928 #define RV1108_DRV_BITS_PER_PIN 2 1929 #define RV1108_DRV_PINS_PER_REG 8 1930 #define RV1108_DRV_BANK_STRIDE 16 1931 1932 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1933 int pin_num, struct regmap **regmap, 1934 int *reg, u8 *bit) 1935 { 1936 struct rockchip_pinctrl_priv *priv = bank->priv; 1937 1938 /* The first 24 pins of the first bank are located in PMU */ 1939 if (bank->bank_num == 0) { 1940 *regmap = priv->regmap_pmu; 1941 *reg = RV1108_DRV_PMU_OFFSET; 1942 } else { 1943 *regmap = priv->regmap_base; 1944 *reg = RV1108_DRV_GRF_OFFSET; 1945 1946 /* correct the offset, as we're starting with the 2nd bank */ 1947 *reg -= 0x10; 1948 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1949 } 1950 1951 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1952 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1953 *bit *= RV1108_DRV_BITS_PER_PIN; 1954 } 1955 1956 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1957 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1958 #define RV1108_SCHMITT_BANK_STRIDE 8 1959 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1960 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1961 1962 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1963 int pin_num, 1964 struct regmap **regmap, 1965 int *reg, u8 *bit) 1966 { 1967 struct rockchip_pinctrl_priv *priv = bank->priv; 1968 int pins_per_reg; 1969 1970 if (bank->bank_num == 0) { 1971 *regmap = priv->regmap_pmu; 1972 *reg = RV1108_SCHMITT_PMU_OFFSET; 1973 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1974 } else { 1975 *regmap = priv->regmap_base; 1976 *reg = RV1108_SCHMITT_GRF_OFFSET; 1977 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1978 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1979 } 1980 *reg += ((pin_num / pins_per_reg) * 4); 1981 *bit = pin_num % pins_per_reg; 1982 1983 return 0; 1984 } 1985 1986 #define RV1126_PULL_PMU_OFFSET 0x40 1987 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 1988 #define RV1126_PULL_PINS_PER_REG 8 1989 #define RV1126_PULL_BITS_PER_PIN 2 1990 #define RV1126_PULL_BANK_STRIDE 16 1991 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 1992 1993 static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1994 int pin_num, struct regmap **regmap, 1995 int *reg, u8 *bit) 1996 { 1997 struct rockchip_pinctrl_priv *priv = bank->priv; 1998 1999 /* The first 24 pins of the first bank are located in PMU */ 2000 if (bank->bank_num == 0) { 2001 if (RV1126_GPIO_C4_D7(pin_num)) { 2002 *regmap = priv->regmap_base; 2003 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 2004 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 2005 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 2006 *bit *= RV1126_PULL_BITS_PER_PIN; 2007 return; 2008 } 2009 *regmap = priv->regmap_pmu; 2010 *reg = RV1126_PULL_PMU_OFFSET; 2011 } else { 2012 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 2013 *regmap = priv->regmap_base; 2014 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; 2015 } 2016 2017 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 2018 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 2019 *bit *= RV1126_PULL_BITS_PER_PIN; 2020 } 2021 2022 #define RV1126_DRV_PMU_OFFSET 0x20 2023 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 2024 #define RV1126_DRV_BITS_PER_PIN 4 2025 #define RV1126_DRV_PINS_PER_REG 4 2026 #define RV1126_DRV_BANK_STRIDE 32 2027 2028 static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2029 int pin_num, struct regmap **regmap, 2030 int *reg, u8 *bit) 2031 { 2032 struct rockchip_pinctrl_priv *priv = bank->priv; 2033 2034 /* The first 24 pins of the first bank are located in PMU */ 2035 if (bank->bank_num == 0) { 2036 if (RV1126_GPIO_C4_D7(pin_num)) { 2037 *regmap = priv->regmap_base; 2038 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 2039 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 2040 *reg -= 0x4; 2041 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 2042 *bit *= RV1126_DRV_BITS_PER_PIN; 2043 return; 2044 } 2045 *regmap = priv->regmap_pmu; 2046 *reg = RV1126_DRV_PMU_OFFSET; 2047 } else { 2048 *regmap = priv->regmap_base; 2049 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 2050 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; 2051 } 2052 2053 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 2054 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 2055 *bit *= RV1126_DRV_BITS_PER_PIN; 2056 } 2057 2058 #define RV1126_SCHMITT_PMU_OFFSET 0x60 2059 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 2060 #define RV1126_SCHMITT_BANK_STRIDE 16 2061 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8 2062 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8 2063 2064 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2065 int pin_num, 2066 struct regmap **regmap, 2067 int *reg, u8 *bit) 2068 { 2069 struct rockchip_pinctrl_priv *priv = bank->priv; 2070 int pins_per_reg; 2071 2072 if (bank->bank_num == 0) { 2073 if (RV1126_GPIO_C4_D7(pin_num)) { 2074 *regmap = priv->regmap_base; 2075 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 2076 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 2077 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 2078 return 0; 2079 } 2080 *regmap = priv->regmap_pmu; 2081 *reg = RV1126_SCHMITT_PMU_OFFSET; 2082 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 2083 } else { 2084 *regmap = priv->regmap_base; 2085 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 2086 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 2087 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; 2088 } 2089 *reg += ((pin_num / pins_per_reg) * 4); 2090 *bit = pin_num % pins_per_reg; 2091 2092 return 0; 2093 } 2094 2095 #define RK1808_PULL_PMU_OFFSET 0x10 2096 #define RK1808_PULL_GRF_OFFSET 0x80 2097 #define RK1808_PULL_PINS_PER_REG 8 2098 #define RK1808_PULL_BITS_PER_PIN 2 2099 #define RK1808_PULL_BANK_STRIDE 16 2100 2101 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2102 int pin_num, 2103 struct regmap **regmap, 2104 int *reg, u8 *bit) 2105 { 2106 struct rockchip_pinctrl_priv *priv = bank->priv; 2107 2108 if (bank->bank_num == 0) { 2109 *regmap = priv->regmap_pmu; 2110 *reg = RK1808_PULL_PMU_OFFSET; 2111 } else { 2112 *reg = RK1808_PULL_GRF_OFFSET; 2113 *regmap = priv->regmap_base; 2114 } 2115 2116 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4); 2117 *bit = (pin_num % RK1808_PULL_PINS_PER_REG); 2118 *bit *= RK1808_PULL_BITS_PER_PIN; 2119 } 2120 2121 #define RK1808_DRV_PMU_OFFSET 0x20 2122 #define RK1808_DRV_GRF_OFFSET 0x140 2123 #define RK1808_DRV_BITS_PER_PIN 2 2124 #define RK1808_DRV_PINS_PER_REG 8 2125 #define RK1808_DRV_BANK_STRIDE 16 2126 2127 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2128 int pin_num, 2129 struct regmap **regmap, 2130 int *reg, u8 *bit) 2131 { 2132 struct rockchip_pinctrl_priv *priv = bank->priv; 2133 2134 if (bank->bank_num == 0) { 2135 *regmap = priv->regmap_pmu; 2136 *reg = RK1808_DRV_PMU_OFFSET; 2137 } else { 2138 *regmap = priv->regmap_base; 2139 *reg = RK1808_DRV_GRF_OFFSET; 2140 } 2141 2142 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4); 2143 *bit = pin_num % RK1808_DRV_PINS_PER_REG; 2144 *bit *= RK1808_DRV_BITS_PER_PIN; 2145 } 2146 2147 #define RK1808_SCHMITT_PMU_OFFSET 0x0040 2148 #define RK1808_SCHMITT_GRF_OFFSET 0x0100 2149 #define RK1808_SCHMITT_BANK_STRIDE 16 2150 #define RK1808_SCHMITT_PINS_PER_REG 8 2151 2152 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2153 int pin_num, 2154 struct regmap **regmap, 2155 int *reg, u8 *bit) 2156 { 2157 struct rockchip_pinctrl_priv *priv = bank->priv; 2158 2159 if (bank->bank_num == 0) { 2160 *regmap = priv->regmap_pmu; 2161 *reg = RK1808_SCHMITT_PMU_OFFSET; 2162 } else { 2163 *regmap = priv->regmap_base; 2164 *reg = RK1808_SCHMITT_GRF_OFFSET; 2165 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE; 2166 } 2167 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4); 2168 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG; 2169 2170 return 0; 2171 } 2172 2173 #define RK2928_PULL_OFFSET 0x118 2174 #define RK2928_PULL_PINS_PER_REG 16 2175 #define RK2928_PULL_BANK_STRIDE 8 2176 2177 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2178 int pin_num, struct regmap **regmap, 2179 int *reg, u8 *bit) 2180 { 2181 struct rockchip_pinctrl_priv *priv = bank->priv; 2182 2183 *regmap = priv->regmap_base; 2184 *reg = RK2928_PULL_OFFSET; 2185 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 2186 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 2187 2188 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 2189 }; 2190 2191 #define RK3128_PULL_OFFSET 0x118 2192 2193 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2194 int pin_num, struct regmap **regmap, 2195 int *reg, u8 *bit) 2196 { 2197 struct rockchip_pinctrl_priv *priv = bank->priv; 2198 2199 *regmap = priv->regmap_base; 2200 *reg = RK3128_PULL_OFFSET; 2201 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 2202 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 2203 2204 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 2205 } 2206 2207 #define RK3188_PULL_OFFSET 0x164 2208 #define RK3188_PULL_BITS_PER_PIN 2 2209 #define RK3188_PULL_PINS_PER_REG 8 2210 #define RK3188_PULL_BANK_STRIDE 16 2211 #define RK3188_PULL_PMU_OFFSET 0x64 2212 2213 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2214 int pin_num, struct regmap **regmap, 2215 int *reg, u8 *bit) 2216 { 2217 struct rockchip_pinctrl_priv *priv = bank->priv; 2218 2219 /* The first 12 pins of the first bank are located elsewhere */ 2220 if (bank->bank_num == 0 && pin_num < 12) { 2221 *regmap = priv->regmap_pmu; 2222 *reg = RK3188_PULL_PMU_OFFSET; 2223 2224 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2225 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2226 *bit *= RK3188_PULL_BITS_PER_PIN; 2227 } else { 2228 *regmap = priv->regmap_base; 2229 *reg = RK3188_PULL_OFFSET; 2230 2231 /* correct the offset, as it is the 2nd pull register */ 2232 *reg -= 4; 2233 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2234 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2235 2236 /* 2237 * The bits in these registers have an inverse ordering 2238 * with the lowest pin being in bits 15:14 and the highest 2239 * pin in bits 1:0 2240 */ 2241 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 2242 *bit *= RK3188_PULL_BITS_PER_PIN; 2243 } 2244 } 2245 2246 #define RK3288_PULL_OFFSET 0x140 2247 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2248 int pin_num, struct regmap **regmap, 2249 int *reg, u8 *bit) 2250 { 2251 struct rockchip_pinctrl_priv *priv = bank->priv; 2252 2253 /* The first 24 pins of the first bank are located in PMU */ 2254 if (bank->bank_num == 0) { 2255 *regmap = priv->regmap_pmu; 2256 *reg = RK3188_PULL_PMU_OFFSET; 2257 2258 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2259 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2260 *bit *= RK3188_PULL_BITS_PER_PIN; 2261 } else { 2262 *regmap = priv->regmap_base; 2263 *reg = RK3288_PULL_OFFSET; 2264 2265 /* correct the offset, as we're starting with the 2nd bank */ 2266 *reg -= 0x10; 2267 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2268 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2269 2270 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2271 *bit *= RK3188_PULL_BITS_PER_PIN; 2272 } 2273 } 2274 2275 #define RK3288_DRV_PMU_OFFSET 0x70 2276 #define RK3288_DRV_GRF_OFFSET 0x1c0 2277 #define RK3288_DRV_BITS_PER_PIN 2 2278 #define RK3288_DRV_PINS_PER_REG 8 2279 #define RK3288_DRV_BANK_STRIDE 16 2280 2281 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2282 int pin_num, struct regmap **regmap, 2283 int *reg, u8 *bit) 2284 { 2285 struct rockchip_pinctrl_priv *priv = bank->priv; 2286 2287 /* The first 24 pins of the first bank are located in PMU */ 2288 if (bank->bank_num == 0) { 2289 *regmap = priv->regmap_pmu; 2290 *reg = RK3288_DRV_PMU_OFFSET; 2291 2292 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2293 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2294 *bit *= RK3288_DRV_BITS_PER_PIN; 2295 } else { 2296 *regmap = priv->regmap_base; 2297 *reg = RK3288_DRV_GRF_OFFSET; 2298 2299 /* correct the offset, as we're starting with the 2nd bank */ 2300 *reg -= 0x10; 2301 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2302 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2303 2304 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2305 *bit *= RK3288_DRV_BITS_PER_PIN; 2306 } 2307 } 2308 2309 #define RK3228_PULL_OFFSET 0x100 2310 2311 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2312 int pin_num, struct regmap **regmap, 2313 int *reg, u8 *bit) 2314 { 2315 struct rockchip_pinctrl_priv *priv = bank->priv; 2316 2317 *regmap = priv->regmap_base; 2318 *reg = RK3228_PULL_OFFSET; 2319 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2320 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2321 2322 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2323 *bit *= RK3188_PULL_BITS_PER_PIN; 2324 } 2325 2326 #define RK3228_DRV_GRF_OFFSET 0x200 2327 2328 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2329 int pin_num, struct regmap **regmap, 2330 int *reg, u8 *bit) 2331 { 2332 struct rockchip_pinctrl_priv *priv = bank->priv; 2333 2334 *regmap = priv->regmap_base; 2335 *reg = RK3228_DRV_GRF_OFFSET; 2336 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2337 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2338 2339 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2340 *bit *= RK3288_DRV_BITS_PER_PIN; 2341 } 2342 2343 #define RK3308_PULL_OFFSET 0xa0 2344 2345 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2346 int pin_num, struct regmap **regmap, 2347 int *reg, u8 *bit) 2348 { 2349 struct rockchip_pinctrl_priv *priv = bank->priv; 2350 2351 *regmap = priv->regmap_base; 2352 *reg = RK3308_PULL_OFFSET; 2353 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2354 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2355 2356 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2357 *bit *= RK3188_PULL_BITS_PER_PIN; 2358 } 2359 2360 #define RK3308_DRV_GRF_OFFSET 0x100 2361 2362 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2363 int pin_num, struct regmap **regmap, 2364 int *reg, u8 *bit) 2365 { 2366 struct rockchip_pinctrl_priv *priv = bank->priv; 2367 2368 *regmap = priv->regmap_base; 2369 *reg = RK3308_DRV_GRF_OFFSET; 2370 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2371 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2372 2373 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2374 *bit *= RK3288_DRV_BITS_PER_PIN; 2375 } 2376 2377 #define RK3308_SCHMITT_PINS_PER_REG 8 2378 #define RK3308_SCHMITT_BANK_STRIDE 16 2379 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 2380 2381 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2382 int pin_num, 2383 struct regmap **regmap, 2384 int *reg, u8 *bit) 2385 { 2386 struct rockchip_pinctrl_priv *priv = bank->priv; 2387 2388 *regmap = priv->regmap_base; 2389 *reg = RK3308_SCHMITT_GRF_OFFSET; 2390 2391 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 2392 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 2393 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 2394 2395 return 0; 2396 } 2397 2398 #define RK3368_PULL_GRF_OFFSET 0x100 2399 #define RK3368_PULL_PMU_OFFSET 0x10 2400 2401 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2402 int pin_num, struct regmap **regmap, 2403 int *reg, u8 *bit) 2404 { 2405 struct rockchip_pinctrl_priv *priv = bank->priv; 2406 2407 /* The first 32 pins of the first bank are located in PMU */ 2408 if (bank->bank_num == 0) { 2409 *regmap = priv->regmap_pmu; 2410 *reg = RK3368_PULL_PMU_OFFSET; 2411 2412 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2413 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2414 *bit *= RK3188_PULL_BITS_PER_PIN; 2415 } else { 2416 *regmap = priv->regmap_base; 2417 *reg = RK3368_PULL_GRF_OFFSET; 2418 2419 /* correct the offset, as we're starting with the 2nd bank */ 2420 *reg -= 0x10; 2421 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2422 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2423 2424 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2425 *bit *= RK3188_PULL_BITS_PER_PIN; 2426 } 2427 } 2428 2429 #define RK3368_DRV_PMU_OFFSET 0x20 2430 #define RK3368_DRV_GRF_OFFSET 0x200 2431 2432 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2433 int pin_num, struct regmap **regmap, 2434 int *reg, u8 *bit) 2435 { 2436 struct rockchip_pinctrl_priv *priv = bank->priv; 2437 2438 /* The first 32 pins of the first bank are located in PMU */ 2439 if (bank->bank_num == 0) { 2440 *regmap = priv->regmap_pmu; 2441 *reg = RK3368_DRV_PMU_OFFSET; 2442 2443 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2444 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2445 *bit *= RK3288_DRV_BITS_PER_PIN; 2446 } else { 2447 *regmap = priv->regmap_base; 2448 *reg = RK3368_DRV_GRF_OFFSET; 2449 2450 /* correct the offset, as we're starting with the 2nd bank */ 2451 *reg -= 0x10; 2452 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2453 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2454 2455 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2456 *bit *= RK3288_DRV_BITS_PER_PIN; 2457 } 2458 } 2459 2460 #define RK3399_PULL_GRF_OFFSET 0xe040 2461 #define RK3399_PULL_PMU_OFFSET 0x40 2462 #define RK3399_DRV_3BITS_PER_PIN 3 2463 2464 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2465 int pin_num, struct regmap **regmap, 2466 int *reg, u8 *bit) 2467 { 2468 struct rockchip_pinctrl_priv *priv = bank->priv; 2469 2470 /* The bank0:16 and bank1:32 pins are located in PMU */ 2471 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2472 *regmap = priv->regmap_pmu; 2473 *reg = RK3399_PULL_PMU_OFFSET; 2474 2475 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2476 2477 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2478 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2479 *bit *= RK3188_PULL_BITS_PER_PIN; 2480 } else { 2481 *regmap = priv->regmap_base; 2482 *reg = RK3399_PULL_GRF_OFFSET; 2483 2484 /* correct the offset, as we're starting with the 3rd bank */ 2485 *reg -= 0x20; 2486 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2487 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2488 2489 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2490 *bit *= RK3188_PULL_BITS_PER_PIN; 2491 } 2492 } 2493 2494 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2495 int pin_num, struct regmap **regmap, 2496 int *reg, u8 *bit) 2497 { 2498 struct rockchip_pinctrl_priv *priv = bank->priv; 2499 int drv_num = (pin_num / 8); 2500 2501 /* The bank0:16 and bank1:32 pins are located in PMU */ 2502 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2503 *regmap = priv->regmap_pmu; 2504 else 2505 *regmap = priv->regmap_base; 2506 2507 *reg = bank->drv[drv_num].offset; 2508 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2509 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2510 *bit = (pin_num % 8) * 3; 2511 else 2512 *bit = (pin_num % 8) * 2; 2513 } 2514 2515 #define RK3308_SLEW_RATE_GRF_OFFSET 0x150 2516 #define RK3308_SLEW_RATE_BANK_STRIDE 16 2517 #define RK3308_SLEW_RATE_PINS_PER_GRF_REG 8 2518 2519 static void rk3308_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, 2520 int pin_num, 2521 struct regmap **regmap, 2522 int *reg, u8 *bit) 2523 { 2524 struct rockchip_pinctrl_priv *priv = bank->priv; 2525 int pins_per_reg; 2526 2527 *regmap = priv->regmap_base; 2528 *reg = RK3308_SLEW_RATE_GRF_OFFSET; 2529 *reg += (bank->bank_num) * RK3308_SLEW_RATE_BANK_STRIDE; 2530 pins_per_reg = RK3308_SLEW_RATE_PINS_PER_GRF_REG; 2531 2532 *reg += ((pin_num / pins_per_reg) * 4); 2533 *bit = pin_num % pins_per_reg; 2534 } 2535 2536 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2537 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2538 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2539 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2540 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2541 { 4, 7, 10, 13, 16, 19, 22, 26 }, 2542 { 0, 2, 4, 6, 6, 8, 10, 12 } 2543 }; 2544 2545 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2546 int pin_num, int strength) 2547 { 2548 struct rockchip_pinctrl_priv *priv = bank->priv; 2549 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2550 struct regmap *regmap; 2551 int reg, ret, i; 2552 u32 data, rmask_bits, temp; 2553 u8 bit; 2554 /* Where need to clean the special mask for rockchip_perpin_drv_list */ 2555 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); 2556 2557 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 2558 pin_num, strength); 2559 2560 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2561 if (ctrl->type == RV1126) { 2562 rmask_bits = RV1126_DRV_BITS_PER_PIN; 2563 ret = strength; 2564 goto config; 2565 } 2566 if (soc_is_rk3308bs()) 2567 drv_type = DRV_TYPE_IO_SMIC; 2568 2569 ret = -EINVAL; 2570 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2571 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2572 ret = i; 2573 break; 2574 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2575 ret = rockchip_perpin_drv_list[drv_type][i]; 2576 break; 2577 } 2578 } 2579 2580 if (ret < 0) { 2581 debug("unsupported driver strength %d\n", strength); 2582 return ret; 2583 } 2584 2585 switch (drv_type) { 2586 case DRV_TYPE_IO_SMIC: 2587 if (ctrl->type == RK3308) { /* RK3308B-S */ 2588 int regval = ret; 2589 2590 data = 0x3 << (bit + 16); 2591 data |= ((regval & 0x3) << bit); 2592 2593 ret = regmap_write(regmap, reg, data); 2594 if (ret < 0) 2595 return ret; 2596 2597 rk3308_calc_slew_rate_reg_and_bit(bank, pin_num, ®map, ®, &bit); 2598 data = BIT(bit + 16) | (((regval > 3) ? 1 : 0) << bit); 2599 2600 return regmap_write(regmap, reg, data); 2601 } 2602 2603 dev_err(info->dev, "unsupported type DRV_TYPE_IO_SMIC\n"); 2604 return -EINVAL; 2605 case DRV_TYPE_IO_1V8_3V0_AUTO: 2606 case DRV_TYPE_IO_3V3_ONLY: 2607 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2608 switch (bit) { 2609 case 0 ... 12: 2610 /* regular case, nothing to do */ 2611 break; 2612 case 15: 2613 /* 2614 * drive-strength offset is special, as it is spread 2615 * over 2 registers, the bit data[15] contains bit 0 2616 * of the value while temp[1:0] contains bits 2 and 1 2617 */ 2618 data = (ret & 0x1) << 15; 2619 temp = (ret >> 0x1) & 0x3; 2620 2621 data |= BIT(31); 2622 ret = regmap_write(regmap, reg, data); 2623 if (ret) 2624 return ret; 2625 2626 temp |= (0x3 << 16); 2627 reg += 0x4; 2628 ret = regmap_write(regmap, reg, temp); 2629 2630 return ret; 2631 case 18 ... 21: 2632 /* setting fully enclosed in the second register */ 2633 reg += 4; 2634 bit -= 16; 2635 break; 2636 default: 2637 debug("unsupported bit: %d for pinctrl drive type: %d\n", 2638 bit, drv_type); 2639 return -EINVAL; 2640 } 2641 break; 2642 case DRV_TYPE_IO_DEFAULT: 2643 case DRV_TYPE_IO_1V8_OR_3V0: 2644 case DRV_TYPE_IO_1V8_ONLY: 2645 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2646 break; 2647 default: 2648 debug("unsupported pinctrl drive type: %d\n", 2649 drv_type); 2650 return -EINVAL; 2651 } 2652 2653 config: 2654 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 2655 regmap_read(regmap, reg, &data); 2656 data &= ~(((1 << rmask_bits) - 1) << bit); 2657 } else { 2658 /* enable the write to the equivalent lower bits */ 2659 data = ((1 << rmask_bits) - 1) << (bit + 16); 2660 } 2661 2662 data |= (ret << bit); 2663 ret = regmap_write(regmap, reg, data); 2664 return ret; 2665 } 2666 2667 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2668 { 2669 PIN_CONFIG_BIAS_DISABLE, 2670 PIN_CONFIG_BIAS_PULL_UP, 2671 PIN_CONFIG_BIAS_PULL_DOWN, 2672 PIN_CONFIG_BIAS_BUS_HOLD 2673 }, 2674 { 2675 PIN_CONFIG_BIAS_DISABLE, 2676 PIN_CONFIG_BIAS_PULL_DOWN, 2677 PIN_CONFIG_BIAS_DISABLE, 2678 PIN_CONFIG_BIAS_PULL_UP 2679 }, 2680 }; 2681 2682 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2683 int pin_num, int pull) 2684 { 2685 struct rockchip_pinctrl_priv *priv = bank->priv; 2686 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2687 struct regmap *regmap; 2688 int reg, ret, i, pull_type; 2689 u8 bit; 2690 u32 data; 2691 2692 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 2693 pin_num, pull); 2694 2695 /* rk3066b does support any pulls */ 2696 if (ctrl->type == RK3066B) 2697 return pull ? -EINVAL : 0; 2698 2699 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2700 2701 switch (ctrl->type) { 2702 case RK2928: 2703 case RK3128: 2704 data = BIT(bit + 16); 2705 if (pull == PIN_CONFIG_BIAS_DISABLE) 2706 data |= BIT(bit); 2707 ret = regmap_write(regmap, reg, data); 2708 break; 2709 case PX30: 2710 case RV1108: 2711 case RV1126: 2712 case RK1808: 2713 case RK3188: 2714 case RK3288: 2715 case RK3308: 2716 case RK3368: 2717 case RK3399: 2718 /* 2719 * Where need to clean the special mask for 2720 * rockchip_pull_list. 2721 */ 2722 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); 2723 ret = -EINVAL; 2724 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2725 i++) { 2726 if (rockchip_pull_list[pull_type][i] == pull) { 2727 ret = i; 2728 break; 2729 } 2730 } 2731 2732 if (ret < 0) { 2733 debug("unsupported pull setting %d\n", pull); 2734 return ret; 2735 } 2736 2737 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 2738 regmap_read(regmap, reg, &data); 2739 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); 2740 } else { 2741 /* enable the write to the equivalent lower bits */ 2742 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2743 } 2744 2745 data |= (ret << bit); 2746 ret = regmap_write(regmap, reg, data); 2747 break; 2748 default: 2749 debug("unsupported pinctrl type\n"); 2750 return -EINVAL; 2751 } 2752 2753 return ret; 2754 } 2755 2756 #define RK3328_SCHMITT_BITS_PER_PIN 1 2757 #define RK3328_SCHMITT_PINS_PER_REG 16 2758 #define RK3328_SCHMITT_BANK_STRIDE 8 2759 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2760 2761 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2762 int pin_num, 2763 struct regmap **regmap, 2764 int *reg, u8 *bit) 2765 { 2766 struct rockchip_pinctrl_priv *priv = bank->priv; 2767 2768 *regmap = priv->regmap_base; 2769 *reg = RK3328_SCHMITT_GRF_OFFSET; 2770 2771 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2772 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2773 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2774 2775 return 0; 2776 } 2777 2778 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2779 int pin_num, int enable) 2780 { 2781 struct rockchip_pinctrl_priv *priv = bank->priv; 2782 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2783 struct regmap *regmap; 2784 int reg, ret; 2785 u8 bit; 2786 u32 data; 2787 2788 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 2789 pin_num, enable); 2790 2791 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2792 if (ret) 2793 return ret; 2794 2795 /* enable the write to the equivalent lower bits */ 2796 data = BIT(bit + 16) | (enable << bit); 2797 2798 return regmap_write(regmap, reg, data); 2799 } 2800 2801 #define PX30_SLEW_RATE_PMU_OFFSET 0x30 2802 #define PX30_SLEW_RATE_GRF_OFFSET 0x90 2803 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16 2804 #define PX30_SLEW_RATE_BANK_STRIDE 16 2805 #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8 2806 2807 static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, 2808 int pin_num, 2809 struct regmap **regmap, 2810 int *reg, u8 *bit) 2811 { 2812 struct rockchip_pinctrl_priv *priv = bank->priv; 2813 int pins_per_reg; 2814 2815 if (bank->bank_num == 0) { 2816 *regmap = priv->regmap_pmu; 2817 *reg = PX30_SLEW_RATE_PMU_OFFSET; 2818 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 2819 } else { 2820 *regmap = priv->regmap_base; 2821 *reg = PX30_SCHMITT_GRF_OFFSET; 2822 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 2823 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 2824 } 2825 *reg += ((pin_num / pins_per_reg) * 4); 2826 *bit = pin_num % pins_per_reg; 2827 2828 return 0; 2829 } 2830 2831 static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank, 2832 int pin_num, int speed) 2833 { 2834 struct rockchip_pinctrl_priv *priv = bank->priv; 2835 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2836 struct regmap *regmap; 2837 int reg, ret; 2838 u8 bit; 2839 u32 data; 2840 2841 debug("setting slew rate of GPIO%d-%d to %d\n", bank->bank_num, 2842 pin_num, speed); 2843 2844 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit); 2845 if (ret) 2846 return ret; 2847 2848 /* enable the write to the equivalent lower bits */ 2849 data = BIT(bit + 16) | (speed << bit); 2850 2851 return regmap_write(regmap, reg, data); 2852 } 2853 2854 /* 2855 * Pinconf_ops handling 2856 */ 2857 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2858 unsigned int pull) 2859 { 2860 switch (ctrl->type) { 2861 case RK2928: 2862 case RK3128: 2863 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2864 pull == PIN_CONFIG_BIAS_DISABLE); 2865 case RK3066B: 2866 return pull ? false : true; 2867 case PX30: 2868 case RV1108: 2869 case RV1126: 2870 case RK1808: 2871 case RK3188: 2872 case RK3288: 2873 case RK3308: 2874 case RK3368: 2875 case RK3399: 2876 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2877 } 2878 2879 return false; 2880 } 2881 2882 /* set the pin config settings for a specified pin */ 2883 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 2884 u32 pin, u32 param, u32 arg) 2885 { 2886 struct rockchip_pinctrl_priv *priv = bank->priv; 2887 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2888 int rc; 2889 2890 switch (param) { 2891 case PIN_CONFIG_BIAS_DISABLE: 2892 rc = rockchip_set_pull(bank, pin, param); 2893 if (rc) 2894 return rc; 2895 break; 2896 2897 case PIN_CONFIG_BIAS_PULL_UP: 2898 case PIN_CONFIG_BIAS_PULL_DOWN: 2899 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2900 case PIN_CONFIG_BIAS_BUS_HOLD: 2901 if (!rockchip_pinconf_pull_valid(ctrl, param)) 2902 return -ENOTSUPP; 2903 2904 if (!arg) 2905 return -EINVAL; 2906 2907 rc = rockchip_set_pull(bank, pin, param); 2908 if (rc) 2909 return rc; 2910 break; 2911 2912 case PIN_CONFIG_DRIVE_STRENGTH: 2913 if (!ctrl->drv_calc_reg) 2914 return -ENOTSUPP; 2915 2916 rc = rockchip_set_drive_perpin(bank, pin, arg); 2917 if (rc < 0) 2918 return rc; 2919 break; 2920 2921 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2922 if (!ctrl->schmitt_calc_reg) 2923 return -ENOTSUPP; 2924 2925 rc = rockchip_set_schmitt(bank, pin, arg); 2926 if (rc < 0) 2927 return rc; 2928 break; 2929 2930 case PIN_CONFIG_SLEW_RATE: 2931 if (!ctrl->slew_rate_calc_reg) 2932 return -ENOTSUPP; 2933 2934 rc = rockchip_set_slew_rate(bank, 2935 pin - bank->pin_base, arg); 2936 if (rc < 0) 2937 return rc; 2938 break; 2939 2940 default: 2941 break; 2942 } 2943 2944 return 0; 2945 } 2946 2947 static const struct pinconf_param rockchip_conf_params[] = { 2948 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 2949 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 2950 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 2951 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 2952 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 2953 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 2954 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 2955 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 2956 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 2957 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, 2958 }; 2959 2960 static int rockchip_pinconf_prop_name_to_param(const char *property, 2961 u32 *default_value) 2962 { 2963 const struct pinconf_param *p, *end; 2964 2965 p = rockchip_conf_params; 2966 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 2967 2968 /* See if this pctldev supports this parameter */ 2969 for (; p < end; p++) { 2970 if (!strcmp(property, p->property)) { 2971 *default_value = p->default_value; 2972 return p->param; 2973 } 2974 } 2975 2976 *default_value = 0; 2977 return -EPERM; 2978 } 2979 2980 static int rockchip_pinctrl_set_state(struct udevice *dev, 2981 struct udevice *config) 2982 { 2983 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2984 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2985 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 2986 u32 bank, pin, mux, conf, arg, default_val; 2987 int ret, count, i; 2988 const char *prop_name; 2989 const void *value; 2990 int prop_len, param; 2991 const u32 *data; 2992 ofnode node; 2993 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 2994 const struct device_node *np; 2995 struct property *pp; 2996 #else 2997 int property_offset, pcfg_node; 2998 const void *blob = gd->fdt_blob; 2999 #endif 3000 data = dev_read_prop(config, "rockchip,pins", &count); 3001 if (count < 0) { 3002 debug("%s: bad array size %d\n", __func__, count); 3003 return -EINVAL; 3004 } 3005 3006 count /= sizeof(u32); 3007 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 3008 debug("%s: unsupported pins array count %d\n", 3009 __func__, count); 3010 return -EINVAL; 3011 } 3012 3013 for (i = 0; i < count; i++) 3014 cells[i] = fdt32_to_cpu(data[i]); 3015 3016 for (i = 0; i < (count >> 2); i++) { 3017 bank = cells[4 * i + 0]; 3018 pin = cells[4 * i + 1]; 3019 mux = cells[4 * i + 2]; 3020 conf = cells[4 * i + 3]; 3021 3022 ret = rockchip_verify_config(dev, bank, pin); 3023 if (ret) 3024 return ret; 3025 3026 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 3027 if (ret) 3028 return ret; 3029 3030 node = ofnode_get_by_phandle(conf); 3031 if (!ofnode_valid(node)) 3032 return -ENODEV; 3033 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 3034 np = ofnode_to_np(node); 3035 for (pp = np->properties; pp; pp = pp->next) { 3036 prop_name = pp->name; 3037 prop_len = pp->length; 3038 value = pp->value; 3039 #else 3040 pcfg_node = ofnode_to_offset(node); 3041 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 3042 value = fdt_getprop_by_offset(blob, property_offset, 3043 &prop_name, &prop_len); 3044 if (!value) 3045 return -ENOENT; 3046 #endif 3047 param = rockchip_pinconf_prop_name_to_param(prop_name, 3048 &default_val); 3049 if (param < 0) 3050 break; 3051 3052 if (prop_len >= sizeof(fdt32_t)) 3053 arg = fdt32_to_cpu(*(fdt32_t *)value); 3054 else 3055 arg = default_val; 3056 3057 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 3058 param, arg); 3059 if (ret) { 3060 debug("%s: rockchip_pinconf_set fail: %d\n", 3061 __func__, ret); 3062 return ret; 3063 } 3064 } 3065 } 3066 3067 return 0; 3068 } 3069 3070 static int rockchip_pinctrl_get_pins_count(struct udevice *dev) 3071 { 3072 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 3073 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 3074 3075 return ctrl->nr_pins; 3076 } 3077 3078 static struct pinctrl_ops rockchip_pinctrl_ops = { 3079 .get_pins_count = rockchip_pinctrl_get_pins_count, 3080 .set_state = rockchip_pinctrl_set_state, 3081 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 3082 }; 3083 3084 static const struct rockchip_pin_ctrl rk3308b_pin_ctrl; 3085 3086 /* retrieve the soc specific data */ 3087 static const struct rockchip_pin_ctrl * 3088 rockchip_pinctrl_get_soc_data(struct udevice *dev) 3089 { 3090 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 3091 const struct rockchip_pin_ctrl *ctrl = 3092 (const struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 3093 struct rockchip_pin_bank *bank; 3094 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3095 u32 nr_pins; 3096 3097 if (soc_is_rk3308b() || soc_is_rk3308bs()) 3098 ctrl = &rk3308b_pin_ctrl; 3099 3100 grf_offs = ctrl->grf_mux_offset; 3101 pmu_offs = ctrl->pmu_mux_offset; 3102 drv_pmu_offs = ctrl->pmu_drv_offset; 3103 drv_grf_offs = ctrl->grf_drv_offset; 3104 bank = ctrl->pin_banks; 3105 3106 /* Ctrl data re-initialize for some Socs */ 3107 if (ctrl->ctrl_data_re_init) { 3108 if (ctrl->ctrl_data_re_init(ctrl)) 3109 return NULL; 3110 } 3111 3112 nr_pins = 0; 3113 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3114 int bank_pins = 0; 3115 3116 bank->priv = priv; 3117 bank->pin_base = nr_pins; 3118 nr_pins += bank->nr_pins; 3119 3120 /* calculate iomux and drv offsets */ 3121 for (j = 0; j < 4; j++) { 3122 struct rockchip_iomux *iom = &bank->iomux[j]; 3123 struct rockchip_drv *drv = &bank->drv[j]; 3124 int inc; 3125 3126 if (bank_pins >= bank->nr_pins) 3127 break; 3128 3129 /* preset iomux offset value, set new start value */ 3130 if (iom->offset >= 0) { 3131 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 3132 pmu_offs = iom->offset; 3133 else 3134 grf_offs = iom->offset; 3135 } else { /* set current iomux offset */ 3136 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || 3137 (iom->type & IOMUX_L_SOURCE_PMU)) ? 3138 pmu_offs : grf_offs; 3139 } 3140 3141 /* preset drv offset value, set new start value */ 3142 if (drv->offset >= 0) { 3143 if (iom->type & IOMUX_SOURCE_PMU) 3144 drv_pmu_offs = drv->offset; 3145 else 3146 drv_grf_offs = drv->offset; 3147 } else { /* set current drv offset */ 3148 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3149 drv_pmu_offs : drv_grf_offs; 3150 } 3151 3152 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3153 i, j, iom->offset, drv->offset); 3154 3155 /* 3156 * Increase offset according to iomux width. 3157 * 4bit iomux'es are spread over two registers. 3158 */ 3159 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3160 IOMUX_WIDTH_3BIT | 3161 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 3162 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 3163 pmu_offs += inc; 3164 else 3165 grf_offs += inc; 3166 3167 /* 3168 * Increase offset according to drv width. 3169 * 3bit drive-strenth'es are spread over two registers. 3170 */ 3171 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3172 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3173 inc = 8; 3174 else 3175 inc = 4; 3176 3177 if (iom->type & IOMUX_SOURCE_PMU) 3178 drv_pmu_offs += inc; 3179 else 3180 drv_grf_offs += inc; 3181 3182 bank_pins += 8; 3183 } 3184 3185 /* calculate the per-bank recalced_mask */ 3186 for (j = 0; j < ctrl->niomux_recalced; j++) { 3187 int pin = 0; 3188 3189 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3190 pin = ctrl->iomux_recalced[j].pin; 3191 bank->recalced_mask |= BIT(pin); 3192 } 3193 } 3194 3195 /* calculate the per-bank route_mask */ 3196 for (j = 0; j < ctrl->niomux_routes; j++) { 3197 int pin = 0; 3198 3199 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3200 pin = ctrl->iomux_routes[j].pin; 3201 bank->route_mask |= BIT(pin); 3202 } 3203 } 3204 } 3205 3206 WARN_ON(nr_pins != ctrl->nr_pins); 3207 3208 return ctrl; 3209 } 3210 3211 /* SoC data specially handle */ 3212 3213 /* rk3308b SoC data initialize */ 3214 #define RK3308B_GRF_SOC_CON13 0x608 3215 #define RK3308B_GRF_SOC_CON15 0x610 3216 3217 /* RK3308B_GRF_SOC_CON13 */ 3218 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) 3219 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 3220 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 3221 3222 /* RK3308B_GRF_SOC_CON15 */ 3223 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) 3224 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 3225 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 3226 3227 static int rk3308b_soc_data_init(struct rockchip_pinctrl_priv *priv) 3228 { 3229 int ret; 3230 3231 /* 3232 * Enable the special ctrl of selected sources. 3233 */ 3234 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13, 3235 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | 3236 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | 3237 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); 3238 if (ret) 3239 return ret; 3240 3241 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15, 3242 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | 3243 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | 3244 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); 3245 if (ret) 3246 return ret; 3247 3248 return 0; 3249 } 3250 3251 static int rockchip_pinctrl_probe(struct udevice *dev) 3252 { 3253 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 3254 const struct rockchip_pin_ctrl *ctrl; 3255 struct udevice *syscon; 3256 struct regmap *regmap; 3257 int ret = 0; 3258 3259 /* get rockchip grf syscon phandle */ 3260 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 3261 &syscon); 3262 if (ret) { 3263 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 3264 return ret; 3265 } 3266 3267 /* get grf-reg base address */ 3268 regmap = syscon_get_regmap(syscon); 3269 if (!regmap) { 3270 debug("unable to find rockchip grf regmap\n"); 3271 return -ENODEV; 3272 } 3273 priv->regmap_base = regmap; 3274 3275 /* option: get pmu-reg base address */ 3276 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 3277 &syscon); 3278 if (!ret) { 3279 /* get pmugrf-reg base address */ 3280 regmap = syscon_get_regmap(syscon); 3281 if (!regmap) { 3282 debug("unable to find rockchip pmu regmap\n"); 3283 return -ENODEV; 3284 } 3285 priv->regmap_pmu = regmap; 3286 } 3287 3288 ctrl = rockchip_pinctrl_get_soc_data(dev); 3289 if (!ctrl) { 3290 debug("driver data not available\n"); 3291 return -EINVAL; 3292 } 3293 3294 /* Special handle for some Socs */ 3295 if (ctrl->soc_data_init) { 3296 ret = ctrl->soc_data_init(priv); 3297 if (ret) 3298 return ret; 3299 } 3300 3301 priv->ctrl = (struct rockchip_pin_ctrl *)ctrl; 3302 return 0; 3303 } 3304 3305 static struct rockchip_pin_bank px30_pin_banks[] = { 3306 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3307 IOMUX_SOURCE_PMU, 3308 IOMUX_SOURCE_PMU, 3309 IOMUX_SOURCE_PMU 3310 ), 3311 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3312 IOMUX_WIDTH_4BIT, 3313 IOMUX_WIDTH_4BIT, 3314 IOMUX_WIDTH_4BIT 3315 ), 3316 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3317 IOMUX_WIDTH_4BIT, 3318 IOMUX_WIDTH_4BIT, 3319 IOMUX_WIDTH_4BIT 3320 ), 3321 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3322 IOMUX_WIDTH_4BIT, 3323 IOMUX_WIDTH_4BIT, 3324 IOMUX_WIDTH_4BIT 3325 ), 3326 }; 3327 3328 static const struct rockchip_pin_ctrl px30_pin_ctrl = { 3329 .pin_banks = px30_pin_banks, 3330 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3331 .nr_pins = 128, 3332 .label = "PX30-GPIO", 3333 .type = PX30, 3334 .grf_mux_offset = 0x0, 3335 .pmu_mux_offset = 0x0, 3336 .iomux_routes = px30_mux_route_data, 3337 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3338 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3339 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3340 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3341 .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit, 3342 }; 3343 3344 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3345 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3346 IOMUX_SOURCE_PMU, 3347 IOMUX_SOURCE_PMU, 3348 IOMUX_SOURCE_PMU), 3349 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3350 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3351 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3352 }; 3353 3354 static const struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3355 .pin_banks = rv1108_pin_banks, 3356 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3357 .nr_pins = 128, 3358 .label = "RV1108-GPIO", 3359 .type = RV1108, 3360 .grf_mux_offset = 0x10, 3361 .pmu_mux_offset = 0x0, 3362 .iomux_recalced = rv1108_mux_recalced_data, 3363 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3364 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3365 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3366 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3367 }; 3368 3369 static struct rockchip_pin_bank rv1126_pin_banks[] = { 3370 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3371 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3372 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3373 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 3374 IOMUX_WIDTH_4BIT), 3375 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 3376 IOMUX_WIDTH_4BIT, 3377 IOMUX_WIDTH_4BIT, 3378 IOMUX_WIDTH_4BIT, 3379 IOMUX_WIDTH_4BIT, 3380 0x10010, 0x10018, 0x10020, 0x10028), 3381 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3382 IOMUX_WIDTH_4BIT, 3383 IOMUX_WIDTH_4BIT, 3384 IOMUX_WIDTH_4BIT, 3385 IOMUX_WIDTH_4BIT), 3386 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3387 IOMUX_WIDTH_4BIT, 3388 IOMUX_WIDTH_4BIT, 3389 IOMUX_WIDTH_4BIT, 3390 IOMUX_WIDTH_4BIT), 3391 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 3392 IOMUX_WIDTH_4BIT, 0, 0, 0), 3393 }; 3394 3395 static const struct rockchip_pin_ctrl rv1126_pin_ctrl = { 3396 .pin_banks = rv1126_pin_banks, 3397 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 3398 .nr_pins = 130, 3399 .label = "RV1126-GPIO", 3400 .type = RV1126, 3401 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 3402 .pmu_mux_offset = 0x0, 3403 .iomux_routes = rv1126_mux_route_data, 3404 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), 3405 .iomux_recalced = rv1126_mux_recalced_data, 3406 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 3407 .pull_calc_reg = rv1126_calc_pull_reg_and_bit, 3408 .drv_calc_reg = rv1126_calc_drv_reg_and_bit, 3409 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit, 3410 }; 3411 3412 static struct rockchip_pin_bank rk1808_pin_banks[] = { 3413 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3414 IOMUX_SOURCE_PMU, 3415 IOMUX_SOURCE_PMU, 3416 IOMUX_SOURCE_PMU, 3417 IOMUX_SOURCE_PMU), 3418 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 3419 IOMUX_WIDTH_4BIT, 3420 IOMUX_WIDTH_4BIT, 3421 IOMUX_WIDTH_4BIT, 3422 IOMUX_WIDTH_4BIT), 3423 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3424 IOMUX_WIDTH_4BIT, 3425 IOMUX_WIDTH_4BIT, 3426 IOMUX_WIDTH_4BIT, 3427 IOMUX_WIDTH_4BIT), 3428 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3429 IOMUX_WIDTH_4BIT, 3430 IOMUX_WIDTH_4BIT, 3431 IOMUX_WIDTH_4BIT, 3432 IOMUX_WIDTH_4BIT), 3433 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", 3434 IOMUX_WIDTH_4BIT, 3435 IOMUX_WIDTH_4BIT, 3436 IOMUX_WIDTH_4BIT, 3437 IOMUX_WIDTH_4BIT), 3438 }; 3439 3440 static const struct rockchip_pin_ctrl rk1808_pin_ctrl = { 3441 .pin_banks = rk1808_pin_banks, 3442 .nr_banks = ARRAY_SIZE(rk1808_pin_banks), 3443 .nr_pins = 160, 3444 .label = "RK1808-GPIO", 3445 .type = RK1808, 3446 .iomux_routes = rk1808_mux_route_data, 3447 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data), 3448 .grf_mux_offset = 0x0, 3449 .pmu_mux_offset = 0x0, 3450 .pull_calc_reg = rk1808_calc_pull_reg_and_bit, 3451 .drv_calc_reg = rk1808_calc_drv_reg_and_bit, 3452 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit, 3453 }; 3454 3455 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3456 PIN_BANK(0, 32, "gpio0"), 3457 PIN_BANK(1, 32, "gpio1"), 3458 PIN_BANK(2, 32, "gpio2"), 3459 PIN_BANK(3, 32, "gpio3"), 3460 }; 3461 3462 static const struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3463 .pin_banks = rk2928_pin_banks, 3464 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3465 .nr_pins = 128, 3466 .label = "RK2928-GPIO", 3467 .type = RK2928, 3468 .grf_mux_offset = 0xa8, 3469 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3470 }; 3471 3472 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3473 PIN_BANK(0, 32, "gpio0"), 3474 PIN_BANK(1, 32, "gpio1"), 3475 PIN_BANK(2, 32, "gpio2"), 3476 }; 3477 3478 static const struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3479 .pin_banks = rk3036_pin_banks, 3480 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3481 .nr_pins = 96, 3482 .label = "RK3036-GPIO", 3483 .type = RK2928, 3484 .grf_mux_offset = 0xa8, 3485 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3486 }; 3487 3488 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3489 PIN_BANK(0, 32, "gpio0"), 3490 PIN_BANK(1, 32, "gpio1"), 3491 PIN_BANK(2, 32, "gpio2"), 3492 PIN_BANK(3, 32, "gpio3"), 3493 PIN_BANK(4, 32, "gpio4"), 3494 PIN_BANK(6, 16, "gpio6"), 3495 }; 3496 3497 static const struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3498 .pin_banks = rk3066a_pin_banks, 3499 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3500 .nr_pins = 176, 3501 .label = "RK3066a-GPIO", 3502 .type = RK2928, 3503 .grf_mux_offset = 0xa8, 3504 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3505 }; 3506 3507 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3508 PIN_BANK(0, 32, "gpio0"), 3509 PIN_BANK(1, 32, "gpio1"), 3510 PIN_BANK(2, 32, "gpio2"), 3511 PIN_BANK(3, 32, "gpio3"), 3512 }; 3513 3514 static const struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3515 .pin_banks = rk3066b_pin_banks, 3516 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3517 .nr_pins = 128, 3518 .label = "RK3066b-GPIO", 3519 .type = RK3066B, 3520 .grf_mux_offset = 0x60, 3521 }; 3522 3523 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3524 PIN_BANK(0, 32, "gpio0"), 3525 PIN_BANK(1, 32, "gpio1"), 3526 PIN_BANK(2, 32, "gpio2"), 3527 PIN_BANK(3, 32, "gpio3"), 3528 }; 3529 3530 static const struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3531 .pin_banks = rk3128_pin_banks, 3532 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3533 .nr_pins = 128, 3534 .label = "RK3128-GPIO", 3535 .type = RK3128, 3536 .grf_mux_offset = 0xa8, 3537 .iomux_recalced = rk3128_mux_recalced_data, 3538 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3539 .iomux_routes = rk3128_mux_route_data, 3540 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3541 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3542 }; 3543 3544 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3545 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3546 PIN_BANK(1, 32, "gpio1"), 3547 PIN_BANK(2, 32, "gpio2"), 3548 PIN_BANK(3, 32, "gpio3"), 3549 }; 3550 3551 static const struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3552 .pin_banks = rk3188_pin_banks, 3553 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3554 .nr_pins = 128, 3555 .label = "RK3188-GPIO", 3556 .type = RK3188, 3557 .grf_mux_offset = 0x60, 3558 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3559 }; 3560 3561 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3562 PIN_BANK(0, 32, "gpio0"), 3563 PIN_BANK(1, 32, "gpio1"), 3564 PIN_BANK(2, 32, "gpio2"), 3565 PIN_BANK(3, 32, "gpio3"), 3566 }; 3567 3568 static const struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3569 .pin_banks = rk3228_pin_banks, 3570 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3571 .nr_pins = 128, 3572 .label = "RK3228-GPIO", 3573 .type = RK3288, 3574 .grf_mux_offset = 0x0, 3575 .iomux_routes = rk3228_mux_route_data, 3576 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3577 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3578 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3579 }; 3580 3581 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3582 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 3583 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3584 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3585 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3586 IOMUX_UNROUTED, 3587 DRV_TYPE_WRITABLE_32BIT, 3588 DRV_TYPE_WRITABLE_32BIT, 3589 DRV_TYPE_WRITABLE_32BIT, 3590 0, 3591 PULL_TYPE_WRITABLE_32BIT, 3592 PULL_TYPE_WRITABLE_32BIT, 3593 PULL_TYPE_WRITABLE_32BIT, 3594 0 3595 ), 3596 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3597 IOMUX_UNROUTED, 3598 IOMUX_UNROUTED, 3599 0 3600 ), 3601 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3602 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3603 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3604 IOMUX_WIDTH_4BIT, 3605 0, 3606 0 3607 ), 3608 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3609 0, 3610 0, 3611 IOMUX_UNROUTED 3612 ), 3613 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3614 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3615 0, 3616 IOMUX_WIDTH_4BIT, 3617 IOMUX_UNROUTED 3618 ), 3619 PIN_BANK(8, 16, "gpio8"), 3620 }; 3621 3622 static const struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3623 .pin_banks = rk3288_pin_banks, 3624 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3625 .nr_pins = 264, 3626 .label = "RK3288-GPIO", 3627 .type = RK3288, 3628 .grf_mux_offset = 0x0, 3629 .pmu_mux_offset = 0x84, 3630 .iomux_routes = rk3288_mux_route_data, 3631 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3632 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3633 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3634 }; 3635 3636 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3637 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 3638 IOMUX_8WIDTH_2BIT, 3639 IOMUX_8WIDTH_2BIT, 3640 IOMUX_8WIDTH_2BIT), 3641 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 3642 IOMUX_8WIDTH_2BIT, 3643 IOMUX_8WIDTH_2BIT, 3644 IOMUX_8WIDTH_2BIT), 3645 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 3646 IOMUX_8WIDTH_2BIT, 3647 IOMUX_8WIDTH_2BIT, 3648 IOMUX_8WIDTH_2BIT), 3649 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 3650 IOMUX_8WIDTH_2BIT, 3651 IOMUX_8WIDTH_2BIT, 3652 IOMUX_8WIDTH_2BIT), 3653 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 3654 IOMUX_8WIDTH_2BIT, 3655 IOMUX_8WIDTH_2BIT, 3656 IOMUX_8WIDTH_2BIT), 3657 }; 3658 3659 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3660 .pin_banks = rk3308_pin_banks, 3661 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3662 .nr_pins = 160, 3663 .label = "RK3308-GPIO", 3664 .type = RK3308, 3665 .grf_mux_offset = 0x0, 3666 .iomux_recalced = rk3308_mux_recalced_data, 3667 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3668 .iomux_routes = rk3308_mux_route_data, 3669 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3670 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3671 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3672 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3673 }; 3674 3675 static const struct rockchip_pin_ctrl rk3308b_pin_ctrl = { 3676 .pin_banks = rk3308_pin_banks, 3677 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3678 .nr_pins = 160, 3679 .label = "RK3308-GPIO", 3680 .type = RK3308, 3681 .grf_mux_offset = 0x0, 3682 .iomux_recalced = rk3308b_mux_recalced_data, 3683 .niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data), 3684 .iomux_routes = rk3308b_mux_route_data, 3685 .niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data), 3686 .soc_data_init = rk3308b_soc_data_init, 3687 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3688 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3689 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3690 }; 3691 3692 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3693 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3694 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3695 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3696 IOMUX_8WIDTH_2BIT, 3697 IOMUX_WIDTH_3BIT, 3698 0), 3699 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3700 IOMUX_WIDTH_3BIT, 3701 IOMUX_WIDTH_3BIT, 3702 0, 3703 0), 3704 }; 3705 3706 static const struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3707 .pin_banks = rk3328_pin_banks, 3708 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3709 .nr_pins = 128, 3710 .label = "RK3328-GPIO", 3711 .type = RK3288, 3712 .grf_mux_offset = 0x0, 3713 .iomux_recalced = rk3328_mux_recalced_data, 3714 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3715 .iomux_routes = rk3328_mux_route_data, 3716 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3717 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3718 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3719 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3720 }; 3721 3722 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3723 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3724 IOMUX_SOURCE_PMU, 3725 IOMUX_SOURCE_PMU, 3726 IOMUX_SOURCE_PMU 3727 ), 3728 PIN_BANK(1, 32, "gpio1"), 3729 PIN_BANK(2, 32, "gpio2"), 3730 PIN_BANK(3, 32, "gpio3"), 3731 }; 3732 3733 static const struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3734 .pin_banks = rk3368_pin_banks, 3735 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3736 .nr_pins = 128, 3737 .label = "RK3368-GPIO", 3738 .type = RK3368, 3739 .grf_mux_offset = 0x0, 3740 .pmu_mux_offset = 0x0, 3741 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3742 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3743 }; 3744 3745 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3746 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3747 IOMUX_SOURCE_PMU, 3748 IOMUX_SOURCE_PMU, 3749 IOMUX_SOURCE_PMU, 3750 IOMUX_SOURCE_PMU, 3751 DRV_TYPE_IO_1V8_ONLY, 3752 DRV_TYPE_IO_1V8_ONLY, 3753 DRV_TYPE_IO_DEFAULT, 3754 DRV_TYPE_IO_DEFAULT, 3755 0x80, 3756 0x88, 3757 -1, 3758 -1, 3759 PULL_TYPE_IO_1V8_ONLY, 3760 PULL_TYPE_IO_1V8_ONLY, 3761 PULL_TYPE_IO_DEFAULT, 3762 PULL_TYPE_IO_DEFAULT 3763 ), 3764 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3765 IOMUX_SOURCE_PMU, 3766 IOMUX_SOURCE_PMU, 3767 IOMUX_SOURCE_PMU, 3768 DRV_TYPE_IO_1V8_OR_3V0, 3769 DRV_TYPE_IO_1V8_OR_3V0, 3770 DRV_TYPE_IO_1V8_OR_3V0, 3771 DRV_TYPE_IO_1V8_OR_3V0, 3772 0xa0, 3773 0xa8, 3774 0xb0, 3775 0xb8 3776 ), 3777 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3778 DRV_TYPE_IO_1V8_OR_3V0, 3779 DRV_TYPE_IO_1V8_ONLY, 3780 DRV_TYPE_IO_1V8_ONLY, 3781 PULL_TYPE_IO_DEFAULT, 3782 PULL_TYPE_IO_DEFAULT, 3783 PULL_TYPE_IO_1V8_ONLY, 3784 PULL_TYPE_IO_1V8_ONLY 3785 ), 3786 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3787 DRV_TYPE_IO_3V3_ONLY, 3788 DRV_TYPE_IO_3V3_ONLY, 3789 DRV_TYPE_IO_1V8_OR_3V0 3790 ), 3791 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3792 DRV_TYPE_IO_1V8_3V0_AUTO, 3793 DRV_TYPE_IO_1V8_OR_3V0, 3794 DRV_TYPE_IO_1V8_OR_3V0 3795 ), 3796 }; 3797 3798 static const struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3799 .pin_banks = rk3399_pin_banks, 3800 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3801 .nr_pins = 160, 3802 .label = "RK3399-GPIO", 3803 .type = RK3399, 3804 .grf_mux_offset = 0xe000, 3805 .pmu_mux_offset = 0x0, 3806 .grf_drv_offset = 0xe100, 3807 .pmu_drv_offset = 0x80, 3808 .iomux_routes = rk3399_mux_route_data, 3809 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3810 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3811 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3812 }; 3813 3814 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 3815 { .compatible = "rockchip,px30-pinctrl", 3816 .data = (ulong)&px30_pin_ctrl }, 3817 { .compatible = "rockchip,rv1108-pinctrl", 3818 .data = (ulong)&rv1108_pin_ctrl }, 3819 { .compatible = "rockchip,rv1126-pinctrl-legency", 3820 .data = (ulong)&rv1126_pin_ctrl }, 3821 { .compatible = "rockchip,rk1808-pinctrl", 3822 .data = (ulong)&rk1808_pin_ctrl }, 3823 { .compatible = "rockchip,rk2928-pinctrl", 3824 .data = (ulong)&rk2928_pin_ctrl }, 3825 { .compatible = "rockchip,rk3036-pinctrl", 3826 .data = (ulong)&rk3036_pin_ctrl }, 3827 { .compatible = "rockchip,rk3066a-pinctrl", 3828 .data = (ulong)&rk3066a_pin_ctrl }, 3829 { .compatible = "rockchip,rk3066b-pinctrl", 3830 .data = (ulong)&rk3066b_pin_ctrl }, 3831 { .compatible = "rockchip,rk3128-pinctrl", 3832 .data = (ulong)&rk3128_pin_ctrl }, 3833 { .compatible = "rockchip,rk3188-pinctrl", 3834 .data = (ulong)&rk3188_pin_ctrl }, 3835 { .compatible = "rockchip,rk3228-pinctrl", 3836 .data = (ulong)&rk3228_pin_ctrl }, 3837 { .compatible = "rockchip,rk3288-pinctrl", 3838 .data = (ulong)&rk3288_pin_ctrl }, 3839 { .compatible = "rockchip,rk3308-pinctrl", 3840 .data = (ulong)&rk3308_pin_ctrl }, 3841 { .compatible = "rockchip,rk3328-pinctrl", 3842 .data = (ulong)&rk3328_pin_ctrl }, 3843 { .compatible = "rockchip,rk3368-pinctrl", 3844 .data = (ulong)&rk3368_pin_ctrl }, 3845 { .compatible = "rockchip,rk3399-pinctrl", 3846 .data = (ulong)&rk3399_pin_ctrl }, 3847 {}, 3848 }; 3849 3850 U_BOOT_DRIVER(pinctrl_rockchip) = { 3851 .name = "rockchip_pinctrl", 3852 .id = UCLASS_PINCTRL, 3853 .of_match = rockchip_pinctrl_dt_match, 3854 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 3855 .ops = &rockchip_pinctrl_ops, 3856 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 3857 .bind = dm_scan_fdt_dev, 3858 #endif 3859 .probe = rockchip_pinctrl_probe, 3860 }; 3861