1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 14 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 15 #define RK_FUNC_GPIO 0 16 #define MAX_ROCKCHIP_PINS_ENTRIES 30 17 18 enum rockchip_pinctrl_type { 19 PX30, 20 RV1108, 21 RK2928, 22 RK3066B, 23 RK3128, 24 RK3188, 25 RK3288, 26 RK3308, 27 RK3368, 28 RK3399, 29 }; 30 31 /** 32 * Encode variants of iomux registers into a type variable 33 */ 34 #define IOMUX_GPIO_ONLY BIT(0) 35 #define IOMUX_WIDTH_4BIT BIT(1) 36 #define IOMUX_SOURCE_PMU BIT(2) 37 #define IOMUX_UNROUTED BIT(3) 38 #define IOMUX_WIDTH_3BIT BIT(4) 39 #define IOMUX_8WIDTH_2BIT BIT(5) 40 #define IOMUX_WRITABLE_32BIT BIT(6) 41 42 /** 43 * @type: iomux variant using IOMUX_* constants 44 * @offset: if initialized to -1 it will be autocalculated, by specifying 45 * an initial offset value the relevant source offset can be reset 46 * to a new value for autocalculating the following iomux registers. 47 */ 48 struct rockchip_iomux { 49 int type; 50 int offset; 51 }; 52 53 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 54 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 55 56 /** 57 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 58 */ 59 enum rockchip_pin_drv_type { 60 DRV_TYPE_IO_DEFAULT = 0, 61 DRV_TYPE_IO_1V8_OR_3V0, 62 DRV_TYPE_IO_1V8_ONLY, 63 DRV_TYPE_IO_1V8_3V0_AUTO, 64 DRV_TYPE_IO_3V3_ONLY, 65 DRV_TYPE_MAX 66 }; 67 68 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 69 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 70 71 /** 72 * enum type index corresponding to rockchip_pull_list arrays index. 73 */ 74 enum rockchip_pin_pull_type { 75 PULL_TYPE_IO_DEFAULT = 0, 76 PULL_TYPE_IO_1V8_ONLY, 77 PULL_TYPE_MAX 78 }; 79 80 /** 81 * @drv_type: drive strength variant using rockchip_perpin_drv_type 82 * @offset: if initialized to -1 it will be autocalculated, by specifying 83 * an initial offset value the relevant source offset can be reset 84 * to a new value for autocalculating the following drive strength 85 * registers. if used chips own cal_drv func instead to calculate 86 * registers offset, the variant could be ignored. 87 */ 88 struct rockchip_drv { 89 enum rockchip_pin_drv_type drv_type; 90 int offset; 91 }; 92 93 /** 94 * @priv: common pinctrl private basedata 95 * @pin_base: first pin number 96 * @nr_pins: number of pins in this bank 97 * @name: name of the bank 98 * @bank_num: number of the bank, to account for holes 99 * @iomux: array describing the 4 iomux sources of the bank 100 * @drv: array describing the 4 drive strength sources of the bank 101 * @pull_type: array describing the 4 pull type sources of the bank 102 * @recalced_mask: bits describing the mux recalced pins of per bank 103 * @route_mask: bits describing the routing pins of per bank 104 */ 105 struct rockchip_pin_bank { 106 struct rockchip_pinctrl_priv *priv; 107 u32 pin_base; 108 u8 nr_pins; 109 char *name; 110 u8 bank_num; 111 struct rockchip_iomux iomux[4]; 112 struct rockchip_drv drv[4]; 113 enum rockchip_pin_pull_type pull_type[4]; 114 u32 recalced_mask; 115 u32 route_mask; 116 }; 117 118 #define PIN_BANK(id, pins, label) \ 119 { \ 120 .bank_num = id, \ 121 .nr_pins = pins, \ 122 .name = label, \ 123 .iomux = { \ 124 { .offset = -1 }, \ 125 { .offset = -1 }, \ 126 { .offset = -1 }, \ 127 { .offset = -1 }, \ 128 }, \ 129 } 130 131 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 132 { \ 133 .bank_num = id, \ 134 .nr_pins = pins, \ 135 .name = label, \ 136 .iomux = { \ 137 { .type = iom0, .offset = -1 }, \ 138 { .type = iom1, .offset = -1 }, \ 139 { .type = iom2, .offset = -1 }, \ 140 { .type = iom3, .offset = -1 }, \ 141 }, \ 142 } 143 144 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 145 { \ 146 .bank_num = id, \ 147 .nr_pins = pins, \ 148 .name = label, \ 149 .iomux = { \ 150 { .offset = -1 }, \ 151 { .offset = -1 }, \ 152 { .offset = -1 }, \ 153 { .offset = -1 }, \ 154 }, \ 155 .drv = { \ 156 { .drv_type = type0, .offset = -1 }, \ 157 { .drv_type = type1, .offset = -1 }, \ 158 { .drv_type = type2, .offset = -1 }, \ 159 { .drv_type = type3, .offset = -1 }, \ 160 }, \ 161 } 162 163 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 164 drv2, drv3, pull0, pull1, \ 165 pull2, pull3) \ 166 { \ 167 .bank_num = id, \ 168 .nr_pins = pins, \ 169 .name = label, \ 170 .iomux = { \ 171 { .offset = -1 }, \ 172 { .offset = -1 }, \ 173 { .offset = -1 }, \ 174 { .offset = -1 }, \ 175 }, \ 176 .drv = { \ 177 { .drv_type = drv0, .offset = -1 }, \ 178 { .drv_type = drv1, .offset = -1 }, \ 179 { .drv_type = drv2, .offset = -1 }, \ 180 { .drv_type = drv3, .offset = -1 }, \ 181 }, \ 182 .pull_type[0] = pull0, \ 183 .pull_type[1] = pull1, \ 184 .pull_type[2] = pull2, \ 185 .pull_type[3] = pull3, \ 186 } 187 188 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 189 iom2, iom3, drv0, drv1, drv2, \ 190 drv3, offset0, offset1, \ 191 offset2, offset3) \ 192 { \ 193 .bank_num = id, \ 194 .nr_pins = pins, \ 195 .name = label, \ 196 .iomux = { \ 197 { .type = iom0, .offset = -1 }, \ 198 { .type = iom1, .offset = -1 }, \ 199 { .type = iom2, .offset = -1 }, \ 200 { .type = iom3, .offset = -1 }, \ 201 }, \ 202 .drv = { \ 203 { .drv_type = drv0, .offset = offset0 }, \ 204 { .drv_type = drv1, .offset = offset1 }, \ 205 { .drv_type = drv2, .offset = offset2 }, \ 206 { .drv_type = drv3, .offset = offset3 }, \ 207 }, \ 208 } 209 210 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 211 iom2, iom3, drv0, drv1, drv2, \ 212 drv3, pull0, pull1, pull2, \ 213 pull3) \ 214 { \ 215 .bank_num = id, \ 216 .nr_pins = pins, \ 217 .name = label, \ 218 .iomux = { \ 219 { .type = iom0, .offset = -1 }, \ 220 { .type = iom1, .offset = -1 }, \ 221 { .type = iom2, .offset = -1 }, \ 222 { .type = iom3, .offset = -1 }, \ 223 }, \ 224 .drv = { \ 225 { .drv_type = drv0, .offset = -1 }, \ 226 { .drv_type = drv1, .offset = -1 }, \ 227 { .drv_type = drv2, .offset = -1 }, \ 228 { .drv_type = drv3, .offset = -1 }, \ 229 }, \ 230 .pull_type[0] = pull0, \ 231 .pull_type[1] = pull1, \ 232 .pull_type[2] = pull2, \ 233 .pull_type[3] = pull3, \ 234 } 235 236 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 237 label, iom0, iom1, iom2, \ 238 iom3, drv0, drv1, drv2, \ 239 drv3, offset0, offset1, \ 240 offset2, offset3, pull0, \ 241 pull1, pull2, pull3) \ 242 { \ 243 .bank_num = id, \ 244 .nr_pins = pins, \ 245 .name = label, \ 246 .iomux = { \ 247 { .type = iom0, .offset = -1 }, \ 248 { .type = iom1, .offset = -1 }, \ 249 { .type = iom2, .offset = -1 }, \ 250 { .type = iom3, .offset = -1 }, \ 251 }, \ 252 .drv = { \ 253 { .drv_type = drv0, .offset = offset0 }, \ 254 { .drv_type = drv1, .offset = offset1 }, \ 255 { .drv_type = drv2, .offset = offset2 }, \ 256 { .drv_type = drv3, .offset = offset3 }, \ 257 }, \ 258 .pull_type[0] = pull0, \ 259 .pull_type[1] = pull1, \ 260 .pull_type[2] = pull2, \ 261 .pull_type[3] = pull3, \ 262 } 263 264 /** 265 * struct rockchip_mux_recalced_data: represent a pin iomux data. 266 * @num: bank number. 267 * @pin: pin number. 268 * @bit: index at register. 269 * @reg: register offset. 270 * @mask: mask bit 271 */ 272 struct rockchip_mux_recalced_data { 273 u8 num; 274 u8 pin; 275 u32 reg; 276 u8 bit; 277 u8 mask; 278 }; 279 280 /** 281 * struct rockchip_mux_recalced_data: represent a pin iomux data. 282 * @bank_num: bank number. 283 * @pin: index at register or used to calc index. 284 * @func: the min pin. 285 * @route_offset: the max pin. 286 * @route_val: the register offset. 287 */ 288 struct rockchip_mux_route_data { 289 u8 bank_num; 290 u8 pin; 291 u8 func; 292 u32 route_offset; 293 u32 route_val; 294 }; 295 296 /** 297 */ 298 struct rockchip_pin_ctrl { 299 struct rockchip_pin_bank *pin_banks; 300 u32 nr_banks; 301 u32 nr_pins; 302 char *label; 303 enum rockchip_pinctrl_type type; 304 int grf_mux_offset; 305 int pmu_mux_offset; 306 int grf_drv_offset; 307 int pmu_drv_offset; 308 struct rockchip_mux_recalced_data *iomux_recalced; 309 u32 niomux_recalced; 310 struct rockchip_mux_route_data *iomux_routes; 311 u32 niomux_routes; 312 313 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 314 int pin_num, struct regmap **regmap, 315 int *reg, u8 *bit); 316 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 317 int pin_num, struct regmap **regmap, 318 int *reg, u8 *bit); 319 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 320 int pin_num, struct regmap **regmap, 321 int *reg, u8 *bit); 322 }; 323 324 /** 325 */ 326 struct rockchip_pinctrl_priv { 327 struct rockchip_pin_ctrl *ctrl; 328 struct regmap *regmap_base; 329 struct regmap *regmap_pmu; 330 331 }; 332 333 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 334 { 335 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 336 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 337 338 if (bank >= ctrl->nr_banks) { 339 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 340 return -EINVAL; 341 } 342 343 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 344 debug("pin conf pin %d >= %d\n", pin, 345 MAX_ROCKCHIP_GPIO_PER_BANK); 346 return -EINVAL; 347 } 348 349 return 0; 350 } 351 352 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 353 { 354 .num = 1, 355 .pin = 0, 356 .reg = 0x418, 357 .bit = 0, 358 .mask = 0x3 359 }, { 360 .num = 1, 361 .pin = 1, 362 .reg = 0x418, 363 .bit = 2, 364 .mask = 0x3 365 }, { 366 .num = 1, 367 .pin = 2, 368 .reg = 0x418, 369 .bit = 4, 370 .mask = 0x3 371 }, { 372 .num = 1, 373 .pin = 3, 374 .reg = 0x418, 375 .bit = 6, 376 .mask = 0x3 377 }, { 378 .num = 1, 379 .pin = 4, 380 .reg = 0x418, 381 .bit = 8, 382 .mask = 0x3 383 }, { 384 .num = 1, 385 .pin = 5, 386 .reg = 0x418, 387 .bit = 10, 388 .mask = 0x3 389 }, { 390 .num = 1, 391 .pin = 6, 392 .reg = 0x418, 393 .bit = 12, 394 .mask = 0x3 395 }, { 396 .num = 1, 397 .pin = 7, 398 .reg = 0x418, 399 .bit = 14, 400 .mask = 0x3 401 }, { 402 .num = 1, 403 .pin = 8, 404 .reg = 0x41c, 405 .bit = 0, 406 .mask = 0x3 407 }, { 408 .num = 1, 409 .pin = 9, 410 .reg = 0x41c, 411 .bit = 2, 412 .mask = 0x3 413 }, 414 }; 415 416 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 417 { 418 .num = 2, 419 .pin = 20, 420 .reg = 0xe8, 421 .bit = 0, 422 .mask = 0x7 423 }, { 424 .num = 2, 425 .pin = 21, 426 .reg = 0xe8, 427 .bit = 4, 428 .mask = 0x7 429 }, { 430 .num = 2, 431 .pin = 22, 432 .reg = 0xe8, 433 .bit = 8, 434 .mask = 0x7 435 }, { 436 .num = 2, 437 .pin = 23, 438 .reg = 0xe8, 439 .bit = 12, 440 .mask = 0x7 441 }, { 442 .num = 2, 443 .pin = 24, 444 .reg = 0xd4, 445 .bit = 12, 446 .mask = 0x7 447 }, 448 }; 449 450 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 451 { 452 .num = 1, 453 .pin = 14, 454 .reg = 0x28, 455 .bit = 12, 456 .mask = 0x7 457 }, { 458 .num = 1, 459 .pin = 15, 460 .reg = 0x2c, 461 .bit = 0, 462 .mask = 0x3 463 }, { 464 .num = 1, 465 .pin = 18, 466 .reg = 0x30, 467 .bit = 4, 468 .mask = 0x7 469 }, { 470 .num = 1, 471 .pin = 19, 472 .reg = 0x30, 473 .bit = 8, 474 .mask = 0x7 475 }, { 476 .num = 1, 477 .pin = 20, 478 .reg = 0x30, 479 .bit = 12, 480 .mask = 0x7 481 }, { 482 .num = 1, 483 .pin = 21, 484 .reg = 0x34, 485 .bit = 0, 486 .mask = 0x7 487 }, { 488 .num = 1, 489 .pin = 22, 490 .reg = 0x34, 491 .bit = 4, 492 .mask = 0x7 493 }, { 494 .num = 1, 495 .pin = 23, 496 .reg = 0x34, 497 .bit = 8, 498 .mask = 0x7 499 }, { 500 .num = 3, 501 .pin = 12, 502 .reg = 0x68, 503 .bit = 8, 504 .mask = 0x7 505 }, { 506 .num = 3, 507 .pin = 13, 508 .reg = 0x68, 509 .bit = 12, 510 .mask = 0x7 511 }, 512 }; 513 514 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 515 { 516 .num = 2, 517 .pin = 12, 518 .reg = 0x24, 519 .bit = 8, 520 .mask = 0x3 521 }, { 522 .num = 2, 523 .pin = 15, 524 .reg = 0x28, 525 .bit = 0, 526 .mask = 0x7 527 }, { 528 .num = 2, 529 .pin = 23, 530 .reg = 0x30, 531 .bit = 14, 532 .mask = 0x3 533 }, 534 }; 535 536 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 537 int *reg, u8 *bit, int *mask) 538 { 539 struct rockchip_pinctrl_priv *priv = bank->priv; 540 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 541 struct rockchip_mux_recalced_data *data; 542 int i; 543 544 for (i = 0; i < ctrl->niomux_recalced; i++) { 545 data = &ctrl->iomux_recalced[i]; 546 if (data->num == bank->bank_num && 547 data->pin == pin) 548 break; 549 } 550 551 if (i >= ctrl->niomux_recalced) 552 return; 553 554 *reg = data->reg; 555 *mask = data->mask; 556 *bit = data->bit; 557 } 558 559 static struct rockchip_mux_route_data px30_mux_route_data[] = { 560 { 561 /* cif-d2m0 */ 562 .bank_num = 2, 563 .pin = 0, 564 .func = 1, 565 .route_offset = 0x184, 566 .route_val = BIT(16 + 7), 567 }, { 568 /* cif-d2m1 */ 569 .bank_num = 3, 570 .pin = 3, 571 .func = 3, 572 .route_offset = 0x184, 573 .route_val = BIT(16 + 7) | BIT(7), 574 }, { 575 /* pdm-m0 */ 576 .bank_num = 3, 577 .pin = 22, 578 .func = 2, 579 .route_offset = 0x184, 580 .route_val = BIT(16 + 8), 581 }, { 582 /* pdm-m1 */ 583 .bank_num = 2, 584 .pin = 22, 585 .func = 1, 586 .route_offset = 0x184, 587 .route_val = BIT(16 + 8) | BIT(8), 588 }, { 589 /* uart2-rxm0 */ 590 .bank_num = 1, 591 .pin = 27, 592 .func = 2, 593 .route_offset = 0x184, 594 .route_val = BIT(16 + 10), 595 }, { 596 /* uart2-rxm1 */ 597 .bank_num = 2, 598 .pin = 14, 599 .func = 2, 600 .route_offset = 0x184, 601 .route_val = BIT(16 + 10) | BIT(10), 602 }, { 603 /* uart3-rxm0 */ 604 .bank_num = 0, 605 .pin = 17, 606 .func = 2, 607 .route_offset = 0x184, 608 .route_val = BIT(16 + 9), 609 }, { 610 /* uart3-rxm1 */ 611 .bank_num = 1, 612 .pin = 15, 613 .func = 2, 614 .route_offset = 0x184, 615 .route_val = BIT(16 + 9) | BIT(9), 616 }, 617 }; 618 619 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 620 { 621 /* spi-0 */ 622 .bank_num = 1, 623 .pin = 10, 624 .func = 1, 625 .route_offset = 0x144, 626 .route_val = BIT(16 + 3) | BIT(16 + 4), 627 }, { 628 /* spi-1 */ 629 .bank_num = 1, 630 .pin = 27, 631 .func = 3, 632 .route_offset = 0x144, 633 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 634 }, { 635 /* spi-2 */ 636 .bank_num = 0, 637 .pin = 13, 638 .func = 2, 639 .route_offset = 0x144, 640 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 641 }, { 642 /* i2s-0 */ 643 .bank_num = 1, 644 .pin = 5, 645 .func = 1, 646 .route_offset = 0x144, 647 .route_val = BIT(16 + 5), 648 }, { 649 /* i2s-1 */ 650 .bank_num = 0, 651 .pin = 14, 652 .func = 1, 653 .route_offset = 0x144, 654 .route_val = BIT(16 + 5) | BIT(5), 655 }, { 656 /* emmc-0 */ 657 .bank_num = 1, 658 .pin = 22, 659 .func = 2, 660 .route_offset = 0x144, 661 .route_val = BIT(16 + 6), 662 }, { 663 /* emmc-1 */ 664 .bank_num = 2, 665 .pin = 4, 666 .func = 2, 667 .route_offset = 0x144, 668 .route_val = BIT(16 + 6) | BIT(6), 669 }, 670 }; 671 672 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 673 { 674 /* pwm0-0 */ 675 .bank_num = 0, 676 .pin = 26, 677 .func = 1, 678 .route_offset = 0x50, 679 .route_val = BIT(16), 680 }, { 681 /* pwm0-1 */ 682 .bank_num = 3, 683 .pin = 21, 684 .func = 1, 685 .route_offset = 0x50, 686 .route_val = BIT(16) | BIT(0), 687 }, { 688 /* pwm1-0 */ 689 .bank_num = 0, 690 .pin = 27, 691 .func = 1, 692 .route_offset = 0x50, 693 .route_val = BIT(16 + 1), 694 }, { 695 /* pwm1-1 */ 696 .bank_num = 0, 697 .pin = 30, 698 .func = 2, 699 .route_offset = 0x50, 700 .route_val = BIT(16 + 1) | BIT(1), 701 }, { 702 /* pwm2-0 */ 703 .bank_num = 0, 704 .pin = 28, 705 .func = 1, 706 .route_offset = 0x50, 707 .route_val = BIT(16 + 2), 708 }, { 709 /* pwm2-1 */ 710 .bank_num = 1, 711 .pin = 12, 712 .func = 2, 713 .route_offset = 0x50, 714 .route_val = BIT(16 + 2) | BIT(2), 715 }, { 716 /* pwm3-0 */ 717 .bank_num = 3, 718 .pin = 26, 719 .func = 1, 720 .route_offset = 0x50, 721 .route_val = BIT(16 + 3), 722 }, { 723 /* pwm3-1 */ 724 .bank_num = 1, 725 .pin = 11, 726 .func = 2, 727 .route_offset = 0x50, 728 .route_val = BIT(16 + 3) | BIT(3), 729 }, { 730 /* sdio-0_d0 */ 731 .bank_num = 1, 732 .pin = 1, 733 .func = 1, 734 .route_offset = 0x50, 735 .route_val = BIT(16 + 4), 736 }, { 737 /* sdio-1_d0 */ 738 .bank_num = 3, 739 .pin = 2, 740 .func = 1, 741 .route_offset = 0x50, 742 .route_val = BIT(16 + 4) | BIT(4), 743 }, { 744 /* spi-0_rx */ 745 .bank_num = 0, 746 .pin = 13, 747 .func = 2, 748 .route_offset = 0x50, 749 .route_val = BIT(16 + 5), 750 }, { 751 /* spi-1_rx */ 752 .bank_num = 2, 753 .pin = 0, 754 .func = 2, 755 .route_offset = 0x50, 756 .route_val = BIT(16 + 5) | BIT(5), 757 }, { 758 /* emmc-0_cmd */ 759 .bank_num = 1, 760 .pin = 22, 761 .func = 2, 762 .route_offset = 0x50, 763 .route_val = BIT(16 + 7), 764 }, { 765 /* emmc-1_cmd */ 766 .bank_num = 2, 767 .pin = 4, 768 .func = 2, 769 .route_offset = 0x50, 770 .route_val = BIT(16 + 7) | BIT(7), 771 }, { 772 /* uart2-0_rx */ 773 .bank_num = 1, 774 .pin = 19, 775 .func = 2, 776 .route_offset = 0x50, 777 .route_val = BIT(16 + 8), 778 }, { 779 /* uart2-1_rx */ 780 .bank_num = 1, 781 .pin = 10, 782 .func = 2, 783 .route_offset = 0x50, 784 .route_val = BIT(16 + 8) | BIT(8), 785 }, { 786 /* uart1-0_rx */ 787 .bank_num = 1, 788 .pin = 10, 789 .func = 1, 790 .route_offset = 0x50, 791 .route_val = BIT(16 + 11), 792 }, { 793 /* uart1-1_rx */ 794 .bank_num = 3, 795 .pin = 13, 796 .func = 1, 797 .route_offset = 0x50, 798 .route_val = BIT(16 + 11) | BIT(11), 799 }, 800 }; 801 802 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 803 { 804 /* edphdmi_cecinoutt1 */ 805 .bank_num = 7, 806 .pin = 16, 807 .func = 2, 808 .route_offset = 0x264, 809 .route_val = BIT(16 + 12) | BIT(12), 810 }, { 811 /* edphdmi_cecinout */ 812 .bank_num = 7, 813 .pin = 23, 814 .func = 4, 815 .route_offset = 0x264, 816 .route_val = BIT(16 + 12), 817 }, 818 }; 819 820 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 821 { 822 /* uart2_rxm0 */ 823 .bank_num = 1, 824 .pin = 22, 825 .func = 2, 826 .route_offset = 0x314, 827 .route_val = BIT(16 + 2) | BIT(16 + 3), 828 }, { 829 /* uart2_rxm1 */ 830 .bank_num = 4, 831 .pin = 26, 832 .func = 2, 833 .route_offset = 0x314, 834 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 835 }, { 836 /* i2c3_sdam0 */ 837 .bank_num = 0, 838 .pin = 23, 839 .func = 2, 840 .route_offset = 0x314, 841 .route_val = BIT(16 + 4), 842 }, { 843 /* i2c3_sdam1 */ 844 .bank_num = 3, 845 .pin = 12, 846 .func = 2, 847 .route_offset = 0x314, 848 .route_val = BIT(16 + 4) | BIT(4), 849 }, 850 }; 851 852 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 853 { 854 /* uart2dbg_rxm0 */ 855 .bank_num = 1, 856 .pin = 1, 857 .func = 2, 858 .route_offset = 0x50, 859 .route_val = BIT(16) | BIT(16 + 1), 860 }, { 861 /* uart2dbg_rxm1 */ 862 .bank_num = 2, 863 .pin = 1, 864 .func = 1, 865 .route_offset = 0x50, 866 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 867 }, { 868 /* gmac-m1_rxd0 */ 869 .bank_num = 1, 870 .pin = 11, 871 .func = 2, 872 .route_offset = 0x50, 873 .route_val = BIT(16 + 2) | BIT(2), 874 }, { 875 /* gmac-m1-optimized_rxd3 */ 876 .bank_num = 1, 877 .pin = 14, 878 .func = 2, 879 .route_offset = 0x50, 880 .route_val = BIT(16 + 10) | BIT(10), 881 }, { 882 /* pdm_sdi0m0 */ 883 .bank_num = 2, 884 .pin = 19, 885 .func = 2, 886 .route_offset = 0x50, 887 .route_val = BIT(16 + 3), 888 }, { 889 /* pdm_sdi0m1 */ 890 .bank_num = 1, 891 .pin = 23, 892 .func = 3, 893 .route_offset = 0x50, 894 .route_val = BIT(16 + 3) | BIT(3), 895 }, { 896 /* spi_rxdm2 */ 897 .bank_num = 3, 898 .pin = 2, 899 .func = 4, 900 .route_offset = 0x50, 901 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 902 }, { 903 /* i2s2_sdim0 */ 904 .bank_num = 1, 905 .pin = 24, 906 .func = 1, 907 .route_offset = 0x50, 908 .route_val = BIT(16 + 6), 909 }, { 910 /* i2s2_sdim1 */ 911 .bank_num = 3, 912 .pin = 2, 913 .func = 6, 914 .route_offset = 0x50, 915 .route_val = BIT(16 + 6) | BIT(6), 916 }, { 917 /* card_iom1 */ 918 .bank_num = 2, 919 .pin = 22, 920 .func = 3, 921 .route_offset = 0x50, 922 .route_val = BIT(16 + 7) | BIT(7), 923 }, { 924 /* tsp_d5m1 */ 925 .bank_num = 2, 926 .pin = 16, 927 .func = 3, 928 .route_offset = 0x50, 929 .route_val = BIT(16 + 8) | BIT(8), 930 }, { 931 /* cif_data5m1 */ 932 .bank_num = 2, 933 .pin = 16, 934 .func = 4, 935 .route_offset = 0x50, 936 .route_val = BIT(16 + 9) | BIT(9), 937 }, 938 }; 939 940 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 941 { 942 /* uart2dbga_rx */ 943 .bank_num = 4, 944 .pin = 8, 945 .func = 2, 946 .route_offset = 0xe21c, 947 .route_val = BIT(16 + 10) | BIT(16 + 11), 948 }, { 949 /* uart2dbgb_rx */ 950 .bank_num = 4, 951 .pin = 16, 952 .func = 2, 953 .route_offset = 0xe21c, 954 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 955 }, { 956 /* uart2dbgc_rx */ 957 .bank_num = 4, 958 .pin = 19, 959 .func = 1, 960 .route_offset = 0xe21c, 961 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 962 }, { 963 /* pcie_clkreqn */ 964 .bank_num = 2, 965 .pin = 26, 966 .func = 2, 967 .route_offset = 0xe21c, 968 .route_val = BIT(16 + 14), 969 }, { 970 /* pcie_clkreqnb */ 971 .bank_num = 4, 972 .pin = 24, 973 .func = 1, 974 .route_offset = 0xe21c, 975 .route_val = BIT(16 + 14) | BIT(14), 976 }, 977 }; 978 979 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 980 int mux, u32 *reg, u32 *value) 981 { 982 struct rockchip_pinctrl_priv *priv = bank->priv; 983 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 984 struct rockchip_mux_route_data *data; 985 int i; 986 987 for (i = 0; i < ctrl->niomux_routes; i++) { 988 data = &ctrl->iomux_routes[i]; 989 if ((data->bank_num == bank->bank_num) && 990 (data->pin == pin) && (data->func == mux)) 991 break; 992 } 993 994 if (i >= ctrl->niomux_routes) 995 return false; 996 997 *reg = data->route_offset; 998 *value = data->route_val; 999 1000 return true; 1001 } 1002 1003 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1004 { 1005 struct rockchip_pinctrl_priv *priv = bank->priv; 1006 int iomux_num = (pin / 8); 1007 struct regmap *regmap; 1008 unsigned int val; 1009 int reg, ret, mask, mux_type; 1010 u8 bit; 1011 1012 if (iomux_num > 3) 1013 return -EINVAL; 1014 1015 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1016 debug("pin %d is unrouted\n", pin); 1017 return -EINVAL; 1018 } 1019 1020 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1021 return RK_FUNC_GPIO; 1022 1023 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1024 ? priv->regmap_pmu : priv->regmap_base; 1025 1026 /* get basic quadrupel of mux registers and the correct reg inside */ 1027 mux_type = bank->iomux[iomux_num].type; 1028 reg = bank->iomux[iomux_num].offset; 1029 if (mux_type & IOMUX_WIDTH_4BIT) { 1030 if ((pin % 8) >= 4) 1031 reg += 0x4; 1032 bit = (pin % 4) * 4; 1033 mask = 0xf; 1034 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1035 if ((pin % 8) >= 5) 1036 reg += 0x4; 1037 bit = (pin % 8 % 5) * 3; 1038 mask = 0x7; 1039 } else { 1040 bit = (pin % 8) * 2; 1041 mask = 0x3; 1042 } 1043 1044 if (bank->recalced_mask & BIT(pin)) 1045 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1046 1047 ret = regmap_read(regmap, reg, &val); 1048 if (ret) 1049 return ret; 1050 1051 return ((val >> bit) & mask); 1052 } 1053 1054 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1055 int index) 1056 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1057 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1058 1059 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1060 } 1061 1062 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1063 int pin, int mux) 1064 { 1065 int iomux_num = (pin / 8); 1066 1067 if (iomux_num > 3) 1068 return -EINVAL; 1069 1070 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1071 debug("pin %d is unrouted\n", pin); 1072 return -EINVAL; 1073 } 1074 1075 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1076 if (mux != IOMUX_GPIO_ONLY) { 1077 debug("pin %d only supports a gpio mux\n", pin); 1078 return -ENOTSUPP; 1079 } 1080 } 1081 1082 return 0; 1083 } 1084 1085 /* 1086 * Set a new mux function for a pin. 1087 * 1088 * The register is divided into the upper and lower 16 bit. When changing 1089 * a value, the previous register value is not read and changed. Instead 1090 * it seems the changed bits are marked in the upper 16 bit, while the 1091 * changed value gets set in the same offset in the lower 16 bit. 1092 * All pin settings seem to be 2 bit wide in both the upper and lower 1093 * parts. 1094 * @bank: pin bank to change 1095 * @pin: pin to change 1096 * @mux: new mux function to set 1097 */ 1098 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1099 { 1100 struct rockchip_pinctrl_priv *priv = bank->priv; 1101 int iomux_num = (pin / 8); 1102 struct regmap *regmap; 1103 int reg, ret, mask, mux_type; 1104 u8 bit; 1105 u32 data, route_reg, route_val; 1106 1107 ret = rockchip_verify_mux(bank, pin, mux); 1108 if (ret < 0) 1109 return ret; 1110 1111 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1112 return 0; 1113 1114 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1115 1116 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1117 ? priv->regmap_pmu : priv->regmap_base; 1118 1119 /* get basic quadrupel of mux registers and the correct reg inside */ 1120 mux_type = bank->iomux[iomux_num].type; 1121 reg = bank->iomux[iomux_num].offset; 1122 if (mux_type & IOMUX_WIDTH_4BIT) { 1123 if ((pin % 8) >= 4) 1124 reg += 0x4; 1125 bit = (pin % 4) * 4; 1126 mask = 0xf; 1127 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1128 if ((pin % 8) >= 5) 1129 reg += 0x4; 1130 bit = (pin % 8 % 5) * 3; 1131 mask = 0x7; 1132 } else { 1133 bit = (pin % 8) * 2; 1134 mask = 0x3; 1135 } 1136 1137 if (bank->recalced_mask & BIT(pin)) 1138 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1139 1140 if (bank->route_mask & BIT(pin)) { 1141 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1142 &route_val)) { 1143 ret = regmap_write(regmap, route_reg, route_val); 1144 if (ret) 1145 return ret; 1146 } 1147 } 1148 1149 if (mux_type & IOMUX_WRITABLE_32BIT) { 1150 regmap_read(regmap, reg, &data); 1151 data &= ~(mask << bit); 1152 } else { 1153 data = (mask << (bit + 16)); 1154 } 1155 1156 data |= (mux & mask) << bit; 1157 ret = regmap_write(regmap, reg, data); 1158 1159 return ret; 1160 } 1161 1162 #define PX30_PULL_PMU_OFFSET 0x10 1163 #define PX30_PULL_GRF_OFFSET 0x60 1164 #define PX30_PULL_BITS_PER_PIN 2 1165 #define PX30_PULL_PINS_PER_REG 8 1166 #define PX30_PULL_BANK_STRIDE 16 1167 1168 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1169 int pin_num, struct regmap **regmap, 1170 int *reg, u8 *bit) 1171 { 1172 struct rockchip_pinctrl_priv *priv = bank->priv; 1173 1174 /* The first 32 pins of the first bank are located in PMU */ 1175 if (bank->bank_num == 0) { 1176 *regmap = priv->regmap_pmu; 1177 *reg = PX30_PULL_PMU_OFFSET; 1178 } else { 1179 *regmap = priv->regmap_base; 1180 *reg = PX30_PULL_GRF_OFFSET; 1181 1182 /* correct the offset, as we're starting with the 2nd bank */ 1183 *reg -= 0x10; 1184 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1185 } 1186 1187 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1188 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1189 *bit *= PX30_PULL_BITS_PER_PIN; 1190 } 1191 1192 #define PX30_DRV_PMU_OFFSET 0x20 1193 #define PX30_DRV_GRF_OFFSET 0xf0 1194 #define PX30_DRV_BITS_PER_PIN 2 1195 #define PX30_DRV_PINS_PER_REG 8 1196 #define PX30_DRV_BANK_STRIDE 16 1197 1198 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1199 int pin_num, struct regmap **regmap, 1200 int *reg, u8 *bit) 1201 { 1202 struct rockchip_pinctrl_priv *priv = bank->priv; 1203 1204 /* The first 32 pins of the first bank are located in PMU */ 1205 if (bank->bank_num == 0) { 1206 *regmap = priv->regmap_pmu; 1207 *reg = PX30_DRV_PMU_OFFSET; 1208 } else { 1209 *regmap = priv->regmap_base; 1210 *reg = PX30_DRV_GRF_OFFSET; 1211 1212 /* correct the offset, as we're starting with the 2nd bank */ 1213 *reg -= 0x10; 1214 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1215 } 1216 1217 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1218 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1219 *bit *= PX30_DRV_BITS_PER_PIN; 1220 } 1221 1222 #define PX30_SCHMITT_PMU_OFFSET 0x38 1223 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1224 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1225 #define PX30_SCHMITT_BANK_STRIDE 16 1226 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1227 1228 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1229 int pin_num, 1230 struct regmap **regmap, 1231 int *reg, u8 *bit) 1232 { 1233 struct rockchip_pinctrl_priv *priv = bank->priv; 1234 int pins_per_reg; 1235 1236 if (bank->bank_num == 0) { 1237 *regmap = priv->regmap_pmu; 1238 *reg = PX30_SCHMITT_PMU_OFFSET; 1239 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1240 } else { 1241 *regmap = priv->regmap_base; 1242 *reg = PX30_SCHMITT_GRF_OFFSET; 1243 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1244 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1245 } 1246 *reg += ((pin_num / pins_per_reg) * 4); 1247 *bit = pin_num % pins_per_reg; 1248 1249 return 0; 1250 } 1251 1252 #define RV1108_PULL_PMU_OFFSET 0x10 1253 #define RV1108_PULL_OFFSET 0x110 1254 #define RV1108_PULL_PINS_PER_REG 8 1255 #define RV1108_PULL_BITS_PER_PIN 2 1256 #define RV1108_PULL_BANK_STRIDE 16 1257 1258 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1259 int pin_num, struct regmap **regmap, 1260 int *reg, u8 *bit) 1261 { 1262 struct rockchip_pinctrl_priv *priv = bank->priv; 1263 1264 /* The first 24 pins of the first bank are located in PMU */ 1265 if (bank->bank_num == 0) { 1266 *regmap = priv->regmap_pmu; 1267 *reg = RV1108_PULL_PMU_OFFSET; 1268 } else { 1269 *reg = RV1108_PULL_OFFSET; 1270 *regmap = priv->regmap_base; 1271 /* correct the offset, as we're starting with the 2nd bank */ 1272 *reg -= 0x10; 1273 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1274 } 1275 1276 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1277 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1278 *bit *= RV1108_PULL_BITS_PER_PIN; 1279 } 1280 1281 #define RV1108_DRV_PMU_OFFSET 0x20 1282 #define RV1108_DRV_GRF_OFFSET 0x210 1283 #define RV1108_DRV_BITS_PER_PIN 2 1284 #define RV1108_DRV_PINS_PER_REG 8 1285 #define RV1108_DRV_BANK_STRIDE 16 1286 1287 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1288 int pin_num, struct regmap **regmap, 1289 int *reg, u8 *bit) 1290 { 1291 struct rockchip_pinctrl_priv *priv = bank->priv; 1292 1293 /* The first 24 pins of the first bank are located in PMU */ 1294 if (bank->bank_num == 0) { 1295 *regmap = priv->regmap_pmu; 1296 *reg = RV1108_DRV_PMU_OFFSET; 1297 } else { 1298 *regmap = priv->regmap_base; 1299 *reg = RV1108_DRV_GRF_OFFSET; 1300 1301 /* correct the offset, as we're starting with the 2nd bank */ 1302 *reg -= 0x10; 1303 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1304 } 1305 1306 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1307 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1308 *bit *= RV1108_DRV_BITS_PER_PIN; 1309 } 1310 1311 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1312 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1313 #define RV1108_SCHMITT_BANK_STRIDE 8 1314 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1315 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1316 1317 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1318 int pin_num, 1319 struct regmap **regmap, 1320 int *reg, u8 *bit) 1321 { 1322 struct rockchip_pinctrl_priv *priv = bank->priv; 1323 int pins_per_reg; 1324 1325 if (bank->bank_num == 0) { 1326 *regmap = priv->regmap_pmu; 1327 *reg = RV1108_SCHMITT_PMU_OFFSET; 1328 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1329 } else { 1330 *regmap = priv->regmap_base; 1331 *reg = RV1108_SCHMITT_GRF_OFFSET; 1332 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1333 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1334 } 1335 *reg += ((pin_num / pins_per_reg) * 4); 1336 *bit = pin_num % pins_per_reg; 1337 1338 return 0; 1339 } 1340 1341 #define RK2928_PULL_OFFSET 0x118 1342 #define RK2928_PULL_PINS_PER_REG 16 1343 #define RK2928_PULL_BANK_STRIDE 8 1344 1345 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1346 int pin_num, struct regmap **regmap, 1347 int *reg, u8 *bit) 1348 { 1349 struct rockchip_pinctrl_priv *priv = bank->priv; 1350 1351 *regmap = priv->regmap_base; 1352 *reg = RK2928_PULL_OFFSET; 1353 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1354 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1355 1356 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1357 }; 1358 1359 #define RK3128_PULL_OFFSET 0x118 1360 1361 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1362 int pin_num, struct regmap **regmap, 1363 int *reg, u8 *bit) 1364 { 1365 struct rockchip_pinctrl_priv *priv = bank->priv; 1366 1367 *regmap = priv->regmap_base; 1368 *reg = RK3128_PULL_OFFSET; 1369 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1370 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1371 1372 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1373 } 1374 1375 #define RK3188_PULL_OFFSET 0x164 1376 #define RK3188_PULL_BITS_PER_PIN 2 1377 #define RK3188_PULL_PINS_PER_REG 8 1378 #define RK3188_PULL_BANK_STRIDE 16 1379 #define RK3188_PULL_PMU_OFFSET 0x64 1380 1381 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1382 int pin_num, struct regmap **regmap, 1383 int *reg, u8 *bit) 1384 { 1385 struct rockchip_pinctrl_priv *priv = bank->priv; 1386 1387 /* The first 12 pins of the first bank are located elsewhere */ 1388 if (bank->bank_num == 0 && pin_num < 12) { 1389 *regmap = priv->regmap_pmu; 1390 *reg = RK3188_PULL_PMU_OFFSET; 1391 1392 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1393 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1394 *bit *= RK3188_PULL_BITS_PER_PIN; 1395 } else { 1396 *regmap = priv->regmap_base; 1397 *reg = RK3188_PULL_OFFSET; 1398 1399 /* correct the offset, as it is the 2nd pull register */ 1400 *reg -= 4; 1401 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1402 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1403 1404 /* 1405 * The bits in these registers have an inverse ordering 1406 * with the lowest pin being in bits 15:14 and the highest 1407 * pin in bits 1:0 1408 */ 1409 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1410 *bit *= RK3188_PULL_BITS_PER_PIN; 1411 } 1412 } 1413 1414 #define RK3288_PULL_OFFSET 0x140 1415 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1416 int pin_num, struct regmap **regmap, 1417 int *reg, u8 *bit) 1418 { 1419 struct rockchip_pinctrl_priv *priv = bank->priv; 1420 1421 /* The first 24 pins of the first bank are located in PMU */ 1422 if (bank->bank_num == 0) { 1423 *regmap = priv->regmap_pmu; 1424 *reg = RK3188_PULL_PMU_OFFSET; 1425 1426 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1427 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1428 *bit *= RK3188_PULL_BITS_PER_PIN; 1429 } else { 1430 *regmap = priv->regmap_base; 1431 *reg = RK3288_PULL_OFFSET; 1432 1433 /* correct the offset, as we're starting with the 2nd bank */ 1434 *reg -= 0x10; 1435 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1436 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1437 1438 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1439 *bit *= RK3188_PULL_BITS_PER_PIN; 1440 } 1441 } 1442 1443 #define RK3288_DRV_PMU_OFFSET 0x70 1444 #define RK3288_DRV_GRF_OFFSET 0x1c0 1445 #define RK3288_DRV_BITS_PER_PIN 2 1446 #define RK3288_DRV_PINS_PER_REG 8 1447 #define RK3288_DRV_BANK_STRIDE 16 1448 1449 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1450 int pin_num, struct regmap **regmap, 1451 int *reg, u8 *bit) 1452 { 1453 struct rockchip_pinctrl_priv *priv = bank->priv; 1454 1455 /* The first 24 pins of the first bank are located in PMU */ 1456 if (bank->bank_num == 0) { 1457 *regmap = priv->regmap_pmu; 1458 *reg = RK3288_DRV_PMU_OFFSET; 1459 1460 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1461 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1462 *bit *= RK3288_DRV_BITS_PER_PIN; 1463 } else { 1464 *regmap = priv->regmap_base; 1465 *reg = RK3288_DRV_GRF_OFFSET; 1466 1467 /* correct the offset, as we're starting with the 2nd bank */ 1468 *reg -= 0x10; 1469 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1470 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1471 1472 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1473 *bit *= RK3288_DRV_BITS_PER_PIN; 1474 } 1475 } 1476 1477 #define RK3228_PULL_OFFSET 0x100 1478 1479 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1480 int pin_num, struct regmap **regmap, 1481 int *reg, u8 *bit) 1482 { 1483 struct rockchip_pinctrl_priv *priv = bank->priv; 1484 1485 *regmap = priv->regmap_base; 1486 *reg = RK3228_PULL_OFFSET; 1487 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1488 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1489 1490 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1491 *bit *= RK3188_PULL_BITS_PER_PIN; 1492 } 1493 1494 #define RK3228_DRV_GRF_OFFSET 0x200 1495 1496 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1497 int pin_num, struct regmap **regmap, 1498 int *reg, u8 *bit) 1499 { 1500 struct rockchip_pinctrl_priv *priv = bank->priv; 1501 1502 *regmap = priv->regmap_base; 1503 *reg = RK3228_DRV_GRF_OFFSET; 1504 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1505 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1506 1507 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1508 *bit *= RK3288_DRV_BITS_PER_PIN; 1509 } 1510 1511 #define RK3308_PULL_OFFSET 0xa0 1512 1513 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1514 int pin_num, struct regmap **regmap, 1515 int *reg, u8 *bit) 1516 { 1517 struct rockchip_pinctrl_priv *priv = bank->priv; 1518 1519 *regmap = priv->regmap_base; 1520 *reg = RK3308_PULL_OFFSET; 1521 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1522 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1523 1524 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1525 *bit *= RK3188_PULL_BITS_PER_PIN; 1526 } 1527 1528 #define RK3308_DRV_GRF_OFFSET 0x100 1529 1530 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1531 int pin_num, struct regmap **regmap, 1532 int *reg, u8 *bit) 1533 { 1534 struct rockchip_pinctrl_priv *priv = bank->priv; 1535 1536 *regmap = priv->regmap_base; 1537 *reg = RK3308_DRV_GRF_OFFSET; 1538 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1539 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1540 1541 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1542 *bit *= RK3288_DRV_BITS_PER_PIN; 1543 } 1544 1545 #define RK3308_SCHMITT_PINS_PER_REG 8 1546 #define RK3308_SCHMITT_BANK_STRIDE 16 1547 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1548 1549 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1550 int pin_num, 1551 struct regmap **regmap, 1552 int *reg, u8 *bit) 1553 { 1554 struct rockchip_pinctrl_priv *priv = bank->priv; 1555 1556 *regmap = priv->regmap_base; 1557 *reg = RK3308_SCHMITT_GRF_OFFSET; 1558 1559 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1560 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1561 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1562 1563 return 0; 1564 } 1565 1566 #define RK3368_PULL_GRF_OFFSET 0x100 1567 #define RK3368_PULL_PMU_OFFSET 0x10 1568 1569 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1570 int pin_num, struct regmap **regmap, 1571 int *reg, u8 *bit) 1572 { 1573 struct rockchip_pinctrl_priv *priv = bank->priv; 1574 1575 /* The first 32 pins of the first bank are located in PMU */ 1576 if (bank->bank_num == 0) { 1577 *regmap = priv->regmap_pmu; 1578 *reg = RK3368_PULL_PMU_OFFSET; 1579 1580 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1581 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1582 *bit *= RK3188_PULL_BITS_PER_PIN; 1583 } else { 1584 *regmap = priv->regmap_base; 1585 *reg = RK3368_PULL_GRF_OFFSET; 1586 1587 /* correct the offset, as we're starting with the 2nd bank */ 1588 *reg -= 0x10; 1589 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1590 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1591 1592 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1593 *bit *= RK3188_PULL_BITS_PER_PIN; 1594 } 1595 } 1596 1597 #define RK3368_DRV_PMU_OFFSET 0x20 1598 #define RK3368_DRV_GRF_OFFSET 0x200 1599 1600 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1601 int pin_num, struct regmap **regmap, 1602 int *reg, u8 *bit) 1603 { 1604 struct rockchip_pinctrl_priv *priv = bank->priv; 1605 1606 /* The first 32 pins of the first bank are located in PMU */ 1607 if (bank->bank_num == 0) { 1608 *regmap = priv->regmap_pmu; 1609 *reg = RK3368_DRV_PMU_OFFSET; 1610 1611 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1612 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1613 *bit *= RK3288_DRV_BITS_PER_PIN; 1614 } else { 1615 *regmap = priv->regmap_base; 1616 *reg = RK3368_DRV_GRF_OFFSET; 1617 1618 /* correct the offset, as we're starting with the 2nd bank */ 1619 *reg -= 0x10; 1620 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1621 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1622 1623 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1624 *bit *= RK3288_DRV_BITS_PER_PIN; 1625 } 1626 } 1627 1628 #define RK3399_PULL_GRF_OFFSET 0xe040 1629 #define RK3399_PULL_PMU_OFFSET 0x40 1630 #define RK3399_DRV_3BITS_PER_PIN 3 1631 1632 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1633 int pin_num, struct regmap **regmap, 1634 int *reg, u8 *bit) 1635 { 1636 struct rockchip_pinctrl_priv *priv = bank->priv; 1637 1638 /* The bank0:16 and bank1:32 pins are located in PMU */ 1639 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1640 *regmap = priv->regmap_pmu; 1641 *reg = RK3399_PULL_PMU_OFFSET; 1642 1643 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1644 1645 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1646 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1647 *bit *= RK3188_PULL_BITS_PER_PIN; 1648 } else { 1649 *regmap = priv->regmap_base; 1650 *reg = RK3399_PULL_GRF_OFFSET; 1651 1652 /* correct the offset, as we're starting with the 3rd bank */ 1653 *reg -= 0x20; 1654 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1655 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1656 1657 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1658 *bit *= RK3188_PULL_BITS_PER_PIN; 1659 } 1660 } 1661 1662 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1663 int pin_num, struct regmap **regmap, 1664 int *reg, u8 *bit) 1665 { 1666 struct rockchip_pinctrl_priv *priv = bank->priv; 1667 int drv_num = (pin_num / 8); 1668 1669 /* The bank0:16 and bank1:32 pins are located in PMU */ 1670 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1671 *regmap = priv->regmap_pmu; 1672 else 1673 *regmap = priv->regmap_base; 1674 1675 *reg = bank->drv[drv_num].offset; 1676 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1677 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1678 *bit = (pin_num % 8) * 3; 1679 else 1680 *bit = (pin_num % 8) * 2; 1681 } 1682 1683 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1684 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1685 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1686 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1687 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1688 { 4, 7, 10, 13, 16, 19, 22, 26 } 1689 }; 1690 1691 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1692 int pin_num, int strength) 1693 { 1694 struct rockchip_pinctrl_priv *priv = bank->priv; 1695 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1696 struct regmap *regmap; 1697 int reg, ret, i; 1698 u32 data, rmask_bits, temp; 1699 u8 bit; 1700 int drv_type = bank->drv[pin_num / 8].drv_type & DRV_TYPE_IO_MASK; 1701 1702 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 1703 pin_num, strength); 1704 1705 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1706 1707 ret = -EINVAL; 1708 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1709 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1710 ret = i; 1711 break; 1712 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1713 ret = rockchip_perpin_drv_list[drv_type][i]; 1714 break; 1715 } 1716 } 1717 1718 if (ret < 0) { 1719 debug("unsupported driver strength %d\n", strength); 1720 return ret; 1721 } 1722 1723 switch (drv_type) { 1724 case DRV_TYPE_IO_1V8_3V0_AUTO: 1725 case DRV_TYPE_IO_3V3_ONLY: 1726 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1727 switch (bit) { 1728 case 0 ... 12: 1729 /* regular case, nothing to do */ 1730 break; 1731 case 15: 1732 /* 1733 * drive-strength offset is special, as it is spread 1734 * over 2 registers, the bit data[15] contains bit 0 1735 * of the value while temp[1:0] contains bits 2 and 1 1736 */ 1737 data = (ret & 0x1) << 15; 1738 temp = (ret >> 0x1) & 0x3; 1739 1740 data |= BIT(31); 1741 ret = regmap_write(regmap, reg, data); 1742 if (ret) 1743 return ret; 1744 1745 temp |= (0x3 << 16); 1746 reg += 0x4; 1747 ret = regmap_write(regmap, reg, temp); 1748 1749 return ret; 1750 case 18 ... 21: 1751 /* setting fully enclosed in the second register */ 1752 reg += 4; 1753 bit -= 16; 1754 break; 1755 default: 1756 debug("unsupported bit: %d for pinctrl drive type: %d\n", 1757 bit, drv_type); 1758 return -EINVAL; 1759 } 1760 break; 1761 case DRV_TYPE_IO_DEFAULT: 1762 case DRV_TYPE_IO_1V8_OR_3V0: 1763 case DRV_TYPE_IO_1V8_ONLY: 1764 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1765 break; 1766 default: 1767 debug("unsupported pinctrl drive type: %d\n", 1768 drv_type); 1769 return -EINVAL; 1770 } 1771 1772 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 1773 regmap_read(regmap, reg, &data); 1774 data &= ~(((1 << rmask_bits) - 1) << bit); 1775 } else { 1776 /* enable the write to the equivalent lower bits */ 1777 data = ((1 << rmask_bits) - 1) << (bit + 16); 1778 } 1779 1780 data |= (ret << bit); 1781 ret = regmap_write(regmap, reg, data); 1782 return ret; 1783 } 1784 1785 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1786 { 1787 PIN_CONFIG_BIAS_DISABLE, 1788 PIN_CONFIG_BIAS_PULL_UP, 1789 PIN_CONFIG_BIAS_PULL_DOWN, 1790 PIN_CONFIG_BIAS_BUS_HOLD 1791 }, 1792 { 1793 PIN_CONFIG_BIAS_DISABLE, 1794 PIN_CONFIG_BIAS_PULL_DOWN, 1795 PIN_CONFIG_BIAS_DISABLE, 1796 PIN_CONFIG_BIAS_PULL_UP 1797 }, 1798 }; 1799 1800 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1801 int pin_num, int pull) 1802 { 1803 struct rockchip_pinctrl_priv *priv = bank->priv; 1804 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1805 struct regmap *regmap; 1806 int reg, ret, i, pull_type; 1807 u8 bit; 1808 u32 data; 1809 1810 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 1811 pin_num, pull); 1812 1813 /* rk3066b does support any pulls */ 1814 if (ctrl->type == RK3066B) 1815 return pull ? -EINVAL : 0; 1816 1817 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1818 1819 switch (ctrl->type) { 1820 case RK2928: 1821 case RK3128: 1822 data = BIT(bit + 16); 1823 if (pull == PIN_CONFIG_BIAS_DISABLE) 1824 data |= BIT(bit); 1825 ret = regmap_write(regmap, reg, data); 1826 break; 1827 case PX30: 1828 case RV1108: 1829 case RK3188: 1830 case RK3288: 1831 case RK3308: 1832 case RK3368: 1833 case RK3399: 1834 pull_type = bank->pull_type[pin_num / 8] & PULL_TYPE_IO_MASK; 1835 ret = -EINVAL; 1836 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 1837 i++) { 1838 if (rockchip_pull_list[pull_type][i] == pull) { 1839 ret = i; 1840 break; 1841 } 1842 } 1843 1844 if (ret < 0) { 1845 debug("unsupported pull setting %d\n", pull); 1846 return ret; 1847 } 1848 1849 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 1850 regmap_read(regmap, reg, &data); 1851 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); 1852 } else { 1853 /* enable the write to the equivalent lower bits */ 1854 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1855 } 1856 1857 data |= (ret << bit); 1858 ret = regmap_write(regmap, reg, data); 1859 break; 1860 default: 1861 debug("unsupported pinctrl type\n"); 1862 return -EINVAL; 1863 } 1864 1865 return ret; 1866 } 1867 1868 #define RK3328_SCHMITT_BITS_PER_PIN 1 1869 #define RK3328_SCHMITT_PINS_PER_REG 16 1870 #define RK3328_SCHMITT_BANK_STRIDE 8 1871 #define RK3328_SCHMITT_GRF_OFFSET 0x380 1872 1873 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1874 int pin_num, 1875 struct regmap **regmap, 1876 int *reg, u8 *bit) 1877 { 1878 struct rockchip_pinctrl_priv *priv = bank->priv; 1879 1880 *regmap = priv->regmap_base; 1881 *reg = RK3328_SCHMITT_GRF_OFFSET; 1882 1883 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 1884 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 1885 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 1886 1887 return 0; 1888 } 1889 1890 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 1891 int pin_num, int enable) 1892 { 1893 struct rockchip_pinctrl_priv *priv = bank->priv; 1894 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1895 struct regmap *regmap; 1896 int reg, ret; 1897 u8 bit; 1898 u32 data; 1899 1900 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 1901 pin_num, enable); 1902 1903 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1904 if (ret) 1905 return ret; 1906 1907 /* enable the write to the equivalent lower bits */ 1908 data = BIT(bit + 16) | (enable << bit); 1909 1910 return regmap_write(regmap, reg, data); 1911 } 1912 1913 /* 1914 * Pinconf_ops handling 1915 */ 1916 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 1917 unsigned int pull) 1918 { 1919 switch (ctrl->type) { 1920 case RK2928: 1921 case RK3128: 1922 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 1923 pull == PIN_CONFIG_BIAS_DISABLE); 1924 case RK3066B: 1925 return pull ? false : true; 1926 case PX30: 1927 case RV1108: 1928 case RK3188: 1929 case RK3288: 1930 case RK3308: 1931 case RK3368: 1932 case RK3399: 1933 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 1934 } 1935 1936 return false; 1937 } 1938 1939 /* set the pin config settings for a specified pin */ 1940 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 1941 u32 pin, u32 param, u32 arg) 1942 { 1943 struct rockchip_pinctrl_priv *priv = bank->priv; 1944 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1945 int rc; 1946 1947 switch (param) { 1948 case PIN_CONFIG_BIAS_DISABLE: 1949 rc = rockchip_set_pull(bank, pin, param); 1950 if (rc) 1951 return rc; 1952 break; 1953 1954 case PIN_CONFIG_BIAS_PULL_UP: 1955 case PIN_CONFIG_BIAS_PULL_DOWN: 1956 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1957 case PIN_CONFIG_BIAS_BUS_HOLD: 1958 if (!rockchip_pinconf_pull_valid(ctrl, param)) 1959 return -ENOTSUPP; 1960 1961 if (!arg) 1962 return -EINVAL; 1963 1964 rc = rockchip_set_pull(bank, pin, param); 1965 if (rc) 1966 return rc; 1967 break; 1968 1969 case PIN_CONFIG_DRIVE_STRENGTH: 1970 if (!ctrl->drv_calc_reg) 1971 return -ENOTSUPP; 1972 1973 rc = rockchip_set_drive_perpin(bank, pin, arg); 1974 if (rc < 0) 1975 return rc; 1976 break; 1977 1978 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1979 if (!ctrl->schmitt_calc_reg) 1980 return -ENOTSUPP; 1981 1982 rc = rockchip_set_schmitt(bank, pin, arg); 1983 if (rc < 0) 1984 return rc; 1985 break; 1986 1987 default: 1988 break; 1989 } 1990 1991 return 0; 1992 } 1993 1994 static const struct pinconf_param rockchip_conf_params[] = { 1995 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 1996 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 1997 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 1998 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 1999 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 2000 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 2001 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 2002 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 2003 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 2004 }; 2005 2006 static int rockchip_pinconf_prop_name_to_param(const char *property, 2007 u32 *default_value) 2008 { 2009 const struct pinconf_param *p, *end; 2010 2011 p = rockchip_conf_params; 2012 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 2013 2014 /* See if this pctldev supports this parameter */ 2015 for (; p < end; p++) { 2016 if (!strcmp(property, p->property)) { 2017 *default_value = p->default_value; 2018 return p->param; 2019 } 2020 } 2021 2022 *default_value = 0; 2023 return -EPERM; 2024 } 2025 2026 static int rockchip_pinctrl_set_state(struct udevice *dev, 2027 struct udevice *config) 2028 { 2029 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2030 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2031 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 2032 u32 bank, pin, mux, conf, arg, default_val; 2033 int ret, count, i; 2034 const char *prop_name; 2035 const void *value; 2036 int prop_len, param; 2037 const u32 *data; 2038 ofnode node; 2039 #ifdef CONFIG_OF_LIVE 2040 const struct device_node *np; 2041 struct property *pp; 2042 #else 2043 int property_offset, pcfg_node; 2044 const void *blob = gd->fdt_blob; 2045 #endif 2046 data = dev_read_prop(config, "rockchip,pins", &count); 2047 if (count < 0) { 2048 debug("%s: bad array size %d\n", __func__, count); 2049 return -EINVAL; 2050 } 2051 2052 count /= sizeof(u32); 2053 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2054 debug("%s: unsupported pins array count %d\n", 2055 __func__, count); 2056 return -EINVAL; 2057 } 2058 2059 for (i = 0; i < count; i++) 2060 cells[i] = fdt32_to_cpu(data[i]); 2061 2062 for (i = 0; i < (count >> 2); i++) { 2063 bank = cells[4 * i + 0]; 2064 pin = cells[4 * i + 1]; 2065 mux = cells[4 * i + 2]; 2066 conf = cells[4 * i + 3]; 2067 2068 ret = rockchip_verify_config(dev, bank, pin); 2069 if (ret) 2070 return ret; 2071 2072 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2073 if (ret) 2074 return ret; 2075 2076 node = ofnode_get_by_phandle(conf); 2077 if (!ofnode_valid(node)) 2078 return -ENODEV; 2079 #ifdef CONFIG_OF_LIVE 2080 np = ofnode_to_np(node); 2081 for (pp = np->properties; pp; pp = pp->next) { 2082 prop_name = pp->name; 2083 prop_len = pp->length; 2084 value = pp->value; 2085 #else 2086 pcfg_node = ofnode_to_offset(node); 2087 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2088 value = fdt_getprop_by_offset(blob, property_offset, 2089 &prop_name, &prop_len); 2090 if (!value) 2091 return -ENOENT; 2092 #endif 2093 param = rockchip_pinconf_prop_name_to_param(prop_name, 2094 &default_val); 2095 if (param < 0) 2096 break; 2097 2098 if (prop_len >= sizeof(fdt32_t)) 2099 arg = fdt32_to_cpu(*(fdt32_t *)value); 2100 else 2101 arg = default_val; 2102 2103 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2104 param, arg); 2105 if (ret) { 2106 debug("%s: rockchip_pinconf_set fail: %d\n", 2107 __func__, ret); 2108 return ret; 2109 } 2110 } 2111 } 2112 2113 return 0; 2114 } 2115 2116 static struct pinctrl_ops rockchip_pinctrl_ops = { 2117 .set_state = rockchip_pinctrl_set_state, 2118 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2119 }; 2120 2121 /* retrieve the soc specific data */ 2122 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 2123 { 2124 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2125 struct rockchip_pin_ctrl *ctrl = 2126 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 2127 struct rockchip_pin_bank *bank; 2128 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2129 2130 grf_offs = ctrl->grf_mux_offset; 2131 pmu_offs = ctrl->pmu_mux_offset; 2132 drv_pmu_offs = ctrl->pmu_drv_offset; 2133 drv_grf_offs = ctrl->grf_drv_offset; 2134 bank = ctrl->pin_banks; 2135 2136 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2137 int bank_pins = 0; 2138 2139 bank->priv = priv; 2140 bank->pin_base = ctrl->nr_pins; 2141 ctrl->nr_pins += bank->nr_pins; 2142 2143 /* calculate iomux and drv offsets */ 2144 for (j = 0; j < 4; j++) { 2145 struct rockchip_iomux *iom = &bank->iomux[j]; 2146 struct rockchip_drv *drv = &bank->drv[j]; 2147 int inc; 2148 2149 if (bank_pins >= bank->nr_pins) 2150 break; 2151 2152 /* preset iomux offset value, set new start value */ 2153 if (iom->offset >= 0) { 2154 if (iom->type & IOMUX_SOURCE_PMU) 2155 pmu_offs = iom->offset; 2156 else 2157 grf_offs = iom->offset; 2158 } else { /* set current iomux offset */ 2159 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2160 pmu_offs : grf_offs; 2161 } 2162 2163 /* preset drv offset value, set new start value */ 2164 if (drv->offset >= 0) { 2165 if (iom->type & IOMUX_SOURCE_PMU) 2166 drv_pmu_offs = drv->offset; 2167 else 2168 drv_grf_offs = drv->offset; 2169 } else { /* set current drv offset */ 2170 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2171 drv_pmu_offs : drv_grf_offs; 2172 } 2173 2174 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2175 i, j, iom->offset, drv->offset); 2176 2177 /* 2178 * Increase offset according to iomux width. 2179 * 4bit iomux'es are spread over two registers. 2180 */ 2181 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2182 IOMUX_WIDTH_3BIT | 2183 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 2184 if (iom->type & IOMUX_SOURCE_PMU) 2185 pmu_offs += inc; 2186 else 2187 grf_offs += inc; 2188 2189 /* 2190 * Increase offset according to drv width. 2191 * 3bit drive-strenth'es are spread over two registers. 2192 */ 2193 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2194 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2195 inc = 8; 2196 else 2197 inc = 4; 2198 2199 if (iom->type & IOMUX_SOURCE_PMU) 2200 drv_pmu_offs += inc; 2201 else 2202 drv_grf_offs += inc; 2203 2204 bank_pins += 8; 2205 } 2206 2207 /* calculate the per-bank recalced_mask */ 2208 for (j = 0; j < ctrl->niomux_recalced; j++) { 2209 int pin = 0; 2210 2211 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2212 pin = ctrl->iomux_recalced[j].pin; 2213 bank->recalced_mask |= BIT(pin); 2214 } 2215 } 2216 2217 /* calculate the per-bank route_mask */ 2218 for (j = 0; j < ctrl->niomux_routes; j++) { 2219 int pin = 0; 2220 2221 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2222 pin = ctrl->iomux_routes[j].pin; 2223 bank->route_mask |= BIT(pin); 2224 } 2225 } 2226 } 2227 2228 return ctrl; 2229 } 2230 2231 static int rockchip_pinctrl_probe(struct udevice *dev) 2232 { 2233 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2234 struct rockchip_pin_ctrl *ctrl; 2235 struct udevice *syscon; 2236 struct regmap *regmap; 2237 int ret = 0; 2238 2239 /* get rockchip grf syscon phandle */ 2240 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2241 &syscon); 2242 if (ret) { 2243 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 2244 return ret; 2245 } 2246 2247 /* get grf-reg base address */ 2248 regmap = syscon_get_regmap(syscon); 2249 if (!regmap) { 2250 debug("unable to find rockchip grf regmap\n"); 2251 return -ENODEV; 2252 } 2253 priv->regmap_base = regmap; 2254 2255 /* option: get pmu-reg base address */ 2256 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 2257 &syscon); 2258 if (!ret) { 2259 /* get pmugrf-reg base address */ 2260 regmap = syscon_get_regmap(syscon); 2261 if (!regmap) { 2262 debug("unable to find rockchip pmu regmap\n"); 2263 return -ENODEV; 2264 } 2265 priv->regmap_pmu = regmap; 2266 } 2267 2268 ctrl = rockchip_pinctrl_get_soc_data(dev); 2269 if (!ctrl) { 2270 debug("driver data not available\n"); 2271 return -EINVAL; 2272 } 2273 2274 priv->ctrl = ctrl; 2275 return 0; 2276 } 2277 2278 static struct rockchip_pin_bank px30_pin_banks[] = { 2279 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2280 IOMUX_SOURCE_PMU, 2281 IOMUX_SOURCE_PMU, 2282 IOMUX_SOURCE_PMU 2283 ), 2284 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2285 IOMUX_WIDTH_4BIT, 2286 IOMUX_WIDTH_4BIT, 2287 IOMUX_WIDTH_4BIT 2288 ), 2289 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2290 IOMUX_WIDTH_4BIT, 2291 IOMUX_WIDTH_4BIT, 2292 IOMUX_WIDTH_4BIT 2293 ), 2294 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2295 IOMUX_WIDTH_4BIT, 2296 IOMUX_WIDTH_4BIT, 2297 IOMUX_WIDTH_4BIT 2298 ), 2299 }; 2300 2301 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2302 .pin_banks = px30_pin_banks, 2303 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2304 .label = "PX30-GPIO", 2305 .type = PX30, 2306 .grf_mux_offset = 0x0, 2307 .pmu_mux_offset = 0x0, 2308 .iomux_routes = px30_mux_route_data, 2309 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2310 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2311 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2312 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2313 }; 2314 2315 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2316 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2317 IOMUX_SOURCE_PMU, 2318 IOMUX_SOURCE_PMU, 2319 IOMUX_SOURCE_PMU), 2320 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2321 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2322 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2323 }; 2324 2325 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2326 .pin_banks = rv1108_pin_banks, 2327 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2328 .label = "RV1108-GPIO", 2329 .type = RV1108, 2330 .grf_mux_offset = 0x10, 2331 .pmu_mux_offset = 0x0, 2332 .iomux_recalced = rv1108_mux_recalced_data, 2333 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2334 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2335 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2336 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2337 }; 2338 2339 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2340 PIN_BANK(0, 32, "gpio0"), 2341 PIN_BANK(1, 32, "gpio1"), 2342 PIN_BANK(2, 32, "gpio2"), 2343 PIN_BANK(3, 32, "gpio3"), 2344 }; 2345 2346 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2347 .pin_banks = rk2928_pin_banks, 2348 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2349 .label = "RK2928-GPIO", 2350 .type = RK2928, 2351 .grf_mux_offset = 0xa8, 2352 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2353 }; 2354 2355 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2356 PIN_BANK(0, 32, "gpio0"), 2357 PIN_BANK(1, 32, "gpio1"), 2358 PIN_BANK(2, 32, "gpio2"), 2359 }; 2360 2361 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2362 .pin_banks = rk3036_pin_banks, 2363 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2364 .label = "RK3036-GPIO", 2365 .type = RK2928, 2366 .grf_mux_offset = 0xa8, 2367 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2368 }; 2369 2370 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2371 PIN_BANK(0, 32, "gpio0"), 2372 PIN_BANK(1, 32, "gpio1"), 2373 PIN_BANK(2, 32, "gpio2"), 2374 PIN_BANK(3, 32, "gpio3"), 2375 PIN_BANK(4, 32, "gpio4"), 2376 PIN_BANK(6, 16, "gpio6"), 2377 }; 2378 2379 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2380 .pin_banks = rk3066a_pin_banks, 2381 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2382 .label = "RK3066a-GPIO", 2383 .type = RK2928, 2384 .grf_mux_offset = 0xa8, 2385 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2386 }; 2387 2388 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2389 PIN_BANK(0, 32, "gpio0"), 2390 PIN_BANK(1, 32, "gpio1"), 2391 PIN_BANK(2, 32, "gpio2"), 2392 PIN_BANK(3, 32, "gpio3"), 2393 }; 2394 2395 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2396 .pin_banks = rk3066b_pin_banks, 2397 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2398 .label = "RK3066b-GPIO", 2399 .type = RK3066B, 2400 .grf_mux_offset = 0x60, 2401 }; 2402 2403 static struct rockchip_pin_bank rk3128_pin_banks[] = { 2404 PIN_BANK(0, 32, "gpio0"), 2405 PIN_BANK(1, 32, "gpio1"), 2406 PIN_BANK(2, 32, "gpio2"), 2407 PIN_BANK(3, 32, "gpio3"), 2408 }; 2409 2410 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 2411 .pin_banks = rk3128_pin_banks, 2412 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 2413 .label = "RK3128-GPIO", 2414 .type = RK3128, 2415 .grf_mux_offset = 0xa8, 2416 .iomux_recalced = rk3128_mux_recalced_data, 2417 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 2418 .iomux_routes = rk3128_mux_route_data, 2419 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 2420 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 2421 }; 2422 2423 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2424 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2425 PIN_BANK(1, 32, "gpio1"), 2426 PIN_BANK(2, 32, "gpio2"), 2427 PIN_BANK(3, 32, "gpio3"), 2428 }; 2429 2430 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2431 .pin_banks = rk3188_pin_banks, 2432 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2433 .label = "RK3188-GPIO", 2434 .type = RK3188, 2435 .grf_mux_offset = 0x60, 2436 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2437 }; 2438 2439 static struct rockchip_pin_bank rk3228_pin_banks[] = { 2440 PIN_BANK(0, 32, "gpio0"), 2441 PIN_BANK(1, 32, "gpio1"), 2442 PIN_BANK(2, 32, "gpio2"), 2443 PIN_BANK(3, 32, "gpio3"), 2444 }; 2445 2446 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 2447 .pin_banks = rk3228_pin_banks, 2448 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 2449 .label = "RK3228-GPIO", 2450 .type = RK3288, 2451 .grf_mux_offset = 0x0, 2452 .iomux_routes = rk3228_mux_route_data, 2453 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 2454 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2455 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2456 }; 2457 2458 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2459 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 2460 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 2461 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 2462 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 2463 IOMUX_UNROUTED, 2464 DRV_TYPE_WRITABLE_32BIT, 2465 DRV_TYPE_WRITABLE_32BIT, 2466 DRV_TYPE_WRITABLE_32BIT, 2467 0, 2468 PULL_TYPE_WRITABLE_32BIT, 2469 PULL_TYPE_WRITABLE_32BIT, 2470 PULL_TYPE_WRITABLE_32BIT, 2471 0 2472 ), 2473 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2474 IOMUX_UNROUTED, 2475 IOMUX_UNROUTED, 2476 0 2477 ), 2478 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2479 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2480 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2481 IOMUX_WIDTH_4BIT, 2482 0, 2483 0 2484 ), 2485 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2486 0, 2487 0, 2488 IOMUX_UNROUTED 2489 ), 2490 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2491 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2492 0, 2493 IOMUX_WIDTH_4BIT, 2494 IOMUX_UNROUTED 2495 ), 2496 PIN_BANK(8, 16, "gpio8"), 2497 }; 2498 2499 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2500 .pin_banks = rk3288_pin_banks, 2501 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2502 .label = "RK3288-GPIO", 2503 .type = RK3288, 2504 .grf_mux_offset = 0x0, 2505 .pmu_mux_offset = 0x84, 2506 .iomux_routes = rk3288_mux_route_data, 2507 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 2508 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2509 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2510 }; 2511 2512 static struct rockchip_pin_bank rk3308_pin_banks[] = { 2513 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 2514 IOMUX_8WIDTH_2BIT, 2515 IOMUX_8WIDTH_2BIT, 2516 IOMUX_8WIDTH_2BIT), 2517 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 2518 IOMUX_8WIDTH_2BIT, 2519 IOMUX_8WIDTH_2BIT, 2520 IOMUX_8WIDTH_2BIT), 2521 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 2522 IOMUX_8WIDTH_2BIT, 2523 IOMUX_8WIDTH_2BIT, 2524 IOMUX_8WIDTH_2BIT), 2525 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 2526 IOMUX_8WIDTH_2BIT, 2527 IOMUX_8WIDTH_2BIT, 2528 IOMUX_8WIDTH_2BIT), 2529 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 2530 IOMUX_8WIDTH_2BIT, 2531 IOMUX_8WIDTH_2BIT, 2532 IOMUX_8WIDTH_2BIT), 2533 }; 2534 2535 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 2536 .pin_banks = rk3308_pin_banks, 2537 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 2538 .label = "RK3308-GPIO", 2539 .type = RK3308, 2540 .grf_mux_offset = 0x0, 2541 .iomux_recalced = rk3308_mux_recalced_data, 2542 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 2543 .iomux_routes = rk3308_mux_route_data, 2544 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 2545 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 2546 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 2547 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 2548 }; 2549 2550 static struct rockchip_pin_bank rk3328_pin_banks[] = { 2551 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 2552 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2553 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 2554 IOMUX_WIDTH_3BIT, 2555 IOMUX_WIDTH_3BIT, 2556 0), 2557 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2558 IOMUX_WIDTH_3BIT, 2559 IOMUX_WIDTH_3BIT, 2560 0, 2561 0), 2562 }; 2563 2564 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 2565 .pin_banks = rk3328_pin_banks, 2566 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 2567 .label = "RK3328-GPIO", 2568 .type = RK3288, 2569 .grf_mux_offset = 0x0, 2570 .iomux_recalced = rk3328_mux_recalced_data, 2571 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 2572 .iomux_routes = rk3328_mux_route_data, 2573 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 2574 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2575 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2576 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 2577 }; 2578 2579 static struct rockchip_pin_bank rk3368_pin_banks[] = { 2580 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2581 IOMUX_SOURCE_PMU, 2582 IOMUX_SOURCE_PMU, 2583 IOMUX_SOURCE_PMU 2584 ), 2585 PIN_BANK(1, 32, "gpio1"), 2586 PIN_BANK(2, 32, "gpio2"), 2587 PIN_BANK(3, 32, "gpio3"), 2588 }; 2589 2590 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 2591 .pin_banks = rk3368_pin_banks, 2592 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 2593 .label = "RK3368-GPIO", 2594 .type = RK3368, 2595 .grf_mux_offset = 0x0, 2596 .pmu_mux_offset = 0x0, 2597 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 2598 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 2599 }; 2600 2601 static struct rockchip_pin_bank rk3399_pin_banks[] = { 2602 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 2603 IOMUX_SOURCE_PMU, 2604 IOMUX_SOURCE_PMU, 2605 IOMUX_SOURCE_PMU, 2606 IOMUX_SOURCE_PMU, 2607 DRV_TYPE_IO_1V8_ONLY, 2608 DRV_TYPE_IO_1V8_ONLY, 2609 DRV_TYPE_IO_DEFAULT, 2610 DRV_TYPE_IO_DEFAULT, 2611 0x80, 2612 0x88, 2613 -1, 2614 -1, 2615 PULL_TYPE_IO_1V8_ONLY, 2616 PULL_TYPE_IO_1V8_ONLY, 2617 PULL_TYPE_IO_DEFAULT, 2618 PULL_TYPE_IO_DEFAULT 2619 ), 2620 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 2621 IOMUX_SOURCE_PMU, 2622 IOMUX_SOURCE_PMU, 2623 IOMUX_SOURCE_PMU, 2624 DRV_TYPE_IO_1V8_OR_3V0, 2625 DRV_TYPE_IO_1V8_OR_3V0, 2626 DRV_TYPE_IO_1V8_OR_3V0, 2627 DRV_TYPE_IO_1V8_OR_3V0, 2628 0xa0, 2629 0xa8, 2630 0xb0, 2631 0xb8 2632 ), 2633 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 2634 DRV_TYPE_IO_1V8_OR_3V0, 2635 DRV_TYPE_IO_1V8_ONLY, 2636 DRV_TYPE_IO_1V8_ONLY, 2637 PULL_TYPE_IO_DEFAULT, 2638 PULL_TYPE_IO_DEFAULT, 2639 PULL_TYPE_IO_1V8_ONLY, 2640 PULL_TYPE_IO_1V8_ONLY 2641 ), 2642 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 2643 DRV_TYPE_IO_3V3_ONLY, 2644 DRV_TYPE_IO_3V3_ONLY, 2645 DRV_TYPE_IO_1V8_OR_3V0 2646 ), 2647 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 2648 DRV_TYPE_IO_1V8_3V0_AUTO, 2649 DRV_TYPE_IO_1V8_OR_3V0, 2650 DRV_TYPE_IO_1V8_OR_3V0 2651 ), 2652 }; 2653 2654 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 2655 .pin_banks = rk3399_pin_banks, 2656 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 2657 .label = "RK3399-GPIO", 2658 .type = RK3399, 2659 .grf_mux_offset = 0xe000, 2660 .pmu_mux_offset = 0x0, 2661 .grf_drv_offset = 0xe100, 2662 .pmu_drv_offset = 0x80, 2663 .iomux_routes = rk3399_mux_route_data, 2664 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 2665 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 2666 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 2667 }; 2668 2669 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 2670 { .compatible = "rockchip,px30-pinctrl", 2671 .data = (ulong)&px30_pin_ctrl }, 2672 { .compatible = "rockchip,rv1108-pinctrl", 2673 .data = (ulong)&rv1108_pin_ctrl }, 2674 { .compatible = "rockchip,rk2928-pinctrl", 2675 .data = (ulong)&rk2928_pin_ctrl }, 2676 { .compatible = "rockchip,rk3036-pinctrl", 2677 .data = (ulong)&rk3036_pin_ctrl }, 2678 { .compatible = "rockchip,rk3066a-pinctrl", 2679 .data = (ulong)&rk3066a_pin_ctrl }, 2680 { .compatible = "rockchip,rk3066b-pinctrl", 2681 .data = (ulong)&rk3066b_pin_ctrl }, 2682 { .compatible = "rockchip,rk3128-pinctrl", 2683 .data = (ulong)&rk3128_pin_ctrl }, 2684 { .compatible = "rockchip,rk3188-pinctrl", 2685 .data = (ulong)&rk3188_pin_ctrl }, 2686 { .compatible = "rockchip,rk3228-pinctrl", 2687 .data = (ulong)&rk3228_pin_ctrl }, 2688 { .compatible = "rockchip,rk3288-pinctrl", 2689 .data = (ulong)&rk3288_pin_ctrl }, 2690 { .compatible = "rockchip,rk3308-pinctrl", 2691 .data = (ulong)&rk3308_pin_ctrl }, 2692 { .compatible = "rockchip,rk3328-pinctrl", 2693 .data = (ulong)&rk3328_pin_ctrl }, 2694 { .compatible = "rockchip,rk3368-pinctrl", 2695 .data = (ulong)&rk3368_pin_ctrl }, 2696 { .compatible = "rockchip,rk3399-pinctrl", 2697 .data = (ulong)&rk3399_pin_ctrl }, 2698 {}, 2699 }; 2700 2701 U_BOOT_DRIVER(pinctrl_rockchip) = { 2702 .name = "rockchip_pinctrl", 2703 .id = UCLASS_PINCTRL, 2704 .of_match = rockchip_pinctrl_dt_match, 2705 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 2706 .ops = &rockchip_pinctrl_ops, 2707 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 2708 .bind = dm_scan_fdt_dev, 2709 #endif 2710 .probe = rockchip_pinctrl_probe, 2711 }; 2712