1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <linux/bitops.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/arch/cpu.h> 15 #include <dt-bindings/pinctrl/rockchip.h> 16 17 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 18 #define RK_FUNC_GPIO 0 19 #define MAX_ROCKCHIP_PINS_ENTRIES 30 20 21 enum rockchip_pinctrl_type { 22 PX30, 23 RV1108, 24 RV1126, 25 RK1808, 26 RK2928, 27 RK3066B, 28 RK3128, 29 RK3188, 30 RK3288, 31 RK3308, 32 RK3368, 33 RK3399, 34 }; 35 36 #define RK_GENMASK_VAL(h, l, v) \ 37 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 38 39 /** 40 * Encode variants of iomux registers into a type variable 41 */ 42 #define IOMUX_GPIO_ONLY BIT(0) 43 #define IOMUX_WIDTH_4BIT BIT(1) 44 #define IOMUX_SOURCE_PMU BIT(2) 45 #define IOMUX_UNROUTED BIT(3) 46 #define IOMUX_WIDTH_3BIT BIT(4) 47 #define IOMUX_8WIDTH_2BIT BIT(5) 48 #define IOMUX_WRITABLE_32BIT BIT(6) 49 #define IOMUX_L_SOURCE_PMU BIT(7) 50 51 /** 52 * @type: iomux variant using IOMUX_* constants 53 * @offset: if initialized to -1 it will be autocalculated, by specifying 54 * an initial offset value the relevant source offset can be reset 55 * to a new value for autocalculating the following iomux registers. 56 */ 57 struct rockchip_iomux { 58 int type; 59 int offset; 60 }; 61 62 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 63 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 64 65 /** 66 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 67 */ 68 enum rockchip_pin_drv_type { 69 DRV_TYPE_IO_DEFAULT = 0, 70 DRV_TYPE_IO_1V8_OR_3V0, 71 DRV_TYPE_IO_1V8_ONLY, 72 DRV_TYPE_IO_1V8_3V0_AUTO, 73 DRV_TYPE_IO_3V3_ONLY, 74 DRV_TYPE_MAX 75 }; 76 77 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 78 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 79 80 /** 81 * enum type index corresponding to rockchip_pull_list arrays index. 82 */ 83 enum rockchip_pin_pull_type { 84 PULL_TYPE_IO_DEFAULT = 0, 85 PULL_TYPE_IO_1V8_ONLY, 86 PULL_TYPE_MAX 87 }; 88 89 /** 90 * enum mux route register type, should be invalid/default/topgrf/pmugrf. 91 * INVALID: means do not need to set mux route 92 * DEFAULT: means same regmap as pin iomux 93 * TOPGRF: means mux route setting in topgrf 94 * PMUGRF: means mux route setting in pmugrf 95 */ 96 enum rockchip_pin_route_type { 97 ROUTE_TYPE_DEFAULT = 0, 98 ROUTE_TYPE_TOPGRF = 1, 99 ROUTE_TYPE_PMUGRF = 2, 100 101 ROUTE_TYPE_INVALID = -1, 102 }; 103 104 /** 105 * @drv_type: drive strength variant using rockchip_perpin_drv_type 106 * @offset: if initialized to -1 it will be autocalculated, by specifying 107 * an initial offset value the relevant source offset can be reset 108 * to a new value for autocalculating the following drive strength 109 * registers. if used chips own cal_drv func instead to calculate 110 * registers offset, the variant could be ignored. 111 */ 112 struct rockchip_drv { 113 enum rockchip_pin_drv_type drv_type; 114 int offset; 115 }; 116 117 /** 118 * @priv: common pinctrl private basedata 119 * @pin_base: first pin number 120 * @nr_pins: number of pins in this bank 121 * @name: name of the bank 122 * @bank_num: number of the bank, to account for holes 123 * @iomux: array describing the 4 iomux sources of the bank 124 * @drv: array describing the 4 drive strength sources of the bank 125 * @pull_type: array describing the 4 pull type sources of the bank 126 * @recalced_mask: bits describing the mux recalced pins of per bank 127 * @route_mask: bits describing the routing pins of per bank 128 */ 129 struct rockchip_pin_bank { 130 struct rockchip_pinctrl_priv *priv; 131 u32 pin_base; 132 u8 nr_pins; 133 char *name; 134 u8 bank_num; 135 struct rockchip_iomux iomux[4]; 136 struct rockchip_drv drv[4]; 137 enum rockchip_pin_pull_type pull_type[4]; 138 u32 recalced_mask; 139 u32 route_mask; 140 }; 141 142 #define PIN_BANK(id, pins, label) \ 143 { \ 144 .bank_num = id, \ 145 .nr_pins = pins, \ 146 .name = label, \ 147 .iomux = { \ 148 { .offset = -1 }, \ 149 { .offset = -1 }, \ 150 { .offset = -1 }, \ 151 { .offset = -1 }, \ 152 }, \ 153 } 154 155 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 156 { \ 157 .bank_num = id, \ 158 .nr_pins = pins, \ 159 .name = label, \ 160 .iomux = { \ 161 { .type = iom0, .offset = -1 }, \ 162 { .type = iom1, .offset = -1 }, \ 163 { .type = iom2, .offset = -1 }, \ 164 { .type = iom3, .offset = -1 }, \ 165 }, \ 166 } 167 168 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ 169 iom3, offset0, offset1, offset2, \ 170 offset3) \ 171 { \ 172 .bank_num = id, \ 173 .nr_pins = pins, \ 174 .name = label, \ 175 .iomux = { \ 176 { .type = iom0, .offset = offset0 }, \ 177 { .type = iom1, .offset = offset1 }, \ 178 { .type = iom2, .offset = offset2 }, \ 179 { .type = iom3, .offset = offset3 }, \ 180 }, \ 181 } 182 183 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 184 { \ 185 .bank_num = id, \ 186 .nr_pins = pins, \ 187 .name = label, \ 188 .iomux = { \ 189 { .offset = -1 }, \ 190 { .offset = -1 }, \ 191 { .offset = -1 }, \ 192 { .offset = -1 }, \ 193 }, \ 194 .drv = { \ 195 { .drv_type = type0, .offset = -1 }, \ 196 { .drv_type = type1, .offset = -1 }, \ 197 { .drv_type = type2, .offset = -1 }, \ 198 { .drv_type = type3, .offset = -1 }, \ 199 }, \ 200 } 201 202 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 203 drv2, drv3, pull0, pull1, \ 204 pull2, pull3) \ 205 { \ 206 .bank_num = id, \ 207 .nr_pins = pins, \ 208 .name = label, \ 209 .iomux = { \ 210 { .offset = -1 }, \ 211 { .offset = -1 }, \ 212 { .offset = -1 }, \ 213 { .offset = -1 }, \ 214 }, \ 215 .drv = { \ 216 { .drv_type = drv0, .offset = -1 }, \ 217 { .drv_type = drv1, .offset = -1 }, \ 218 { .drv_type = drv2, .offset = -1 }, \ 219 { .drv_type = drv3, .offset = -1 }, \ 220 }, \ 221 .pull_type[0] = pull0, \ 222 .pull_type[1] = pull1, \ 223 .pull_type[2] = pull2, \ 224 .pull_type[3] = pull3, \ 225 } 226 227 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 228 iom2, iom3, drv0, drv1, drv2, \ 229 drv3, offset0, offset1, \ 230 offset2, offset3) \ 231 { \ 232 .bank_num = id, \ 233 .nr_pins = pins, \ 234 .name = label, \ 235 .iomux = { \ 236 { .type = iom0, .offset = -1 }, \ 237 { .type = iom1, .offset = -1 }, \ 238 { .type = iom2, .offset = -1 }, \ 239 { .type = iom3, .offset = -1 }, \ 240 }, \ 241 .drv = { \ 242 { .drv_type = drv0, .offset = offset0 }, \ 243 { .drv_type = drv1, .offset = offset1 }, \ 244 { .drv_type = drv2, .offset = offset2 }, \ 245 { .drv_type = drv3, .offset = offset3 }, \ 246 }, \ 247 } 248 249 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 250 iom2, iom3, drv0, drv1, drv2, \ 251 drv3, pull0, pull1, pull2, \ 252 pull3) \ 253 { \ 254 .bank_num = id, \ 255 .nr_pins = pins, \ 256 .name = label, \ 257 .iomux = { \ 258 { .type = iom0, .offset = -1 }, \ 259 { .type = iom1, .offset = -1 }, \ 260 { .type = iom2, .offset = -1 }, \ 261 { .type = iom3, .offset = -1 }, \ 262 }, \ 263 .drv = { \ 264 { .drv_type = drv0, .offset = -1 }, \ 265 { .drv_type = drv1, .offset = -1 }, \ 266 { .drv_type = drv2, .offset = -1 }, \ 267 { .drv_type = drv3, .offset = -1 }, \ 268 }, \ 269 .pull_type[0] = pull0, \ 270 .pull_type[1] = pull1, \ 271 .pull_type[2] = pull2, \ 272 .pull_type[3] = pull3, \ 273 } 274 275 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 276 label, iom0, iom1, iom2, \ 277 iom3, drv0, drv1, drv2, \ 278 drv3, offset0, offset1, \ 279 offset2, offset3, pull0, \ 280 pull1, pull2, pull3) \ 281 { \ 282 .bank_num = id, \ 283 .nr_pins = pins, \ 284 .name = label, \ 285 .iomux = { \ 286 { .type = iom0, .offset = -1 }, \ 287 { .type = iom1, .offset = -1 }, \ 288 { .type = iom2, .offset = -1 }, \ 289 { .type = iom3, .offset = -1 }, \ 290 }, \ 291 .drv = { \ 292 { .drv_type = drv0, .offset = offset0 }, \ 293 { .drv_type = drv1, .offset = offset1 }, \ 294 { .drv_type = drv2, .offset = offset2 }, \ 295 { .drv_type = drv3, .offset = offset3 }, \ 296 }, \ 297 .pull_type[0] = pull0, \ 298 .pull_type[1] = pull1, \ 299 .pull_type[2] = pull2, \ 300 .pull_type[3] = pull3, \ 301 } 302 303 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 304 { \ 305 .bank_num = ID, \ 306 .pin = PIN, \ 307 .func = FUNC, \ 308 .route_offset = REG, \ 309 .route_val = VAL, \ 310 .route_type = FLAG, \ 311 } 312 313 #define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ 314 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT) 315 316 #define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ 317 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF) 318 319 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ 320 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF) 321 322 /** 323 * struct rockchip_mux_recalced_data: represent a pin iomux data. 324 * @num: bank number. 325 * @pin: pin number. 326 * @bit: index at register. 327 * @reg: register offset. 328 * @mask: mask bit 329 */ 330 struct rockchip_mux_recalced_data { 331 u8 num; 332 u8 pin; 333 u32 reg; 334 u8 bit; 335 u8 mask; 336 }; 337 338 /** 339 * struct rockchip_mux_recalced_data: represent a pin iomux data. 340 * @bank_num: bank number. 341 * @pin: index at register or used to calc index. 342 * @func: the min pin. 343 * @route_type: the register type. 344 * @route_offset: the max pin. 345 * @route_val: the register offset. 346 */ 347 struct rockchip_mux_route_data { 348 u8 bank_num; 349 u8 pin; 350 u8 func; 351 enum rockchip_pin_route_type route_type : 8; 352 u32 route_offset; 353 u32 route_val; 354 }; 355 356 /** 357 */ 358 struct rockchip_pin_ctrl { 359 struct rockchip_pin_bank *pin_banks; 360 u32 nr_banks; 361 u32 nr_pins; 362 char *label; 363 enum rockchip_pinctrl_type type; 364 int grf_mux_offset; 365 int pmu_mux_offset; 366 int grf_drv_offset; 367 int pmu_drv_offset; 368 struct rockchip_mux_recalced_data *iomux_recalced; 369 u32 niomux_recalced; 370 struct rockchip_mux_route_data *iomux_routes; 371 u32 niomux_routes; 372 373 int (*ctrl_data_re_init)(const struct rockchip_pin_ctrl *ctrl); 374 375 int (*soc_data_init)(struct rockchip_pinctrl_priv *info); 376 377 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 378 int pin_num, struct regmap **regmap, 379 int *reg, u8 *bit); 380 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 381 int pin_num, struct regmap **regmap, 382 int *reg, u8 *bit); 383 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 384 int pin_num, struct regmap **regmap, 385 int *reg, u8 *bit); 386 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank, 387 int pin_num, struct regmap **regmap, 388 int *reg, u8 *bit); 389 }; 390 391 /** 392 */ 393 struct rockchip_pinctrl_priv { 394 struct rockchip_pin_ctrl *ctrl; 395 struct regmap *regmap_base; 396 struct regmap *regmap_pmu; 397 398 }; 399 400 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 401 { 402 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 403 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 404 405 if (bank >= ctrl->nr_banks) { 406 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 407 return -EINVAL; 408 } 409 410 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 411 debug("pin conf pin %d >= %d\n", pin, 412 MAX_ROCKCHIP_GPIO_PER_BANK); 413 return -EINVAL; 414 } 415 416 return 0; 417 } 418 419 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 420 { 421 .num = 1, 422 .pin = 0, 423 .reg = 0x418, 424 .bit = 0, 425 .mask = 0x3 426 }, { 427 .num = 1, 428 .pin = 1, 429 .reg = 0x418, 430 .bit = 2, 431 .mask = 0x3 432 }, { 433 .num = 1, 434 .pin = 2, 435 .reg = 0x418, 436 .bit = 4, 437 .mask = 0x3 438 }, { 439 .num = 1, 440 .pin = 3, 441 .reg = 0x418, 442 .bit = 6, 443 .mask = 0x3 444 }, { 445 .num = 1, 446 .pin = 4, 447 .reg = 0x418, 448 .bit = 8, 449 .mask = 0x3 450 }, { 451 .num = 1, 452 .pin = 5, 453 .reg = 0x418, 454 .bit = 10, 455 .mask = 0x3 456 }, { 457 .num = 1, 458 .pin = 6, 459 .reg = 0x418, 460 .bit = 12, 461 .mask = 0x3 462 }, { 463 .num = 1, 464 .pin = 7, 465 .reg = 0x418, 466 .bit = 14, 467 .mask = 0x3 468 }, { 469 .num = 1, 470 .pin = 8, 471 .reg = 0x41c, 472 .bit = 0, 473 .mask = 0x3 474 }, { 475 .num = 1, 476 .pin = 9, 477 .reg = 0x41c, 478 .bit = 2, 479 .mask = 0x3 480 }, 481 }; 482 483 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 484 { 485 .num = 0, 486 .pin = 20, 487 .reg = 0x10000, 488 .bit = 0, 489 .mask = 0xf 490 }, 491 { 492 .num = 0, 493 .pin = 21, 494 .reg = 0x10000, 495 .bit = 4, 496 .mask = 0xf 497 }, 498 { 499 .num = 0, 500 .pin = 22, 501 .reg = 0x10000, 502 .bit = 8, 503 .mask = 0xf 504 }, 505 { 506 .num = 0, 507 .pin = 23, 508 .reg = 0x10000, 509 .bit = 12, 510 .mask = 0xf 511 }, 512 }; 513 514 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 515 { 516 .num = 2, 517 .pin = 20, 518 .reg = 0xe8, 519 .bit = 0, 520 .mask = 0x7 521 }, { 522 .num = 2, 523 .pin = 21, 524 .reg = 0xe8, 525 .bit = 4, 526 .mask = 0x7 527 }, { 528 .num = 2, 529 .pin = 22, 530 .reg = 0xe8, 531 .bit = 8, 532 .mask = 0x7 533 }, { 534 .num = 2, 535 .pin = 23, 536 .reg = 0xe8, 537 .bit = 12, 538 .mask = 0x7 539 }, { 540 .num = 2, 541 .pin = 24, 542 .reg = 0xd4, 543 .bit = 12, 544 .mask = 0x7 545 }, 546 }; 547 548 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 549 { 550 .num = 1, 551 .pin = 14, 552 .reg = 0x28, 553 .bit = 12, 554 .mask = 0x7 555 }, { 556 .num = 1, 557 .pin = 15, 558 .reg = 0x2c, 559 .bit = 0, 560 .mask = 0x3 561 }, { 562 .num = 1, 563 .pin = 18, 564 .reg = 0x30, 565 .bit = 4, 566 .mask = 0x7 567 }, { 568 .num = 1, 569 .pin = 19, 570 .reg = 0x30, 571 .bit = 8, 572 .mask = 0x7 573 }, { 574 .num = 1, 575 .pin = 20, 576 .reg = 0x30, 577 .bit = 12, 578 .mask = 0x7 579 }, { 580 .num = 1, 581 .pin = 21, 582 .reg = 0x34, 583 .bit = 0, 584 .mask = 0x7 585 }, { 586 .num = 1, 587 .pin = 22, 588 .reg = 0x34, 589 .bit = 4, 590 .mask = 0x7 591 }, { 592 .num = 1, 593 .pin = 23, 594 .reg = 0x34, 595 .bit = 8, 596 .mask = 0x7 597 }, { 598 .num = 3, 599 .pin = 12, 600 .reg = 0x68, 601 .bit = 8, 602 .mask = 0x7 603 }, { 604 .num = 3, 605 .pin = 13, 606 .reg = 0x68, 607 .bit = 12, 608 .mask = 0x7 609 }, 610 }; 611 612 static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { 613 { 614 .num = 1, 615 .pin = 14, 616 .reg = 0x28, 617 .bit = 12, 618 .mask = 0xf 619 }, { 620 .num = 1, 621 .pin = 15, 622 .reg = 0x2c, 623 .bit = 0, 624 .mask = 0x3 625 }, { 626 .num = 1, 627 .pin = 18, 628 .reg = 0x30, 629 .bit = 4, 630 .mask = 0xf 631 }, { 632 .num = 1, 633 .pin = 19, 634 .reg = 0x30, 635 .bit = 8, 636 .mask = 0xf 637 }, { 638 .num = 1, 639 .pin = 20, 640 .reg = 0x30, 641 .bit = 12, 642 .mask = 0xf 643 }, { 644 .num = 1, 645 .pin = 21, 646 .reg = 0x34, 647 .bit = 0, 648 .mask = 0xf 649 }, { 650 .num = 1, 651 .pin = 22, 652 .reg = 0x34, 653 .bit = 4, 654 .mask = 0xf 655 }, { 656 .num = 1, 657 .pin = 23, 658 .reg = 0x34, 659 .bit = 8, 660 .mask = 0xf 661 }, { 662 .num = 3, 663 .pin = 12, 664 .reg = 0x68, 665 .bit = 8, 666 .mask = 0xf 667 }, { 668 .num = 3, 669 .pin = 13, 670 .reg = 0x68, 671 .bit = 12, 672 .mask = 0xf 673 }, { 674 .num = 2, 675 .pin = 2, 676 .reg = 0x608, 677 .bit = 0, 678 .mask = 0x7 679 }, { 680 .num = 2, 681 .pin = 3, 682 .reg = 0x608, 683 .bit = 4, 684 .mask = 0x7 685 }, { 686 .num = 2, 687 .pin = 16, 688 .reg = 0x610, 689 .bit = 8, 690 .mask = 0x7 691 }, { 692 .num = 3, 693 .pin = 10, 694 .reg = 0x610, 695 .bit = 0, 696 .mask = 0x7 697 }, { 698 .num = 3, 699 .pin = 11, 700 .reg = 0x610, 701 .bit = 4, 702 .mask = 0x7 703 }, 704 }; 705 706 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 707 { 708 .num = 2, 709 .pin = 12, 710 .reg = 0x24, 711 .bit = 8, 712 .mask = 0x3 713 }, { 714 .num = 2, 715 .pin = 15, 716 .reg = 0x28, 717 .bit = 0, 718 .mask = 0x7 719 }, { 720 .num = 2, 721 .pin = 23, 722 .reg = 0x30, 723 .bit = 14, 724 .mask = 0x3 725 }, 726 }; 727 728 static struct rockchip_mux_route_data rv1126_mux_route_data[] = { 729 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ 730 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ 731 732 MR_TOPGRF(RK_GPIO0, RK_PD4, RK_FUNC_4, 0x10260, RK_GENMASK_VAL(2, 3, 0)), /* I2S1_MCLK_M0 */ 733 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(2, 3, 1)), /* I2S1_MCLK_M1 */ 734 MR_TOPGRF(RK_GPIO2, RK_PC7, RK_FUNC_6, 0x10260, RK_GENMASK_VAL(2, 3, 2)), /* I2S1_MCLK_M2 */ 735 736 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ 737 MR_TOPGRF(RK_GPIO2, RK_PB3, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ 738 739 MR_TOPGRF(RK_GPIO3, RK_PD4, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ 740 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ 741 742 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ 743 MR_TOPGRF(RK_GPIO2, RK_PD1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ 744 745 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(4, 5, 0)), /* I2C3_SCL_M0 */ 746 MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(4, 5, 1)), /* I2C3_SCL_M1 */ 747 MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(4, 5, 2)), /* I2C3_SCL_M2 */ 748 749 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ 750 MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ 751 752 MR_TOPGRF(RK_GPIO2, RK_PA5, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(8, 9, 0)), /* I2C5_SCL_M0 */ 753 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(8, 9, 1)), /* I2C5_SCL_M1 */ 754 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(8, 9, 2)), /* I2C5_SCL_M2 */ 755 756 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(10, 11, 0)), /* SPI1_CLK_M0 */ 757 MR_TOPGRF(RK_GPIO1, RK_PC6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(10, 11, 1)), /* SPI1_CLK_M1 */ 758 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_6, 0x10264, RK_GENMASK_VAL(10, 11, 2)), /* SPI1_CLK_M2 */ 759 760 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ 761 MR_TOPGRF(RK_GPIO2, RK_PB7, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ 762 763 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ 764 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ 765 766 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */ 767 MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */ 768 769 MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */ 770 MR_TOPGRF(RK_GPIO2, RK_PD6, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */ 771 772 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */ 773 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */ 774 775 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ 776 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ 777 778 MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ 779 MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ 780 781 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(10, 11, 0)), /* UART3_TX_M0 */ 782 MR_TOPGRF(RK_GPIO1, RK_PA7, RK_FUNC_2, 0x10268, RK_GENMASK_VAL(10, 11, 1)), /* UART3_TX_M1 */ 783 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(10, 11, 2)), /* UART3_TX_M2 */ 784 785 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(12, 13, 0)), /* UART4_TX_M0 */ 786 MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(12, 13, 1)), /* UART4_TX_M1 */ 787 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(12, 13, 2)), /* UART4_TX_M2 */ 788 789 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(14, 15, 0)), /* UART5_TX_M0 */ 790 MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(14, 15, 1)), /* UART5_TX_M1 */ 791 MR_TOPGRF(RK_GPIO2, RK_PA0, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(14, 15, 2)), /* UART5_TX_M2 */ 792 793 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */ 794 MR_PMUGRF(RK_GPIO2, RK_PB3, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */ 795 796 MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */ 797 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */ 798 799 MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */ 800 MR_PMUGRF(RK_GPIO2, RK_PB1, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */ 801 802 MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ 803 MR_PMUGRF(RK_GPIO2, RK_PB0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ 804 805 MR_PMUGRF(RK_GPIO0, RK_PC2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */ 806 MR_PMUGRF(RK_GPIO2, RK_PA7, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */ 807 808 MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */ 809 MR_PMUGRF(RK_GPIO2, RK_PA6, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */ 810 811 MR_PMUGRF(RK_GPIO0, RK_PB2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */ 812 MR_PMUGRF(RK_GPIO2, RK_PD4, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */ 813 814 MR_PMUGRF(RK_GPIO0, RK_PB1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ 815 MR_PMUGRF(RK_GPIO3, RK_PA0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ 816 817 MR_PMUGRF(RK_GPIO0, RK_PB0, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(0, 1, 0)), /* SPI0_CLK_M0 */ 818 MR_PMUGRF(RK_GPIO2, RK_PA1, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(0, 1, 1)), /* SPI0_CLK_M1 */ 819 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_6, 0x0118, RK_GENMASK_VAL(0, 1, 2)), /* SPI0_CLK_M2 */ 820 821 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ 822 MR_PMUGRF(RK_GPIO1, RK_PD0, RK_FUNC_5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ 823 }; 824 825 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 826 int *reg, u8 *bit, int *mask) 827 { 828 struct rockchip_pinctrl_priv *priv = bank->priv; 829 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 830 struct rockchip_mux_recalced_data *data; 831 int i; 832 833 for (i = 0; i < ctrl->niomux_recalced; i++) { 834 data = &ctrl->iomux_recalced[i]; 835 if (data->num == bank->bank_num && 836 data->pin == pin) 837 break; 838 } 839 840 if (i >= ctrl->niomux_recalced) 841 return; 842 843 *reg = data->reg; 844 *mask = data->mask; 845 *bit = data->bit; 846 } 847 848 static struct rockchip_mux_route_data px30_mux_route_data[] = { 849 { 850 /* cif-d2m0 */ 851 .bank_num = 2, 852 .pin = 0, 853 .func = 1, 854 .route_offset = 0x184, 855 .route_val = BIT(16 + 7), 856 }, { 857 /* cif-d2m1 */ 858 .bank_num = 3, 859 .pin = 3, 860 .func = 3, 861 .route_offset = 0x184, 862 .route_val = BIT(16 + 7) | BIT(7), 863 }, { 864 /* pdm-m0 */ 865 .bank_num = 3, 866 .pin = 22, 867 .func = 2, 868 .route_offset = 0x184, 869 .route_val = BIT(16 + 8), 870 }, { 871 /* pdm-m1 */ 872 .bank_num = 2, 873 .pin = 22, 874 .func = 1, 875 .route_offset = 0x184, 876 .route_val = BIT(16 + 8) | BIT(8), 877 }, { 878 /* uart2-rxm0 */ 879 .bank_num = 1, 880 .pin = 27, 881 .func = 2, 882 .route_offset = 0x184, 883 .route_val = BIT(16 + 10), 884 }, { 885 /* uart2-rxm1 */ 886 .bank_num = 2, 887 .pin = 14, 888 .func = 2, 889 .route_offset = 0x184, 890 .route_val = BIT(16 + 10) | BIT(10), 891 }, { 892 /* uart3-rxm0 */ 893 .bank_num = 0, 894 .pin = 17, 895 .func = 2, 896 .route_offset = 0x184, 897 .route_val = BIT(16 + 9), 898 }, { 899 /* uart3-rxm1 */ 900 .bank_num = 1, 901 .pin = 15, 902 .func = 2, 903 .route_offset = 0x184, 904 .route_val = BIT(16 + 9) | BIT(9), 905 }, 906 }; 907 908 static struct rockchip_mux_route_data rk1808_mux_route_data[] = { 909 { 910 /* i2c2m0_sda */ 911 .bank_num = 3, 912 .pin = 12, 913 .func = 2, 914 .route_offset = 0x190, 915 .route_val = BIT(16 + 3), 916 }, { 917 /* i2c2m1_sda */ 918 .bank_num = 1, 919 .pin = 13, 920 .func = 2, 921 .route_offset = 0x190, 922 .route_val = BIT(16 + 3) | BIT(3), 923 }, { 924 /* uart2_rxm0 */ 925 .bank_num = 4, 926 .pin = 3, 927 .func = 2, 928 .route_offset = 0x190, 929 .route_val = BIT(16 + 14) | BIT(16 + 15), 930 }, { 931 /* uart2_rxm1 */ 932 .bank_num = 2, 933 .pin = 25, 934 .func = 2, 935 .route_offset = 0x190, 936 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15), 937 }, { 938 /* uart2_rxm2 */ 939 .bank_num = 3, 940 .pin = 4, 941 .func = 2, 942 .route_offset = 0x190, 943 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15), 944 }, 945 }; 946 947 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 948 { 949 /* spi-0 */ 950 .bank_num = 1, 951 .pin = 10, 952 .func = 1, 953 .route_offset = 0x144, 954 .route_val = BIT(16 + 3) | BIT(16 + 4), 955 }, { 956 /* spi-1 */ 957 .bank_num = 1, 958 .pin = 27, 959 .func = 3, 960 .route_offset = 0x144, 961 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 962 }, { 963 /* spi-2 */ 964 .bank_num = 0, 965 .pin = 13, 966 .func = 2, 967 .route_offset = 0x144, 968 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 969 }, { 970 /* i2s-0 */ 971 .bank_num = 1, 972 .pin = 5, 973 .func = 1, 974 .route_offset = 0x144, 975 .route_val = BIT(16 + 5), 976 }, { 977 /* i2s-1 */ 978 .bank_num = 0, 979 .pin = 14, 980 .func = 1, 981 .route_offset = 0x144, 982 .route_val = BIT(16 + 5) | BIT(5), 983 }, { 984 /* emmc-0 */ 985 .bank_num = 1, 986 .pin = 22, 987 .func = 2, 988 .route_offset = 0x144, 989 .route_val = BIT(16 + 6), 990 }, { 991 /* emmc-1 */ 992 .bank_num = 2, 993 .pin = 4, 994 .func = 2, 995 .route_offset = 0x144, 996 .route_val = BIT(16 + 6) | BIT(6), 997 }, 998 }; 999 1000 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 1001 { 1002 /* pwm0-0 */ 1003 .bank_num = 0, 1004 .pin = 26, 1005 .func = 1, 1006 .route_offset = 0x50, 1007 .route_val = BIT(16), 1008 }, { 1009 /* pwm0-1 */ 1010 .bank_num = 3, 1011 .pin = 21, 1012 .func = 1, 1013 .route_offset = 0x50, 1014 .route_val = BIT(16) | BIT(0), 1015 }, { 1016 /* pwm1-0 */ 1017 .bank_num = 0, 1018 .pin = 27, 1019 .func = 1, 1020 .route_offset = 0x50, 1021 .route_val = BIT(16 + 1), 1022 }, { 1023 /* pwm1-1 */ 1024 .bank_num = 0, 1025 .pin = 30, 1026 .func = 2, 1027 .route_offset = 0x50, 1028 .route_val = BIT(16 + 1) | BIT(1), 1029 }, { 1030 /* pwm2-0 */ 1031 .bank_num = 0, 1032 .pin = 28, 1033 .func = 1, 1034 .route_offset = 0x50, 1035 .route_val = BIT(16 + 2), 1036 }, { 1037 /* pwm2-1 */ 1038 .bank_num = 1, 1039 .pin = 12, 1040 .func = 2, 1041 .route_offset = 0x50, 1042 .route_val = BIT(16 + 2) | BIT(2), 1043 }, { 1044 /* pwm3-0 */ 1045 .bank_num = 3, 1046 .pin = 26, 1047 .func = 1, 1048 .route_offset = 0x50, 1049 .route_val = BIT(16 + 3), 1050 }, { 1051 /* pwm3-1 */ 1052 .bank_num = 1, 1053 .pin = 11, 1054 .func = 2, 1055 .route_offset = 0x50, 1056 .route_val = BIT(16 + 3) | BIT(3), 1057 }, { 1058 /* sdio-0_d0 */ 1059 .bank_num = 1, 1060 .pin = 1, 1061 .func = 1, 1062 .route_offset = 0x50, 1063 .route_val = BIT(16 + 4), 1064 }, { 1065 /* sdio-1_d0 */ 1066 .bank_num = 3, 1067 .pin = 2, 1068 .func = 1, 1069 .route_offset = 0x50, 1070 .route_val = BIT(16 + 4) | BIT(4), 1071 }, { 1072 /* spi-0_rx */ 1073 .bank_num = 0, 1074 .pin = 13, 1075 .func = 2, 1076 .route_offset = 0x50, 1077 .route_val = BIT(16 + 5), 1078 }, { 1079 /* spi-1_rx */ 1080 .bank_num = 2, 1081 .pin = 0, 1082 .func = 2, 1083 .route_offset = 0x50, 1084 .route_val = BIT(16 + 5) | BIT(5), 1085 }, { 1086 /* emmc-0_cmd */ 1087 .bank_num = 1, 1088 .pin = 22, 1089 .func = 2, 1090 .route_offset = 0x50, 1091 .route_val = BIT(16 + 7), 1092 }, { 1093 /* emmc-1_cmd */ 1094 .bank_num = 2, 1095 .pin = 4, 1096 .func = 2, 1097 .route_offset = 0x50, 1098 .route_val = BIT(16 + 7) | BIT(7), 1099 }, { 1100 /* uart2-0_rx */ 1101 .bank_num = 1, 1102 .pin = 19, 1103 .func = 2, 1104 .route_offset = 0x50, 1105 .route_val = BIT(16 + 8), 1106 }, { 1107 /* uart2-1_rx */ 1108 .bank_num = 1, 1109 .pin = 10, 1110 .func = 2, 1111 .route_offset = 0x50, 1112 .route_val = BIT(16 + 8) | BIT(8), 1113 }, { 1114 /* uart1-0_rx */ 1115 .bank_num = 1, 1116 .pin = 10, 1117 .func = 1, 1118 .route_offset = 0x50, 1119 .route_val = BIT(16 + 11), 1120 }, { 1121 /* uart1-1_rx */ 1122 .bank_num = 3, 1123 .pin = 13, 1124 .func = 1, 1125 .route_offset = 0x50, 1126 .route_val = BIT(16 + 11) | BIT(11), 1127 }, 1128 }; 1129 1130 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 1131 { 1132 /* edphdmi_cecinoutt1 */ 1133 .bank_num = 7, 1134 .pin = 16, 1135 .func = 2, 1136 .route_offset = 0x264, 1137 .route_val = BIT(16 + 12) | BIT(12), 1138 }, { 1139 /* edphdmi_cecinout */ 1140 .bank_num = 7, 1141 .pin = 23, 1142 .func = 4, 1143 .route_offset = 0x264, 1144 .route_val = BIT(16 + 12), 1145 }, 1146 }; 1147 1148 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 1149 { 1150 /* rtc_clk */ 1151 .bank_num = 0, 1152 .pin = 19, 1153 .func = 1, 1154 .route_offset = 0x314, 1155 .route_val = BIT(16 + 0) | BIT(0), 1156 }, { 1157 /* uart2_rxm0 */ 1158 .bank_num = 1, 1159 .pin = 22, 1160 .func = 2, 1161 .route_offset = 0x314, 1162 .route_val = BIT(16 + 2) | BIT(16 + 3), 1163 }, { 1164 /* uart2_rxm1 */ 1165 .bank_num = 4, 1166 .pin = 26, 1167 .func = 2, 1168 .route_offset = 0x314, 1169 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1170 }, { 1171 /* i2c3_sdam0 */ 1172 .bank_num = 0, 1173 .pin = 23, 1174 .func = 2, 1175 .route_offset = 0x314, 1176 .route_val = BIT(16 + 4), 1177 }, { 1178 /* i2c3_sdam1 */ 1179 .bank_num = 3, 1180 .pin = 12, 1181 .func = 2, 1182 .route_offset = 0x314, 1183 .route_val = BIT(16 + 4) | BIT(4), 1184 }, { 1185 /* i2s-8ch-1-sclktxm0 */ 1186 .bank_num = 1, 1187 .pin = 3, 1188 .func = 2, 1189 .route_offset = 0x308, 1190 .route_val = BIT(16 + 3), 1191 }, { 1192 /* i2s-8ch-1-sclkrxm0 */ 1193 .bank_num = 1, 1194 .pin = 4, 1195 .func = 2, 1196 .route_offset = 0x308, 1197 .route_val = BIT(16 + 3), 1198 }, { 1199 /* i2s-8ch-1-sclktxm1 */ 1200 .bank_num = 1, 1201 .pin = 13, 1202 .func = 2, 1203 .route_offset = 0x308, 1204 .route_val = BIT(16 + 3) | BIT(3), 1205 }, { 1206 /* i2s-8ch-1-sclkrxm1 */ 1207 .bank_num = 1, 1208 .pin = 14, 1209 .func = 2, 1210 .route_offset = 0x308, 1211 .route_val = BIT(16 + 3) | BIT(3), 1212 }, { 1213 /* pdm-clkm0 */ 1214 .bank_num = 1, 1215 .pin = 4, 1216 .func = 3, 1217 .route_offset = 0x308, 1218 .route_val = BIT(16 + 12) | BIT(16 + 13), 1219 }, { 1220 /* pdm-clkm1 */ 1221 .bank_num = 1, 1222 .pin = 14, 1223 .func = 4, 1224 .route_offset = 0x308, 1225 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1226 }, { 1227 /* pdm-clkm2 */ 1228 .bank_num = 2, 1229 .pin = 6, 1230 .func = 2, 1231 .route_offset = 0x308, 1232 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1233 }, { 1234 /* pdm-clkm-m2 */ 1235 .bank_num = 2, 1236 .pin = 4, 1237 .func = 3, 1238 .route_offset = 0x600, 1239 .route_val = BIT(16 + 2) | BIT(2), 1240 }, 1241 }; 1242 1243 static struct rockchip_mux_route_data rk3308b_mux_route_data[] = { 1244 { 1245 /* rtc_clk */ 1246 .bank_num = 0, 1247 .pin = 19, 1248 .func = 1, 1249 .route_offset = 0x314, 1250 .route_val = BIT(16 + 0) | BIT(0), 1251 }, { 1252 /* uart2_rxm0 */ 1253 .bank_num = 1, 1254 .pin = 22, 1255 .func = 2, 1256 .route_offset = 0x314, 1257 .route_val = BIT(16 + 2) | BIT(16 + 3), 1258 }, { 1259 /* uart2_rxm1 */ 1260 .bank_num = 4, 1261 .pin = 26, 1262 .func = 2, 1263 .route_offset = 0x314, 1264 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1265 }, { 1266 /* i2c3_sdam0 */ 1267 .bank_num = 0, 1268 .pin = 15, 1269 .func = 2, 1270 .route_offset = 0x608, 1271 .route_val = BIT(16 + 8) | BIT(16 + 9), 1272 }, { 1273 /* i2c3_sdam1 */ 1274 .bank_num = 3, 1275 .pin = 12, 1276 .func = 2, 1277 .route_offset = 0x608, 1278 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 1279 }, { 1280 /* i2c3_sdam2 */ 1281 .bank_num = 2, 1282 .pin = 0, 1283 .func = 3, 1284 .route_offset = 0x608, 1285 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 1286 }, { 1287 /* i2s-8ch-1-sclktxm0 */ 1288 .bank_num = 1, 1289 .pin = 3, 1290 .func = 2, 1291 .route_offset = 0x308, 1292 .route_val = BIT(16 + 3), 1293 }, { 1294 /* i2s-8ch-1-sclkrxm0 */ 1295 .bank_num = 1, 1296 .pin = 4, 1297 .func = 2, 1298 .route_offset = 0x308, 1299 .route_val = BIT(16 + 3), 1300 }, { 1301 /* i2s-8ch-1-sclktxm1 */ 1302 .bank_num = 1, 1303 .pin = 13, 1304 .func = 2, 1305 .route_offset = 0x308, 1306 .route_val = BIT(16 + 3) | BIT(3), 1307 }, { 1308 /* i2s-8ch-1-sclkrxm1 */ 1309 .bank_num = 1, 1310 .pin = 14, 1311 .func = 2, 1312 .route_offset = 0x308, 1313 .route_val = BIT(16 + 3) | BIT(3), 1314 }, { 1315 /* pdm-clkm0 */ 1316 .bank_num = 1, 1317 .pin = 4, 1318 .func = 3, 1319 .route_offset = 0x308, 1320 .route_val = BIT(16 + 12) | BIT(16 + 13), 1321 }, { 1322 /* pdm-clkm1 */ 1323 .bank_num = 1, 1324 .pin = 14, 1325 .func = 4, 1326 .route_offset = 0x308, 1327 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1328 }, { 1329 /* pdm-clkm2 */ 1330 .bank_num = 2, 1331 .pin = 6, 1332 .func = 2, 1333 .route_offset = 0x308, 1334 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1335 }, { 1336 /* pdm-clkm-m2 */ 1337 .bank_num = 2, 1338 .pin = 4, 1339 .func = 3, 1340 .route_offset = 0x600, 1341 .route_val = BIT(16 + 2) | BIT(2), 1342 }, { 1343 /* spi1_miso */ 1344 .bank_num = 3, 1345 .pin = 10, 1346 .func = 3, 1347 .route_offset = 0x314, 1348 .route_val = BIT(16 + 9), 1349 }, { 1350 /* spi1_miso_m1 */ 1351 .bank_num = 2, 1352 .pin = 4, 1353 .func = 2, 1354 .route_offset = 0x314, 1355 .route_val = BIT(16 + 9) | BIT(9), 1356 }, { 1357 /* owire_m0 */ 1358 .bank_num = 0, 1359 .pin = 11, 1360 .func = 3, 1361 .route_offset = 0x314, 1362 .route_val = BIT(16 + 10) | BIT(16 + 11), 1363 }, { 1364 /* owire_m1 */ 1365 .bank_num = 1, 1366 .pin = 22, 1367 .func = 7, 1368 .route_offset = 0x314, 1369 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1370 }, { 1371 /* owire_m2 */ 1372 .bank_num = 2, 1373 .pin = 2, 1374 .func = 5, 1375 .route_offset = 0x314, 1376 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1377 }, { 1378 /* can_rxd_m0 */ 1379 .bank_num = 0, 1380 .pin = 11, 1381 .func = 2, 1382 .route_offset = 0x314, 1383 .route_val = BIT(16 + 12) | BIT(16 + 13), 1384 }, { 1385 /* can_rxd_m1 */ 1386 .bank_num = 1, 1387 .pin = 22, 1388 .func = 5, 1389 .route_offset = 0x314, 1390 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1391 }, { 1392 /* can_rxd_m2 */ 1393 .bank_num = 2, 1394 .pin = 2, 1395 .func = 4, 1396 .route_offset = 0x314, 1397 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1398 }, { 1399 /* mac_rxd0_m0 */ 1400 .bank_num = 1, 1401 .pin = 20, 1402 .func = 3, 1403 .route_offset = 0x314, 1404 .route_val = BIT(16 + 14), 1405 }, { 1406 /* mac_rxd0_m1 */ 1407 .bank_num = 4, 1408 .pin = 2, 1409 .func = 2, 1410 .route_offset = 0x314, 1411 .route_val = BIT(16 + 14) | BIT(14), 1412 }, { 1413 /* uart3_rx */ 1414 .bank_num = 3, 1415 .pin = 12, 1416 .func = 4, 1417 .route_offset = 0x314, 1418 .route_val = BIT(16 + 15), 1419 }, { 1420 /* uart3_rx_m1 */ 1421 .bank_num = 0, 1422 .pin = 17, 1423 .func = 3, 1424 .route_offset = 0x314, 1425 .route_val = BIT(16 + 15) | BIT(15), 1426 }, 1427 }; 1428 1429 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1430 { 1431 /* uart2dbg_rxm0 */ 1432 .bank_num = 1, 1433 .pin = 1, 1434 .func = 2, 1435 .route_offset = 0x50, 1436 .route_val = BIT(16) | BIT(16 + 1), 1437 }, { 1438 /* uart2dbg_rxm1 */ 1439 .bank_num = 2, 1440 .pin = 1, 1441 .func = 1, 1442 .route_offset = 0x50, 1443 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1444 }, { 1445 /* gmac-m1_rxd0 */ 1446 .bank_num = 1, 1447 .pin = 11, 1448 .func = 2, 1449 .route_offset = 0x50, 1450 .route_val = BIT(16 + 2) | BIT(2), 1451 }, { 1452 /* gmac-m1-optimized_rxd3 */ 1453 .bank_num = 1, 1454 .pin = 14, 1455 .func = 2, 1456 .route_offset = 0x50, 1457 .route_val = BIT(16 + 10) | BIT(10), 1458 }, { 1459 /* pdm_sdi0m0 */ 1460 .bank_num = 2, 1461 .pin = 19, 1462 .func = 2, 1463 .route_offset = 0x50, 1464 .route_val = BIT(16 + 3), 1465 }, { 1466 /* pdm_sdi0m1 */ 1467 .bank_num = 1, 1468 .pin = 23, 1469 .func = 3, 1470 .route_offset = 0x50, 1471 .route_val = BIT(16 + 3) | BIT(3), 1472 }, { 1473 /* spi_rxdm2 */ 1474 .bank_num = 3, 1475 .pin = 2, 1476 .func = 4, 1477 .route_offset = 0x50, 1478 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1479 }, { 1480 /* i2s2_sdim0 */ 1481 .bank_num = 1, 1482 .pin = 24, 1483 .func = 1, 1484 .route_offset = 0x50, 1485 .route_val = BIT(16 + 6), 1486 }, { 1487 /* i2s2_sdim1 */ 1488 .bank_num = 3, 1489 .pin = 2, 1490 .func = 6, 1491 .route_offset = 0x50, 1492 .route_val = BIT(16 + 6) | BIT(6), 1493 }, { 1494 /* card_iom1 */ 1495 .bank_num = 2, 1496 .pin = 22, 1497 .func = 3, 1498 .route_offset = 0x50, 1499 .route_val = BIT(16 + 7) | BIT(7), 1500 }, { 1501 /* tsp_d5m1 */ 1502 .bank_num = 2, 1503 .pin = 16, 1504 .func = 3, 1505 .route_offset = 0x50, 1506 .route_val = BIT(16 + 8) | BIT(8), 1507 }, { 1508 /* cif_data5m1 */ 1509 .bank_num = 2, 1510 .pin = 16, 1511 .func = 4, 1512 .route_offset = 0x50, 1513 .route_val = BIT(16 + 9) | BIT(9), 1514 }, 1515 }; 1516 1517 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1518 { 1519 /* uart2dbga_rx */ 1520 .bank_num = 4, 1521 .pin = 8, 1522 .func = 2, 1523 .route_offset = 0xe21c, 1524 .route_val = BIT(16 + 10) | BIT(16 + 11), 1525 }, { 1526 /* uart2dbgb_rx */ 1527 .bank_num = 4, 1528 .pin = 16, 1529 .func = 2, 1530 .route_offset = 0xe21c, 1531 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1532 }, { 1533 /* uart2dbgc_rx */ 1534 .bank_num = 4, 1535 .pin = 19, 1536 .func = 1, 1537 .route_offset = 0xe21c, 1538 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1539 }, { 1540 /* pcie_clkreqn */ 1541 .bank_num = 2, 1542 .pin = 26, 1543 .func = 2, 1544 .route_offset = 0xe21c, 1545 .route_val = BIT(16 + 14), 1546 }, { 1547 /* pcie_clkreqnb */ 1548 .bank_num = 4, 1549 .pin = 24, 1550 .func = 1, 1551 .route_offset = 0xe21c, 1552 .route_val = BIT(16 + 14) | BIT(14), 1553 }, 1554 }; 1555 1556 static enum rockchip_pin_route_type 1557 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1558 int mux, u32 *reg, u32 *value) 1559 { 1560 struct rockchip_pinctrl_priv *priv = bank->priv; 1561 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1562 struct rockchip_mux_route_data *data; 1563 int i; 1564 1565 for (i = 0; i < ctrl->niomux_routes; i++) { 1566 data = &ctrl->iomux_routes[i]; 1567 if ((data->bank_num == bank->bank_num) && 1568 (data->pin == pin) && (data->func == mux)) 1569 break; 1570 } 1571 1572 if (i >= ctrl->niomux_routes) 1573 return ROUTE_TYPE_INVALID; 1574 1575 *reg = data->route_offset; 1576 *value = data->route_val; 1577 1578 return data->route_type; 1579 } 1580 1581 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1582 { 1583 struct rockchip_pinctrl_priv *priv = bank->priv; 1584 int iomux_num = (pin / 8); 1585 struct regmap *regmap; 1586 unsigned int val; 1587 int reg, ret, mask, mux_type; 1588 u8 bit; 1589 1590 if (iomux_num > 3) 1591 return -EINVAL; 1592 1593 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1594 debug("pin %d is unrouted\n", pin); 1595 return -EINVAL; 1596 } 1597 1598 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1599 return RK_FUNC_GPIO; 1600 1601 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1602 regmap = priv->regmap_pmu; 1603 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1604 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 1605 else 1606 regmap = priv->regmap_base; 1607 1608 /* get basic quadrupel of mux registers and the correct reg inside */ 1609 mux_type = bank->iomux[iomux_num].type; 1610 reg = bank->iomux[iomux_num].offset; 1611 if (mux_type & IOMUX_WIDTH_4BIT) { 1612 if ((pin % 8) >= 4) 1613 reg += 0x4; 1614 bit = (pin % 4) * 4; 1615 mask = 0xf; 1616 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1617 if ((pin % 8) >= 5) 1618 reg += 0x4; 1619 bit = (pin % 8 % 5) * 3; 1620 mask = 0x7; 1621 } else { 1622 bit = (pin % 8) * 2; 1623 mask = 0x3; 1624 } 1625 1626 if (bank->recalced_mask & BIT(pin)) 1627 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1628 1629 ret = regmap_read(regmap, reg, &val); 1630 if (ret) 1631 return ret; 1632 1633 return ((val >> bit) & mask); 1634 } 1635 1636 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1637 int index) 1638 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1639 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1640 1641 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1642 } 1643 1644 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1645 int pin, int mux) 1646 { 1647 int iomux_num = (pin / 8); 1648 1649 if (iomux_num > 3) 1650 return -EINVAL; 1651 1652 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1653 debug("pin %d is unrouted\n", pin); 1654 return -EINVAL; 1655 } 1656 1657 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1658 if (mux != IOMUX_GPIO_ONLY) { 1659 debug("pin %d only supports a gpio mux\n", pin); 1660 return -ENOTSUPP; 1661 } 1662 } 1663 1664 return 0; 1665 } 1666 1667 /* 1668 * Set a new mux function for a pin. 1669 * 1670 * The register is divided into the upper and lower 16 bit. When changing 1671 * a value, the previous register value is not read and changed. Instead 1672 * it seems the changed bits are marked in the upper 16 bit, while the 1673 * changed value gets set in the same offset in the lower 16 bit. 1674 * All pin settings seem to be 2 bit wide in both the upper and lower 1675 * parts. 1676 * @bank: pin bank to change 1677 * @pin: pin to change 1678 * @mux: new mux function to set 1679 */ 1680 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1681 { 1682 struct rockchip_pinctrl_priv *priv = bank->priv; 1683 int iomux_num = (pin / 8); 1684 struct regmap *regmap; 1685 int reg, ret, mask, mux_type; 1686 u8 bit; 1687 u32 data; 1688 1689 ret = rockchip_verify_mux(bank, pin, mux); 1690 if (ret < 0) 1691 return ret; 1692 1693 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1694 return 0; 1695 1696 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1697 1698 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1699 regmap = priv->regmap_pmu; 1700 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1701 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 1702 else 1703 regmap = priv->regmap_base; 1704 1705 /* get basic quadrupel of mux registers and the correct reg inside */ 1706 mux_type = bank->iomux[iomux_num].type; 1707 reg = bank->iomux[iomux_num].offset; 1708 if (mux_type & IOMUX_WIDTH_4BIT) { 1709 if ((pin % 8) >= 4) 1710 reg += 0x4; 1711 bit = (pin % 4) * 4; 1712 mask = 0xf; 1713 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1714 if ((pin % 8) >= 5) 1715 reg += 0x4; 1716 bit = (pin % 8 % 5) * 3; 1717 mask = 0x7; 1718 } else { 1719 bit = (pin % 8) * 2; 1720 mask = 0x3; 1721 } 1722 1723 if (bank->recalced_mask & BIT(pin)) 1724 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1725 1726 if (bank->route_mask & BIT(pin)) { 1727 u32 route_reg = 0, route_val = 0; 1728 1729 ret = rockchip_get_mux_route(bank, pin, mux, 1730 &route_reg, &route_val); 1731 switch (ret) { 1732 case ROUTE_TYPE_DEFAULT: 1733 regmap_write(regmap, route_reg, route_val); 1734 break; 1735 case ROUTE_TYPE_TOPGRF: 1736 regmap_write(priv->regmap_base, route_reg, route_val); 1737 break; 1738 case ROUTE_TYPE_PMUGRF: 1739 regmap_write(priv->regmap_pmu, route_reg, route_val); 1740 break; 1741 case ROUTE_TYPE_INVALID: /* Fall through */ 1742 default: 1743 break; 1744 } 1745 } 1746 1747 if (mux_type & IOMUX_WRITABLE_32BIT) { 1748 regmap_read(regmap, reg, &data); 1749 data &= ~(mask << bit); 1750 } else { 1751 data = (mask << (bit + 16)); 1752 } 1753 1754 data |= (mux & mask) << bit; 1755 ret = regmap_write(regmap, reg, data); 1756 1757 return ret; 1758 } 1759 1760 #define PX30_PULL_PMU_OFFSET 0x10 1761 #define PX30_PULL_GRF_OFFSET 0x60 1762 #define PX30_PULL_BITS_PER_PIN 2 1763 #define PX30_PULL_PINS_PER_REG 8 1764 #define PX30_PULL_BANK_STRIDE 16 1765 1766 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1767 int pin_num, struct regmap **regmap, 1768 int *reg, u8 *bit) 1769 { 1770 struct rockchip_pinctrl_priv *priv = bank->priv; 1771 1772 /* The first 32 pins of the first bank are located in PMU */ 1773 if (bank->bank_num == 0) { 1774 *regmap = priv->regmap_pmu; 1775 *reg = PX30_PULL_PMU_OFFSET; 1776 } else { 1777 *regmap = priv->regmap_base; 1778 *reg = PX30_PULL_GRF_OFFSET; 1779 1780 /* correct the offset, as we're starting with the 2nd bank */ 1781 *reg -= 0x10; 1782 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1783 } 1784 1785 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1786 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1787 *bit *= PX30_PULL_BITS_PER_PIN; 1788 } 1789 1790 #define PX30_DRV_PMU_OFFSET 0x20 1791 #define PX30_DRV_GRF_OFFSET 0xf0 1792 #define PX30_DRV_BITS_PER_PIN 2 1793 #define PX30_DRV_PINS_PER_REG 8 1794 #define PX30_DRV_BANK_STRIDE 16 1795 1796 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1797 int pin_num, struct regmap **regmap, 1798 int *reg, u8 *bit) 1799 { 1800 struct rockchip_pinctrl_priv *priv = bank->priv; 1801 1802 /* The first 32 pins of the first bank are located in PMU */ 1803 if (bank->bank_num == 0) { 1804 *regmap = priv->regmap_pmu; 1805 *reg = PX30_DRV_PMU_OFFSET; 1806 } else { 1807 *regmap = priv->regmap_base; 1808 *reg = PX30_DRV_GRF_OFFSET; 1809 1810 /* correct the offset, as we're starting with the 2nd bank */ 1811 *reg -= 0x10; 1812 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1813 } 1814 1815 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1816 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1817 *bit *= PX30_DRV_BITS_PER_PIN; 1818 } 1819 1820 #define PX30_SCHMITT_PMU_OFFSET 0x38 1821 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1822 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1823 #define PX30_SCHMITT_BANK_STRIDE 16 1824 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1825 1826 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1827 int pin_num, 1828 struct regmap **regmap, 1829 int *reg, u8 *bit) 1830 { 1831 struct rockchip_pinctrl_priv *priv = bank->priv; 1832 int pins_per_reg; 1833 1834 if (bank->bank_num == 0) { 1835 *regmap = priv->regmap_pmu; 1836 *reg = PX30_SCHMITT_PMU_OFFSET; 1837 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1838 } else { 1839 *regmap = priv->regmap_base; 1840 *reg = PX30_SCHMITT_GRF_OFFSET; 1841 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1842 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1843 } 1844 *reg += ((pin_num / pins_per_reg) * 4); 1845 *bit = pin_num % pins_per_reg; 1846 1847 return 0; 1848 } 1849 1850 #define RV1108_PULL_PMU_OFFSET 0x10 1851 #define RV1108_PULL_OFFSET 0x110 1852 #define RV1108_PULL_PINS_PER_REG 8 1853 #define RV1108_PULL_BITS_PER_PIN 2 1854 #define RV1108_PULL_BANK_STRIDE 16 1855 1856 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1857 int pin_num, struct regmap **regmap, 1858 int *reg, u8 *bit) 1859 { 1860 struct rockchip_pinctrl_priv *priv = bank->priv; 1861 1862 /* The first 24 pins of the first bank are located in PMU */ 1863 if (bank->bank_num == 0) { 1864 *regmap = priv->regmap_pmu; 1865 *reg = RV1108_PULL_PMU_OFFSET; 1866 } else { 1867 *reg = RV1108_PULL_OFFSET; 1868 *regmap = priv->regmap_base; 1869 /* correct the offset, as we're starting with the 2nd bank */ 1870 *reg -= 0x10; 1871 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1872 } 1873 1874 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1875 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1876 *bit *= RV1108_PULL_BITS_PER_PIN; 1877 } 1878 1879 #define RV1108_DRV_PMU_OFFSET 0x20 1880 #define RV1108_DRV_GRF_OFFSET 0x210 1881 #define RV1108_DRV_BITS_PER_PIN 2 1882 #define RV1108_DRV_PINS_PER_REG 8 1883 #define RV1108_DRV_BANK_STRIDE 16 1884 1885 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1886 int pin_num, struct regmap **regmap, 1887 int *reg, u8 *bit) 1888 { 1889 struct rockchip_pinctrl_priv *priv = bank->priv; 1890 1891 /* The first 24 pins of the first bank are located in PMU */ 1892 if (bank->bank_num == 0) { 1893 *regmap = priv->regmap_pmu; 1894 *reg = RV1108_DRV_PMU_OFFSET; 1895 } else { 1896 *regmap = priv->regmap_base; 1897 *reg = RV1108_DRV_GRF_OFFSET; 1898 1899 /* correct the offset, as we're starting with the 2nd bank */ 1900 *reg -= 0x10; 1901 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1902 } 1903 1904 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1905 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1906 *bit *= RV1108_DRV_BITS_PER_PIN; 1907 } 1908 1909 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1910 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1911 #define RV1108_SCHMITT_BANK_STRIDE 8 1912 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1913 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1914 1915 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1916 int pin_num, 1917 struct regmap **regmap, 1918 int *reg, u8 *bit) 1919 { 1920 struct rockchip_pinctrl_priv *priv = bank->priv; 1921 int pins_per_reg; 1922 1923 if (bank->bank_num == 0) { 1924 *regmap = priv->regmap_pmu; 1925 *reg = RV1108_SCHMITT_PMU_OFFSET; 1926 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1927 } else { 1928 *regmap = priv->regmap_base; 1929 *reg = RV1108_SCHMITT_GRF_OFFSET; 1930 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1931 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1932 } 1933 *reg += ((pin_num / pins_per_reg) * 4); 1934 *bit = pin_num % pins_per_reg; 1935 1936 return 0; 1937 } 1938 1939 #define RV1126_PULL_PMU_OFFSET 0x40 1940 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 1941 #define RV1126_PULL_PINS_PER_REG 8 1942 #define RV1126_PULL_BITS_PER_PIN 2 1943 #define RV1126_PULL_BANK_STRIDE 16 1944 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 1945 1946 static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1947 int pin_num, struct regmap **regmap, 1948 int *reg, u8 *bit) 1949 { 1950 struct rockchip_pinctrl_priv *priv = bank->priv; 1951 1952 /* The first 24 pins of the first bank are located in PMU */ 1953 if (bank->bank_num == 0) { 1954 if (RV1126_GPIO_C4_D7(pin_num)) { 1955 *regmap = priv->regmap_base; 1956 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1957 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 1958 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 1959 *bit *= RV1126_PULL_BITS_PER_PIN; 1960 return; 1961 } 1962 *regmap = priv->regmap_pmu; 1963 *reg = RV1126_PULL_PMU_OFFSET; 1964 } else { 1965 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1966 *regmap = priv->regmap_base; 1967 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; 1968 } 1969 1970 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 1971 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 1972 *bit *= RV1126_PULL_BITS_PER_PIN; 1973 } 1974 1975 #define RV1126_DRV_PMU_OFFSET 0x20 1976 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 1977 #define RV1126_DRV_BITS_PER_PIN 4 1978 #define RV1126_DRV_PINS_PER_REG 4 1979 #define RV1126_DRV_BANK_STRIDE 32 1980 1981 static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1982 int pin_num, struct regmap **regmap, 1983 int *reg, u8 *bit) 1984 { 1985 struct rockchip_pinctrl_priv *priv = bank->priv; 1986 1987 /* The first 24 pins of the first bank are located in PMU */ 1988 if (bank->bank_num == 0) { 1989 if (RV1126_GPIO_C4_D7(pin_num)) { 1990 *regmap = priv->regmap_base; 1991 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1992 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 1993 *reg -= 0x4; 1994 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1995 *bit *= RV1126_DRV_BITS_PER_PIN; 1996 return; 1997 } 1998 *regmap = priv->regmap_pmu; 1999 *reg = RV1126_DRV_PMU_OFFSET; 2000 } else { 2001 *regmap = priv->regmap_base; 2002 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 2003 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; 2004 } 2005 2006 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 2007 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 2008 *bit *= RV1126_DRV_BITS_PER_PIN; 2009 } 2010 2011 #define RV1126_SCHMITT_PMU_OFFSET 0x60 2012 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 2013 #define RV1126_SCHMITT_BANK_STRIDE 16 2014 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8 2015 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8 2016 2017 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2018 int pin_num, 2019 struct regmap **regmap, 2020 int *reg, u8 *bit) 2021 { 2022 struct rockchip_pinctrl_priv *priv = bank->priv; 2023 int pins_per_reg; 2024 2025 if (bank->bank_num == 0) { 2026 if (RV1126_GPIO_C4_D7(pin_num)) { 2027 *regmap = priv->regmap_base; 2028 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 2029 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 2030 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 2031 return 0; 2032 } 2033 *regmap = priv->regmap_pmu; 2034 *reg = RV1126_SCHMITT_PMU_OFFSET; 2035 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 2036 } else { 2037 *regmap = priv->regmap_base; 2038 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 2039 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 2040 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; 2041 } 2042 *reg += ((pin_num / pins_per_reg) * 4); 2043 *bit = pin_num % pins_per_reg; 2044 2045 return 0; 2046 } 2047 2048 #define RK1808_PULL_PMU_OFFSET 0x10 2049 #define RK1808_PULL_GRF_OFFSET 0x80 2050 #define RK1808_PULL_PINS_PER_REG 8 2051 #define RK1808_PULL_BITS_PER_PIN 2 2052 #define RK1808_PULL_BANK_STRIDE 16 2053 2054 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2055 int pin_num, 2056 struct regmap **regmap, 2057 int *reg, u8 *bit) 2058 { 2059 struct rockchip_pinctrl_priv *priv = bank->priv; 2060 2061 if (bank->bank_num == 0) { 2062 *regmap = priv->regmap_pmu; 2063 *reg = RK1808_PULL_PMU_OFFSET; 2064 } else { 2065 *reg = RK1808_PULL_GRF_OFFSET; 2066 *regmap = priv->regmap_base; 2067 } 2068 2069 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4); 2070 *bit = (pin_num % RK1808_PULL_PINS_PER_REG); 2071 *bit *= RK1808_PULL_BITS_PER_PIN; 2072 } 2073 2074 #define RK1808_DRV_PMU_OFFSET 0x20 2075 #define RK1808_DRV_GRF_OFFSET 0x140 2076 #define RK1808_DRV_BITS_PER_PIN 2 2077 #define RK1808_DRV_PINS_PER_REG 8 2078 #define RK1808_DRV_BANK_STRIDE 16 2079 2080 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2081 int pin_num, 2082 struct regmap **regmap, 2083 int *reg, u8 *bit) 2084 { 2085 struct rockchip_pinctrl_priv *priv = bank->priv; 2086 2087 if (bank->bank_num == 0) { 2088 *regmap = priv->regmap_pmu; 2089 *reg = RK1808_DRV_PMU_OFFSET; 2090 } else { 2091 *regmap = priv->regmap_base; 2092 *reg = RK1808_DRV_GRF_OFFSET; 2093 } 2094 2095 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4); 2096 *bit = pin_num % RK1808_DRV_PINS_PER_REG; 2097 *bit *= RK1808_DRV_BITS_PER_PIN; 2098 } 2099 2100 #define RK1808_SCHMITT_PMU_OFFSET 0x0040 2101 #define RK1808_SCHMITT_GRF_OFFSET 0x0100 2102 #define RK1808_SCHMITT_BANK_STRIDE 16 2103 #define RK1808_SCHMITT_PINS_PER_REG 8 2104 2105 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2106 int pin_num, 2107 struct regmap **regmap, 2108 int *reg, u8 *bit) 2109 { 2110 struct rockchip_pinctrl_priv *priv = bank->priv; 2111 2112 if (bank->bank_num == 0) { 2113 *regmap = priv->regmap_pmu; 2114 *reg = RK1808_SCHMITT_PMU_OFFSET; 2115 } else { 2116 *regmap = priv->regmap_base; 2117 *reg = RK1808_SCHMITT_GRF_OFFSET; 2118 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE; 2119 } 2120 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4); 2121 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG; 2122 2123 return 0; 2124 } 2125 2126 #define RK2928_PULL_OFFSET 0x118 2127 #define RK2928_PULL_PINS_PER_REG 16 2128 #define RK2928_PULL_BANK_STRIDE 8 2129 2130 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2131 int pin_num, struct regmap **regmap, 2132 int *reg, u8 *bit) 2133 { 2134 struct rockchip_pinctrl_priv *priv = bank->priv; 2135 2136 *regmap = priv->regmap_base; 2137 *reg = RK2928_PULL_OFFSET; 2138 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 2139 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 2140 2141 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 2142 }; 2143 2144 #define RK3128_PULL_OFFSET 0x118 2145 2146 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2147 int pin_num, struct regmap **regmap, 2148 int *reg, u8 *bit) 2149 { 2150 struct rockchip_pinctrl_priv *priv = bank->priv; 2151 2152 *regmap = priv->regmap_base; 2153 *reg = RK3128_PULL_OFFSET; 2154 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 2155 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 2156 2157 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 2158 } 2159 2160 #define RK3188_PULL_OFFSET 0x164 2161 #define RK3188_PULL_BITS_PER_PIN 2 2162 #define RK3188_PULL_PINS_PER_REG 8 2163 #define RK3188_PULL_BANK_STRIDE 16 2164 #define RK3188_PULL_PMU_OFFSET 0x64 2165 2166 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2167 int pin_num, struct regmap **regmap, 2168 int *reg, u8 *bit) 2169 { 2170 struct rockchip_pinctrl_priv *priv = bank->priv; 2171 2172 /* The first 12 pins of the first bank are located elsewhere */ 2173 if (bank->bank_num == 0 && pin_num < 12) { 2174 *regmap = priv->regmap_pmu; 2175 *reg = RK3188_PULL_PMU_OFFSET; 2176 2177 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2178 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2179 *bit *= RK3188_PULL_BITS_PER_PIN; 2180 } else { 2181 *regmap = priv->regmap_base; 2182 *reg = RK3188_PULL_OFFSET; 2183 2184 /* correct the offset, as it is the 2nd pull register */ 2185 *reg -= 4; 2186 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2187 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2188 2189 /* 2190 * The bits in these registers have an inverse ordering 2191 * with the lowest pin being in bits 15:14 and the highest 2192 * pin in bits 1:0 2193 */ 2194 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 2195 *bit *= RK3188_PULL_BITS_PER_PIN; 2196 } 2197 } 2198 2199 #define RK3288_PULL_OFFSET 0x140 2200 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2201 int pin_num, struct regmap **regmap, 2202 int *reg, u8 *bit) 2203 { 2204 struct rockchip_pinctrl_priv *priv = bank->priv; 2205 2206 /* The first 24 pins of the first bank are located in PMU */ 2207 if (bank->bank_num == 0) { 2208 *regmap = priv->regmap_pmu; 2209 *reg = RK3188_PULL_PMU_OFFSET; 2210 2211 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2212 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2213 *bit *= RK3188_PULL_BITS_PER_PIN; 2214 } else { 2215 *regmap = priv->regmap_base; 2216 *reg = RK3288_PULL_OFFSET; 2217 2218 /* correct the offset, as we're starting with the 2nd bank */ 2219 *reg -= 0x10; 2220 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2221 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2222 2223 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2224 *bit *= RK3188_PULL_BITS_PER_PIN; 2225 } 2226 } 2227 2228 #define RK3288_DRV_PMU_OFFSET 0x70 2229 #define RK3288_DRV_GRF_OFFSET 0x1c0 2230 #define RK3288_DRV_BITS_PER_PIN 2 2231 #define RK3288_DRV_PINS_PER_REG 8 2232 #define RK3288_DRV_BANK_STRIDE 16 2233 2234 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2235 int pin_num, struct regmap **regmap, 2236 int *reg, u8 *bit) 2237 { 2238 struct rockchip_pinctrl_priv *priv = bank->priv; 2239 2240 /* The first 24 pins of the first bank are located in PMU */ 2241 if (bank->bank_num == 0) { 2242 *regmap = priv->regmap_pmu; 2243 *reg = RK3288_DRV_PMU_OFFSET; 2244 2245 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2246 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2247 *bit *= RK3288_DRV_BITS_PER_PIN; 2248 } else { 2249 *regmap = priv->regmap_base; 2250 *reg = RK3288_DRV_GRF_OFFSET; 2251 2252 /* correct the offset, as we're starting with the 2nd bank */ 2253 *reg -= 0x10; 2254 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2255 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2256 2257 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2258 *bit *= RK3288_DRV_BITS_PER_PIN; 2259 } 2260 } 2261 2262 #define RK3228_PULL_OFFSET 0x100 2263 2264 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2265 int pin_num, struct regmap **regmap, 2266 int *reg, u8 *bit) 2267 { 2268 struct rockchip_pinctrl_priv *priv = bank->priv; 2269 2270 *regmap = priv->regmap_base; 2271 *reg = RK3228_PULL_OFFSET; 2272 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2273 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2274 2275 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2276 *bit *= RK3188_PULL_BITS_PER_PIN; 2277 } 2278 2279 #define RK3228_DRV_GRF_OFFSET 0x200 2280 2281 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2282 int pin_num, struct regmap **regmap, 2283 int *reg, u8 *bit) 2284 { 2285 struct rockchip_pinctrl_priv *priv = bank->priv; 2286 2287 *regmap = priv->regmap_base; 2288 *reg = RK3228_DRV_GRF_OFFSET; 2289 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2290 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2291 2292 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2293 *bit *= RK3288_DRV_BITS_PER_PIN; 2294 } 2295 2296 #define RK3308_PULL_OFFSET 0xa0 2297 2298 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2299 int pin_num, struct regmap **regmap, 2300 int *reg, u8 *bit) 2301 { 2302 struct rockchip_pinctrl_priv *priv = bank->priv; 2303 2304 *regmap = priv->regmap_base; 2305 *reg = RK3308_PULL_OFFSET; 2306 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2307 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2308 2309 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2310 *bit *= RK3188_PULL_BITS_PER_PIN; 2311 } 2312 2313 #define RK3308_DRV_GRF_OFFSET 0x100 2314 2315 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2316 int pin_num, struct regmap **regmap, 2317 int *reg, u8 *bit) 2318 { 2319 struct rockchip_pinctrl_priv *priv = bank->priv; 2320 2321 *regmap = priv->regmap_base; 2322 *reg = RK3308_DRV_GRF_OFFSET; 2323 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2324 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2325 2326 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2327 *bit *= RK3288_DRV_BITS_PER_PIN; 2328 } 2329 2330 #define RK3308_SCHMITT_PINS_PER_REG 8 2331 #define RK3308_SCHMITT_BANK_STRIDE 16 2332 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 2333 2334 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2335 int pin_num, 2336 struct regmap **regmap, 2337 int *reg, u8 *bit) 2338 { 2339 struct rockchip_pinctrl_priv *priv = bank->priv; 2340 2341 *regmap = priv->regmap_base; 2342 *reg = RK3308_SCHMITT_GRF_OFFSET; 2343 2344 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 2345 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 2346 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 2347 2348 return 0; 2349 } 2350 2351 #define RK3368_PULL_GRF_OFFSET 0x100 2352 #define RK3368_PULL_PMU_OFFSET 0x10 2353 2354 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2355 int pin_num, struct regmap **regmap, 2356 int *reg, u8 *bit) 2357 { 2358 struct rockchip_pinctrl_priv *priv = bank->priv; 2359 2360 /* The first 32 pins of the first bank are located in PMU */ 2361 if (bank->bank_num == 0) { 2362 *regmap = priv->regmap_pmu; 2363 *reg = RK3368_PULL_PMU_OFFSET; 2364 2365 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2366 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2367 *bit *= RK3188_PULL_BITS_PER_PIN; 2368 } else { 2369 *regmap = priv->regmap_base; 2370 *reg = RK3368_PULL_GRF_OFFSET; 2371 2372 /* correct the offset, as we're starting with the 2nd bank */ 2373 *reg -= 0x10; 2374 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2375 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2376 2377 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2378 *bit *= RK3188_PULL_BITS_PER_PIN; 2379 } 2380 } 2381 2382 #define RK3368_DRV_PMU_OFFSET 0x20 2383 #define RK3368_DRV_GRF_OFFSET 0x200 2384 2385 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2386 int pin_num, struct regmap **regmap, 2387 int *reg, u8 *bit) 2388 { 2389 struct rockchip_pinctrl_priv *priv = bank->priv; 2390 2391 /* The first 32 pins of the first bank are located in PMU */ 2392 if (bank->bank_num == 0) { 2393 *regmap = priv->regmap_pmu; 2394 *reg = RK3368_DRV_PMU_OFFSET; 2395 2396 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2397 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2398 *bit *= RK3288_DRV_BITS_PER_PIN; 2399 } else { 2400 *regmap = priv->regmap_base; 2401 *reg = RK3368_DRV_GRF_OFFSET; 2402 2403 /* correct the offset, as we're starting with the 2nd bank */ 2404 *reg -= 0x10; 2405 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2406 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2407 2408 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2409 *bit *= RK3288_DRV_BITS_PER_PIN; 2410 } 2411 } 2412 2413 #define RK3399_PULL_GRF_OFFSET 0xe040 2414 #define RK3399_PULL_PMU_OFFSET 0x40 2415 #define RK3399_DRV_3BITS_PER_PIN 3 2416 2417 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2418 int pin_num, struct regmap **regmap, 2419 int *reg, u8 *bit) 2420 { 2421 struct rockchip_pinctrl_priv *priv = bank->priv; 2422 2423 /* The bank0:16 and bank1:32 pins are located in PMU */ 2424 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2425 *regmap = priv->regmap_pmu; 2426 *reg = RK3399_PULL_PMU_OFFSET; 2427 2428 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2429 2430 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2431 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2432 *bit *= RK3188_PULL_BITS_PER_PIN; 2433 } else { 2434 *regmap = priv->regmap_base; 2435 *reg = RK3399_PULL_GRF_OFFSET; 2436 2437 /* correct the offset, as we're starting with the 3rd bank */ 2438 *reg -= 0x20; 2439 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2440 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2441 2442 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2443 *bit *= RK3188_PULL_BITS_PER_PIN; 2444 } 2445 } 2446 2447 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2448 int pin_num, struct regmap **regmap, 2449 int *reg, u8 *bit) 2450 { 2451 struct rockchip_pinctrl_priv *priv = bank->priv; 2452 int drv_num = (pin_num / 8); 2453 2454 /* The bank0:16 and bank1:32 pins are located in PMU */ 2455 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2456 *regmap = priv->regmap_pmu; 2457 else 2458 *regmap = priv->regmap_base; 2459 2460 *reg = bank->drv[drv_num].offset; 2461 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2462 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2463 *bit = (pin_num % 8) * 3; 2464 else 2465 *bit = (pin_num % 8) * 2; 2466 } 2467 2468 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2469 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2470 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2471 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2472 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2473 { 4, 7, 10, 13, 16, 19, 22, 26 } 2474 }; 2475 2476 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2477 int pin_num, int strength) 2478 { 2479 struct rockchip_pinctrl_priv *priv = bank->priv; 2480 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2481 struct regmap *regmap; 2482 int reg, ret, i; 2483 u32 data, rmask_bits, temp; 2484 u8 bit; 2485 /* Where need to clean the special mask for rockchip_perpin_drv_list */ 2486 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); 2487 2488 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 2489 pin_num, strength); 2490 2491 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2492 if (ctrl->type == RV1126) { 2493 rmask_bits = RV1126_DRV_BITS_PER_PIN; 2494 ret = strength; 2495 goto config; 2496 } 2497 2498 ret = -EINVAL; 2499 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2500 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2501 ret = i; 2502 break; 2503 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2504 ret = rockchip_perpin_drv_list[drv_type][i]; 2505 break; 2506 } 2507 } 2508 2509 if (ret < 0) { 2510 debug("unsupported driver strength %d\n", strength); 2511 return ret; 2512 } 2513 2514 switch (drv_type) { 2515 case DRV_TYPE_IO_1V8_3V0_AUTO: 2516 case DRV_TYPE_IO_3V3_ONLY: 2517 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2518 switch (bit) { 2519 case 0 ... 12: 2520 /* regular case, nothing to do */ 2521 break; 2522 case 15: 2523 /* 2524 * drive-strength offset is special, as it is spread 2525 * over 2 registers, the bit data[15] contains bit 0 2526 * of the value while temp[1:0] contains bits 2 and 1 2527 */ 2528 data = (ret & 0x1) << 15; 2529 temp = (ret >> 0x1) & 0x3; 2530 2531 data |= BIT(31); 2532 ret = regmap_write(regmap, reg, data); 2533 if (ret) 2534 return ret; 2535 2536 temp |= (0x3 << 16); 2537 reg += 0x4; 2538 ret = regmap_write(regmap, reg, temp); 2539 2540 return ret; 2541 case 18 ... 21: 2542 /* setting fully enclosed in the second register */ 2543 reg += 4; 2544 bit -= 16; 2545 break; 2546 default: 2547 debug("unsupported bit: %d for pinctrl drive type: %d\n", 2548 bit, drv_type); 2549 return -EINVAL; 2550 } 2551 break; 2552 case DRV_TYPE_IO_DEFAULT: 2553 case DRV_TYPE_IO_1V8_OR_3V0: 2554 case DRV_TYPE_IO_1V8_ONLY: 2555 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2556 break; 2557 default: 2558 debug("unsupported pinctrl drive type: %d\n", 2559 drv_type); 2560 return -EINVAL; 2561 } 2562 2563 config: 2564 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 2565 regmap_read(regmap, reg, &data); 2566 data &= ~(((1 << rmask_bits) - 1) << bit); 2567 } else { 2568 /* enable the write to the equivalent lower bits */ 2569 data = ((1 << rmask_bits) - 1) << (bit + 16); 2570 } 2571 2572 data |= (ret << bit); 2573 ret = regmap_write(regmap, reg, data); 2574 return ret; 2575 } 2576 2577 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2578 { 2579 PIN_CONFIG_BIAS_DISABLE, 2580 PIN_CONFIG_BIAS_PULL_UP, 2581 PIN_CONFIG_BIAS_PULL_DOWN, 2582 PIN_CONFIG_BIAS_BUS_HOLD 2583 }, 2584 { 2585 PIN_CONFIG_BIAS_DISABLE, 2586 PIN_CONFIG_BIAS_PULL_DOWN, 2587 PIN_CONFIG_BIAS_DISABLE, 2588 PIN_CONFIG_BIAS_PULL_UP 2589 }, 2590 }; 2591 2592 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2593 int pin_num, int pull) 2594 { 2595 struct rockchip_pinctrl_priv *priv = bank->priv; 2596 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2597 struct regmap *regmap; 2598 int reg, ret, i, pull_type; 2599 u8 bit; 2600 u32 data; 2601 2602 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 2603 pin_num, pull); 2604 2605 /* rk3066b does support any pulls */ 2606 if (ctrl->type == RK3066B) 2607 return pull ? -EINVAL : 0; 2608 2609 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2610 2611 switch (ctrl->type) { 2612 case RK2928: 2613 case RK3128: 2614 data = BIT(bit + 16); 2615 if (pull == PIN_CONFIG_BIAS_DISABLE) 2616 data |= BIT(bit); 2617 ret = regmap_write(regmap, reg, data); 2618 break; 2619 case PX30: 2620 case RV1108: 2621 case RV1126: 2622 case RK1808: 2623 case RK3188: 2624 case RK3288: 2625 case RK3308: 2626 case RK3368: 2627 case RK3399: 2628 /* 2629 * Where need to clean the special mask for 2630 * rockchip_pull_list. 2631 */ 2632 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); 2633 ret = -EINVAL; 2634 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2635 i++) { 2636 if (rockchip_pull_list[pull_type][i] == pull) { 2637 ret = i; 2638 break; 2639 } 2640 } 2641 2642 if (ret < 0) { 2643 debug("unsupported pull setting %d\n", pull); 2644 return ret; 2645 } 2646 2647 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 2648 regmap_read(regmap, reg, &data); 2649 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); 2650 } else { 2651 /* enable the write to the equivalent lower bits */ 2652 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2653 } 2654 2655 data |= (ret << bit); 2656 ret = regmap_write(regmap, reg, data); 2657 break; 2658 default: 2659 debug("unsupported pinctrl type\n"); 2660 return -EINVAL; 2661 } 2662 2663 return ret; 2664 } 2665 2666 #define RK3328_SCHMITT_BITS_PER_PIN 1 2667 #define RK3328_SCHMITT_PINS_PER_REG 16 2668 #define RK3328_SCHMITT_BANK_STRIDE 8 2669 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2670 2671 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2672 int pin_num, 2673 struct regmap **regmap, 2674 int *reg, u8 *bit) 2675 { 2676 struct rockchip_pinctrl_priv *priv = bank->priv; 2677 2678 *regmap = priv->regmap_base; 2679 *reg = RK3328_SCHMITT_GRF_OFFSET; 2680 2681 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2682 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2683 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2684 2685 return 0; 2686 } 2687 2688 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2689 int pin_num, int enable) 2690 { 2691 struct rockchip_pinctrl_priv *priv = bank->priv; 2692 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2693 struct regmap *regmap; 2694 int reg, ret; 2695 u8 bit; 2696 u32 data; 2697 2698 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 2699 pin_num, enable); 2700 2701 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2702 if (ret) 2703 return ret; 2704 2705 /* enable the write to the equivalent lower bits */ 2706 data = BIT(bit + 16) | (enable << bit); 2707 2708 return regmap_write(regmap, reg, data); 2709 } 2710 2711 #define PX30_SLEW_RATE_PMU_OFFSET 0x30 2712 #define PX30_SLEW_RATE_GRF_OFFSET 0x90 2713 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16 2714 #define PX30_SLEW_RATE_BANK_STRIDE 16 2715 #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8 2716 2717 static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, 2718 int pin_num, 2719 struct regmap **regmap, 2720 int *reg, u8 *bit) 2721 { 2722 struct rockchip_pinctrl_priv *priv = bank->priv; 2723 int pins_per_reg; 2724 2725 if (bank->bank_num == 0) { 2726 *regmap = priv->regmap_pmu; 2727 *reg = PX30_SLEW_RATE_PMU_OFFSET; 2728 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 2729 } else { 2730 *regmap = priv->regmap_base; 2731 *reg = PX30_SCHMITT_GRF_OFFSET; 2732 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 2733 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 2734 } 2735 *reg += ((pin_num / pins_per_reg) * 4); 2736 *bit = pin_num % pins_per_reg; 2737 2738 return 0; 2739 } 2740 2741 static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank, 2742 int pin_num, int speed) 2743 { 2744 struct rockchip_pinctrl_priv *priv = bank->priv; 2745 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2746 struct regmap *regmap; 2747 int reg, ret; 2748 u8 bit; 2749 u32 data; 2750 2751 debug("setting slew rate of GPIO%d-%d to %d\n", bank->bank_num, 2752 pin_num, speed); 2753 2754 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit); 2755 if (ret) 2756 return ret; 2757 2758 /* enable the write to the equivalent lower bits */ 2759 data = BIT(bit + 16) | (speed << bit); 2760 2761 return regmap_write(regmap, reg, data); 2762 } 2763 2764 /* 2765 * Pinconf_ops handling 2766 */ 2767 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2768 unsigned int pull) 2769 { 2770 switch (ctrl->type) { 2771 case RK2928: 2772 case RK3128: 2773 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2774 pull == PIN_CONFIG_BIAS_DISABLE); 2775 case RK3066B: 2776 return pull ? false : true; 2777 case PX30: 2778 case RV1108: 2779 case RV1126: 2780 case RK1808: 2781 case RK3188: 2782 case RK3288: 2783 case RK3308: 2784 case RK3368: 2785 case RK3399: 2786 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2787 } 2788 2789 return false; 2790 } 2791 2792 /* set the pin config settings for a specified pin */ 2793 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 2794 u32 pin, u32 param, u32 arg) 2795 { 2796 struct rockchip_pinctrl_priv *priv = bank->priv; 2797 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2798 int rc; 2799 2800 switch (param) { 2801 case PIN_CONFIG_BIAS_DISABLE: 2802 rc = rockchip_set_pull(bank, pin, param); 2803 if (rc) 2804 return rc; 2805 break; 2806 2807 case PIN_CONFIG_BIAS_PULL_UP: 2808 case PIN_CONFIG_BIAS_PULL_DOWN: 2809 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2810 case PIN_CONFIG_BIAS_BUS_HOLD: 2811 if (!rockchip_pinconf_pull_valid(ctrl, param)) 2812 return -ENOTSUPP; 2813 2814 if (!arg) 2815 return -EINVAL; 2816 2817 rc = rockchip_set_pull(bank, pin, param); 2818 if (rc) 2819 return rc; 2820 break; 2821 2822 case PIN_CONFIG_DRIVE_STRENGTH: 2823 if (!ctrl->drv_calc_reg) 2824 return -ENOTSUPP; 2825 2826 rc = rockchip_set_drive_perpin(bank, pin, arg); 2827 if (rc < 0) 2828 return rc; 2829 break; 2830 2831 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2832 if (!ctrl->schmitt_calc_reg) 2833 return -ENOTSUPP; 2834 2835 rc = rockchip_set_schmitt(bank, pin, arg); 2836 if (rc < 0) 2837 return rc; 2838 break; 2839 2840 case PIN_CONFIG_SLEW_RATE: 2841 if (!ctrl->slew_rate_calc_reg) 2842 return -ENOTSUPP; 2843 2844 rc = rockchip_set_slew_rate(bank, 2845 pin - bank->pin_base, arg); 2846 if (rc < 0) 2847 return rc; 2848 break; 2849 2850 default: 2851 break; 2852 } 2853 2854 return 0; 2855 } 2856 2857 static const struct pinconf_param rockchip_conf_params[] = { 2858 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 2859 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 2860 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 2861 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 2862 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 2863 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 2864 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 2865 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 2866 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 2867 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, 2868 }; 2869 2870 static int rockchip_pinconf_prop_name_to_param(const char *property, 2871 u32 *default_value) 2872 { 2873 const struct pinconf_param *p, *end; 2874 2875 p = rockchip_conf_params; 2876 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 2877 2878 /* See if this pctldev supports this parameter */ 2879 for (; p < end; p++) { 2880 if (!strcmp(property, p->property)) { 2881 *default_value = p->default_value; 2882 return p->param; 2883 } 2884 } 2885 2886 *default_value = 0; 2887 return -EPERM; 2888 } 2889 2890 static int rockchip_pinctrl_set_state(struct udevice *dev, 2891 struct udevice *config) 2892 { 2893 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2894 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2895 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 2896 u32 bank, pin, mux, conf, arg, default_val; 2897 int ret, count, i; 2898 const char *prop_name; 2899 const void *value; 2900 int prop_len, param; 2901 const u32 *data; 2902 ofnode node; 2903 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 2904 const struct device_node *np; 2905 struct property *pp; 2906 #else 2907 int property_offset, pcfg_node; 2908 const void *blob = gd->fdt_blob; 2909 #endif 2910 data = dev_read_prop(config, "rockchip,pins", &count); 2911 if (count < 0) { 2912 debug("%s: bad array size %d\n", __func__, count); 2913 return -EINVAL; 2914 } 2915 2916 count /= sizeof(u32); 2917 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2918 debug("%s: unsupported pins array count %d\n", 2919 __func__, count); 2920 return -EINVAL; 2921 } 2922 2923 for (i = 0; i < count; i++) 2924 cells[i] = fdt32_to_cpu(data[i]); 2925 2926 for (i = 0; i < (count >> 2); i++) { 2927 bank = cells[4 * i + 0]; 2928 pin = cells[4 * i + 1]; 2929 mux = cells[4 * i + 2]; 2930 conf = cells[4 * i + 3]; 2931 2932 ret = rockchip_verify_config(dev, bank, pin); 2933 if (ret) 2934 return ret; 2935 2936 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2937 if (ret) 2938 return ret; 2939 2940 node = ofnode_get_by_phandle(conf); 2941 if (!ofnode_valid(node)) 2942 return -ENODEV; 2943 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 2944 np = ofnode_to_np(node); 2945 for (pp = np->properties; pp; pp = pp->next) { 2946 prop_name = pp->name; 2947 prop_len = pp->length; 2948 value = pp->value; 2949 #else 2950 pcfg_node = ofnode_to_offset(node); 2951 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2952 value = fdt_getprop_by_offset(blob, property_offset, 2953 &prop_name, &prop_len); 2954 if (!value) 2955 return -ENOENT; 2956 #endif 2957 param = rockchip_pinconf_prop_name_to_param(prop_name, 2958 &default_val); 2959 if (param < 0) 2960 break; 2961 2962 if (prop_len >= sizeof(fdt32_t)) 2963 arg = fdt32_to_cpu(*(fdt32_t *)value); 2964 else 2965 arg = default_val; 2966 2967 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2968 param, arg); 2969 if (ret) { 2970 debug("%s: rockchip_pinconf_set fail: %d\n", 2971 __func__, ret); 2972 return ret; 2973 } 2974 } 2975 } 2976 2977 return 0; 2978 } 2979 2980 static int rockchip_pinctrl_get_pins_count(struct udevice *dev) 2981 { 2982 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2983 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2984 2985 return ctrl->nr_pins; 2986 } 2987 2988 static struct pinctrl_ops rockchip_pinctrl_ops = { 2989 .get_pins_count = rockchip_pinctrl_get_pins_count, 2990 .set_state = rockchip_pinctrl_set_state, 2991 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2992 }; 2993 2994 static const struct rockchip_pin_ctrl rk3308b_pin_ctrl; 2995 2996 /* retrieve the soc specific data */ 2997 static const struct rockchip_pin_ctrl * 2998 rockchip_pinctrl_get_soc_data(struct udevice *dev) 2999 { 3000 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 3001 const struct rockchip_pin_ctrl *ctrl = 3002 (const struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 3003 struct rockchip_pin_bank *bank; 3004 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3005 u32 nr_pins; 3006 3007 if (soc_is_rk3308b()) 3008 ctrl = &rk3308b_pin_ctrl; 3009 3010 grf_offs = ctrl->grf_mux_offset; 3011 pmu_offs = ctrl->pmu_mux_offset; 3012 drv_pmu_offs = ctrl->pmu_drv_offset; 3013 drv_grf_offs = ctrl->grf_drv_offset; 3014 bank = ctrl->pin_banks; 3015 3016 /* Ctrl data re-initialize for some Socs */ 3017 if (ctrl->ctrl_data_re_init) { 3018 if (ctrl->ctrl_data_re_init(ctrl)) 3019 return NULL; 3020 } 3021 3022 nr_pins = 0; 3023 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3024 int bank_pins = 0; 3025 3026 bank->priv = priv; 3027 bank->pin_base = nr_pins; 3028 nr_pins += bank->nr_pins; 3029 3030 /* calculate iomux and drv offsets */ 3031 for (j = 0; j < 4; j++) { 3032 struct rockchip_iomux *iom = &bank->iomux[j]; 3033 struct rockchip_drv *drv = &bank->drv[j]; 3034 int inc; 3035 3036 if (bank_pins >= bank->nr_pins) 3037 break; 3038 3039 /* preset iomux offset value, set new start value */ 3040 if (iom->offset >= 0) { 3041 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 3042 pmu_offs = iom->offset; 3043 else 3044 grf_offs = iom->offset; 3045 } else { /* set current iomux offset */ 3046 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || 3047 (iom->type & IOMUX_L_SOURCE_PMU)) ? 3048 pmu_offs : grf_offs; 3049 } 3050 3051 /* preset drv offset value, set new start value */ 3052 if (drv->offset >= 0) { 3053 if (iom->type & IOMUX_SOURCE_PMU) 3054 drv_pmu_offs = drv->offset; 3055 else 3056 drv_grf_offs = drv->offset; 3057 } else { /* set current drv offset */ 3058 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3059 drv_pmu_offs : drv_grf_offs; 3060 } 3061 3062 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3063 i, j, iom->offset, drv->offset); 3064 3065 /* 3066 * Increase offset according to iomux width. 3067 * 4bit iomux'es are spread over two registers. 3068 */ 3069 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3070 IOMUX_WIDTH_3BIT | 3071 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 3072 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 3073 pmu_offs += inc; 3074 else 3075 grf_offs += inc; 3076 3077 /* 3078 * Increase offset according to drv width. 3079 * 3bit drive-strenth'es are spread over two registers. 3080 */ 3081 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3082 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3083 inc = 8; 3084 else 3085 inc = 4; 3086 3087 if (iom->type & IOMUX_SOURCE_PMU) 3088 drv_pmu_offs += inc; 3089 else 3090 drv_grf_offs += inc; 3091 3092 bank_pins += 8; 3093 } 3094 3095 /* calculate the per-bank recalced_mask */ 3096 for (j = 0; j < ctrl->niomux_recalced; j++) { 3097 int pin = 0; 3098 3099 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3100 pin = ctrl->iomux_recalced[j].pin; 3101 bank->recalced_mask |= BIT(pin); 3102 } 3103 } 3104 3105 /* calculate the per-bank route_mask */ 3106 for (j = 0; j < ctrl->niomux_routes; j++) { 3107 int pin = 0; 3108 3109 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3110 pin = ctrl->iomux_routes[j].pin; 3111 bank->route_mask |= BIT(pin); 3112 } 3113 } 3114 } 3115 3116 WARN_ON(nr_pins != ctrl->nr_pins); 3117 3118 return ctrl; 3119 } 3120 3121 /* SoC data specially handle */ 3122 3123 /* rk3308b SoC data initialize */ 3124 #define RK3308B_GRF_SOC_CON13 0x608 3125 #define RK3308B_GRF_SOC_CON15 0x610 3126 3127 /* RK3308B_GRF_SOC_CON13 */ 3128 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) 3129 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 3130 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 3131 3132 /* RK3308B_GRF_SOC_CON15 */ 3133 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) 3134 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 3135 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 3136 3137 static int rk3308b_soc_data_init(struct rockchip_pinctrl_priv *priv) 3138 { 3139 int ret; 3140 3141 /* 3142 * Enable the special ctrl of selected sources. 3143 */ 3144 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13, 3145 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | 3146 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | 3147 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); 3148 if (ret) 3149 return ret; 3150 3151 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15, 3152 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | 3153 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | 3154 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); 3155 if (ret) 3156 return ret; 3157 3158 return 0; 3159 } 3160 3161 static int rockchip_pinctrl_probe(struct udevice *dev) 3162 { 3163 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 3164 const struct rockchip_pin_ctrl *ctrl; 3165 struct udevice *syscon; 3166 struct regmap *regmap; 3167 int ret = 0; 3168 3169 /* get rockchip grf syscon phandle */ 3170 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 3171 &syscon); 3172 if (ret) { 3173 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 3174 return ret; 3175 } 3176 3177 /* get grf-reg base address */ 3178 regmap = syscon_get_regmap(syscon); 3179 if (!regmap) { 3180 debug("unable to find rockchip grf regmap\n"); 3181 return -ENODEV; 3182 } 3183 priv->regmap_base = regmap; 3184 3185 /* option: get pmu-reg base address */ 3186 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 3187 &syscon); 3188 if (!ret) { 3189 /* get pmugrf-reg base address */ 3190 regmap = syscon_get_regmap(syscon); 3191 if (!regmap) { 3192 debug("unable to find rockchip pmu regmap\n"); 3193 return -ENODEV; 3194 } 3195 priv->regmap_pmu = regmap; 3196 } 3197 3198 ctrl = rockchip_pinctrl_get_soc_data(dev); 3199 if (!ctrl) { 3200 debug("driver data not available\n"); 3201 return -EINVAL; 3202 } 3203 3204 /* Special handle for some Socs */ 3205 if (ctrl->soc_data_init) { 3206 ret = ctrl->soc_data_init(priv); 3207 if (ret) 3208 return ret; 3209 } 3210 3211 priv->ctrl = (struct rockchip_pin_ctrl *)ctrl; 3212 return 0; 3213 } 3214 3215 static struct rockchip_pin_bank px30_pin_banks[] = { 3216 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3217 IOMUX_SOURCE_PMU, 3218 IOMUX_SOURCE_PMU, 3219 IOMUX_SOURCE_PMU 3220 ), 3221 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3222 IOMUX_WIDTH_4BIT, 3223 IOMUX_WIDTH_4BIT, 3224 IOMUX_WIDTH_4BIT 3225 ), 3226 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3227 IOMUX_WIDTH_4BIT, 3228 IOMUX_WIDTH_4BIT, 3229 IOMUX_WIDTH_4BIT 3230 ), 3231 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3232 IOMUX_WIDTH_4BIT, 3233 IOMUX_WIDTH_4BIT, 3234 IOMUX_WIDTH_4BIT 3235 ), 3236 }; 3237 3238 static const struct rockchip_pin_ctrl px30_pin_ctrl = { 3239 .pin_banks = px30_pin_banks, 3240 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3241 .nr_pins = 128, 3242 .label = "PX30-GPIO", 3243 .type = PX30, 3244 .grf_mux_offset = 0x0, 3245 .pmu_mux_offset = 0x0, 3246 .iomux_routes = px30_mux_route_data, 3247 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3248 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3249 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3250 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3251 .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit, 3252 }; 3253 3254 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3255 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3256 IOMUX_SOURCE_PMU, 3257 IOMUX_SOURCE_PMU, 3258 IOMUX_SOURCE_PMU), 3259 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3260 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3261 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3262 }; 3263 3264 static const struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3265 .pin_banks = rv1108_pin_banks, 3266 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3267 .nr_pins = 128, 3268 .label = "RV1108-GPIO", 3269 .type = RV1108, 3270 .grf_mux_offset = 0x10, 3271 .pmu_mux_offset = 0x0, 3272 .iomux_recalced = rv1108_mux_recalced_data, 3273 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3274 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3275 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3276 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3277 }; 3278 3279 static struct rockchip_pin_bank rv1126_pin_banks[] = { 3280 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3281 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3282 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3283 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 3284 IOMUX_WIDTH_4BIT), 3285 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 3286 IOMUX_WIDTH_4BIT, 3287 IOMUX_WIDTH_4BIT, 3288 IOMUX_WIDTH_4BIT, 3289 IOMUX_WIDTH_4BIT, 3290 0x10010, 0x10018, 0x10020, 0x10028), 3291 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3292 IOMUX_WIDTH_4BIT, 3293 IOMUX_WIDTH_4BIT, 3294 IOMUX_WIDTH_4BIT, 3295 IOMUX_WIDTH_4BIT), 3296 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3297 IOMUX_WIDTH_4BIT, 3298 IOMUX_WIDTH_4BIT, 3299 IOMUX_WIDTH_4BIT, 3300 IOMUX_WIDTH_4BIT), 3301 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 3302 IOMUX_WIDTH_4BIT, 0, 0, 0), 3303 }; 3304 3305 static const struct rockchip_pin_ctrl rv1126_pin_ctrl = { 3306 .pin_banks = rv1126_pin_banks, 3307 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 3308 .nr_pins = 130, 3309 .label = "RV1126-GPIO", 3310 .type = RV1126, 3311 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 3312 .pmu_mux_offset = 0x0, 3313 .iomux_routes = rv1126_mux_route_data, 3314 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), 3315 .iomux_recalced = rv1126_mux_recalced_data, 3316 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 3317 .pull_calc_reg = rv1126_calc_pull_reg_and_bit, 3318 .drv_calc_reg = rv1126_calc_drv_reg_and_bit, 3319 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit, 3320 }; 3321 3322 static struct rockchip_pin_bank rk1808_pin_banks[] = { 3323 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3324 IOMUX_SOURCE_PMU, 3325 IOMUX_SOURCE_PMU, 3326 IOMUX_SOURCE_PMU, 3327 IOMUX_SOURCE_PMU), 3328 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 3329 IOMUX_WIDTH_4BIT, 3330 IOMUX_WIDTH_4BIT, 3331 IOMUX_WIDTH_4BIT, 3332 IOMUX_WIDTH_4BIT), 3333 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3334 IOMUX_WIDTH_4BIT, 3335 IOMUX_WIDTH_4BIT, 3336 IOMUX_WIDTH_4BIT, 3337 IOMUX_WIDTH_4BIT), 3338 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3339 IOMUX_WIDTH_4BIT, 3340 IOMUX_WIDTH_4BIT, 3341 IOMUX_WIDTH_4BIT, 3342 IOMUX_WIDTH_4BIT), 3343 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", 3344 IOMUX_WIDTH_4BIT, 3345 IOMUX_WIDTH_4BIT, 3346 IOMUX_WIDTH_4BIT, 3347 IOMUX_WIDTH_4BIT), 3348 }; 3349 3350 static const struct rockchip_pin_ctrl rk1808_pin_ctrl = { 3351 .pin_banks = rk1808_pin_banks, 3352 .nr_banks = ARRAY_SIZE(rk1808_pin_banks), 3353 .nr_pins = 160, 3354 .label = "RK1808-GPIO", 3355 .type = RK1808, 3356 .iomux_routes = rk1808_mux_route_data, 3357 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data), 3358 .grf_mux_offset = 0x0, 3359 .pmu_mux_offset = 0x0, 3360 .pull_calc_reg = rk1808_calc_pull_reg_and_bit, 3361 .drv_calc_reg = rk1808_calc_drv_reg_and_bit, 3362 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit, 3363 }; 3364 3365 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3366 PIN_BANK(0, 32, "gpio0"), 3367 PIN_BANK(1, 32, "gpio1"), 3368 PIN_BANK(2, 32, "gpio2"), 3369 PIN_BANK(3, 32, "gpio3"), 3370 }; 3371 3372 static const struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3373 .pin_banks = rk2928_pin_banks, 3374 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3375 .nr_pins = 128, 3376 .label = "RK2928-GPIO", 3377 .type = RK2928, 3378 .grf_mux_offset = 0xa8, 3379 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3380 }; 3381 3382 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3383 PIN_BANK(0, 32, "gpio0"), 3384 PIN_BANK(1, 32, "gpio1"), 3385 PIN_BANK(2, 32, "gpio2"), 3386 }; 3387 3388 static const struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3389 .pin_banks = rk3036_pin_banks, 3390 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3391 .nr_pins = 96, 3392 .label = "RK3036-GPIO", 3393 .type = RK2928, 3394 .grf_mux_offset = 0xa8, 3395 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3396 }; 3397 3398 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3399 PIN_BANK(0, 32, "gpio0"), 3400 PIN_BANK(1, 32, "gpio1"), 3401 PIN_BANK(2, 32, "gpio2"), 3402 PIN_BANK(3, 32, "gpio3"), 3403 PIN_BANK(4, 32, "gpio4"), 3404 PIN_BANK(6, 16, "gpio6"), 3405 }; 3406 3407 static const struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3408 .pin_banks = rk3066a_pin_banks, 3409 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3410 .nr_pins = 176, 3411 .label = "RK3066a-GPIO", 3412 .type = RK2928, 3413 .grf_mux_offset = 0xa8, 3414 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3415 }; 3416 3417 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3418 PIN_BANK(0, 32, "gpio0"), 3419 PIN_BANK(1, 32, "gpio1"), 3420 PIN_BANK(2, 32, "gpio2"), 3421 PIN_BANK(3, 32, "gpio3"), 3422 }; 3423 3424 static const struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3425 .pin_banks = rk3066b_pin_banks, 3426 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3427 .nr_pins = 128, 3428 .label = "RK3066b-GPIO", 3429 .type = RK3066B, 3430 .grf_mux_offset = 0x60, 3431 }; 3432 3433 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3434 PIN_BANK(0, 32, "gpio0"), 3435 PIN_BANK(1, 32, "gpio1"), 3436 PIN_BANK(2, 32, "gpio2"), 3437 PIN_BANK(3, 32, "gpio3"), 3438 }; 3439 3440 static const struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3441 .pin_banks = rk3128_pin_banks, 3442 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3443 .nr_pins = 128, 3444 .label = "RK3128-GPIO", 3445 .type = RK3128, 3446 .grf_mux_offset = 0xa8, 3447 .iomux_recalced = rk3128_mux_recalced_data, 3448 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3449 .iomux_routes = rk3128_mux_route_data, 3450 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3451 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3452 }; 3453 3454 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3455 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3456 PIN_BANK(1, 32, "gpio1"), 3457 PIN_BANK(2, 32, "gpio2"), 3458 PIN_BANK(3, 32, "gpio3"), 3459 }; 3460 3461 static const struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3462 .pin_banks = rk3188_pin_banks, 3463 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3464 .nr_pins = 128, 3465 .label = "RK3188-GPIO", 3466 .type = RK3188, 3467 .grf_mux_offset = 0x60, 3468 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3469 }; 3470 3471 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3472 PIN_BANK(0, 32, "gpio0"), 3473 PIN_BANK(1, 32, "gpio1"), 3474 PIN_BANK(2, 32, "gpio2"), 3475 PIN_BANK(3, 32, "gpio3"), 3476 }; 3477 3478 static const struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3479 .pin_banks = rk3228_pin_banks, 3480 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3481 .nr_pins = 128, 3482 .label = "RK3228-GPIO", 3483 .type = RK3288, 3484 .grf_mux_offset = 0x0, 3485 .iomux_routes = rk3228_mux_route_data, 3486 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3487 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3488 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3489 }; 3490 3491 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3492 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 3493 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3494 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3495 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3496 IOMUX_UNROUTED, 3497 DRV_TYPE_WRITABLE_32BIT, 3498 DRV_TYPE_WRITABLE_32BIT, 3499 DRV_TYPE_WRITABLE_32BIT, 3500 0, 3501 PULL_TYPE_WRITABLE_32BIT, 3502 PULL_TYPE_WRITABLE_32BIT, 3503 PULL_TYPE_WRITABLE_32BIT, 3504 0 3505 ), 3506 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3507 IOMUX_UNROUTED, 3508 IOMUX_UNROUTED, 3509 0 3510 ), 3511 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3512 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3513 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3514 IOMUX_WIDTH_4BIT, 3515 0, 3516 0 3517 ), 3518 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3519 0, 3520 0, 3521 IOMUX_UNROUTED 3522 ), 3523 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3524 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3525 0, 3526 IOMUX_WIDTH_4BIT, 3527 IOMUX_UNROUTED 3528 ), 3529 PIN_BANK(8, 16, "gpio8"), 3530 }; 3531 3532 static const struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3533 .pin_banks = rk3288_pin_banks, 3534 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3535 .nr_pins = 264, 3536 .label = "RK3288-GPIO", 3537 .type = RK3288, 3538 .grf_mux_offset = 0x0, 3539 .pmu_mux_offset = 0x84, 3540 .iomux_routes = rk3288_mux_route_data, 3541 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3542 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3543 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3544 }; 3545 3546 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3547 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 3548 IOMUX_8WIDTH_2BIT, 3549 IOMUX_8WIDTH_2BIT, 3550 IOMUX_8WIDTH_2BIT), 3551 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 3552 IOMUX_8WIDTH_2BIT, 3553 IOMUX_8WIDTH_2BIT, 3554 IOMUX_8WIDTH_2BIT), 3555 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 3556 IOMUX_8WIDTH_2BIT, 3557 IOMUX_8WIDTH_2BIT, 3558 IOMUX_8WIDTH_2BIT), 3559 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 3560 IOMUX_8WIDTH_2BIT, 3561 IOMUX_8WIDTH_2BIT, 3562 IOMUX_8WIDTH_2BIT), 3563 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 3564 IOMUX_8WIDTH_2BIT, 3565 IOMUX_8WIDTH_2BIT, 3566 IOMUX_8WIDTH_2BIT), 3567 }; 3568 3569 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3570 .pin_banks = rk3308_pin_banks, 3571 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3572 .nr_pins = 160, 3573 .label = "RK3308-GPIO", 3574 .type = RK3308, 3575 .grf_mux_offset = 0x0, 3576 .iomux_recalced = rk3308_mux_recalced_data, 3577 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3578 .iomux_routes = rk3308_mux_route_data, 3579 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3580 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3581 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3582 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3583 }; 3584 3585 static const struct rockchip_pin_ctrl rk3308b_pin_ctrl = { 3586 .pin_banks = rk3308_pin_banks, 3587 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3588 .nr_pins = 160, 3589 .label = "RK3308-GPIO", 3590 .type = RK3308, 3591 .grf_mux_offset = 0x0, 3592 .iomux_recalced = rk3308b_mux_recalced_data, 3593 .niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data), 3594 .iomux_routes = rk3308b_mux_route_data, 3595 .niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data), 3596 .soc_data_init = rk3308b_soc_data_init, 3597 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3598 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3599 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3600 }; 3601 3602 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3603 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3604 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3605 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3606 IOMUX_WIDTH_3BIT, 3607 IOMUX_WIDTH_3BIT, 3608 0), 3609 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3610 IOMUX_WIDTH_3BIT, 3611 IOMUX_WIDTH_3BIT, 3612 0, 3613 0), 3614 }; 3615 3616 static const struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3617 .pin_banks = rk3328_pin_banks, 3618 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3619 .nr_pins = 128, 3620 .label = "RK3328-GPIO", 3621 .type = RK3288, 3622 .grf_mux_offset = 0x0, 3623 .iomux_recalced = rk3328_mux_recalced_data, 3624 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3625 .iomux_routes = rk3328_mux_route_data, 3626 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3627 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3628 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3629 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3630 }; 3631 3632 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3633 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3634 IOMUX_SOURCE_PMU, 3635 IOMUX_SOURCE_PMU, 3636 IOMUX_SOURCE_PMU 3637 ), 3638 PIN_BANK(1, 32, "gpio1"), 3639 PIN_BANK(2, 32, "gpio2"), 3640 PIN_BANK(3, 32, "gpio3"), 3641 }; 3642 3643 static const struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3644 .pin_banks = rk3368_pin_banks, 3645 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3646 .nr_pins = 128, 3647 .label = "RK3368-GPIO", 3648 .type = RK3368, 3649 .grf_mux_offset = 0x0, 3650 .pmu_mux_offset = 0x0, 3651 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3652 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3653 }; 3654 3655 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3656 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3657 IOMUX_SOURCE_PMU, 3658 IOMUX_SOURCE_PMU, 3659 IOMUX_SOURCE_PMU, 3660 IOMUX_SOURCE_PMU, 3661 DRV_TYPE_IO_1V8_ONLY, 3662 DRV_TYPE_IO_1V8_ONLY, 3663 DRV_TYPE_IO_DEFAULT, 3664 DRV_TYPE_IO_DEFAULT, 3665 0x80, 3666 0x88, 3667 -1, 3668 -1, 3669 PULL_TYPE_IO_1V8_ONLY, 3670 PULL_TYPE_IO_1V8_ONLY, 3671 PULL_TYPE_IO_DEFAULT, 3672 PULL_TYPE_IO_DEFAULT 3673 ), 3674 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3675 IOMUX_SOURCE_PMU, 3676 IOMUX_SOURCE_PMU, 3677 IOMUX_SOURCE_PMU, 3678 DRV_TYPE_IO_1V8_OR_3V0, 3679 DRV_TYPE_IO_1V8_OR_3V0, 3680 DRV_TYPE_IO_1V8_OR_3V0, 3681 DRV_TYPE_IO_1V8_OR_3V0, 3682 0xa0, 3683 0xa8, 3684 0xb0, 3685 0xb8 3686 ), 3687 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3688 DRV_TYPE_IO_1V8_OR_3V0, 3689 DRV_TYPE_IO_1V8_ONLY, 3690 DRV_TYPE_IO_1V8_ONLY, 3691 PULL_TYPE_IO_DEFAULT, 3692 PULL_TYPE_IO_DEFAULT, 3693 PULL_TYPE_IO_1V8_ONLY, 3694 PULL_TYPE_IO_1V8_ONLY 3695 ), 3696 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3697 DRV_TYPE_IO_3V3_ONLY, 3698 DRV_TYPE_IO_3V3_ONLY, 3699 DRV_TYPE_IO_1V8_OR_3V0 3700 ), 3701 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3702 DRV_TYPE_IO_1V8_3V0_AUTO, 3703 DRV_TYPE_IO_1V8_OR_3V0, 3704 DRV_TYPE_IO_1V8_OR_3V0 3705 ), 3706 }; 3707 3708 static const struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3709 .pin_banks = rk3399_pin_banks, 3710 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3711 .nr_pins = 160, 3712 .label = "RK3399-GPIO", 3713 .type = RK3399, 3714 .grf_mux_offset = 0xe000, 3715 .pmu_mux_offset = 0x0, 3716 .grf_drv_offset = 0xe100, 3717 .pmu_drv_offset = 0x80, 3718 .iomux_routes = rk3399_mux_route_data, 3719 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3720 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3721 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3722 }; 3723 3724 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 3725 { .compatible = "rockchip,px30-pinctrl", 3726 .data = (ulong)&px30_pin_ctrl }, 3727 { .compatible = "rockchip,rv1108-pinctrl", 3728 .data = (ulong)&rv1108_pin_ctrl }, 3729 { .compatible = "rockchip,rv1126-pinctrl-legency", 3730 .data = (ulong)&rv1126_pin_ctrl }, 3731 { .compatible = "rockchip,rk1808-pinctrl", 3732 .data = (ulong)&rk1808_pin_ctrl }, 3733 { .compatible = "rockchip,rk2928-pinctrl", 3734 .data = (ulong)&rk2928_pin_ctrl }, 3735 { .compatible = "rockchip,rk3036-pinctrl", 3736 .data = (ulong)&rk3036_pin_ctrl }, 3737 { .compatible = "rockchip,rk3066a-pinctrl", 3738 .data = (ulong)&rk3066a_pin_ctrl }, 3739 { .compatible = "rockchip,rk3066b-pinctrl", 3740 .data = (ulong)&rk3066b_pin_ctrl }, 3741 { .compatible = "rockchip,rk3128-pinctrl", 3742 .data = (ulong)&rk3128_pin_ctrl }, 3743 { .compatible = "rockchip,rk3188-pinctrl", 3744 .data = (ulong)&rk3188_pin_ctrl }, 3745 { .compatible = "rockchip,rk3228-pinctrl", 3746 .data = (ulong)&rk3228_pin_ctrl }, 3747 { .compatible = "rockchip,rk3288-pinctrl", 3748 .data = (ulong)&rk3288_pin_ctrl }, 3749 { .compatible = "rockchip,rk3308-pinctrl", 3750 .data = (ulong)&rk3308_pin_ctrl }, 3751 { .compatible = "rockchip,rk3328-pinctrl", 3752 .data = (ulong)&rk3328_pin_ctrl }, 3753 { .compatible = "rockchip,rk3368-pinctrl", 3754 .data = (ulong)&rk3368_pin_ctrl }, 3755 { .compatible = "rockchip,rk3399-pinctrl", 3756 .data = (ulong)&rk3399_pin_ctrl }, 3757 {}, 3758 }; 3759 3760 U_BOOT_DRIVER(pinctrl_rockchip) = { 3761 .name = "rockchip_pinctrl", 3762 .id = UCLASS_PINCTRL, 3763 .of_match = rockchip_pinctrl_dt_match, 3764 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 3765 .ops = &rockchip_pinctrl_ops, 3766 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 3767 .bind = dm_scan_fdt_dev, 3768 #endif 3769 .probe = rockchip_pinctrl_probe, 3770 }; 3771