1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 14 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 15 #define RK_FUNC_GPIO 0 16 #define MAX_ROCKCHIP_PINS_ENTRIES 30 17 18 enum rockchip_pinctrl_type { 19 PX30, 20 RV1108, 21 RK2928, 22 RK3066B, 23 RK3128, 24 RK3188, 25 RK3288, 26 RK3308, 27 RK3368, 28 RK3399, 29 }; 30 31 /** 32 * Encode variants of iomux registers into a type variable 33 */ 34 #define IOMUX_GPIO_ONLY BIT(0) 35 #define IOMUX_WIDTH_4BIT BIT(1) 36 #define IOMUX_SOURCE_PMU BIT(2) 37 #define IOMUX_UNROUTED BIT(3) 38 #define IOMUX_WIDTH_3BIT BIT(4) 39 #define IOMUX_8WIDTH_2BIT BIT(5) 40 #define IOMUX_WRITABLE_32BIT BIT(6) 41 42 /** 43 * @type: iomux variant using IOMUX_* constants 44 * @offset: if initialized to -1 it will be autocalculated, by specifying 45 * an initial offset value the relevant source offset can be reset 46 * to a new value for autocalculating the following iomux registers. 47 */ 48 struct rockchip_iomux { 49 int type; 50 int offset; 51 }; 52 53 /** 54 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 55 */ 56 enum rockchip_pin_drv_type { 57 DRV_TYPE_IO_DEFAULT = 0, 58 DRV_TYPE_IO_1V8_OR_3V0, 59 DRV_TYPE_IO_1V8_ONLY, 60 DRV_TYPE_IO_1V8_3V0_AUTO, 61 DRV_TYPE_IO_3V3_ONLY, 62 DRV_TYPE_MAX 63 }; 64 65 /** 66 * enum type index corresponding to rockchip_pull_list arrays index. 67 */ 68 enum rockchip_pin_pull_type { 69 PULL_TYPE_IO_DEFAULT = 0, 70 PULL_TYPE_IO_1V8_ONLY, 71 PULL_TYPE_MAX 72 }; 73 74 /** 75 * @drv_type: drive strength variant using rockchip_perpin_drv_type 76 * @offset: if initialized to -1 it will be autocalculated, by specifying 77 * an initial offset value the relevant source offset can be reset 78 * to a new value for autocalculating the following drive strength 79 * registers. if used chips own cal_drv func instead to calculate 80 * registers offset, the variant could be ignored. 81 */ 82 struct rockchip_drv { 83 enum rockchip_pin_drv_type drv_type; 84 int offset; 85 }; 86 87 /** 88 * @priv: common pinctrl private basedata 89 * @pin_base: first pin number 90 * @nr_pins: number of pins in this bank 91 * @name: name of the bank 92 * @bank_num: number of the bank, to account for holes 93 * @iomux: array describing the 4 iomux sources of the bank 94 * @drv: array describing the 4 drive strength sources of the bank 95 * @pull_type: array describing the 4 pull type sources of the bank 96 * @recalced_mask: bits describing the mux recalced pins of per bank 97 * @route_mask: bits describing the routing pins of per bank 98 */ 99 struct rockchip_pin_bank { 100 struct rockchip_pinctrl_priv *priv; 101 u32 pin_base; 102 u8 nr_pins; 103 char *name; 104 u8 bank_num; 105 struct rockchip_iomux iomux[4]; 106 struct rockchip_drv drv[4]; 107 enum rockchip_pin_pull_type pull_type[4]; 108 u32 recalced_mask; 109 u32 route_mask; 110 }; 111 112 #define PIN_BANK(id, pins, label) \ 113 { \ 114 .bank_num = id, \ 115 .nr_pins = pins, \ 116 .name = label, \ 117 .iomux = { \ 118 { .offset = -1 }, \ 119 { .offset = -1 }, \ 120 { .offset = -1 }, \ 121 { .offset = -1 }, \ 122 }, \ 123 } 124 125 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 126 { \ 127 .bank_num = id, \ 128 .nr_pins = pins, \ 129 .name = label, \ 130 .iomux = { \ 131 { .type = iom0, .offset = -1 }, \ 132 { .type = iom1, .offset = -1 }, \ 133 { .type = iom2, .offset = -1 }, \ 134 { .type = iom3, .offset = -1 }, \ 135 }, \ 136 } 137 138 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 139 { \ 140 .bank_num = id, \ 141 .nr_pins = pins, \ 142 .name = label, \ 143 .iomux = { \ 144 { .offset = -1 }, \ 145 { .offset = -1 }, \ 146 { .offset = -1 }, \ 147 { .offset = -1 }, \ 148 }, \ 149 .drv = { \ 150 { .drv_type = type0, .offset = -1 }, \ 151 { .drv_type = type1, .offset = -1 }, \ 152 { .drv_type = type2, .offset = -1 }, \ 153 { .drv_type = type3, .offset = -1 }, \ 154 }, \ 155 } 156 157 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 158 drv2, drv3, pull0, pull1, \ 159 pull2, pull3) \ 160 { \ 161 .bank_num = id, \ 162 .nr_pins = pins, \ 163 .name = label, \ 164 .iomux = { \ 165 { .offset = -1 }, \ 166 { .offset = -1 }, \ 167 { .offset = -1 }, \ 168 { .offset = -1 }, \ 169 }, \ 170 .drv = { \ 171 { .drv_type = drv0, .offset = -1 }, \ 172 { .drv_type = drv1, .offset = -1 }, \ 173 { .drv_type = drv2, .offset = -1 }, \ 174 { .drv_type = drv3, .offset = -1 }, \ 175 }, \ 176 .pull_type[0] = pull0, \ 177 .pull_type[1] = pull1, \ 178 .pull_type[2] = pull2, \ 179 .pull_type[3] = pull3, \ 180 } 181 182 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 183 iom2, iom3, drv0, drv1, drv2, \ 184 drv3, offset0, offset1, \ 185 offset2, offset3) \ 186 { \ 187 .bank_num = id, \ 188 .nr_pins = pins, \ 189 .name = label, \ 190 .iomux = { \ 191 { .type = iom0, .offset = -1 }, \ 192 { .type = iom1, .offset = -1 }, \ 193 { .type = iom2, .offset = -1 }, \ 194 { .type = iom3, .offset = -1 }, \ 195 }, \ 196 .drv = { \ 197 { .drv_type = drv0, .offset = offset0 }, \ 198 { .drv_type = drv1, .offset = offset1 }, \ 199 { .drv_type = drv2, .offset = offset2 }, \ 200 { .drv_type = drv3, .offset = offset3 }, \ 201 }, \ 202 } 203 204 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 205 label, iom0, iom1, iom2, \ 206 iom3, drv0, drv1, drv2, \ 207 drv3, offset0, offset1, \ 208 offset2, offset3, pull0, \ 209 pull1, pull2, pull3) \ 210 { \ 211 .bank_num = id, \ 212 .nr_pins = pins, \ 213 .name = label, \ 214 .iomux = { \ 215 { .type = iom0, .offset = -1 }, \ 216 { .type = iom1, .offset = -1 }, \ 217 { .type = iom2, .offset = -1 }, \ 218 { .type = iom3, .offset = -1 }, \ 219 }, \ 220 .drv = { \ 221 { .drv_type = drv0, .offset = offset0 }, \ 222 { .drv_type = drv1, .offset = offset1 }, \ 223 { .drv_type = drv2, .offset = offset2 }, \ 224 { .drv_type = drv3, .offset = offset3 }, \ 225 }, \ 226 .pull_type[0] = pull0, \ 227 .pull_type[1] = pull1, \ 228 .pull_type[2] = pull2, \ 229 .pull_type[3] = pull3, \ 230 } 231 232 /** 233 * struct rockchip_mux_recalced_data: represent a pin iomux data. 234 * @num: bank number. 235 * @pin: pin number. 236 * @bit: index at register. 237 * @reg: register offset. 238 * @mask: mask bit 239 */ 240 struct rockchip_mux_recalced_data { 241 u8 num; 242 u8 pin; 243 u32 reg; 244 u8 bit; 245 u8 mask; 246 }; 247 248 /** 249 * struct rockchip_mux_recalced_data: represent a pin iomux data. 250 * @bank_num: bank number. 251 * @pin: index at register or used to calc index. 252 * @func: the min pin. 253 * @route_offset: the max pin. 254 * @route_val: the register offset. 255 */ 256 struct rockchip_mux_route_data { 257 u8 bank_num; 258 u8 pin; 259 u8 func; 260 u32 route_offset; 261 u32 route_val; 262 }; 263 264 /** 265 */ 266 struct rockchip_pin_ctrl { 267 struct rockchip_pin_bank *pin_banks; 268 u32 nr_banks; 269 u32 nr_pins; 270 char *label; 271 enum rockchip_pinctrl_type type; 272 int grf_mux_offset; 273 int pmu_mux_offset; 274 int grf_drv_offset; 275 int pmu_drv_offset; 276 struct rockchip_mux_recalced_data *iomux_recalced; 277 u32 niomux_recalced; 278 struct rockchip_mux_route_data *iomux_routes; 279 u32 niomux_routes; 280 281 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 282 int pin_num, struct regmap **regmap, 283 int *reg, u8 *bit); 284 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 285 int pin_num, struct regmap **regmap, 286 int *reg, u8 *bit); 287 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 288 int pin_num, struct regmap **regmap, 289 int *reg, u8 *bit); 290 }; 291 292 /** 293 */ 294 struct rockchip_pinctrl_priv { 295 struct rockchip_pin_ctrl *ctrl; 296 struct regmap *regmap_base; 297 struct regmap *regmap_pmu; 298 299 }; 300 301 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 302 { 303 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 304 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 305 306 if (bank >= ctrl->nr_banks) { 307 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 308 return -EINVAL; 309 } 310 311 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 312 debug("pin conf pin %d >= %d\n", pin, 313 MAX_ROCKCHIP_GPIO_PER_BANK); 314 return -EINVAL; 315 } 316 317 return 0; 318 } 319 320 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 321 { 322 .num = 1, 323 .pin = 0, 324 .reg = 0x418, 325 .bit = 0, 326 .mask = 0x3 327 }, { 328 .num = 1, 329 .pin = 1, 330 .reg = 0x418, 331 .bit = 2, 332 .mask = 0x3 333 }, { 334 .num = 1, 335 .pin = 2, 336 .reg = 0x418, 337 .bit = 4, 338 .mask = 0x3 339 }, { 340 .num = 1, 341 .pin = 3, 342 .reg = 0x418, 343 .bit = 6, 344 .mask = 0x3 345 }, { 346 .num = 1, 347 .pin = 4, 348 .reg = 0x418, 349 .bit = 8, 350 .mask = 0x3 351 }, { 352 .num = 1, 353 .pin = 5, 354 .reg = 0x418, 355 .bit = 10, 356 .mask = 0x3 357 }, { 358 .num = 1, 359 .pin = 6, 360 .reg = 0x418, 361 .bit = 12, 362 .mask = 0x3 363 }, { 364 .num = 1, 365 .pin = 7, 366 .reg = 0x418, 367 .bit = 14, 368 .mask = 0x3 369 }, { 370 .num = 1, 371 .pin = 8, 372 .reg = 0x41c, 373 .bit = 0, 374 .mask = 0x3 375 }, { 376 .num = 1, 377 .pin = 9, 378 .reg = 0x41c, 379 .bit = 2, 380 .mask = 0x3 381 }, 382 }; 383 384 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 385 { 386 .num = 2, 387 .pin = 20, 388 .reg = 0xe8, 389 .bit = 0, 390 .mask = 0x7 391 }, { 392 .num = 2, 393 .pin = 21, 394 .reg = 0xe8, 395 .bit = 4, 396 .mask = 0x7 397 }, { 398 .num = 2, 399 .pin = 22, 400 .reg = 0xe8, 401 .bit = 8, 402 .mask = 0x7 403 }, { 404 .num = 2, 405 .pin = 23, 406 .reg = 0xe8, 407 .bit = 12, 408 .mask = 0x7 409 }, { 410 .num = 2, 411 .pin = 24, 412 .reg = 0xd4, 413 .bit = 12, 414 .mask = 0x7 415 }, 416 }; 417 418 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 419 { 420 .num = 1, 421 .pin = 14, 422 .reg = 0x28, 423 .bit = 12, 424 .mask = 0x7 425 }, { 426 .num = 1, 427 .pin = 15, 428 .reg = 0x2c, 429 .bit = 0, 430 .mask = 0x3 431 }, { 432 .num = 1, 433 .pin = 18, 434 .reg = 0x30, 435 .bit = 4, 436 .mask = 0x7 437 }, { 438 .num = 1, 439 .pin = 19, 440 .reg = 0x30, 441 .bit = 8, 442 .mask = 0x7 443 }, { 444 .num = 1, 445 .pin = 20, 446 .reg = 0x30, 447 .bit = 12, 448 .mask = 0x7 449 }, { 450 .num = 1, 451 .pin = 21, 452 .reg = 0x34, 453 .bit = 0, 454 .mask = 0x7 455 }, { 456 .num = 1, 457 .pin = 22, 458 .reg = 0x34, 459 .bit = 4, 460 .mask = 0x7 461 }, { 462 .num = 1, 463 .pin = 23, 464 .reg = 0x34, 465 .bit = 8, 466 .mask = 0x7 467 }, { 468 .num = 3, 469 .pin = 12, 470 .reg = 0x68, 471 .bit = 8, 472 .mask = 0x7 473 }, { 474 .num = 3, 475 .pin = 13, 476 .reg = 0x68, 477 .bit = 12, 478 .mask = 0x7 479 }, 480 }; 481 482 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 483 { 484 .num = 2, 485 .pin = 12, 486 .reg = 0x24, 487 .bit = 8, 488 .mask = 0x3 489 }, { 490 .num = 2, 491 .pin = 15, 492 .reg = 0x28, 493 .bit = 0, 494 .mask = 0x7 495 }, { 496 .num = 2, 497 .pin = 23, 498 .reg = 0x30, 499 .bit = 14, 500 .mask = 0x3 501 }, 502 }; 503 504 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 505 int *reg, u8 *bit, int *mask) 506 { 507 struct rockchip_pinctrl_priv *priv = bank->priv; 508 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 509 struct rockchip_mux_recalced_data *data; 510 int i; 511 512 for (i = 0; i < ctrl->niomux_recalced; i++) { 513 data = &ctrl->iomux_recalced[i]; 514 if (data->num == bank->bank_num && 515 data->pin == pin) 516 break; 517 } 518 519 if (i >= ctrl->niomux_recalced) 520 return; 521 522 *reg = data->reg; 523 *mask = data->mask; 524 *bit = data->bit; 525 } 526 527 static struct rockchip_mux_route_data px30_mux_route_data[] = { 528 { 529 /* cif-d2m0 */ 530 .bank_num = 2, 531 .pin = 0, 532 .func = 1, 533 .route_offset = 0x184, 534 .route_val = BIT(16 + 7), 535 }, { 536 /* cif-d2m1 */ 537 .bank_num = 3, 538 .pin = 3, 539 .func = 3, 540 .route_offset = 0x184, 541 .route_val = BIT(16 + 7) | BIT(7), 542 }, { 543 /* pdm-m0 */ 544 .bank_num = 3, 545 .pin = 22, 546 .func = 2, 547 .route_offset = 0x184, 548 .route_val = BIT(16 + 8), 549 }, { 550 /* pdm-m1 */ 551 .bank_num = 2, 552 .pin = 22, 553 .func = 1, 554 .route_offset = 0x184, 555 .route_val = BIT(16 + 8) | BIT(8), 556 }, { 557 /* uart2-rxm0 */ 558 .bank_num = 1, 559 .pin = 27, 560 .func = 2, 561 .route_offset = 0x184, 562 .route_val = BIT(16 + 10), 563 }, { 564 /* uart2-rxm1 */ 565 .bank_num = 2, 566 .pin = 14, 567 .func = 2, 568 .route_offset = 0x184, 569 .route_val = BIT(16 + 10) | BIT(10), 570 }, { 571 /* uart3-rxm0 */ 572 .bank_num = 0, 573 .pin = 17, 574 .func = 2, 575 .route_offset = 0x184, 576 .route_val = BIT(16 + 9), 577 }, { 578 /* uart3-rxm1 */ 579 .bank_num = 1, 580 .pin = 15, 581 .func = 2, 582 .route_offset = 0x184, 583 .route_val = BIT(16 + 9) | BIT(9), 584 }, 585 }; 586 587 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 588 { 589 /* spi-0 */ 590 .bank_num = 1, 591 .pin = 10, 592 .func = 1, 593 .route_offset = 0x144, 594 .route_val = BIT(16 + 3) | BIT(16 + 4), 595 }, { 596 /* spi-1 */ 597 .bank_num = 1, 598 .pin = 27, 599 .func = 3, 600 .route_offset = 0x144, 601 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 602 }, { 603 /* spi-2 */ 604 .bank_num = 0, 605 .pin = 13, 606 .func = 2, 607 .route_offset = 0x144, 608 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 609 }, { 610 /* i2s-0 */ 611 .bank_num = 1, 612 .pin = 5, 613 .func = 1, 614 .route_offset = 0x144, 615 .route_val = BIT(16 + 5), 616 }, { 617 /* i2s-1 */ 618 .bank_num = 0, 619 .pin = 14, 620 .func = 1, 621 .route_offset = 0x144, 622 .route_val = BIT(16 + 5) | BIT(5), 623 }, { 624 /* emmc-0 */ 625 .bank_num = 1, 626 .pin = 22, 627 .func = 2, 628 .route_offset = 0x144, 629 .route_val = BIT(16 + 6), 630 }, { 631 /* emmc-1 */ 632 .bank_num = 2, 633 .pin = 4, 634 .func = 2, 635 .route_offset = 0x144, 636 .route_val = BIT(16 + 6) | BIT(6), 637 }, 638 }; 639 640 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 641 { 642 /* pwm0-0 */ 643 .bank_num = 0, 644 .pin = 26, 645 .func = 1, 646 .route_offset = 0x50, 647 .route_val = BIT(16), 648 }, { 649 /* pwm0-1 */ 650 .bank_num = 3, 651 .pin = 21, 652 .func = 1, 653 .route_offset = 0x50, 654 .route_val = BIT(16) | BIT(0), 655 }, { 656 /* pwm1-0 */ 657 .bank_num = 0, 658 .pin = 27, 659 .func = 1, 660 .route_offset = 0x50, 661 .route_val = BIT(16 + 1), 662 }, { 663 /* pwm1-1 */ 664 .bank_num = 0, 665 .pin = 30, 666 .func = 2, 667 .route_offset = 0x50, 668 .route_val = BIT(16 + 1) | BIT(1), 669 }, { 670 /* pwm2-0 */ 671 .bank_num = 0, 672 .pin = 28, 673 .func = 1, 674 .route_offset = 0x50, 675 .route_val = BIT(16 + 2), 676 }, { 677 /* pwm2-1 */ 678 .bank_num = 1, 679 .pin = 12, 680 .func = 2, 681 .route_offset = 0x50, 682 .route_val = BIT(16 + 2) | BIT(2), 683 }, { 684 /* pwm3-0 */ 685 .bank_num = 3, 686 .pin = 26, 687 .func = 1, 688 .route_offset = 0x50, 689 .route_val = BIT(16 + 3), 690 }, { 691 /* pwm3-1 */ 692 .bank_num = 1, 693 .pin = 11, 694 .func = 2, 695 .route_offset = 0x50, 696 .route_val = BIT(16 + 3) | BIT(3), 697 }, { 698 /* sdio-0_d0 */ 699 .bank_num = 1, 700 .pin = 1, 701 .func = 1, 702 .route_offset = 0x50, 703 .route_val = BIT(16 + 4), 704 }, { 705 /* sdio-1_d0 */ 706 .bank_num = 3, 707 .pin = 2, 708 .func = 1, 709 .route_offset = 0x50, 710 .route_val = BIT(16 + 4) | BIT(4), 711 }, { 712 /* spi-0_rx */ 713 .bank_num = 0, 714 .pin = 13, 715 .func = 2, 716 .route_offset = 0x50, 717 .route_val = BIT(16 + 5), 718 }, { 719 /* spi-1_rx */ 720 .bank_num = 2, 721 .pin = 0, 722 .func = 2, 723 .route_offset = 0x50, 724 .route_val = BIT(16 + 5) | BIT(5), 725 }, { 726 /* emmc-0_cmd */ 727 .bank_num = 1, 728 .pin = 22, 729 .func = 2, 730 .route_offset = 0x50, 731 .route_val = BIT(16 + 7), 732 }, { 733 /* emmc-1_cmd */ 734 .bank_num = 2, 735 .pin = 4, 736 .func = 2, 737 .route_offset = 0x50, 738 .route_val = BIT(16 + 7) | BIT(7), 739 }, { 740 /* uart2-0_rx */ 741 .bank_num = 1, 742 .pin = 19, 743 .func = 2, 744 .route_offset = 0x50, 745 .route_val = BIT(16 + 8), 746 }, { 747 /* uart2-1_rx */ 748 .bank_num = 1, 749 .pin = 10, 750 .func = 2, 751 .route_offset = 0x50, 752 .route_val = BIT(16 + 8) | BIT(8), 753 }, { 754 /* uart1-0_rx */ 755 .bank_num = 1, 756 .pin = 10, 757 .func = 1, 758 .route_offset = 0x50, 759 .route_val = BIT(16 + 11), 760 }, { 761 /* uart1-1_rx */ 762 .bank_num = 3, 763 .pin = 13, 764 .func = 1, 765 .route_offset = 0x50, 766 .route_val = BIT(16 + 11) | BIT(11), 767 }, 768 }; 769 770 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 771 { 772 /* edphdmi_cecinoutt1 */ 773 .bank_num = 7, 774 .pin = 16, 775 .func = 2, 776 .route_offset = 0x264, 777 .route_val = BIT(16 + 12) | BIT(12), 778 }, { 779 /* edphdmi_cecinout */ 780 .bank_num = 7, 781 .pin = 23, 782 .func = 4, 783 .route_offset = 0x264, 784 .route_val = BIT(16 + 12), 785 }, 786 }; 787 788 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 789 { 790 /* uart2_rxm0 */ 791 .bank_num = 1, 792 .pin = 22, 793 .func = 2, 794 .route_offset = 0x314, 795 .route_val = BIT(16 + 2) | BIT(16 + 3), 796 }, { 797 /* uart2_rxm1 */ 798 .bank_num = 4, 799 .pin = 26, 800 .func = 2, 801 .route_offset = 0x314, 802 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 803 }, { 804 /* i2c3_sdam0 */ 805 .bank_num = 0, 806 .pin = 23, 807 .func = 2, 808 .route_offset = 0x314, 809 .route_val = BIT(16 + 4), 810 }, { 811 /* i2c3_sdam1 */ 812 .bank_num = 3, 813 .pin = 12, 814 .func = 2, 815 .route_offset = 0x314, 816 .route_val = BIT(16 + 4) | BIT(4), 817 }, 818 }; 819 820 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 821 { 822 /* uart2dbg_rxm0 */ 823 .bank_num = 1, 824 .pin = 1, 825 .func = 2, 826 .route_offset = 0x50, 827 .route_val = BIT(16) | BIT(16 + 1), 828 }, { 829 /* uart2dbg_rxm1 */ 830 .bank_num = 2, 831 .pin = 1, 832 .func = 1, 833 .route_offset = 0x50, 834 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 835 }, { 836 /* gmac-m1_rxd0 */ 837 .bank_num = 1, 838 .pin = 11, 839 .func = 2, 840 .route_offset = 0x50, 841 .route_val = BIT(16 + 2) | BIT(2), 842 }, { 843 /* gmac-m1-optimized_rxd3 */ 844 .bank_num = 1, 845 .pin = 14, 846 .func = 2, 847 .route_offset = 0x50, 848 .route_val = BIT(16 + 10) | BIT(10), 849 }, { 850 /* pdm_sdi0m0 */ 851 .bank_num = 2, 852 .pin = 19, 853 .func = 2, 854 .route_offset = 0x50, 855 .route_val = BIT(16 + 3), 856 }, { 857 /* pdm_sdi0m1 */ 858 .bank_num = 1, 859 .pin = 23, 860 .func = 3, 861 .route_offset = 0x50, 862 .route_val = BIT(16 + 3) | BIT(3), 863 }, { 864 /* spi_rxdm2 */ 865 .bank_num = 3, 866 .pin = 2, 867 .func = 4, 868 .route_offset = 0x50, 869 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 870 }, { 871 /* i2s2_sdim0 */ 872 .bank_num = 1, 873 .pin = 24, 874 .func = 1, 875 .route_offset = 0x50, 876 .route_val = BIT(16 + 6), 877 }, { 878 /* i2s2_sdim1 */ 879 .bank_num = 3, 880 .pin = 2, 881 .func = 6, 882 .route_offset = 0x50, 883 .route_val = BIT(16 + 6) | BIT(6), 884 }, { 885 /* card_iom1 */ 886 .bank_num = 2, 887 .pin = 22, 888 .func = 3, 889 .route_offset = 0x50, 890 .route_val = BIT(16 + 7) | BIT(7), 891 }, { 892 /* tsp_d5m1 */ 893 .bank_num = 2, 894 .pin = 16, 895 .func = 3, 896 .route_offset = 0x50, 897 .route_val = BIT(16 + 8) | BIT(8), 898 }, { 899 /* cif_data5m1 */ 900 .bank_num = 2, 901 .pin = 16, 902 .func = 4, 903 .route_offset = 0x50, 904 .route_val = BIT(16 + 9) | BIT(9), 905 }, 906 }; 907 908 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 909 { 910 /* uart2dbga_rx */ 911 .bank_num = 4, 912 .pin = 8, 913 .func = 2, 914 .route_offset = 0xe21c, 915 .route_val = BIT(16 + 10) | BIT(16 + 11), 916 }, { 917 /* uart2dbgb_rx */ 918 .bank_num = 4, 919 .pin = 16, 920 .func = 2, 921 .route_offset = 0xe21c, 922 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 923 }, { 924 /* uart2dbgc_rx */ 925 .bank_num = 4, 926 .pin = 19, 927 .func = 1, 928 .route_offset = 0xe21c, 929 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 930 }, { 931 /* pcie_clkreqn */ 932 .bank_num = 2, 933 .pin = 26, 934 .func = 2, 935 .route_offset = 0xe21c, 936 .route_val = BIT(16 + 14), 937 }, { 938 /* pcie_clkreqnb */ 939 .bank_num = 4, 940 .pin = 24, 941 .func = 1, 942 .route_offset = 0xe21c, 943 .route_val = BIT(16 + 14) | BIT(14), 944 }, 945 }; 946 947 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 948 int mux, u32 *reg, u32 *value) 949 { 950 struct rockchip_pinctrl_priv *priv = bank->priv; 951 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 952 struct rockchip_mux_route_data *data; 953 int i; 954 955 for (i = 0; i < ctrl->niomux_routes; i++) { 956 data = &ctrl->iomux_routes[i]; 957 if ((data->bank_num == bank->bank_num) && 958 (data->pin == pin) && (data->func == mux)) 959 break; 960 } 961 962 if (i >= ctrl->niomux_routes) 963 return false; 964 965 *reg = data->route_offset; 966 *value = data->route_val; 967 968 return true; 969 } 970 971 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 972 { 973 struct rockchip_pinctrl_priv *priv = bank->priv; 974 int iomux_num = (pin / 8); 975 struct regmap *regmap; 976 unsigned int val; 977 int reg, ret, mask, mux_type; 978 u8 bit; 979 980 if (iomux_num > 3) 981 return -EINVAL; 982 983 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 984 debug("pin %d is unrouted\n", pin); 985 return -EINVAL; 986 } 987 988 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 989 return RK_FUNC_GPIO; 990 991 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 992 ? priv->regmap_pmu : priv->regmap_base; 993 994 /* get basic quadrupel of mux registers and the correct reg inside */ 995 mux_type = bank->iomux[iomux_num].type; 996 reg = bank->iomux[iomux_num].offset; 997 if (mux_type & IOMUX_WIDTH_4BIT) { 998 if ((pin % 8) >= 4) 999 reg += 0x4; 1000 bit = (pin % 4) * 4; 1001 mask = 0xf; 1002 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1003 if ((pin % 8) >= 5) 1004 reg += 0x4; 1005 bit = (pin % 8 % 5) * 3; 1006 mask = 0x7; 1007 } else { 1008 bit = (pin % 8) * 2; 1009 mask = 0x3; 1010 } 1011 1012 if (bank->recalced_mask & BIT(pin)) 1013 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1014 1015 ret = regmap_read(regmap, reg, &val); 1016 if (ret) 1017 return ret; 1018 1019 return ((val >> bit) & mask); 1020 } 1021 1022 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1023 int index) 1024 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1025 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1026 1027 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1028 } 1029 1030 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1031 int pin, int mux) 1032 { 1033 int iomux_num = (pin / 8); 1034 1035 if (iomux_num > 3) 1036 return -EINVAL; 1037 1038 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1039 debug("pin %d is unrouted\n", pin); 1040 return -EINVAL; 1041 } 1042 1043 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1044 if (mux != IOMUX_GPIO_ONLY) { 1045 debug("pin %d only supports a gpio mux\n", pin); 1046 return -ENOTSUPP; 1047 } 1048 } 1049 1050 return 0; 1051 } 1052 1053 /* 1054 * Set a new mux function for a pin. 1055 * 1056 * The register is divided into the upper and lower 16 bit. When changing 1057 * a value, the previous register value is not read and changed. Instead 1058 * it seems the changed bits are marked in the upper 16 bit, while the 1059 * changed value gets set in the same offset in the lower 16 bit. 1060 * All pin settings seem to be 2 bit wide in both the upper and lower 1061 * parts. 1062 * @bank: pin bank to change 1063 * @pin: pin to change 1064 * @mux: new mux function to set 1065 */ 1066 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1067 { 1068 struct rockchip_pinctrl_priv *priv = bank->priv; 1069 int iomux_num = (pin / 8); 1070 struct regmap *regmap; 1071 int reg, ret, mask, mux_type; 1072 u8 bit; 1073 u32 data, route_reg, route_val; 1074 1075 ret = rockchip_verify_mux(bank, pin, mux); 1076 if (ret < 0) 1077 return ret; 1078 1079 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1080 return 0; 1081 1082 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1083 1084 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1085 ? priv->regmap_pmu : priv->regmap_base; 1086 1087 /* get basic quadrupel of mux registers and the correct reg inside */ 1088 mux_type = bank->iomux[iomux_num].type; 1089 reg = bank->iomux[iomux_num].offset; 1090 if (mux_type & IOMUX_WIDTH_4BIT) { 1091 if ((pin % 8) >= 4) 1092 reg += 0x4; 1093 bit = (pin % 4) * 4; 1094 mask = 0xf; 1095 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1096 if ((pin % 8) >= 5) 1097 reg += 0x4; 1098 bit = (pin % 8 % 5) * 3; 1099 mask = 0x7; 1100 } else { 1101 bit = (pin % 8) * 2; 1102 mask = 0x3; 1103 } 1104 1105 if (bank->recalced_mask & BIT(pin)) 1106 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1107 1108 if (bank->route_mask & BIT(pin)) { 1109 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1110 &route_val)) { 1111 ret = regmap_write(regmap, route_reg, route_val); 1112 if (ret) 1113 return ret; 1114 } 1115 } 1116 1117 if (mux_type & IOMUX_WRITABLE_32BIT) { 1118 regmap_read(regmap, reg, &data); 1119 data &= ~(mask << bit); 1120 } else { 1121 data = (mask << (bit + 16)); 1122 } 1123 1124 data |= (mux & mask) << bit; 1125 ret = regmap_write(regmap, reg, data); 1126 1127 return ret; 1128 } 1129 1130 #define PX30_PULL_PMU_OFFSET 0x10 1131 #define PX30_PULL_GRF_OFFSET 0x60 1132 #define PX30_PULL_BITS_PER_PIN 2 1133 #define PX30_PULL_PINS_PER_REG 8 1134 #define PX30_PULL_BANK_STRIDE 16 1135 1136 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1137 int pin_num, struct regmap **regmap, 1138 int *reg, u8 *bit) 1139 { 1140 struct rockchip_pinctrl_priv *priv = bank->priv; 1141 1142 /* The first 32 pins of the first bank are located in PMU */ 1143 if (bank->bank_num == 0) { 1144 *regmap = priv->regmap_pmu; 1145 *reg = PX30_PULL_PMU_OFFSET; 1146 } else { 1147 *regmap = priv->regmap_base; 1148 *reg = PX30_PULL_GRF_OFFSET; 1149 1150 /* correct the offset, as we're starting with the 2nd bank */ 1151 *reg -= 0x10; 1152 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1153 } 1154 1155 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1156 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1157 *bit *= PX30_PULL_BITS_PER_PIN; 1158 } 1159 1160 #define PX30_DRV_PMU_OFFSET 0x20 1161 #define PX30_DRV_GRF_OFFSET 0xf0 1162 #define PX30_DRV_BITS_PER_PIN 2 1163 #define PX30_DRV_PINS_PER_REG 8 1164 #define PX30_DRV_BANK_STRIDE 16 1165 1166 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1167 int pin_num, struct regmap **regmap, 1168 int *reg, u8 *bit) 1169 { 1170 struct rockchip_pinctrl_priv *priv = bank->priv; 1171 1172 /* The first 32 pins of the first bank are located in PMU */ 1173 if (bank->bank_num == 0) { 1174 *regmap = priv->regmap_pmu; 1175 *reg = PX30_DRV_PMU_OFFSET; 1176 } else { 1177 *regmap = priv->regmap_base; 1178 *reg = PX30_DRV_GRF_OFFSET; 1179 1180 /* correct the offset, as we're starting with the 2nd bank */ 1181 *reg -= 0x10; 1182 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1183 } 1184 1185 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1186 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1187 *bit *= PX30_DRV_BITS_PER_PIN; 1188 } 1189 1190 #define PX30_SCHMITT_PMU_OFFSET 0x38 1191 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1192 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1193 #define PX30_SCHMITT_BANK_STRIDE 16 1194 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1195 1196 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1197 int pin_num, 1198 struct regmap **regmap, 1199 int *reg, u8 *bit) 1200 { 1201 struct rockchip_pinctrl_priv *priv = bank->priv; 1202 int pins_per_reg; 1203 1204 if (bank->bank_num == 0) { 1205 *regmap = priv->regmap_pmu; 1206 *reg = PX30_SCHMITT_PMU_OFFSET; 1207 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1208 } else { 1209 *regmap = priv->regmap_base; 1210 *reg = PX30_SCHMITT_GRF_OFFSET; 1211 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1212 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1213 } 1214 *reg += ((pin_num / pins_per_reg) * 4); 1215 *bit = pin_num % pins_per_reg; 1216 1217 return 0; 1218 } 1219 1220 #define RV1108_PULL_PMU_OFFSET 0x10 1221 #define RV1108_PULL_OFFSET 0x110 1222 #define RV1108_PULL_PINS_PER_REG 8 1223 #define RV1108_PULL_BITS_PER_PIN 2 1224 #define RV1108_PULL_BANK_STRIDE 16 1225 1226 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1227 int pin_num, struct regmap **regmap, 1228 int *reg, u8 *bit) 1229 { 1230 struct rockchip_pinctrl_priv *priv = bank->priv; 1231 1232 /* The first 24 pins of the first bank are located in PMU */ 1233 if (bank->bank_num == 0) { 1234 *regmap = priv->regmap_pmu; 1235 *reg = RV1108_PULL_PMU_OFFSET; 1236 } else { 1237 *reg = RV1108_PULL_OFFSET; 1238 *regmap = priv->regmap_base; 1239 /* correct the offset, as we're starting with the 2nd bank */ 1240 *reg -= 0x10; 1241 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1242 } 1243 1244 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1245 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1246 *bit *= RV1108_PULL_BITS_PER_PIN; 1247 } 1248 1249 #define RV1108_DRV_PMU_OFFSET 0x20 1250 #define RV1108_DRV_GRF_OFFSET 0x210 1251 #define RV1108_DRV_BITS_PER_PIN 2 1252 #define RV1108_DRV_PINS_PER_REG 8 1253 #define RV1108_DRV_BANK_STRIDE 16 1254 1255 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1256 int pin_num, struct regmap **regmap, 1257 int *reg, u8 *bit) 1258 { 1259 struct rockchip_pinctrl_priv *priv = bank->priv; 1260 1261 /* The first 24 pins of the first bank are located in PMU */ 1262 if (bank->bank_num == 0) { 1263 *regmap = priv->regmap_pmu; 1264 *reg = RV1108_DRV_PMU_OFFSET; 1265 } else { 1266 *regmap = priv->regmap_base; 1267 *reg = RV1108_DRV_GRF_OFFSET; 1268 1269 /* correct the offset, as we're starting with the 2nd bank */ 1270 *reg -= 0x10; 1271 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1272 } 1273 1274 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1275 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1276 *bit *= RV1108_DRV_BITS_PER_PIN; 1277 } 1278 1279 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1280 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1281 #define RV1108_SCHMITT_BANK_STRIDE 8 1282 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1283 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1284 1285 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1286 int pin_num, 1287 struct regmap **regmap, 1288 int *reg, u8 *bit) 1289 { 1290 struct rockchip_pinctrl_priv *priv = bank->priv; 1291 int pins_per_reg; 1292 1293 if (bank->bank_num == 0) { 1294 *regmap = priv->regmap_pmu; 1295 *reg = RV1108_SCHMITT_PMU_OFFSET; 1296 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1297 } else { 1298 *regmap = priv->regmap_base; 1299 *reg = RV1108_SCHMITT_GRF_OFFSET; 1300 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1301 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1302 } 1303 *reg += ((pin_num / pins_per_reg) * 4); 1304 *bit = pin_num % pins_per_reg; 1305 1306 return 0; 1307 } 1308 1309 #define RK2928_PULL_OFFSET 0x118 1310 #define RK2928_PULL_PINS_PER_REG 16 1311 #define RK2928_PULL_BANK_STRIDE 8 1312 1313 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1314 int pin_num, struct regmap **regmap, 1315 int *reg, u8 *bit) 1316 { 1317 struct rockchip_pinctrl_priv *priv = bank->priv; 1318 1319 *regmap = priv->regmap_base; 1320 *reg = RK2928_PULL_OFFSET; 1321 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1322 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1323 1324 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1325 }; 1326 1327 #define RK3128_PULL_OFFSET 0x118 1328 1329 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1330 int pin_num, struct regmap **regmap, 1331 int *reg, u8 *bit) 1332 { 1333 struct rockchip_pinctrl_priv *priv = bank->priv; 1334 1335 *regmap = priv->regmap_base; 1336 *reg = RK3128_PULL_OFFSET; 1337 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1338 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1339 1340 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1341 } 1342 1343 #define RK3188_PULL_OFFSET 0x164 1344 #define RK3188_PULL_BITS_PER_PIN 2 1345 #define RK3188_PULL_PINS_PER_REG 8 1346 #define RK3188_PULL_BANK_STRIDE 16 1347 #define RK3188_PULL_PMU_OFFSET 0x64 1348 1349 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1350 int pin_num, struct regmap **regmap, 1351 int *reg, u8 *bit) 1352 { 1353 struct rockchip_pinctrl_priv *priv = bank->priv; 1354 1355 /* The first 12 pins of the first bank are located elsewhere */ 1356 if (bank->bank_num == 0 && pin_num < 12) { 1357 *regmap = priv->regmap_pmu; 1358 *reg = RK3188_PULL_PMU_OFFSET; 1359 1360 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1361 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1362 *bit *= RK3188_PULL_BITS_PER_PIN; 1363 } else { 1364 *regmap = priv->regmap_base; 1365 *reg = RK3188_PULL_OFFSET; 1366 1367 /* correct the offset, as it is the 2nd pull register */ 1368 *reg -= 4; 1369 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1370 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1371 1372 /* 1373 * The bits in these registers have an inverse ordering 1374 * with the lowest pin being in bits 15:14 and the highest 1375 * pin in bits 1:0 1376 */ 1377 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1378 *bit *= RK3188_PULL_BITS_PER_PIN; 1379 } 1380 } 1381 1382 #define RK3288_PULL_OFFSET 0x140 1383 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1384 int pin_num, struct regmap **regmap, 1385 int *reg, u8 *bit) 1386 { 1387 struct rockchip_pinctrl_priv *priv = bank->priv; 1388 1389 /* The first 24 pins of the first bank are located in PMU */ 1390 if (bank->bank_num == 0) { 1391 *regmap = priv->regmap_pmu; 1392 *reg = RK3188_PULL_PMU_OFFSET; 1393 1394 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1395 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1396 *bit *= RK3188_PULL_BITS_PER_PIN; 1397 } else { 1398 *regmap = priv->regmap_base; 1399 *reg = RK3288_PULL_OFFSET; 1400 1401 /* correct the offset, as we're starting with the 2nd bank */ 1402 *reg -= 0x10; 1403 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1404 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1405 1406 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1407 *bit *= RK3188_PULL_BITS_PER_PIN; 1408 } 1409 } 1410 1411 #define RK3288_DRV_PMU_OFFSET 0x70 1412 #define RK3288_DRV_GRF_OFFSET 0x1c0 1413 #define RK3288_DRV_BITS_PER_PIN 2 1414 #define RK3288_DRV_PINS_PER_REG 8 1415 #define RK3288_DRV_BANK_STRIDE 16 1416 1417 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1418 int pin_num, struct regmap **regmap, 1419 int *reg, u8 *bit) 1420 { 1421 struct rockchip_pinctrl_priv *priv = bank->priv; 1422 1423 /* The first 24 pins of the first bank are located in PMU */ 1424 if (bank->bank_num == 0) { 1425 *regmap = priv->regmap_pmu; 1426 *reg = RK3288_DRV_PMU_OFFSET; 1427 1428 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1429 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1430 *bit *= RK3288_DRV_BITS_PER_PIN; 1431 } else { 1432 *regmap = priv->regmap_base; 1433 *reg = RK3288_DRV_GRF_OFFSET; 1434 1435 /* correct the offset, as we're starting with the 2nd bank */ 1436 *reg -= 0x10; 1437 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1438 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1439 1440 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1441 *bit *= RK3288_DRV_BITS_PER_PIN; 1442 } 1443 } 1444 1445 #define RK3228_PULL_OFFSET 0x100 1446 1447 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1448 int pin_num, struct regmap **regmap, 1449 int *reg, u8 *bit) 1450 { 1451 struct rockchip_pinctrl_priv *priv = bank->priv; 1452 1453 *regmap = priv->regmap_base; 1454 *reg = RK3228_PULL_OFFSET; 1455 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1456 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1457 1458 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1459 *bit *= RK3188_PULL_BITS_PER_PIN; 1460 } 1461 1462 #define RK3228_DRV_GRF_OFFSET 0x200 1463 1464 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1465 int pin_num, struct regmap **regmap, 1466 int *reg, u8 *bit) 1467 { 1468 struct rockchip_pinctrl_priv *priv = bank->priv; 1469 1470 *regmap = priv->regmap_base; 1471 *reg = RK3228_DRV_GRF_OFFSET; 1472 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1473 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1474 1475 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1476 *bit *= RK3288_DRV_BITS_PER_PIN; 1477 } 1478 1479 #define RK3308_PULL_OFFSET 0xa0 1480 1481 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1482 int pin_num, struct regmap **regmap, 1483 int *reg, u8 *bit) 1484 { 1485 struct rockchip_pinctrl_priv *priv = bank->priv; 1486 1487 *regmap = priv->regmap_base; 1488 *reg = RK3308_PULL_OFFSET; 1489 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1490 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1491 1492 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1493 *bit *= RK3188_PULL_BITS_PER_PIN; 1494 } 1495 1496 #define RK3308_DRV_GRF_OFFSET 0x100 1497 1498 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1499 int pin_num, struct regmap **regmap, 1500 int *reg, u8 *bit) 1501 { 1502 struct rockchip_pinctrl_priv *priv = bank->priv; 1503 1504 *regmap = priv->regmap_base; 1505 *reg = RK3308_DRV_GRF_OFFSET; 1506 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1507 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1508 1509 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1510 *bit *= RK3288_DRV_BITS_PER_PIN; 1511 } 1512 1513 #define RK3308_SCHMITT_PINS_PER_REG 8 1514 #define RK3308_SCHMITT_BANK_STRIDE 16 1515 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1516 1517 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1518 int pin_num, 1519 struct regmap **regmap, 1520 int *reg, u8 *bit) 1521 { 1522 struct rockchip_pinctrl_priv *priv = bank->priv; 1523 1524 *regmap = priv->regmap_base; 1525 *reg = RK3308_SCHMITT_GRF_OFFSET; 1526 1527 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1528 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1529 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1530 1531 return 0; 1532 } 1533 1534 #define RK3368_PULL_GRF_OFFSET 0x100 1535 #define RK3368_PULL_PMU_OFFSET 0x10 1536 1537 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1538 int pin_num, struct regmap **regmap, 1539 int *reg, u8 *bit) 1540 { 1541 struct rockchip_pinctrl_priv *priv = bank->priv; 1542 1543 /* The first 32 pins of the first bank are located in PMU */ 1544 if (bank->bank_num == 0) { 1545 *regmap = priv->regmap_pmu; 1546 *reg = RK3368_PULL_PMU_OFFSET; 1547 1548 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1549 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1550 *bit *= RK3188_PULL_BITS_PER_PIN; 1551 } else { 1552 *regmap = priv->regmap_base; 1553 *reg = RK3368_PULL_GRF_OFFSET; 1554 1555 /* correct the offset, as we're starting with the 2nd bank */ 1556 *reg -= 0x10; 1557 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1558 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1559 1560 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1561 *bit *= RK3188_PULL_BITS_PER_PIN; 1562 } 1563 } 1564 1565 #define RK3368_DRV_PMU_OFFSET 0x20 1566 #define RK3368_DRV_GRF_OFFSET 0x200 1567 1568 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1569 int pin_num, struct regmap **regmap, 1570 int *reg, u8 *bit) 1571 { 1572 struct rockchip_pinctrl_priv *priv = bank->priv; 1573 1574 /* The first 32 pins of the first bank are located in PMU */ 1575 if (bank->bank_num == 0) { 1576 *regmap = priv->regmap_pmu; 1577 *reg = RK3368_DRV_PMU_OFFSET; 1578 1579 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1580 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1581 *bit *= RK3288_DRV_BITS_PER_PIN; 1582 } else { 1583 *regmap = priv->regmap_base; 1584 *reg = RK3368_DRV_GRF_OFFSET; 1585 1586 /* correct the offset, as we're starting with the 2nd bank */ 1587 *reg -= 0x10; 1588 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1589 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1590 1591 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1592 *bit *= RK3288_DRV_BITS_PER_PIN; 1593 } 1594 } 1595 1596 #define RK3399_PULL_GRF_OFFSET 0xe040 1597 #define RK3399_PULL_PMU_OFFSET 0x40 1598 #define RK3399_DRV_3BITS_PER_PIN 3 1599 1600 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1601 int pin_num, struct regmap **regmap, 1602 int *reg, u8 *bit) 1603 { 1604 struct rockchip_pinctrl_priv *priv = bank->priv; 1605 1606 /* The bank0:16 and bank1:32 pins are located in PMU */ 1607 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1608 *regmap = priv->regmap_pmu; 1609 *reg = RK3399_PULL_PMU_OFFSET; 1610 1611 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1612 1613 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1614 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1615 *bit *= RK3188_PULL_BITS_PER_PIN; 1616 } else { 1617 *regmap = priv->regmap_base; 1618 *reg = RK3399_PULL_GRF_OFFSET; 1619 1620 /* correct the offset, as we're starting with the 3rd bank */ 1621 *reg -= 0x20; 1622 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1623 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1624 1625 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1626 *bit *= RK3188_PULL_BITS_PER_PIN; 1627 } 1628 } 1629 1630 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1631 int pin_num, struct regmap **regmap, 1632 int *reg, u8 *bit) 1633 { 1634 struct rockchip_pinctrl_priv *priv = bank->priv; 1635 int drv_num = (pin_num / 8); 1636 1637 /* The bank0:16 and bank1:32 pins are located in PMU */ 1638 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1639 *regmap = priv->regmap_pmu; 1640 else 1641 *regmap = priv->regmap_base; 1642 1643 *reg = bank->drv[drv_num].offset; 1644 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1645 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1646 *bit = (pin_num % 8) * 3; 1647 else 1648 *bit = (pin_num % 8) * 2; 1649 } 1650 1651 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1652 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1653 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1654 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1655 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1656 { 4, 7, 10, 13, 16, 19, 22, 26 } 1657 }; 1658 1659 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1660 int pin_num, int strength) 1661 { 1662 struct rockchip_pinctrl_priv *priv = bank->priv; 1663 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1664 struct regmap *regmap; 1665 int reg, ret, i; 1666 u32 data, rmask_bits, temp; 1667 u8 bit; 1668 int drv_type = bank->drv[pin_num / 8].drv_type; 1669 1670 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 1671 pin_num, strength); 1672 1673 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1674 1675 ret = -EINVAL; 1676 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1677 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1678 ret = i; 1679 break; 1680 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1681 ret = rockchip_perpin_drv_list[drv_type][i]; 1682 break; 1683 } 1684 } 1685 1686 if (ret < 0) { 1687 debug("unsupported driver strength %d\n", strength); 1688 return ret; 1689 } 1690 1691 switch (drv_type) { 1692 case DRV_TYPE_IO_1V8_3V0_AUTO: 1693 case DRV_TYPE_IO_3V3_ONLY: 1694 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1695 switch (bit) { 1696 case 0 ... 12: 1697 /* regular case, nothing to do */ 1698 break; 1699 case 15: 1700 /* 1701 * drive-strength offset is special, as it is spread 1702 * over 2 registers, the bit data[15] contains bit 0 1703 * of the value while temp[1:0] contains bits 2 and 1 1704 */ 1705 data = (ret & 0x1) << 15; 1706 temp = (ret >> 0x1) & 0x3; 1707 1708 data |= BIT(31); 1709 ret = regmap_write(regmap, reg, data); 1710 if (ret) 1711 return ret; 1712 1713 temp |= (0x3 << 16); 1714 reg += 0x4; 1715 ret = regmap_write(regmap, reg, temp); 1716 1717 return ret; 1718 case 18 ... 21: 1719 /* setting fully enclosed in the second register */ 1720 reg += 4; 1721 bit -= 16; 1722 break; 1723 default: 1724 debug("unsupported bit: %d for pinctrl drive type: %d\n", 1725 bit, drv_type); 1726 return -EINVAL; 1727 } 1728 break; 1729 case DRV_TYPE_IO_DEFAULT: 1730 case DRV_TYPE_IO_1V8_OR_3V0: 1731 case DRV_TYPE_IO_1V8_ONLY: 1732 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1733 break; 1734 default: 1735 debug("unsupported pinctrl drive type: %d\n", 1736 drv_type); 1737 return -EINVAL; 1738 } 1739 1740 /* enable the write to the equivalent lower bits */ 1741 data = ((1 << rmask_bits) - 1) << (bit + 16); 1742 data |= (ret << bit); 1743 1744 ret = regmap_write(regmap, reg, data); 1745 return ret; 1746 } 1747 1748 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1749 { 1750 PIN_CONFIG_BIAS_DISABLE, 1751 PIN_CONFIG_BIAS_PULL_UP, 1752 PIN_CONFIG_BIAS_PULL_DOWN, 1753 PIN_CONFIG_BIAS_BUS_HOLD 1754 }, 1755 { 1756 PIN_CONFIG_BIAS_DISABLE, 1757 PIN_CONFIG_BIAS_PULL_DOWN, 1758 PIN_CONFIG_BIAS_DISABLE, 1759 PIN_CONFIG_BIAS_PULL_UP 1760 }, 1761 }; 1762 1763 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1764 int pin_num, int pull) 1765 { 1766 struct rockchip_pinctrl_priv *priv = bank->priv; 1767 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1768 struct regmap *regmap; 1769 int reg, ret, i, pull_type; 1770 u8 bit; 1771 u32 data; 1772 1773 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 1774 pin_num, pull); 1775 1776 /* rk3066b does support any pulls */ 1777 if (ctrl->type == RK3066B) 1778 return pull ? -EINVAL : 0; 1779 1780 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1781 1782 switch (ctrl->type) { 1783 case RK2928: 1784 case RK3128: 1785 data = BIT(bit + 16); 1786 if (pull == PIN_CONFIG_BIAS_DISABLE) 1787 data |= BIT(bit); 1788 ret = regmap_write(regmap, reg, data); 1789 break; 1790 case PX30: 1791 case RV1108: 1792 case RK3188: 1793 case RK3288: 1794 case RK3308: 1795 case RK3368: 1796 case RK3399: 1797 pull_type = bank->pull_type[pin_num / 8]; 1798 ret = -EINVAL; 1799 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 1800 i++) { 1801 if (rockchip_pull_list[pull_type][i] == pull) { 1802 ret = i; 1803 break; 1804 } 1805 } 1806 1807 if (ret < 0) { 1808 debug("unsupported pull setting %d\n", pull); 1809 return ret; 1810 } 1811 1812 /* enable the write to the equivalent lower bits */ 1813 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1814 data |= (ret << bit); 1815 1816 ret = regmap_write(regmap, reg, data); 1817 break; 1818 default: 1819 debug("unsupported pinctrl type\n"); 1820 return -EINVAL; 1821 } 1822 1823 return ret; 1824 } 1825 1826 #define RK3328_SCHMITT_BITS_PER_PIN 1 1827 #define RK3328_SCHMITT_PINS_PER_REG 16 1828 #define RK3328_SCHMITT_BANK_STRIDE 8 1829 #define RK3328_SCHMITT_GRF_OFFSET 0x380 1830 1831 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1832 int pin_num, 1833 struct regmap **regmap, 1834 int *reg, u8 *bit) 1835 { 1836 struct rockchip_pinctrl_priv *priv = bank->priv; 1837 1838 *regmap = priv->regmap_base; 1839 *reg = RK3328_SCHMITT_GRF_OFFSET; 1840 1841 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 1842 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 1843 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 1844 1845 return 0; 1846 } 1847 1848 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 1849 int pin_num, int enable) 1850 { 1851 struct rockchip_pinctrl_priv *priv = bank->priv; 1852 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1853 struct regmap *regmap; 1854 int reg, ret; 1855 u8 bit; 1856 u32 data; 1857 1858 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 1859 pin_num, enable); 1860 1861 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1862 if (ret) 1863 return ret; 1864 1865 /* enable the write to the equivalent lower bits */ 1866 data = BIT(bit + 16) | (enable << bit); 1867 1868 return regmap_write(regmap, reg, data); 1869 } 1870 1871 /* 1872 * Pinconf_ops handling 1873 */ 1874 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 1875 unsigned int pull) 1876 { 1877 switch (ctrl->type) { 1878 case RK2928: 1879 case RK3128: 1880 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 1881 pull == PIN_CONFIG_BIAS_DISABLE); 1882 case RK3066B: 1883 return pull ? false : true; 1884 case PX30: 1885 case RV1108: 1886 case RK3188: 1887 case RK3288: 1888 case RK3308: 1889 case RK3368: 1890 case RK3399: 1891 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 1892 } 1893 1894 return false; 1895 } 1896 1897 /* set the pin config settings for a specified pin */ 1898 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 1899 u32 pin, u32 param, u32 arg) 1900 { 1901 struct rockchip_pinctrl_priv *priv = bank->priv; 1902 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1903 int rc; 1904 1905 switch (param) { 1906 case PIN_CONFIG_BIAS_DISABLE: 1907 rc = rockchip_set_pull(bank, pin, param); 1908 if (rc) 1909 return rc; 1910 break; 1911 1912 case PIN_CONFIG_BIAS_PULL_UP: 1913 case PIN_CONFIG_BIAS_PULL_DOWN: 1914 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1915 case PIN_CONFIG_BIAS_BUS_HOLD: 1916 if (!rockchip_pinconf_pull_valid(ctrl, param)) 1917 return -ENOTSUPP; 1918 1919 if (!arg) 1920 return -EINVAL; 1921 1922 rc = rockchip_set_pull(bank, pin, param); 1923 if (rc) 1924 return rc; 1925 break; 1926 1927 case PIN_CONFIG_DRIVE_STRENGTH: 1928 if (!ctrl->drv_calc_reg) 1929 return -ENOTSUPP; 1930 1931 rc = rockchip_set_drive_perpin(bank, pin, arg); 1932 if (rc < 0) 1933 return rc; 1934 break; 1935 1936 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1937 if (!ctrl->schmitt_calc_reg) 1938 return -ENOTSUPP; 1939 1940 rc = rockchip_set_schmitt(bank, pin, arg); 1941 if (rc < 0) 1942 return rc; 1943 break; 1944 1945 default: 1946 break; 1947 } 1948 1949 return 0; 1950 } 1951 1952 static const struct pinconf_param rockchip_conf_params[] = { 1953 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 1954 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 1955 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 1956 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 1957 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 1958 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 1959 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 1960 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 1961 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 1962 }; 1963 1964 static int rockchip_pinconf_prop_name_to_param(const char *property, 1965 u32 *default_value) 1966 { 1967 const struct pinconf_param *p, *end; 1968 1969 p = rockchip_conf_params; 1970 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 1971 1972 /* See if this pctldev supports this parameter */ 1973 for (; p < end; p++) { 1974 if (!strcmp(property, p->property)) { 1975 *default_value = p->default_value; 1976 return p->param; 1977 } 1978 } 1979 1980 *default_value = 0; 1981 return -EPERM; 1982 } 1983 1984 static int rockchip_pinctrl_set_state(struct udevice *dev, 1985 struct udevice *config) 1986 { 1987 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1988 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1989 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 1990 u32 bank, pin, mux, conf, arg, default_val; 1991 int ret, count, i; 1992 const char *prop_name; 1993 const void *value; 1994 int prop_len, param; 1995 const u32 *data; 1996 ofnode node; 1997 #ifdef CONFIG_OF_LIVE 1998 const struct device_node *np; 1999 struct property *pp; 2000 #else 2001 int property_offset, pcfg_node; 2002 const void *blob = gd->fdt_blob; 2003 #endif 2004 data = dev_read_prop(config, "rockchip,pins", &count); 2005 if (count < 0) { 2006 debug("%s: bad array size %d\n", __func__, count); 2007 return -EINVAL; 2008 } 2009 2010 count /= sizeof(u32); 2011 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2012 debug("%s: unsupported pins array count %d\n", 2013 __func__, count); 2014 return -EINVAL; 2015 } 2016 2017 for (i = 0; i < count; i++) 2018 cells[i] = fdt32_to_cpu(data[i]); 2019 2020 for (i = 0; i < (count >> 2); i++) { 2021 bank = cells[4 * i + 0]; 2022 pin = cells[4 * i + 1]; 2023 mux = cells[4 * i + 2]; 2024 conf = cells[4 * i + 3]; 2025 2026 ret = rockchip_verify_config(dev, bank, pin); 2027 if (ret) 2028 return ret; 2029 2030 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2031 if (ret) 2032 return ret; 2033 2034 node = ofnode_get_by_phandle(conf); 2035 if (!ofnode_valid(node)) 2036 return -ENODEV; 2037 #ifdef CONFIG_OF_LIVE 2038 np = ofnode_to_np(node); 2039 for (pp = np->properties; pp; pp = pp->next) { 2040 prop_name = pp->name; 2041 prop_len = pp->length; 2042 value = pp->value; 2043 #else 2044 pcfg_node = ofnode_to_offset(node); 2045 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2046 value = fdt_getprop_by_offset(blob, property_offset, 2047 &prop_name, &prop_len); 2048 if (!value) 2049 return -ENOENT; 2050 #endif 2051 param = rockchip_pinconf_prop_name_to_param(prop_name, 2052 &default_val); 2053 if (param < 0) 2054 break; 2055 2056 if (prop_len >= sizeof(fdt32_t)) 2057 arg = fdt32_to_cpu(*(fdt32_t *)value); 2058 else 2059 arg = default_val; 2060 2061 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2062 param, arg); 2063 if (ret) { 2064 debug("%s: rockchip_pinconf_set fail: %d\n", 2065 __func__, ret); 2066 return ret; 2067 } 2068 } 2069 } 2070 2071 return 0; 2072 } 2073 2074 static struct pinctrl_ops rockchip_pinctrl_ops = { 2075 .set_state = rockchip_pinctrl_set_state, 2076 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2077 }; 2078 2079 /* retrieve the soc specific data */ 2080 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 2081 { 2082 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2083 struct rockchip_pin_ctrl *ctrl = 2084 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 2085 struct rockchip_pin_bank *bank; 2086 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2087 2088 grf_offs = ctrl->grf_mux_offset; 2089 pmu_offs = ctrl->pmu_mux_offset; 2090 drv_pmu_offs = ctrl->pmu_drv_offset; 2091 drv_grf_offs = ctrl->grf_drv_offset; 2092 bank = ctrl->pin_banks; 2093 2094 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2095 int bank_pins = 0; 2096 2097 bank->priv = priv; 2098 bank->pin_base = ctrl->nr_pins; 2099 ctrl->nr_pins += bank->nr_pins; 2100 2101 /* calculate iomux and drv offsets */ 2102 for (j = 0; j < 4; j++) { 2103 struct rockchip_iomux *iom = &bank->iomux[j]; 2104 struct rockchip_drv *drv = &bank->drv[j]; 2105 int inc; 2106 2107 if (bank_pins >= bank->nr_pins) 2108 break; 2109 2110 /* preset iomux offset value, set new start value */ 2111 if (iom->offset >= 0) { 2112 if (iom->type & IOMUX_SOURCE_PMU) 2113 pmu_offs = iom->offset; 2114 else 2115 grf_offs = iom->offset; 2116 } else { /* set current iomux offset */ 2117 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2118 pmu_offs : grf_offs; 2119 } 2120 2121 /* preset drv offset value, set new start value */ 2122 if (drv->offset >= 0) { 2123 if (iom->type & IOMUX_SOURCE_PMU) 2124 drv_pmu_offs = drv->offset; 2125 else 2126 drv_grf_offs = drv->offset; 2127 } else { /* set current drv offset */ 2128 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2129 drv_pmu_offs : drv_grf_offs; 2130 } 2131 2132 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2133 i, j, iom->offset, drv->offset); 2134 2135 /* 2136 * Increase offset according to iomux width. 2137 * 4bit iomux'es are spread over two registers. 2138 */ 2139 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2140 IOMUX_WIDTH_3BIT | 2141 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 2142 if (iom->type & IOMUX_SOURCE_PMU) 2143 pmu_offs += inc; 2144 else 2145 grf_offs += inc; 2146 2147 /* 2148 * Increase offset according to drv width. 2149 * 3bit drive-strenth'es are spread over two registers. 2150 */ 2151 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2152 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2153 inc = 8; 2154 else 2155 inc = 4; 2156 2157 if (iom->type & IOMUX_SOURCE_PMU) 2158 drv_pmu_offs += inc; 2159 else 2160 drv_grf_offs += inc; 2161 2162 bank_pins += 8; 2163 } 2164 2165 /* calculate the per-bank recalced_mask */ 2166 for (j = 0; j < ctrl->niomux_recalced; j++) { 2167 int pin = 0; 2168 2169 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2170 pin = ctrl->iomux_recalced[j].pin; 2171 bank->recalced_mask |= BIT(pin); 2172 } 2173 } 2174 2175 /* calculate the per-bank route_mask */ 2176 for (j = 0; j < ctrl->niomux_routes; j++) { 2177 int pin = 0; 2178 2179 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2180 pin = ctrl->iomux_routes[j].pin; 2181 bank->route_mask |= BIT(pin); 2182 } 2183 } 2184 } 2185 2186 return ctrl; 2187 } 2188 2189 static int rockchip_pinctrl_probe(struct udevice *dev) 2190 { 2191 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2192 struct rockchip_pin_ctrl *ctrl; 2193 struct udevice *syscon; 2194 struct regmap *regmap; 2195 int ret = 0; 2196 2197 /* get rockchip grf syscon phandle */ 2198 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2199 &syscon); 2200 if (ret) { 2201 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 2202 return ret; 2203 } 2204 2205 /* get grf-reg base address */ 2206 regmap = syscon_get_regmap(syscon); 2207 if (!regmap) { 2208 debug("unable to find rockchip grf regmap\n"); 2209 return -ENODEV; 2210 } 2211 priv->regmap_base = regmap; 2212 2213 /* option: get pmu-reg base address */ 2214 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 2215 &syscon); 2216 if (!ret) { 2217 /* get pmugrf-reg base address */ 2218 regmap = syscon_get_regmap(syscon); 2219 if (!regmap) { 2220 debug("unable to find rockchip pmu regmap\n"); 2221 return -ENODEV; 2222 } 2223 priv->regmap_pmu = regmap; 2224 } 2225 2226 ctrl = rockchip_pinctrl_get_soc_data(dev); 2227 if (!ctrl) { 2228 debug("driver data not available\n"); 2229 return -EINVAL; 2230 } 2231 2232 priv->ctrl = ctrl; 2233 return 0; 2234 } 2235 2236 static struct rockchip_pin_bank px30_pin_banks[] = { 2237 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2238 IOMUX_SOURCE_PMU, 2239 IOMUX_SOURCE_PMU, 2240 IOMUX_SOURCE_PMU 2241 ), 2242 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2243 IOMUX_WIDTH_4BIT, 2244 IOMUX_WIDTH_4BIT, 2245 IOMUX_WIDTH_4BIT 2246 ), 2247 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2248 IOMUX_WIDTH_4BIT, 2249 IOMUX_WIDTH_4BIT, 2250 IOMUX_WIDTH_4BIT 2251 ), 2252 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2253 IOMUX_WIDTH_4BIT, 2254 IOMUX_WIDTH_4BIT, 2255 IOMUX_WIDTH_4BIT 2256 ), 2257 }; 2258 2259 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2260 .pin_banks = px30_pin_banks, 2261 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2262 .label = "PX30-GPIO", 2263 .type = PX30, 2264 .grf_mux_offset = 0x0, 2265 .pmu_mux_offset = 0x0, 2266 .iomux_routes = px30_mux_route_data, 2267 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2268 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2269 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2270 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2271 }; 2272 2273 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2274 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2275 IOMUX_SOURCE_PMU, 2276 IOMUX_SOURCE_PMU, 2277 IOMUX_SOURCE_PMU), 2278 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2279 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2280 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2281 }; 2282 2283 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2284 .pin_banks = rv1108_pin_banks, 2285 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2286 .label = "RV1108-GPIO", 2287 .type = RV1108, 2288 .grf_mux_offset = 0x10, 2289 .pmu_mux_offset = 0x0, 2290 .iomux_recalced = rv1108_mux_recalced_data, 2291 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2292 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2293 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2294 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2295 }; 2296 2297 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2298 PIN_BANK(0, 32, "gpio0"), 2299 PIN_BANK(1, 32, "gpio1"), 2300 PIN_BANK(2, 32, "gpio2"), 2301 PIN_BANK(3, 32, "gpio3"), 2302 }; 2303 2304 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2305 .pin_banks = rk2928_pin_banks, 2306 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2307 .label = "RK2928-GPIO", 2308 .type = RK2928, 2309 .grf_mux_offset = 0xa8, 2310 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2311 }; 2312 2313 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2314 PIN_BANK(0, 32, "gpio0"), 2315 PIN_BANK(1, 32, "gpio1"), 2316 PIN_BANK(2, 32, "gpio2"), 2317 }; 2318 2319 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2320 .pin_banks = rk3036_pin_banks, 2321 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2322 .label = "RK3036-GPIO", 2323 .type = RK2928, 2324 .grf_mux_offset = 0xa8, 2325 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2326 }; 2327 2328 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2329 PIN_BANK(0, 32, "gpio0"), 2330 PIN_BANK(1, 32, "gpio1"), 2331 PIN_BANK(2, 32, "gpio2"), 2332 PIN_BANK(3, 32, "gpio3"), 2333 PIN_BANK(4, 32, "gpio4"), 2334 PIN_BANK(6, 16, "gpio6"), 2335 }; 2336 2337 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2338 .pin_banks = rk3066a_pin_banks, 2339 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2340 .label = "RK3066a-GPIO", 2341 .type = RK2928, 2342 .grf_mux_offset = 0xa8, 2343 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2344 }; 2345 2346 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2347 PIN_BANK(0, 32, "gpio0"), 2348 PIN_BANK(1, 32, "gpio1"), 2349 PIN_BANK(2, 32, "gpio2"), 2350 PIN_BANK(3, 32, "gpio3"), 2351 }; 2352 2353 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2354 .pin_banks = rk3066b_pin_banks, 2355 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2356 .label = "RK3066b-GPIO", 2357 .type = RK3066B, 2358 .grf_mux_offset = 0x60, 2359 }; 2360 2361 static struct rockchip_pin_bank rk3128_pin_banks[] = { 2362 PIN_BANK(0, 32, "gpio0"), 2363 PIN_BANK(1, 32, "gpio1"), 2364 PIN_BANK(2, 32, "gpio2"), 2365 PIN_BANK(3, 32, "gpio3"), 2366 }; 2367 2368 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 2369 .pin_banks = rk3128_pin_banks, 2370 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 2371 .label = "RK3128-GPIO", 2372 .type = RK3128, 2373 .grf_mux_offset = 0xa8, 2374 .iomux_recalced = rk3128_mux_recalced_data, 2375 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 2376 .iomux_routes = rk3128_mux_route_data, 2377 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 2378 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 2379 }; 2380 2381 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2382 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2383 PIN_BANK(1, 32, "gpio1"), 2384 PIN_BANK(2, 32, "gpio2"), 2385 PIN_BANK(3, 32, "gpio3"), 2386 }; 2387 2388 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2389 .pin_banks = rk3188_pin_banks, 2390 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2391 .label = "RK3188-GPIO", 2392 .type = RK3188, 2393 .grf_mux_offset = 0x60, 2394 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2395 }; 2396 2397 static struct rockchip_pin_bank rk3228_pin_banks[] = { 2398 PIN_BANK(0, 32, "gpio0"), 2399 PIN_BANK(1, 32, "gpio1"), 2400 PIN_BANK(2, 32, "gpio2"), 2401 PIN_BANK(3, 32, "gpio3"), 2402 }; 2403 2404 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 2405 .pin_banks = rk3228_pin_banks, 2406 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 2407 .label = "RK3228-GPIO", 2408 .type = RK3288, 2409 .grf_mux_offset = 0x0, 2410 .iomux_routes = rk3228_mux_route_data, 2411 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 2412 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2413 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2414 }; 2415 2416 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2417 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 2418 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 2419 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 2420 IOMUX_UNROUTED 2421 ), 2422 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2423 IOMUX_UNROUTED, 2424 IOMUX_UNROUTED, 2425 0 2426 ), 2427 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2428 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2429 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2430 IOMUX_WIDTH_4BIT, 2431 0, 2432 0 2433 ), 2434 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2435 0, 2436 0, 2437 IOMUX_UNROUTED 2438 ), 2439 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2440 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2441 0, 2442 IOMUX_WIDTH_4BIT, 2443 IOMUX_UNROUTED 2444 ), 2445 PIN_BANK(8, 16, "gpio8"), 2446 }; 2447 2448 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2449 .pin_banks = rk3288_pin_banks, 2450 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2451 .label = "RK3288-GPIO", 2452 .type = RK3288, 2453 .grf_mux_offset = 0x0, 2454 .pmu_mux_offset = 0x84, 2455 .iomux_routes = rk3288_mux_route_data, 2456 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 2457 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2458 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2459 }; 2460 2461 static struct rockchip_pin_bank rk3308_pin_banks[] = { 2462 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 2463 IOMUX_8WIDTH_2BIT, 2464 IOMUX_8WIDTH_2BIT, 2465 IOMUX_8WIDTH_2BIT), 2466 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 2467 IOMUX_8WIDTH_2BIT, 2468 IOMUX_8WIDTH_2BIT, 2469 IOMUX_8WIDTH_2BIT), 2470 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 2471 IOMUX_8WIDTH_2BIT, 2472 IOMUX_8WIDTH_2BIT, 2473 IOMUX_8WIDTH_2BIT), 2474 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 2475 IOMUX_8WIDTH_2BIT, 2476 IOMUX_8WIDTH_2BIT, 2477 IOMUX_8WIDTH_2BIT), 2478 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 2479 IOMUX_8WIDTH_2BIT, 2480 IOMUX_8WIDTH_2BIT, 2481 IOMUX_8WIDTH_2BIT), 2482 }; 2483 2484 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 2485 .pin_banks = rk3308_pin_banks, 2486 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 2487 .label = "RK3308-GPIO", 2488 .type = RK3308, 2489 .grf_mux_offset = 0x0, 2490 .iomux_recalced = rk3308_mux_recalced_data, 2491 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 2492 .iomux_routes = rk3308_mux_route_data, 2493 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 2494 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 2495 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 2496 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 2497 }; 2498 2499 static struct rockchip_pin_bank rk3328_pin_banks[] = { 2500 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 2501 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2502 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 2503 IOMUX_WIDTH_3BIT, 2504 IOMUX_WIDTH_3BIT, 2505 0), 2506 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2507 IOMUX_WIDTH_3BIT, 2508 IOMUX_WIDTH_3BIT, 2509 0, 2510 0), 2511 }; 2512 2513 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 2514 .pin_banks = rk3328_pin_banks, 2515 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 2516 .label = "RK3328-GPIO", 2517 .type = RK3288, 2518 .grf_mux_offset = 0x0, 2519 .iomux_recalced = rk3328_mux_recalced_data, 2520 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 2521 .iomux_routes = rk3328_mux_route_data, 2522 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 2523 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2524 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2525 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 2526 }; 2527 2528 static struct rockchip_pin_bank rk3368_pin_banks[] = { 2529 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2530 IOMUX_SOURCE_PMU, 2531 IOMUX_SOURCE_PMU, 2532 IOMUX_SOURCE_PMU 2533 ), 2534 PIN_BANK(1, 32, "gpio1"), 2535 PIN_BANK(2, 32, "gpio2"), 2536 PIN_BANK(3, 32, "gpio3"), 2537 }; 2538 2539 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 2540 .pin_banks = rk3368_pin_banks, 2541 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 2542 .label = "RK3368-GPIO", 2543 .type = RK3368, 2544 .grf_mux_offset = 0x0, 2545 .pmu_mux_offset = 0x0, 2546 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 2547 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 2548 }; 2549 2550 static struct rockchip_pin_bank rk3399_pin_banks[] = { 2551 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 2552 IOMUX_SOURCE_PMU, 2553 IOMUX_SOURCE_PMU, 2554 IOMUX_SOURCE_PMU, 2555 IOMUX_SOURCE_PMU, 2556 DRV_TYPE_IO_1V8_ONLY, 2557 DRV_TYPE_IO_1V8_ONLY, 2558 DRV_TYPE_IO_DEFAULT, 2559 DRV_TYPE_IO_DEFAULT, 2560 0x80, 2561 0x88, 2562 -1, 2563 -1, 2564 PULL_TYPE_IO_1V8_ONLY, 2565 PULL_TYPE_IO_1V8_ONLY, 2566 PULL_TYPE_IO_DEFAULT, 2567 PULL_TYPE_IO_DEFAULT 2568 ), 2569 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 2570 IOMUX_SOURCE_PMU, 2571 IOMUX_SOURCE_PMU, 2572 IOMUX_SOURCE_PMU, 2573 DRV_TYPE_IO_1V8_OR_3V0, 2574 DRV_TYPE_IO_1V8_OR_3V0, 2575 DRV_TYPE_IO_1V8_OR_3V0, 2576 DRV_TYPE_IO_1V8_OR_3V0, 2577 0xa0, 2578 0xa8, 2579 0xb0, 2580 0xb8 2581 ), 2582 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 2583 DRV_TYPE_IO_1V8_OR_3V0, 2584 DRV_TYPE_IO_1V8_ONLY, 2585 DRV_TYPE_IO_1V8_ONLY, 2586 PULL_TYPE_IO_DEFAULT, 2587 PULL_TYPE_IO_DEFAULT, 2588 PULL_TYPE_IO_1V8_ONLY, 2589 PULL_TYPE_IO_1V8_ONLY 2590 ), 2591 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 2592 DRV_TYPE_IO_3V3_ONLY, 2593 DRV_TYPE_IO_3V3_ONLY, 2594 DRV_TYPE_IO_1V8_OR_3V0 2595 ), 2596 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 2597 DRV_TYPE_IO_1V8_3V0_AUTO, 2598 DRV_TYPE_IO_1V8_OR_3V0, 2599 DRV_TYPE_IO_1V8_OR_3V0 2600 ), 2601 }; 2602 2603 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 2604 .pin_banks = rk3399_pin_banks, 2605 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 2606 .label = "RK3399-GPIO", 2607 .type = RK3399, 2608 .grf_mux_offset = 0xe000, 2609 .pmu_mux_offset = 0x0, 2610 .grf_drv_offset = 0xe100, 2611 .pmu_drv_offset = 0x80, 2612 .iomux_routes = rk3399_mux_route_data, 2613 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 2614 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 2615 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 2616 }; 2617 2618 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 2619 { .compatible = "rockchip,px30-pinctrl", 2620 .data = (ulong)&px30_pin_ctrl }, 2621 { .compatible = "rockchip,rv1108-pinctrl", 2622 .data = (ulong)&rv1108_pin_ctrl }, 2623 { .compatible = "rockchip,rk2928-pinctrl", 2624 .data = (ulong)&rk2928_pin_ctrl }, 2625 { .compatible = "rockchip,rk3036-pinctrl", 2626 .data = (ulong)&rk3036_pin_ctrl }, 2627 { .compatible = "rockchip,rk3066a-pinctrl", 2628 .data = (ulong)&rk3066a_pin_ctrl }, 2629 { .compatible = "rockchip,rk3066b-pinctrl", 2630 .data = (ulong)&rk3066b_pin_ctrl }, 2631 { .compatible = "rockchip,rk3128-pinctrl", 2632 .data = (ulong)&rk3128_pin_ctrl }, 2633 { .compatible = "rockchip,rk3188-pinctrl", 2634 .data = (ulong)&rk3188_pin_ctrl }, 2635 { .compatible = "rockchip,rk3228-pinctrl", 2636 .data = (ulong)&rk3228_pin_ctrl }, 2637 { .compatible = "rockchip,rk3288-pinctrl", 2638 .data = (ulong)&rk3288_pin_ctrl }, 2639 { .compatible = "rockchip,rk3308-pinctrl", 2640 .data = (ulong)&rk3308_pin_ctrl }, 2641 { .compatible = "rockchip,rk3328-pinctrl", 2642 .data = (ulong)&rk3328_pin_ctrl }, 2643 { .compatible = "rockchip,rk3368-pinctrl", 2644 .data = (ulong)&rk3368_pin_ctrl }, 2645 { .compatible = "rockchip,rk3399-pinctrl", 2646 .data = (ulong)&rk3399_pin_ctrl }, 2647 {}, 2648 }; 2649 2650 U_BOOT_DRIVER(pinctrl_rockchip) = { 2651 .name = "rockchip_pinctrl", 2652 .id = UCLASS_PINCTRL, 2653 .of_match = rockchip_pinctrl_dt_match, 2654 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 2655 .ops = &rockchip_pinctrl_ops, 2656 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 2657 .bind = dm_scan_fdt_dev, 2658 #endif 2659 .probe = rockchip_pinctrl_probe, 2660 }; 2661