1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <linux/bitops.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/arch/cpu.h> 15 #include <dt-bindings/pinctrl/rockchip.h> 16 17 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 18 #define RK_FUNC_GPIO 0 19 #define MAX_ROCKCHIP_PINS_ENTRIES 30 20 21 enum rockchip_pinctrl_type { 22 PX30, 23 RV1108, 24 RV1126, 25 RK1808, 26 RK2928, 27 RK3066B, 28 RK3128, 29 RK3188, 30 RK3288, 31 RK3308, 32 RK3368, 33 RK3399, 34 }; 35 36 #define RK_GENMASK_VAL(h, l, v) \ 37 (GENMASK((h) + 16, (l) + 16) | ((v) & GENMASK(h, l)) << (h)) 38 39 /** 40 * Encode variants of iomux registers into a type variable 41 */ 42 #define IOMUX_GPIO_ONLY BIT(0) 43 #define IOMUX_WIDTH_4BIT BIT(1) 44 #define IOMUX_SOURCE_PMU BIT(2) 45 #define IOMUX_UNROUTED BIT(3) 46 #define IOMUX_WIDTH_3BIT BIT(4) 47 #define IOMUX_8WIDTH_2BIT BIT(5) 48 #define IOMUX_WRITABLE_32BIT BIT(6) 49 #define IOMUX_L_SOURCE_PMU BIT(7) 50 51 /** 52 * @type: iomux variant using IOMUX_* constants 53 * @offset: if initialized to -1 it will be autocalculated, by specifying 54 * an initial offset value the relevant source offset can be reset 55 * to a new value for autocalculating the following iomux registers. 56 */ 57 struct rockchip_iomux { 58 int type; 59 int offset; 60 }; 61 62 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 63 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 64 65 /** 66 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 67 */ 68 enum rockchip_pin_drv_type { 69 DRV_TYPE_IO_DEFAULT = 0, 70 DRV_TYPE_IO_1V8_OR_3V0, 71 DRV_TYPE_IO_1V8_ONLY, 72 DRV_TYPE_IO_1V8_3V0_AUTO, 73 DRV_TYPE_IO_3V3_ONLY, 74 DRV_TYPE_MAX 75 }; 76 77 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 78 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 79 80 /** 81 * enum type index corresponding to rockchip_pull_list arrays index. 82 */ 83 enum rockchip_pin_pull_type { 84 PULL_TYPE_IO_DEFAULT = 0, 85 PULL_TYPE_IO_1V8_ONLY, 86 PULL_TYPE_MAX 87 }; 88 89 /** 90 * @drv_type: drive strength variant using rockchip_perpin_drv_type 91 * @offset: if initialized to -1 it will be autocalculated, by specifying 92 * an initial offset value the relevant source offset can be reset 93 * to a new value for autocalculating the following drive strength 94 * registers. if used chips own cal_drv func instead to calculate 95 * registers offset, the variant could be ignored. 96 */ 97 struct rockchip_drv { 98 enum rockchip_pin_drv_type drv_type; 99 int offset; 100 }; 101 102 /** 103 * @priv: common pinctrl private basedata 104 * @pin_base: first pin number 105 * @nr_pins: number of pins in this bank 106 * @name: name of the bank 107 * @bank_num: number of the bank, to account for holes 108 * @iomux: array describing the 4 iomux sources of the bank 109 * @drv: array describing the 4 drive strength sources of the bank 110 * @pull_type: array describing the 4 pull type sources of the bank 111 * @recalced_mask: bits describing the mux recalced pins of per bank 112 * @route_mask: bits describing the routing pins of per bank 113 */ 114 struct rockchip_pin_bank { 115 struct rockchip_pinctrl_priv *priv; 116 u32 pin_base; 117 u8 nr_pins; 118 char *name; 119 u8 bank_num; 120 struct rockchip_iomux iomux[4]; 121 struct rockchip_drv drv[4]; 122 enum rockchip_pin_pull_type pull_type[4]; 123 u32 recalced_mask; 124 u32 route_mask; 125 }; 126 127 #define PIN_BANK(id, pins, label) \ 128 { \ 129 .bank_num = id, \ 130 .nr_pins = pins, \ 131 .name = label, \ 132 .iomux = { \ 133 { .offset = -1 }, \ 134 { .offset = -1 }, \ 135 { .offset = -1 }, \ 136 { .offset = -1 }, \ 137 }, \ 138 } 139 140 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 141 { \ 142 .bank_num = id, \ 143 .nr_pins = pins, \ 144 .name = label, \ 145 .iomux = { \ 146 { .type = iom0, .offset = -1 }, \ 147 { .type = iom1, .offset = -1 }, \ 148 { .type = iom2, .offset = -1 }, \ 149 { .type = iom3, .offset = -1 }, \ 150 }, \ 151 } 152 153 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ 154 iom3, offset0, offset1, offset2, \ 155 offset3) \ 156 { \ 157 .bank_num = id, \ 158 .nr_pins = pins, \ 159 .name = label, \ 160 .iomux = { \ 161 { .type = iom0, .offset = offset0 }, \ 162 { .type = iom1, .offset = offset1 }, \ 163 { .type = iom2, .offset = offset2 }, \ 164 { .type = iom3, .offset = offset3 }, \ 165 }, \ 166 } 167 168 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 169 { \ 170 .bank_num = id, \ 171 .nr_pins = pins, \ 172 .name = label, \ 173 .iomux = { \ 174 { .offset = -1 }, \ 175 { .offset = -1 }, \ 176 { .offset = -1 }, \ 177 { .offset = -1 }, \ 178 }, \ 179 .drv = { \ 180 { .drv_type = type0, .offset = -1 }, \ 181 { .drv_type = type1, .offset = -1 }, \ 182 { .drv_type = type2, .offset = -1 }, \ 183 { .drv_type = type3, .offset = -1 }, \ 184 }, \ 185 } 186 187 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 188 drv2, drv3, pull0, pull1, \ 189 pull2, pull3) \ 190 { \ 191 .bank_num = id, \ 192 .nr_pins = pins, \ 193 .name = label, \ 194 .iomux = { \ 195 { .offset = -1 }, \ 196 { .offset = -1 }, \ 197 { .offset = -1 }, \ 198 { .offset = -1 }, \ 199 }, \ 200 .drv = { \ 201 { .drv_type = drv0, .offset = -1 }, \ 202 { .drv_type = drv1, .offset = -1 }, \ 203 { .drv_type = drv2, .offset = -1 }, \ 204 { .drv_type = drv3, .offset = -1 }, \ 205 }, \ 206 .pull_type[0] = pull0, \ 207 .pull_type[1] = pull1, \ 208 .pull_type[2] = pull2, \ 209 .pull_type[3] = pull3, \ 210 } 211 212 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 213 iom2, iom3, drv0, drv1, drv2, \ 214 drv3, offset0, offset1, \ 215 offset2, offset3) \ 216 { \ 217 .bank_num = id, \ 218 .nr_pins = pins, \ 219 .name = label, \ 220 .iomux = { \ 221 { .type = iom0, .offset = -1 }, \ 222 { .type = iom1, .offset = -1 }, \ 223 { .type = iom2, .offset = -1 }, \ 224 { .type = iom3, .offset = -1 }, \ 225 }, \ 226 .drv = { \ 227 { .drv_type = drv0, .offset = offset0 }, \ 228 { .drv_type = drv1, .offset = offset1 }, \ 229 { .drv_type = drv2, .offset = offset2 }, \ 230 { .drv_type = drv3, .offset = offset3 }, \ 231 }, \ 232 } 233 234 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 235 iom2, iom3, drv0, drv1, drv2, \ 236 drv3, pull0, pull1, pull2, \ 237 pull3) \ 238 { \ 239 .bank_num = id, \ 240 .nr_pins = pins, \ 241 .name = label, \ 242 .iomux = { \ 243 { .type = iom0, .offset = -1 }, \ 244 { .type = iom1, .offset = -1 }, \ 245 { .type = iom2, .offset = -1 }, \ 246 { .type = iom3, .offset = -1 }, \ 247 }, \ 248 .drv = { \ 249 { .drv_type = drv0, .offset = -1 }, \ 250 { .drv_type = drv1, .offset = -1 }, \ 251 { .drv_type = drv2, .offset = -1 }, \ 252 { .drv_type = drv3, .offset = -1 }, \ 253 }, \ 254 .pull_type[0] = pull0, \ 255 .pull_type[1] = pull1, \ 256 .pull_type[2] = pull2, \ 257 .pull_type[3] = pull3, \ 258 } 259 260 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 261 label, iom0, iom1, iom2, \ 262 iom3, drv0, drv1, drv2, \ 263 drv3, offset0, offset1, \ 264 offset2, offset3, pull0, \ 265 pull1, pull2, pull3) \ 266 { \ 267 .bank_num = id, \ 268 .nr_pins = pins, \ 269 .name = label, \ 270 .iomux = { \ 271 { .type = iom0, .offset = -1 }, \ 272 { .type = iom1, .offset = -1 }, \ 273 { .type = iom2, .offset = -1 }, \ 274 { .type = iom3, .offset = -1 }, \ 275 }, \ 276 .drv = { \ 277 { .drv_type = drv0, .offset = offset0 }, \ 278 { .drv_type = drv1, .offset = offset1 }, \ 279 { .drv_type = drv2, .offset = offset2 }, \ 280 { .drv_type = drv3, .offset = offset3 }, \ 281 }, \ 282 .pull_type[0] = pull0, \ 283 .pull_type[1] = pull1, \ 284 .pull_type[2] = pull2, \ 285 .pull_type[3] = pull3, \ 286 } 287 288 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL) \ 289 { \ 290 .bank_num = ID, \ 291 .pin = PIN, \ 292 .func = FUNC, \ 293 .route_offset = REG, \ 294 .route_val = VAL, \ 295 } 296 297 /** 298 * struct rockchip_mux_recalced_data: represent a pin iomux data. 299 * @num: bank number. 300 * @pin: pin number. 301 * @bit: index at register. 302 * @reg: register offset. 303 * @mask: mask bit 304 */ 305 struct rockchip_mux_recalced_data { 306 u8 num; 307 u8 pin; 308 u32 reg; 309 u8 bit; 310 u8 mask; 311 }; 312 313 /** 314 * struct rockchip_mux_recalced_data: represent a pin iomux data. 315 * @bank_num: bank number. 316 * @pin: index at register or used to calc index. 317 * @func: the min pin. 318 * @route_offset: the max pin. 319 * @route_val: the register offset. 320 */ 321 struct rockchip_mux_route_data { 322 u8 bank_num; 323 u8 pin; 324 u8 func; 325 u32 route_offset; 326 u32 route_val; 327 }; 328 329 /** 330 */ 331 struct rockchip_pin_ctrl { 332 struct rockchip_pin_bank *pin_banks; 333 u32 nr_banks; 334 u32 nr_pins; 335 char *label; 336 enum rockchip_pinctrl_type type; 337 int grf_mux_offset; 338 int pmu_mux_offset; 339 int grf_drv_offset; 340 int pmu_drv_offset; 341 struct rockchip_mux_recalced_data *iomux_recalced; 342 u32 niomux_recalced; 343 struct rockchip_mux_route_data *iomux_routes; 344 u32 niomux_routes; 345 346 int (*ctrl_data_re_init)(struct rockchip_pin_ctrl *ctrl); 347 348 int (*soc_data_init)(struct rockchip_pinctrl_priv *info); 349 350 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 351 int pin_num, struct regmap **regmap, 352 int *reg, u8 *bit); 353 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 354 int pin_num, struct regmap **regmap, 355 int *reg, u8 *bit); 356 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 357 int pin_num, struct regmap **regmap, 358 int *reg, u8 *bit); 359 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank, 360 int pin_num, struct regmap **regmap, 361 int *reg, u8 *bit); 362 }; 363 364 /** 365 */ 366 struct rockchip_pinctrl_priv { 367 struct rockchip_pin_ctrl *ctrl; 368 struct regmap *regmap_base; 369 struct regmap *regmap_pmu; 370 371 }; 372 373 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 374 { 375 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 376 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 377 378 if (bank >= ctrl->nr_banks) { 379 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 380 return -EINVAL; 381 } 382 383 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 384 debug("pin conf pin %d >= %d\n", pin, 385 MAX_ROCKCHIP_GPIO_PER_BANK); 386 return -EINVAL; 387 } 388 389 return 0; 390 } 391 392 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 393 { 394 .num = 1, 395 .pin = 0, 396 .reg = 0x418, 397 .bit = 0, 398 .mask = 0x3 399 }, { 400 .num = 1, 401 .pin = 1, 402 .reg = 0x418, 403 .bit = 2, 404 .mask = 0x3 405 }, { 406 .num = 1, 407 .pin = 2, 408 .reg = 0x418, 409 .bit = 4, 410 .mask = 0x3 411 }, { 412 .num = 1, 413 .pin = 3, 414 .reg = 0x418, 415 .bit = 6, 416 .mask = 0x3 417 }, { 418 .num = 1, 419 .pin = 4, 420 .reg = 0x418, 421 .bit = 8, 422 .mask = 0x3 423 }, { 424 .num = 1, 425 .pin = 5, 426 .reg = 0x418, 427 .bit = 10, 428 .mask = 0x3 429 }, { 430 .num = 1, 431 .pin = 6, 432 .reg = 0x418, 433 .bit = 12, 434 .mask = 0x3 435 }, { 436 .num = 1, 437 .pin = 7, 438 .reg = 0x418, 439 .bit = 14, 440 .mask = 0x3 441 }, { 442 .num = 1, 443 .pin = 8, 444 .reg = 0x41c, 445 .bit = 0, 446 .mask = 0x3 447 }, { 448 .num = 1, 449 .pin = 9, 450 .reg = 0x41c, 451 .bit = 2, 452 .mask = 0x3 453 }, 454 }; 455 456 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 457 { 458 .num = 0, 459 .pin = 20, 460 .reg = 0x10000, 461 .bit = 0, 462 .mask = 0xf 463 }, 464 { 465 .num = 0, 466 .pin = 21, 467 .reg = 0x10000, 468 .bit = 4, 469 .mask = 0xf 470 }, 471 { 472 .num = 0, 473 .pin = 22, 474 .reg = 0x10000, 475 .bit = 8, 476 .mask = 0xf 477 }, 478 { 479 .num = 0, 480 .pin = 23, 481 .reg = 0x10000, 482 .bit = 12, 483 .mask = 0xf 484 }, 485 }; 486 487 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 488 { 489 .num = 2, 490 .pin = 20, 491 .reg = 0xe8, 492 .bit = 0, 493 .mask = 0x7 494 }, { 495 .num = 2, 496 .pin = 21, 497 .reg = 0xe8, 498 .bit = 4, 499 .mask = 0x7 500 }, { 501 .num = 2, 502 .pin = 22, 503 .reg = 0xe8, 504 .bit = 8, 505 .mask = 0x7 506 }, { 507 .num = 2, 508 .pin = 23, 509 .reg = 0xe8, 510 .bit = 12, 511 .mask = 0x7 512 }, { 513 .num = 2, 514 .pin = 24, 515 .reg = 0xd4, 516 .bit = 12, 517 .mask = 0x7 518 }, 519 }; 520 521 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 522 { 523 .num = 1, 524 .pin = 14, 525 .reg = 0x28, 526 .bit = 12, 527 .mask = 0x7 528 }, { 529 .num = 1, 530 .pin = 15, 531 .reg = 0x2c, 532 .bit = 0, 533 .mask = 0x3 534 }, { 535 .num = 1, 536 .pin = 18, 537 .reg = 0x30, 538 .bit = 4, 539 .mask = 0x7 540 }, { 541 .num = 1, 542 .pin = 19, 543 .reg = 0x30, 544 .bit = 8, 545 .mask = 0x7 546 }, { 547 .num = 1, 548 .pin = 20, 549 .reg = 0x30, 550 .bit = 12, 551 .mask = 0x7 552 }, { 553 .num = 1, 554 .pin = 21, 555 .reg = 0x34, 556 .bit = 0, 557 .mask = 0x7 558 }, { 559 .num = 1, 560 .pin = 22, 561 .reg = 0x34, 562 .bit = 4, 563 .mask = 0x7 564 }, { 565 .num = 1, 566 .pin = 23, 567 .reg = 0x34, 568 .bit = 8, 569 .mask = 0x7 570 }, { 571 .num = 3, 572 .pin = 12, 573 .reg = 0x68, 574 .bit = 8, 575 .mask = 0x7 576 }, { 577 .num = 3, 578 .pin = 13, 579 .reg = 0x68, 580 .bit = 12, 581 .mask = 0x7 582 }, 583 }; 584 585 static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { 586 { 587 .num = 1, 588 .pin = 14, 589 .reg = 0x28, 590 .bit = 12, 591 .mask = 0xf 592 }, { 593 .num = 1, 594 .pin = 15, 595 .reg = 0x2c, 596 .bit = 0, 597 .mask = 0x3 598 }, { 599 .num = 1, 600 .pin = 18, 601 .reg = 0x30, 602 .bit = 4, 603 .mask = 0xf 604 }, { 605 .num = 1, 606 .pin = 19, 607 .reg = 0x30, 608 .bit = 8, 609 .mask = 0xf 610 }, { 611 .num = 1, 612 .pin = 20, 613 .reg = 0x30, 614 .bit = 12, 615 .mask = 0xf 616 }, { 617 .num = 1, 618 .pin = 21, 619 .reg = 0x34, 620 .bit = 0, 621 .mask = 0xf 622 }, { 623 .num = 1, 624 .pin = 22, 625 .reg = 0x34, 626 .bit = 4, 627 .mask = 0xf 628 }, { 629 .num = 1, 630 .pin = 23, 631 .reg = 0x34, 632 .bit = 8, 633 .mask = 0xf 634 }, { 635 .num = 3, 636 .pin = 12, 637 .reg = 0x68, 638 .bit = 8, 639 .mask = 0xf 640 }, { 641 .num = 3, 642 .pin = 13, 643 .reg = 0x68, 644 .bit = 12, 645 .mask = 0xf 646 }, { 647 .num = 2, 648 .pin = 2, 649 .reg = 0x608, 650 .bit = 0, 651 .mask = 0x7 652 }, { 653 .num = 2, 654 .pin = 3, 655 .reg = 0x608, 656 .bit = 4, 657 .mask = 0x7 658 }, { 659 .num = 2, 660 .pin = 16, 661 .reg = 0x610, 662 .bit = 8, 663 .mask = 0x7 664 }, { 665 .num = 3, 666 .pin = 10, 667 .reg = 0x610, 668 .bit = 0, 669 .mask = 0x7 670 }, { 671 .num = 3, 672 .pin = 11, 673 .reg = 0x610, 674 .bit = 4, 675 .mask = 0x7 676 }, 677 }; 678 679 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 680 { 681 .num = 2, 682 .pin = 12, 683 .reg = 0x24, 684 .bit = 8, 685 .mask = 0x3 686 }, { 687 .num = 2, 688 .pin = 15, 689 .reg = 0x28, 690 .bit = 0, 691 .mask = 0x7 692 }, { 693 .num = 2, 694 .pin = 23, 695 .reg = 0x30, 696 .bit = 14, 697 .mask = 0x3 698 }, 699 }; 700 701 static struct rockchip_mux_route_data rv1126_mux_route_data[] = { 702 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ 703 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PB0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ 704 705 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO0, RK_PD4, RK_FUNC_4, 0x10260, RK_GENMASK_VAL(2, 3, 0)), /* I2S1_MCLK_M0 */ 706 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(2, 3, 1)), /* I2S1_MCLK_M1 */ 707 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PC7, RK_FUNC_6, 0x10260, RK_GENMASK_VAL(2, 3, 2)), /* I2S1_MCLK_M2 */ 708 709 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO1, RK_PD0, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ 710 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PB3, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ 711 712 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PD4, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ 713 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PC0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ 714 715 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PC6, RK_FUNC_1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ 716 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PD1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ 717 718 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA4, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(4, 5, 0)), /* I2C3_SCL_M0 */ 719 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PD4, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(4, 5, 1)), /* I2C3_SCL_M1 */ 720 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO1, RK_PD6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(4, 5, 2)), /* I2C3_SCL_M2 */ 721 722 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA0, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ 723 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ 724 725 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PA5, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(8, 9, 0)), /* I2C5_SCL_M0 */ 726 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PB0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(8, 9, 1)), /* I2C5_SCL_M1 */ 727 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO1, RK_PD0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(8, 9, 2)), /* I2C5_SCL_M2 */ 728 729 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PC0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(10, 11, 0)), /* SPI1_CLK_M0 */ 730 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO1, RK_PC6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(10, 11, 1)), /* SPI1_CLK_M1 */ 731 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PD5, RK_FUNC_6, 0x10264, RK_GENMASK_VAL(10, 11, 2)), /* SPI1_CLK_M2 */ 732 733 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ 734 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PB7, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ 735 736 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ 737 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA7, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ 738 739 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA4, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */ 740 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PD7, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */ 741 742 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA5, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */ 743 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PD6, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */ 744 745 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA6, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */ 746 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PD5, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */ 747 748 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA7, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ 749 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA1, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ 750 751 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO1, RK_PA5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ 752 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA2, RK_FUNC_1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ 753 754 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PC6, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(10, 11, 0)), /* UART3_TX_M0 */ 755 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO1, RK_PA7, RK_FUNC_2, 0x10268, RK_GENMASK_VAL(10, 11, 1)), /* UART3_TX_M1 */ 756 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(10, 11, 2)), /* UART3_TX_M2 */ 757 758 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA4, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(12, 13, 0)), /* UART4_TX_M0 */ 759 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(12, 13, 1)), /* UART4_TX_M1 */ 760 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(12, 13, 2)), /* UART4_TX_M2 */ 761 762 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO3, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(14, 15, 0)), /* UART5_TX_M0 */ 763 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PB0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(14, 15, 1)), /* UART5_TX_M1 */ 764 PIN_BANK_MUX_ROUTE_FLAGS(RK_GPIO2, RK_PA0, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(14, 15, 2)), /* UART5_TX_M2 */ 765 }; 766 767 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 768 int *reg, u8 *bit, int *mask) 769 { 770 struct rockchip_pinctrl_priv *priv = bank->priv; 771 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 772 struct rockchip_mux_recalced_data *data; 773 int i; 774 775 for (i = 0; i < ctrl->niomux_recalced; i++) { 776 data = &ctrl->iomux_recalced[i]; 777 if (data->num == bank->bank_num && 778 data->pin == pin) 779 break; 780 } 781 782 if (i >= ctrl->niomux_recalced) 783 return; 784 785 *reg = data->reg; 786 *mask = data->mask; 787 *bit = data->bit; 788 } 789 790 static struct rockchip_mux_route_data px30_mux_route_data[] = { 791 { 792 /* cif-d2m0 */ 793 .bank_num = 2, 794 .pin = 0, 795 .func = 1, 796 .route_offset = 0x184, 797 .route_val = BIT(16 + 7), 798 }, { 799 /* cif-d2m1 */ 800 .bank_num = 3, 801 .pin = 3, 802 .func = 3, 803 .route_offset = 0x184, 804 .route_val = BIT(16 + 7) | BIT(7), 805 }, { 806 /* pdm-m0 */ 807 .bank_num = 3, 808 .pin = 22, 809 .func = 2, 810 .route_offset = 0x184, 811 .route_val = BIT(16 + 8), 812 }, { 813 /* pdm-m1 */ 814 .bank_num = 2, 815 .pin = 22, 816 .func = 1, 817 .route_offset = 0x184, 818 .route_val = BIT(16 + 8) | BIT(8), 819 }, { 820 /* uart2-rxm0 */ 821 .bank_num = 1, 822 .pin = 27, 823 .func = 2, 824 .route_offset = 0x184, 825 .route_val = BIT(16 + 10), 826 }, { 827 /* uart2-rxm1 */ 828 .bank_num = 2, 829 .pin = 14, 830 .func = 2, 831 .route_offset = 0x184, 832 .route_val = BIT(16 + 10) | BIT(10), 833 }, { 834 /* uart3-rxm0 */ 835 .bank_num = 0, 836 .pin = 17, 837 .func = 2, 838 .route_offset = 0x184, 839 .route_val = BIT(16 + 9), 840 }, { 841 /* uart3-rxm1 */ 842 .bank_num = 1, 843 .pin = 15, 844 .func = 2, 845 .route_offset = 0x184, 846 .route_val = BIT(16 + 9) | BIT(9), 847 }, 848 }; 849 850 static struct rockchip_mux_route_data rk1808_mux_route_data[] = { 851 { 852 /* i2c2m0_sda */ 853 .bank_num = 3, 854 .pin = 12, 855 .func = 2, 856 .route_offset = 0x190, 857 .route_val = BIT(16 + 3), 858 }, { 859 /* i2c2m1_sda */ 860 .bank_num = 1, 861 .pin = 13, 862 .func = 2, 863 .route_offset = 0x190, 864 .route_val = BIT(16 + 3) | BIT(3), 865 }, { 866 /* uart2_rxm0 */ 867 .bank_num = 4, 868 .pin = 3, 869 .func = 2, 870 .route_offset = 0x190, 871 .route_val = BIT(16 + 14) | BIT(16 + 15), 872 }, { 873 /* uart2_rxm1 */ 874 .bank_num = 2, 875 .pin = 25, 876 .func = 2, 877 .route_offset = 0x190, 878 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15), 879 }, { 880 /* uart2_rxm2 */ 881 .bank_num = 3, 882 .pin = 4, 883 .func = 2, 884 .route_offset = 0x190, 885 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15), 886 }, 887 }; 888 889 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 890 { 891 /* spi-0 */ 892 .bank_num = 1, 893 .pin = 10, 894 .func = 1, 895 .route_offset = 0x144, 896 .route_val = BIT(16 + 3) | BIT(16 + 4), 897 }, { 898 /* spi-1 */ 899 .bank_num = 1, 900 .pin = 27, 901 .func = 3, 902 .route_offset = 0x144, 903 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 904 }, { 905 /* spi-2 */ 906 .bank_num = 0, 907 .pin = 13, 908 .func = 2, 909 .route_offset = 0x144, 910 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 911 }, { 912 /* i2s-0 */ 913 .bank_num = 1, 914 .pin = 5, 915 .func = 1, 916 .route_offset = 0x144, 917 .route_val = BIT(16 + 5), 918 }, { 919 /* i2s-1 */ 920 .bank_num = 0, 921 .pin = 14, 922 .func = 1, 923 .route_offset = 0x144, 924 .route_val = BIT(16 + 5) | BIT(5), 925 }, { 926 /* emmc-0 */ 927 .bank_num = 1, 928 .pin = 22, 929 .func = 2, 930 .route_offset = 0x144, 931 .route_val = BIT(16 + 6), 932 }, { 933 /* emmc-1 */ 934 .bank_num = 2, 935 .pin = 4, 936 .func = 2, 937 .route_offset = 0x144, 938 .route_val = BIT(16 + 6) | BIT(6), 939 }, 940 }; 941 942 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 943 { 944 /* pwm0-0 */ 945 .bank_num = 0, 946 .pin = 26, 947 .func = 1, 948 .route_offset = 0x50, 949 .route_val = BIT(16), 950 }, { 951 /* pwm0-1 */ 952 .bank_num = 3, 953 .pin = 21, 954 .func = 1, 955 .route_offset = 0x50, 956 .route_val = BIT(16) | BIT(0), 957 }, { 958 /* pwm1-0 */ 959 .bank_num = 0, 960 .pin = 27, 961 .func = 1, 962 .route_offset = 0x50, 963 .route_val = BIT(16 + 1), 964 }, { 965 /* pwm1-1 */ 966 .bank_num = 0, 967 .pin = 30, 968 .func = 2, 969 .route_offset = 0x50, 970 .route_val = BIT(16 + 1) | BIT(1), 971 }, { 972 /* pwm2-0 */ 973 .bank_num = 0, 974 .pin = 28, 975 .func = 1, 976 .route_offset = 0x50, 977 .route_val = BIT(16 + 2), 978 }, { 979 /* pwm2-1 */ 980 .bank_num = 1, 981 .pin = 12, 982 .func = 2, 983 .route_offset = 0x50, 984 .route_val = BIT(16 + 2) | BIT(2), 985 }, { 986 /* pwm3-0 */ 987 .bank_num = 3, 988 .pin = 26, 989 .func = 1, 990 .route_offset = 0x50, 991 .route_val = BIT(16 + 3), 992 }, { 993 /* pwm3-1 */ 994 .bank_num = 1, 995 .pin = 11, 996 .func = 2, 997 .route_offset = 0x50, 998 .route_val = BIT(16 + 3) | BIT(3), 999 }, { 1000 /* sdio-0_d0 */ 1001 .bank_num = 1, 1002 .pin = 1, 1003 .func = 1, 1004 .route_offset = 0x50, 1005 .route_val = BIT(16 + 4), 1006 }, { 1007 /* sdio-1_d0 */ 1008 .bank_num = 3, 1009 .pin = 2, 1010 .func = 1, 1011 .route_offset = 0x50, 1012 .route_val = BIT(16 + 4) | BIT(4), 1013 }, { 1014 /* spi-0_rx */ 1015 .bank_num = 0, 1016 .pin = 13, 1017 .func = 2, 1018 .route_offset = 0x50, 1019 .route_val = BIT(16 + 5), 1020 }, { 1021 /* spi-1_rx */ 1022 .bank_num = 2, 1023 .pin = 0, 1024 .func = 2, 1025 .route_offset = 0x50, 1026 .route_val = BIT(16 + 5) | BIT(5), 1027 }, { 1028 /* emmc-0_cmd */ 1029 .bank_num = 1, 1030 .pin = 22, 1031 .func = 2, 1032 .route_offset = 0x50, 1033 .route_val = BIT(16 + 7), 1034 }, { 1035 /* emmc-1_cmd */ 1036 .bank_num = 2, 1037 .pin = 4, 1038 .func = 2, 1039 .route_offset = 0x50, 1040 .route_val = BIT(16 + 7) | BIT(7), 1041 }, { 1042 /* uart2-0_rx */ 1043 .bank_num = 1, 1044 .pin = 19, 1045 .func = 2, 1046 .route_offset = 0x50, 1047 .route_val = BIT(16 + 8), 1048 }, { 1049 /* uart2-1_rx */ 1050 .bank_num = 1, 1051 .pin = 10, 1052 .func = 2, 1053 .route_offset = 0x50, 1054 .route_val = BIT(16 + 8) | BIT(8), 1055 }, { 1056 /* uart1-0_rx */ 1057 .bank_num = 1, 1058 .pin = 10, 1059 .func = 1, 1060 .route_offset = 0x50, 1061 .route_val = BIT(16 + 11), 1062 }, { 1063 /* uart1-1_rx */ 1064 .bank_num = 3, 1065 .pin = 13, 1066 .func = 1, 1067 .route_offset = 0x50, 1068 .route_val = BIT(16 + 11) | BIT(11), 1069 }, 1070 }; 1071 1072 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 1073 { 1074 /* edphdmi_cecinoutt1 */ 1075 .bank_num = 7, 1076 .pin = 16, 1077 .func = 2, 1078 .route_offset = 0x264, 1079 .route_val = BIT(16 + 12) | BIT(12), 1080 }, { 1081 /* edphdmi_cecinout */ 1082 .bank_num = 7, 1083 .pin = 23, 1084 .func = 4, 1085 .route_offset = 0x264, 1086 .route_val = BIT(16 + 12), 1087 }, 1088 }; 1089 1090 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 1091 { 1092 /* rtc_clk */ 1093 .bank_num = 0, 1094 .pin = 19, 1095 .func = 1, 1096 .route_offset = 0x314, 1097 .route_val = BIT(16 + 0) | BIT(0), 1098 }, { 1099 /* uart2_rxm0 */ 1100 .bank_num = 1, 1101 .pin = 22, 1102 .func = 2, 1103 .route_offset = 0x314, 1104 .route_val = BIT(16 + 2) | BIT(16 + 3), 1105 }, { 1106 /* uart2_rxm1 */ 1107 .bank_num = 4, 1108 .pin = 26, 1109 .func = 2, 1110 .route_offset = 0x314, 1111 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1112 }, { 1113 /* i2c3_sdam0 */ 1114 .bank_num = 0, 1115 .pin = 23, 1116 .func = 2, 1117 .route_offset = 0x314, 1118 .route_val = BIT(16 + 4), 1119 }, { 1120 /* i2c3_sdam1 */ 1121 .bank_num = 3, 1122 .pin = 12, 1123 .func = 2, 1124 .route_offset = 0x314, 1125 .route_val = BIT(16 + 4) | BIT(4), 1126 }, { 1127 /* i2s-8ch-1-sclktxm0 */ 1128 .bank_num = 1, 1129 .pin = 3, 1130 .func = 2, 1131 .route_offset = 0x308, 1132 .route_val = BIT(16 + 3), 1133 }, { 1134 /* i2s-8ch-1-sclkrxm0 */ 1135 .bank_num = 1, 1136 .pin = 4, 1137 .func = 2, 1138 .route_offset = 0x308, 1139 .route_val = BIT(16 + 3), 1140 }, { 1141 /* i2s-8ch-1-sclktxm1 */ 1142 .bank_num = 1, 1143 .pin = 13, 1144 .func = 2, 1145 .route_offset = 0x308, 1146 .route_val = BIT(16 + 3) | BIT(3), 1147 }, { 1148 /* i2s-8ch-1-sclkrxm1 */ 1149 .bank_num = 1, 1150 .pin = 14, 1151 .func = 2, 1152 .route_offset = 0x308, 1153 .route_val = BIT(16 + 3) | BIT(3), 1154 }, { 1155 /* pdm-clkm0 */ 1156 .bank_num = 1, 1157 .pin = 4, 1158 .func = 3, 1159 .route_offset = 0x308, 1160 .route_val = BIT(16 + 12) | BIT(16 + 13), 1161 }, { 1162 /* pdm-clkm1 */ 1163 .bank_num = 1, 1164 .pin = 14, 1165 .func = 4, 1166 .route_offset = 0x308, 1167 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1168 }, { 1169 /* pdm-clkm2 */ 1170 .bank_num = 2, 1171 .pin = 6, 1172 .func = 2, 1173 .route_offset = 0x308, 1174 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1175 }, { 1176 /* pdm-clkm-m2 */ 1177 .bank_num = 2, 1178 .pin = 4, 1179 .func = 3, 1180 .route_offset = 0x600, 1181 .route_val = BIT(16 + 2) | BIT(2), 1182 }, 1183 }; 1184 1185 static struct rockchip_mux_route_data rk3308b_mux_route_data[] = { 1186 { 1187 /* rtc_clk */ 1188 .bank_num = 0, 1189 .pin = 19, 1190 .func = 1, 1191 .route_offset = 0x314, 1192 .route_val = BIT(16 + 0) | BIT(0), 1193 }, { 1194 /* uart2_rxm0 */ 1195 .bank_num = 1, 1196 .pin = 22, 1197 .func = 2, 1198 .route_offset = 0x314, 1199 .route_val = BIT(16 + 2) | BIT(16 + 3), 1200 }, { 1201 /* uart2_rxm1 */ 1202 .bank_num = 4, 1203 .pin = 26, 1204 .func = 2, 1205 .route_offset = 0x314, 1206 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1207 }, { 1208 /* i2c3_sdam0 */ 1209 .bank_num = 0, 1210 .pin = 15, 1211 .func = 2, 1212 .route_offset = 0x608, 1213 .route_val = BIT(16 + 8) | BIT(16 + 9), 1214 }, { 1215 /* i2c3_sdam1 */ 1216 .bank_num = 3, 1217 .pin = 12, 1218 .func = 2, 1219 .route_offset = 0x608, 1220 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 1221 }, { 1222 /* i2c3_sdam2 */ 1223 .bank_num = 2, 1224 .pin = 0, 1225 .func = 3, 1226 .route_offset = 0x608, 1227 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 1228 }, { 1229 /* i2s-8ch-1-sclktxm0 */ 1230 .bank_num = 1, 1231 .pin = 3, 1232 .func = 2, 1233 .route_offset = 0x308, 1234 .route_val = BIT(16 + 3), 1235 }, { 1236 /* i2s-8ch-1-sclkrxm0 */ 1237 .bank_num = 1, 1238 .pin = 4, 1239 .func = 2, 1240 .route_offset = 0x308, 1241 .route_val = BIT(16 + 3), 1242 }, { 1243 /* i2s-8ch-1-sclktxm1 */ 1244 .bank_num = 1, 1245 .pin = 13, 1246 .func = 2, 1247 .route_offset = 0x308, 1248 .route_val = BIT(16 + 3) | BIT(3), 1249 }, { 1250 /* i2s-8ch-1-sclkrxm1 */ 1251 .bank_num = 1, 1252 .pin = 14, 1253 .func = 2, 1254 .route_offset = 0x308, 1255 .route_val = BIT(16 + 3) | BIT(3), 1256 }, { 1257 /* pdm-clkm0 */ 1258 .bank_num = 1, 1259 .pin = 4, 1260 .func = 3, 1261 .route_offset = 0x308, 1262 .route_val = BIT(16 + 12) | BIT(16 + 13), 1263 }, { 1264 /* pdm-clkm1 */ 1265 .bank_num = 1, 1266 .pin = 14, 1267 .func = 4, 1268 .route_offset = 0x308, 1269 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1270 }, { 1271 /* pdm-clkm2 */ 1272 .bank_num = 2, 1273 .pin = 6, 1274 .func = 2, 1275 .route_offset = 0x308, 1276 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1277 }, { 1278 /* pdm-clkm-m2 */ 1279 .bank_num = 2, 1280 .pin = 4, 1281 .func = 3, 1282 .route_offset = 0x600, 1283 .route_val = BIT(16 + 2) | BIT(2), 1284 }, { 1285 /* spi1_miso */ 1286 .bank_num = 3, 1287 .pin = 10, 1288 .func = 3, 1289 .route_offset = 0x314, 1290 .route_val = BIT(16 + 9), 1291 }, { 1292 /* spi1_miso_m1 */ 1293 .bank_num = 2, 1294 .pin = 4, 1295 .func = 2, 1296 .route_offset = 0x314, 1297 .route_val = BIT(16 + 9) | BIT(9), 1298 }, { 1299 /* owire_m0 */ 1300 .bank_num = 0, 1301 .pin = 11, 1302 .func = 3, 1303 .route_offset = 0x314, 1304 .route_val = BIT(16 + 10) | BIT(16 + 11), 1305 }, { 1306 /* owire_m1 */ 1307 .bank_num = 1, 1308 .pin = 22, 1309 .func = 7, 1310 .route_offset = 0x314, 1311 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1312 }, { 1313 /* owire_m2 */ 1314 .bank_num = 2, 1315 .pin = 2, 1316 .func = 5, 1317 .route_offset = 0x314, 1318 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1319 }, { 1320 /* can_rxd_m0 */ 1321 .bank_num = 0, 1322 .pin = 11, 1323 .func = 2, 1324 .route_offset = 0x314, 1325 .route_val = BIT(16 + 12) | BIT(16 + 13), 1326 }, { 1327 /* can_rxd_m1 */ 1328 .bank_num = 1, 1329 .pin = 22, 1330 .func = 5, 1331 .route_offset = 0x314, 1332 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1333 }, { 1334 /* can_rxd_m2 */ 1335 .bank_num = 2, 1336 .pin = 2, 1337 .func = 4, 1338 .route_offset = 0x314, 1339 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1340 }, { 1341 /* mac_rxd0_m0 */ 1342 .bank_num = 1, 1343 .pin = 20, 1344 .func = 3, 1345 .route_offset = 0x314, 1346 .route_val = BIT(16 + 14), 1347 }, { 1348 /* mac_rxd0_m1 */ 1349 .bank_num = 4, 1350 .pin = 2, 1351 .func = 2, 1352 .route_offset = 0x314, 1353 .route_val = BIT(16 + 14) | BIT(14), 1354 }, { 1355 /* uart3_rx */ 1356 .bank_num = 3, 1357 .pin = 12, 1358 .func = 4, 1359 .route_offset = 0x314, 1360 .route_val = BIT(16 + 15), 1361 }, { 1362 /* uart3_rx_m1 */ 1363 .bank_num = 0, 1364 .pin = 17, 1365 .func = 3, 1366 .route_offset = 0x314, 1367 .route_val = BIT(16 + 15) | BIT(15), 1368 }, 1369 }; 1370 1371 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1372 { 1373 /* uart2dbg_rxm0 */ 1374 .bank_num = 1, 1375 .pin = 1, 1376 .func = 2, 1377 .route_offset = 0x50, 1378 .route_val = BIT(16) | BIT(16 + 1), 1379 }, { 1380 /* uart2dbg_rxm1 */ 1381 .bank_num = 2, 1382 .pin = 1, 1383 .func = 1, 1384 .route_offset = 0x50, 1385 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1386 }, { 1387 /* gmac-m1_rxd0 */ 1388 .bank_num = 1, 1389 .pin = 11, 1390 .func = 2, 1391 .route_offset = 0x50, 1392 .route_val = BIT(16 + 2) | BIT(2), 1393 }, { 1394 /* gmac-m1-optimized_rxd3 */ 1395 .bank_num = 1, 1396 .pin = 14, 1397 .func = 2, 1398 .route_offset = 0x50, 1399 .route_val = BIT(16 + 10) | BIT(10), 1400 }, { 1401 /* pdm_sdi0m0 */ 1402 .bank_num = 2, 1403 .pin = 19, 1404 .func = 2, 1405 .route_offset = 0x50, 1406 .route_val = BIT(16 + 3), 1407 }, { 1408 /* pdm_sdi0m1 */ 1409 .bank_num = 1, 1410 .pin = 23, 1411 .func = 3, 1412 .route_offset = 0x50, 1413 .route_val = BIT(16 + 3) | BIT(3), 1414 }, { 1415 /* spi_rxdm2 */ 1416 .bank_num = 3, 1417 .pin = 2, 1418 .func = 4, 1419 .route_offset = 0x50, 1420 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1421 }, { 1422 /* i2s2_sdim0 */ 1423 .bank_num = 1, 1424 .pin = 24, 1425 .func = 1, 1426 .route_offset = 0x50, 1427 .route_val = BIT(16 + 6), 1428 }, { 1429 /* i2s2_sdim1 */ 1430 .bank_num = 3, 1431 .pin = 2, 1432 .func = 6, 1433 .route_offset = 0x50, 1434 .route_val = BIT(16 + 6) | BIT(6), 1435 }, { 1436 /* card_iom1 */ 1437 .bank_num = 2, 1438 .pin = 22, 1439 .func = 3, 1440 .route_offset = 0x50, 1441 .route_val = BIT(16 + 7) | BIT(7), 1442 }, { 1443 /* tsp_d5m1 */ 1444 .bank_num = 2, 1445 .pin = 16, 1446 .func = 3, 1447 .route_offset = 0x50, 1448 .route_val = BIT(16 + 8) | BIT(8), 1449 }, { 1450 /* cif_data5m1 */ 1451 .bank_num = 2, 1452 .pin = 16, 1453 .func = 4, 1454 .route_offset = 0x50, 1455 .route_val = BIT(16 + 9) | BIT(9), 1456 }, 1457 }; 1458 1459 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1460 { 1461 /* uart2dbga_rx */ 1462 .bank_num = 4, 1463 .pin = 8, 1464 .func = 2, 1465 .route_offset = 0xe21c, 1466 .route_val = BIT(16 + 10) | BIT(16 + 11), 1467 }, { 1468 /* uart2dbgb_rx */ 1469 .bank_num = 4, 1470 .pin = 16, 1471 .func = 2, 1472 .route_offset = 0xe21c, 1473 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1474 }, { 1475 /* uart2dbgc_rx */ 1476 .bank_num = 4, 1477 .pin = 19, 1478 .func = 1, 1479 .route_offset = 0xe21c, 1480 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1481 }, { 1482 /* pcie_clkreqn */ 1483 .bank_num = 2, 1484 .pin = 26, 1485 .func = 2, 1486 .route_offset = 0xe21c, 1487 .route_val = BIT(16 + 14), 1488 }, { 1489 /* pcie_clkreqnb */ 1490 .bank_num = 4, 1491 .pin = 24, 1492 .func = 1, 1493 .route_offset = 0xe21c, 1494 .route_val = BIT(16 + 14) | BIT(14), 1495 }, 1496 }; 1497 1498 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1499 int mux, u32 *reg, u32 *value) 1500 { 1501 struct rockchip_pinctrl_priv *priv = bank->priv; 1502 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1503 struct rockchip_mux_route_data *data; 1504 int i; 1505 1506 for (i = 0; i < ctrl->niomux_routes; i++) { 1507 data = &ctrl->iomux_routes[i]; 1508 if ((data->bank_num == bank->bank_num) && 1509 (data->pin == pin) && (data->func == mux)) 1510 break; 1511 } 1512 1513 if (i >= ctrl->niomux_routes) 1514 return false; 1515 1516 *reg = data->route_offset; 1517 *value = data->route_val; 1518 1519 return true; 1520 } 1521 1522 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1523 { 1524 struct rockchip_pinctrl_priv *priv = bank->priv; 1525 int iomux_num = (pin / 8); 1526 struct regmap *regmap; 1527 unsigned int val; 1528 int reg, ret, mask, mux_type; 1529 u8 bit; 1530 1531 if (iomux_num > 3) 1532 return -EINVAL; 1533 1534 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1535 debug("pin %d is unrouted\n", pin); 1536 return -EINVAL; 1537 } 1538 1539 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1540 return RK_FUNC_GPIO; 1541 1542 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1543 regmap = priv->regmap_pmu; 1544 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1545 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 1546 else 1547 regmap = priv->regmap_base; 1548 1549 /* get basic quadrupel of mux registers and the correct reg inside */ 1550 mux_type = bank->iomux[iomux_num].type; 1551 reg = bank->iomux[iomux_num].offset; 1552 if (mux_type & IOMUX_WIDTH_4BIT) { 1553 if ((pin % 8) >= 4) 1554 reg += 0x4; 1555 bit = (pin % 4) * 4; 1556 mask = 0xf; 1557 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1558 if ((pin % 8) >= 5) 1559 reg += 0x4; 1560 bit = (pin % 8 % 5) * 3; 1561 mask = 0x7; 1562 } else { 1563 bit = (pin % 8) * 2; 1564 mask = 0x3; 1565 } 1566 1567 if (bank->recalced_mask & BIT(pin)) 1568 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1569 1570 ret = regmap_read(regmap, reg, &val); 1571 if (ret) 1572 return ret; 1573 1574 return ((val >> bit) & mask); 1575 } 1576 1577 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1578 int index) 1579 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1580 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1581 1582 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1583 } 1584 1585 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1586 int pin, int mux) 1587 { 1588 int iomux_num = (pin / 8); 1589 1590 if (iomux_num > 3) 1591 return -EINVAL; 1592 1593 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1594 debug("pin %d is unrouted\n", pin); 1595 return -EINVAL; 1596 } 1597 1598 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1599 if (mux != IOMUX_GPIO_ONLY) { 1600 debug("pin %d only supports a gpio mux\n", pin); 1601 return -ENOTSUPP; 1602 } 1603 } 1604 1605 return 0; 1606 } 1607 1608 /* 1609 * Set a new mux function for a pin. 1610 * 1611 * The register is divided into the upper and lower 16 bit. When changing 1612 * a value, the previous register value is not read and changed. Instead 1613 * it seems the changed bits are marked in the upper 16 bit, while the 1614 * changed value gets set in the same offset in the lower 16 bit. 1615 * All pin settings seem to be 2 bit wide in both the upper and lower 1616 * parts. 1617 * @bank: pin bank to change 1618 * @pin: pin to change 1619 * @mux: new mux function to set 1620 */ 1621 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1622 { 1623 struct rockchip_pinctrl_priv *priv = bank->priv; 1624 int iomux_num = (pin / 8); 1625 struct regmap *regmap; 1626 int reg, ret, mask, mux_type; 1627 u8 bit; 1628 u32 data, route_reg, route_val; 1629 1630 ret = rockchip_verify_mux(bank, pin, mux); 1631 if (ret < 0) 1632 return ret; 1633 1634 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1635 return 0; 1636 1637 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1638 1639 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1640 regmap = priv->regmap_pmu; 1641 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1642 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 1643 else 1644 regmap = priv->regmap_base; 1645 1646 /* get basic quadrupel of mux registers and the correct reg inside */ 1647 mux_type = bank->iomux[iomux_num].type; 1648 reg = bank->iomux[iomux_num].offset; 1649 if (mux_type & IOMUX_WIDTH_4BIT) { 1650 if ((pin % 8) >= 4) 1651 reg += 0x4; 1652 bit = (pin % 4) * 4; 1653 mask = 0xf; 1654 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1655 if ((pin % 8) >= 5) 1656 reg += 0x4; 1657 bit = (pin % 8 % 5) * 3; 1658 mask = 0x7; 1659 } else { 1660 bit = (pin % 8) * 2; 1661 mask = 0x3; 1662 } 1663 1664 if (bank->recalced_mask & BIT(pin)) 1665 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1666 1667 if (bank->route_mask & BIT(pin)) { 1668 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1669 &route_val)) { 1670 ret = regmap_write(regmap, route_reg, route_val); 1671 if (ret) 1672 return ret; 1673 } 1674 } 1675 1676 if (mux_type & IOMUX_WRITABLE_32BIT) { 1677 regmap_read(regmap, reg, &data); 1678 data &= ~(mask << bit); 1679 } else { 1680 data = (mask << (bit + 16)); 1681 } 1682 1683 data |= (mux & mask) << bit; 1684 ret = regmap_write(regmap, reg, data); 1685 1686 return ret; 1687 } 1688 1689 #define PX30_PULL_PMU_OFFSET 0x10 1690 #define PX30_PULL_GRF_OFFSET 0x60 1691 #define PX30_PULL_BITS_PER_PIN 2 1692 #define PX30_PULL_PINS_PER_REG 8 1693 #define PX30_PULL_BANK_STRIDE 16 1694 1695 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1696 int pin_num, struct regmap **regmap, 1697 int *reg, u8 *bit) 1698 { 1699 struct rockchip_pinctrl_priv *priv = bank->priv; 1700 1701 /* The first 32 pins of the first bank are located in PMU */ 1702 if (bank->bank_num == 0) { 1703 *regmap = priv->regmap_pmu; 1704 *reg = PX30_PULL_PMU_OFFSET; 1705 } else { 1706 *regmap = priv->regmap_base; 1707 *reg = PX30_PULL_GRF_OFFSET; 1708 1709 /* correct the offset, as we're starting with the 2nd bank */ 1710 *reg -= 0x10; 1711 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1712 } 1713 1714 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1715 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1716 *bit *= PX30_PULL_BITS_PER_PIN; 1717 } 1718 1719 #define PX30_DRV_PMU_OFFSET 0x20 1720 #define PX30_DRV_GRF_OFFSET 0xf0 1721 #define PX30_DRV_BITS_PER_PIN 2 1722 #define PX30_DRV_PINS_PER_REG 8 1723 #define PX30_DRV_BANK_STRIDE 16 1724 1725 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1726 int pin_num, struct regmap **regmap, 1727 int *reg, u8 *bit) 1728 { 1729 struct rockchip_pinctrl_priv *priv = bank->priv; 1730 1731 /* The first 32 pins of the first bank are located in PMU */ 1732 if (bank->bank_num == 0) { 1733 *regmap = priv->regmap_pmu; 1734 *reg = PX30_DRV_PMU_OFFSET; 1735 } else { 1736 *regmap = priv->regmap_base; 1737 *reg = PX30_DRV_GRF_OFFSET; 1738 1739 /* correct the offset, as we're starting with the 2nd bank */ 1740 *reg -= 0x10; 1741 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1742 } 1743 1744 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1745 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1746 *bit *= PX30_DRV_BITS_PER_PIN; 1747 } 1748 1749 #define PX30_SCHMITT_PMU_OFFSET 0x38 1750 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1751 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1752 #define PX30_SCHMITT_BANK_STRIDE 16 1753 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1754 1755 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1756 int pin_num, 1757 struct regmap **regmap, 1758 int *reg, u8 *bit) 1759 { 1760 struct rockchip_pinctrl_priv *priv = bank->priv; 1761 int pins_per_reg; 1762 1763 if (bank->bank_num == 0) { 1764 *regmap = priv->regmap_pmu; 1765 *reg = PX30_SCHMITT_PMU_OFFSET; 1766 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1767 } else { 1768 *regmap = priv->regmap_base; 1769 *reg = PX30_SCHMITT_GRF_OFFSET; 1770 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1771 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1772 } 1773 *reg += ((pin_num / pins_per_reg) * 4); 1774 *bit = pin_num % pins_per_reg; 1775 1776 return 0; 1777 } 1778 1779 #define RV1108_PULL_PMU_OFFSET 0x10 1780 #define RV1108_PULL_OFFSET 0x110 1781 #define RV1108_PULL_PINS_PER_REG 8 1782 #define RV1108_PULL_BITS_PER_PIN 2 1783 #define RV1108_PULL_BANK_STRIDE 16 1784 1785 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1786 int pin_num, struct regmap **regmap, 1787 int *reg, u8 *bit) 1788 { 1789 struct rockchip_pinctrl_priv *priv = bank->priv; 1790 1791 /* The first 24 pins of the first bank are located in PMU */ 1792 if (bank->bank_num == 0) { 1793 *regmap = priv->regmap_pmu; 1794 *reg = RV1108_PULL_PMU_OFFSET; 1795 } else { 1796 *reg = RV1108_PULL_OFFSET; 1797 *regmap = priv->regmap_base; 1798 /* correct the offset, as we're starting with the 2nd bank */ 1799 *reg -= 0x10; 1800 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1801 } 1802 1803 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1804 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1805 *bit *= RV1108_PULL_BITS_PER_PIN; 1806 } 1807 1808 #define RV1108_DRV_PMU_OFFSET 0x20 1809 #define RV1108_DRV_GRF_OFFSET 0x210 1810 #define RV1108_DRV_BITS_PER_PIN 2 1811 #define RV1108_DRV_PINS_PER_REG 8 1812 #define RV1108_DRV_BANK_STRIDE 16 1813 1814 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1815 int pin_num, struct regmap **regmap, 1816 int *reg, u8 *bit) 1817 { 1818 struct rockchip_pinctrl_priv *priv = bank->priv; 1819 1820 /* The first 24 pins of the first bank are located in PMU */ 1821 if (bank->bank_num == 0) { 1822 *regmap = priv->regmap_pmu; 1823 *reg = RV1108_DRV_PMU_OFFSET; 1824 } else { 1825 *regmap = priv->regmap_base; 1826 *reg = RV1108_DRV_GRF_OFFSET; 1827 1828 /* correct the offset, as we're starting with the 2nd bank */ 1829 *reg -= 0x10; 1830 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1831 } 1832 1833 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1834 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1835 *bit *= RV1108_DRV_BITS_PER_PIN; 1836 } 1837 1838 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1839 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1840 #define RV1108_SCHMITT_BANK_STRIDE 8 1841 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1842 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1843 1844 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1845 int pin_num, 1846 struct regmap **regmap, 1847 int *reg, u8 *bit) 1848 { 1849 struct rockchip_pinctrl_priv *priv = bank->priv; 1850 int pins_per_reg; 1851 1852 if (bank->bank_num == 0) { 1853 *regmap = priv->regmap_pmu; 1854 *reg = RV1108_SCHMITT_PMU_OFFSET; 1855 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1856 } else { 1857 *regmap = priv->regmap_base; 1858 *reg = RV1108_SCHMITT_GRF_OFFSET; 1859 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1860 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1861 } 1862 *reg += ((pin_num / pins_per_reg) * 4); 1863 *bit = pin_num % pins_per_reg; 1864 1865 return 0; 1866 } 1867 1868 #define RV1126_PULL_PMU_OFFSET 0x40 1869 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 1870 #define RV1126_PULL_PINS_PER_REG 8 1871 #define RV1126_PULL_BITS_PER_PIN 2 1872 #define RV1126_PULL_BANK_STRIDE 16 1873 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 1874 1875 static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1876 int pin_num, struct regmap **regmap, 1877 int *reg, u8 *bit) 1878 { 1879 struct rockchip_pinctrl_priv *priv = bank->priv; 1880 1881 /* The first 24 pins of the first bank are located in PMU */ 1882 if (bank->bank_num == 0) { 1883 if (RV1126_GPIO_C4_D7(pin_num)) { 1884 *regmap = priv->regmap_base; 1885 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1886 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 1887 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 1888 *bit *= RV1126_PULL_BITS_PER_PIN; 1889 return; 1890 } 1891 *regmap = priv->regmap_pmu; 1892 *reg = RV1126_PULL_PMU_OFFSET; 1893 } else { 1894 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1895 *regmap = priv->regmap_base; 1896 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; 1897 } 1898 1899 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 1900 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 1901 *bit *= RV1126_PULL_BITS_PER_PIN; 1902 } 1903 1904 #define RV1126_DRV_PMU_OFFSET 0x20 1905 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 1906 #define RV1126_DRV_BITS_PER_PIN 4 1907 #define RV1126_DRV_PINS_PER_REG 4 1908 #define RV1126_DRV_BANK_STRIDE 32 1909 1910 static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1911 int pin_num, struct regmap **regmap, 1912 int *reg, u8 *bit) 1913 { 1914 struct rockchip_pinctrl_priv *priv = bank->priv; 1915 1916 /* The first 24 pins of the first bank are located in PMU */ 1917 if (bank->bank_num == 0) { 1918 if (RV1126_GPIO_C4_D7(pin_num)) { 1919 *regmap = priv->regmap_base; 1920 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1921 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 1922 *reg -= 0x4; 1923 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1924 *bit *= RV1126_DRV_BITS_PER_PIN; 1925 return; 1926 } 1927 *regmap = priv->regmap_pmu; 1928 *reg = RV1126_DRV_PMU_OFFSET; 1929 } else { 1930 *regmap = priv->regmap_base; 1931 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1932 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; 1933 } 1934 1935 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 1936 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1937 *bit *= RV1126_DRV_BITS_PER_PIN; 1938 } 1939 1940 #define RV1126_SCHMITT_PMU_OFFSET 0x60 1941 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 1942 #define RV1126_SCHMITT_BANK_STRIDE 16 1943 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8 1944 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8 1945 1946 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1947 int pin_num, 1948 struct regmap **regmap, 1949 int *reg, u8 *bit) 1950 { 1951 struct rockchip_pinctrl_priv *priv = bank->priv; 1952 int pins_per_reg; 1953 1954 if (bank->bank_num == 0) { 1955 if (RV1126_GPIO_C4_D7(pin_num)) { 1956 *regmap = priv->regmap_base; 1957 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1958 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 1959 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 1960 return 0; 1961 } 1962 *regmap = priv->regmap_pmu; 1963 *reg = RV1126_SCHMITT_PMU_OFFSET; 1964 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 1965 } else { 1966 *regmap = priv->regmap_base; 1967 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1968 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 1969 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; 1970 } 1971 *reg += ((pin_num / pins_per_reg) * 4); 1972 *bit = pin_num % pins_per_reg; 1973 1974 return 0; 1975 } 1976 1977 #define RK1808_PULL_PMU_OFFSET 0x10 1978 #define RK1808_PULL_GRF_OFFSET 0x80 1979 #define RK1808_PULL_PINS_PER_REG 8 1980 #define RK1808_PULL_BITS_PER_PIN 2 1981 #define RK1808_PULL_BANK_STRIDE 16 1982 1983 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1984 int pin_num, 1985 struct regmap **regmap, 1986 int *reg, u8 *bit) 1987 { 1988 struct rockchip_pinctrl_priv *priv = bank->priv; 1989 1990 if (bank->bank_num == 0) { 1991 *regmap = priv->regmap_pmu; 1992 *reg = RK1808_PULL_PMU_OFFSET; 1993 } else { 1994 *reg = RK1808_PULL_GRF_OFFSET; 1995 *regmap = priv->regmap_base; 1996 } 1997 1998 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4); 1999 *bit = (pin_num % RK1808_PULL_PINS_PER_REG); 2000 *bit *= RK1808_PULL_BITS_PER_PIN; 2001 } 2002 2003 #define RK1808_DRV_PMU_OFFSET 0x20 2004 #define RK1808_DRV_GRF_OFFSET 0x140 2005 #define RK1808_DRV_BITS_PER_PIN 2 2006 #define RK1808_DRV_PINS_PER_REG 8 2007 #define RK1808_DRV_BANK_STRIDE 16 2008 2009 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2010 int pin_num, 2011 struct regmap **regmap, 2012 int *reg, u8 *bit) 2013 { 2014 struct rockchip_pinctrl_priv *priv = bank->priv; 2015 2016 if (bank->bank_num == 0) { 2017 *regmap = priv->regmap_pmu; 2018 *reg = RK1808_DRV_PMU_OFFSET; 2019 } else { 2020 *regmap = priv->regmap_base; 2021 *reg = RK1808_DRV_GRF_OFFSET; 2022 } 2023 2024 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4); 2025 *bit = pin_num % RK1808_DRV_PINS_PER_REG; 2026 *bit *= RK1808_DRV_BITS_PER_PIN; 2027 } 2028 2029 #define RK1808_SCHMITT_PMU_OFFSET 0x0040 2030 #define RK1808_SCHMITT_GRF_OFFSET 0x0100 2031 #define RK1808_SCHMITT_BANK_STRIDE 16 2032 #define RK1808_SCHMITT_PINS_PER_REG 8 2033 2034 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2035 int pin_num, 2036 struct regmap **regmap, 2037 int *reg, u8 *bit) 2038 { 2039 struct rockchip_pinctrl_priv *priv = bank->priv; 2040 2041 if (bank->bank_num == 0) { 2042 *regmap = priv->regmap_pmu; 2043 *reg = RK1808_SCHMITT_PMU_OFFSET; 2044 } else { 2045 *regmap = priv->regmap_base; 2046 *reg = RK1808_SCHMITT_GRF_OFFSET; 2047 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE; 2048 } 2049 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4); 2050 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG; 2051 2052 return 0; 2053 } 2054 2055 #define RK2928_PULL_OFFSET 0x118 2056 #define RK2928_PULL_PINS_PER_REG 16 2057 #define RK2928_PULL_BANK_STRIDE 8 2058 2059 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2060 int pin_num, struct regmap **regmap, 2061 int *reg, u8 *bit) 2062 { 2063 struct rockchip_pinctrl_priv *priv = bank->priv; 2064 2065 *regmap = priv->regmap_base; 2066 *reg = RK2928_PULL_OFFSET; 2067 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 2068 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 2069 2070 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 2071 }; 2072 2073 #define RK3128_PULL_OFFSET 0x118 2074 2075 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2076 int pin_num, struct regmap **regmap, 2077 int *reg, u8 *bit) 2078 { 2079 struct rockchip_pinctrl_priv *priv = bank->priv; 2080 2081 *regmap = priv->regmap_base; 2082 *reg = RK3128_PULL_OFFSET; 2083 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 2084 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 2085 2086 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 2087 } 2088 2089 #define RK3188_PULL_OFFSET 0x164 2090 #define RK3188_PULL_BITS_PER_PIN 2 2091 #define RK3188_PULL_PINS_PER_REG 8 2092 #define RK3188_PULL_BANK_STRIDE 16 2093 #define RK3188_PULL_PMU_OFFSET 0x64 2094 2095 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2096 int pin_num, struct regmap **regmap, 2097 int *reg, u8 *bit) 2098 { 2099 struct rockchip_pinctrl_priv *priv = bank->priv; 2100 2101 /* The first 12 pins of the first bank are located elsewhere */ 2102 if (bank->bank_num == 0 && pin_num < 12) { 2103 *regmap = priv->regmap_pmu; 2104 *reg = RK3188_PULL_PMU_OFFSET; 2105 2106 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2107 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2108 *bit *= RK3188_PULL_BITS_PER_PIN; 2109 } else { 2110 *regmap = priv->regmap_base; 2111 *reg = RK3188_PULL_OFFSET; 2112 2113 /* correct the offset, as it is the 2nd pull register */ 2114 *reg -= 4; 2115 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2116 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2117 2118 /* 2119 * The bits in these registers have an inverse ordering 2120 * with the lowest pin being in bits 15:14 and the highest 2121 * pin in bits 1:0 2122 */ 2123 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 2124 *bit *= RK3188_PULL_BITS_PER_PIN; 2125 } 2126 } 2127 2128 #define RK3288_PULL_OFFSET 0x140 2129 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2130 int pin_num, struct regmap **regmap, 2131 int *reg, u8 *bit) 2132 { 2133 struct rockchip_pinctrl_priv *priv = bank->priv; 2134 2135 /* The first 24 pins of the first bank are located in PMU */ 2136 if (bank->bank_num == 0) { 2137 *regmap = priv->regmap_pmu; 2138 *reg = RK3188_PULL_PMU_OFFSET; 2139 2140 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2141 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2142 *bit *= RK3188_PULL_BITS_PER_PIN; 2143 } else { 2144 *regmap = priv->regmap_base; 2145 *reg = RK3288_PULL_OFFSET; 2146 2147 /* correct the offset, as we're starting with the 2nd bank */ 2148 *reg -= 0x10; 2149 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2150 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2151 2152 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2153 *bit *= RK3188_PULL_BITS_PER_PIN; 2154 } 2155 } 2156 2157 #define RK3288_DRV_PMU_OFFSET 0x70 2158 #define RK3288_DRV_GRF_OFFSET 0x1c0 2159 #define RK3288_DRV_BITS_PER_PIN 2 2160 #define RK3288_DRV_PINS_PER_REG 8 2161 #define RK3288_DRV_BANK_STRIDE 16 2162 2163 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2164 int pin_num, struct regmap **regmap, 2165 int *reg, u8 *bit) 2166 { 2167 struct rockchip_pinctrl_priv *priv = bank->priv; 2168 2169 /* The first 24 pins of the first bank are located in PMU */ 2170 if (bank->bank_num == 0) { 2171 *regmap = priv->regmap_pmu; 2172 *reg = RK3288_DRV_PMU_OFFSET; 2173 2174 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2175 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2176 *bit *= RK3288_DRV_BITS_PER_PIN; 2177 } else { 2178 *regmap = priv->regmap_base; 2179 *reg = RK3288_DRV_GRF_OFFSET; 2180 2181 /* correct the offset, as we're starting with the 2nd bank */ 2182 *reg -= 0x10; 2183 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2184 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2185 2186 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2187 *bit *= RK3288_DRV_BITS_PER_PIN; 2188 } 2189 } 2190 2191 #define RK3228_PULL_OFFSET 0x100 2192 2193 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2194 int pin_num, struct regmap **regmap, 2195 int *reg, u8 *bit) 2196 { 2197 struct rockchip_pinctrl_priv *priv = bank->priv; 2198 2199 *regmap = priv->regmap_base; 2200 *reg = RK3228_PULL_OFFSET; 2201 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2202 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2203 2204 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2205 *bit *= RK3188_PULL_BITS_PER_PIN; 2206 } 2207 2208 #define RK3228_DRV_GRF_OFFSET 0x200 2209 2210 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2211 int pin_num, struct regmap **regmap, 2212 int *reg, u8 *bit) 2213 { 2214 struct rockchip_pinctrl_priv *priv = bank->priv; 2215 2216 *regmap = priv->regmap_base; 2217 *reg = RK3228_DRV_GRF_OFFSET; 2218 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2219 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2220 2221 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2222 *bit *= RK3288_DRV_BITS_PER_PIN; 2223 } 2224 2225 #define RK3308_PULL_OFFSET 0xa0 2226 2227 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2228 int pin_num, struct regmap **regmap, 2229 int *reg, u8 *bit) 2230 { 2231 struct rockchip_pinctrl_priv *priv = bank->priv; 2232 2233 *regmap = priv->regmap_base; 2234 *reg = RK3308_PULL_OFFSET; 2235 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2236 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2237 2238 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2239 *bit *= RK3188_PULL_BITS_PER_PIN; 2240 } 2241 2242 #define RK3308_DRV_GRF_OFFSET 0x100 2243 2244 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2245 int pin_num, struct regmap **regmap, 2246 int *reg, u8 *bit) 2247 { 2248 struct rockchip_pinctrl_priv *priv = bank->priv; 2249 2250 *regmap = priv->regmap_base; 2251 *reg = RK3308_DRV_GRF_OFFSET; 2252 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2253 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2254 2255 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2256 *bit *= RK3288_DRV_BITS_PER_PIN; 2257 } 2258 2259 #define RK3308_SCHMITT_PINS_PER_REG 8 2260 #define RK3308_SCHMITT_BANK_STRIDE 16 2261 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 2262 2263 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2264 int pin_num, 2265 struct regmap **regmap, 2266 int *reg, u8 *bit) 2267 { 2268 struct rockchip_pinctrl_priv *priv = bank->priv; 2269 2270 *regmap = priv->regmap_base; 2271 *reg = RK3308_SCHMITT_GRF_OFFSET; 2272 2273 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 2274 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 2275 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 2276 2277 return 0; 2278 } 2279 2280 #define RK3368_PULL_GRF_OFFSET 0x100 2281 #define RK3368_PULL_PMU_OFFSET 0x10 2282 2283 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2284 int pin_num, struct regmap **regmap, 2285 int *reg, u8 *bit) 2286 { 2287 struct rockchip_pinctrl_priv *priv = bank->priv; 2288 2289 /* The first 32 pins of the first bank are located in PMU */ 2290 if (bank->bank_num == 0) { 2291 *regmap = priv->regmap_pmu; 2292 *reg = RK3368_PULL_PMU_OFFSET; 2293 2294 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2295 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2296 *bit *= RK3188_PULL_BITS_PER_PIN; 2297 } else { 2298 *regmap = priv->regmap_base; 2299 *reg = RK3368_PULL_GRF_OFFSET; 2300 2301 /* correct the offset, as we're starting with the 2nd bank */ 2302 *reg -= 0x10; 2303 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2304 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2305 2306 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2307 *bit *= RK3188_PULL_BITS_PER_PIN; 2308 } 2309 } 2310 2311 #define RK3368_DRV_PMU_OFFSET 0x20 2312 #define RK3368_DRV_GRF_OFFSET 0x200 2313 2314 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2315 int pin_num, struct regmap **regmap, 2316 int *reg, u8 *bit) 2317 { 2318 struct rockchip_pinctrl_priv *priv = bank->priv; 2319 2320 /* The first 32 pins of the first bank are located in PMU */ 2321 if (bank->bank_num == 0) { 2322 *regmap = priv->regmap_pmu; 2323 *reg = RK3368_DRV_PMU_OFFSET; 2324 2325 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2326 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2327 *bit *= RK3288_DRV_BITS_PER_PIN; 2328 } else { 2329 *regmap = priv->regmap_base; 2330 *reg = RK3368_DRV_GRF_OFFSET; 2331 2332 /* correct the offset, as we're starting with the 2nd bank */ 2333 *reg -= 0x10; 2334 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2335 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2336 2337 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2338 *bit *= RK3288_DRV_BITS_PER_PIN; 2339 } 2340 } 2341 2342 #define RK3399_PULL_GRF_OFFSET 0xe040 2343 #define RK3399_PULL_PMU_OFFSET 0x40 2344 #define RK3399_DRV_3BITS_PER_PIN 3 2345 2346 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2347 int pin_num, struct regmap **regmap, 2348 int *reg, u8 *bit) 2349 { 2350 struct rockchip_pinctrl_priv *priv = bank->priv; 2351 2352 /* The bank0:16 and bank1:32 pins are located in PMU */ 2353 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2354 *regmap = priv->regmap_pmu; 2355 *reg = RK3399_PULL_PMU_OFFSET; 2356 2357 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2358 2359 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2360 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2361 *bit *= RK3188_PULL_BITS_PER_PIN; 2362 } else { 2363 *regmap = priv->regmap_base; 2364 *reg = RK3399_PULL_GRF_OFFSET; 2365 2366 /* correct the offset, as we're starting with the 3rd bank */ 2367 *reg -= 0x20; 2368 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2369 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2370 2371 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2372 *bit *= RK3188_PULL_BITS_PER_PIN; 2373 } 2374 } 2375 2376 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2377 int pin_num, struct regmap **regmap, 2378 int *reg, u8 *bit) 2379 { 2380 struct rockchip_pinctrl_priv *priv = bank->priv; 2381 int drv_num = (pin_num / 8); 2382 2383 /* The bank0:16 and bank1:32 pins are located in PMU */ 2384 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2385 *regmap = priv->regmap_pmu; 2386 else 2387 *regmap = priv->regmap_base; 2388 2389 *reg = bank->drv[drv_num].offset; 2390 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2391 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2392 *bit = (pin_num % 8) * 3; 2393 else 2394 *bit = (pin_num % 8) * 2; 2395 } 2396 2397 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2398 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2399 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2400 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2401 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2402 { 4, 7, 10, 13, 16, 19, 22, 26 } 2403 }; 2404 2405 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2406 int pin_num, int strength) 2407 { 2408 struct rockchip_pinctrl_priv *priv = bank->priv; 2409 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2410 struct regmap *regmap; 2411 int reg, ret, i; 2412 u32 data, rmask_bits, temp; 2413 u8 bit; 2414 /* Where need to clean the special mask for rockchip_perpin_drv_list */ 2415 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); 2416 2417 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 2418 pin_num, strength); 2419 2420 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2421 if (ctrl->type == RV1126) { 2422 rmask_bits = RV1126_DRV_BITS_PER_PIN; 2423 ret = strength; 2424 goto config; 2425 } 2426 2427 ret = -EINVAL; 2428 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2429 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2430 ret = i; 2431 break; 2432 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2433 ret = rockchip_perpin_drv_list[drv_type][i]; 2434 break; 2435 } 2436 } 2437 2438 if (ret < 0) { 2439 debug("unsupported driver strength %d\n", strength); 2440 return ret; 2441 } 2442 2443 switch (drv_type) { 2444 case DRV_TYPE_IO_1V8_3V0_AUTO: 2445 case DRV_TYPE_IO_3V3_ONLY: 2446 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2447 switch (bit) { 2448 case 0 ... 12: 2449 /* regular case, nothing to do */ 2450 break; 2451 case 15: 2452 /* 2453 * drive-strength offset is special, as it is spread 2454 * over 2 registers, the bit data[15] contains bit 0 2455 * of the value while temp[1:0] contains bits 2 and 1 2456 */ 2457 data = (ret & 0x1) << 15; 2458 temp = (ret >> 0x1) & 0x3; 2459 2460 data |= BIT(31); 2461 ret = regmap_write(regmap, reg, data); 2462 if (ret) 2463 return ret; 2464 2465 temp |= (0x3 << 16); 2466 reg += 0x4; 2467 ret = regmap_write(regmap, reg, temp); 2468 2469 return ret; 2470 case 18 ... 21: 2471 /* setting fully enclosed in the second register */ 2472 reg += 4; 2473 bit -= 16; 2474 break; 2475 default: 2476 debug("unsupported bit: %d for pinctrl drive type: %d\n", 2477 bit, drv_type); 2478 return -EINVAL; 2479 } 2480 break; 2481 case DRV_TYPE_IO_DEFAULT: 2482 case DRV_TYPE_IO_1V8_OR_3V0: 2483 case DRV_TYPE_IO_1V8_ONLY: 2484 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2485 break; 2486 default: 2487 debug("unsupported pinctrl drive type: %d\n", 2488 drv_type); 2489 return -EINVAL; 2490 } 2491 2492 config: 2493 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 2494 regmap_read(regmap, reg, &data); 2495 data &= ~(((1 << rmask_bits) - 1) << bit); 2496 } else { 2497 /* enable the write to the equivalent lower bits */ 2498 data = ((1 << rmask_bits) - 1) << (bit + 16); 2499 } 2500 2501 data |= (ret << bit); 2502 ret = regmap_write(regmap, reg, data); 2503 return ret; 2504 } 2505 2506 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2507 { 2508 PIN_CONFIG_BIAS_DISABLE, 2509 PIN_CONFIG_BIAS_PULL_UP, 2510 PIN_CONFIG_BIAS_PULL_DOWN, 2511 PIN_CONFIG_BIAS_BUS_HOLD 2512 }, 2513 { 2514 PIN_CONFIG_BIAS_DISABLE, 2515 PIN_CONFIG_BIAS_PULL_DOWN, 2516 PIN_CONFIG_BIAS_DISABLE, 2517 PIN_CONFIG_BIAS_PULL_UP 2518 }, 2519 }; 2520 2521 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2522 int pin_num, int pull) 2523 { 2524 struct rockchip_pinctrl_priv *priv = bank->priv; 2525 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2526 struct regmap *regmap; 2527 int reg, ret, i, pull_type; 2528 u8 bit; 2529 u32 data; 2530 2531 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 2532 pin_num, pull); 2533 2534 /* rk3066b does support any pulls */ 2535 if (ctrl->type == RK3066B) 2536 return pull ? -EINVAL : 0; 2537 2538 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2539 2540 switch (ctrl->type) { 2541 case RK2928: 2542 case RK3128: 2543 data = BIT(bit + 16); 2544 if (pull == PIN_CONFIG_BIAS_DISABLE) 2545 data |= BIT(bit); 2546 ret = regmap_write(regmap, reg, data); 2547 break; 2548 case PX30: 2549 case RV1108: 2550 case RV1126: 2551 case RK1808: 2552 case RK3188: 2553 case RK3288: 2554 case RK3308: 2555 case RK3368: 2556 case RK3399: 2557 /* 2558 * Where need to clean the special mask for 2559 * rockchip_pull_list. 2560 */ 2561 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); 2562 ret = -EINVAL; 2563 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2564 i++) { 2565 if (rockchip_pull_list[pull_type][i] == pull) { 2566 ret = i; 2567 break; 2568 } 2569 } 2570 2571 if (ret < 0) { 2572 debug("unsupported pull setting %d\n", pull); 2573 return ret; 2574 } 2575 2576 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 2577 regmap_read(regmap, reg, &data); 2578 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); 2579 } else { 2580 /* enable the write to the equivalent lower bits */ 2581 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2582 } 2583 2584 data |= (ret << bit); 2585 ret = regmap_write(regmap, reg, data); 2586 break; 2587 default: 2588 debug("unsupported pinctrl type\n"); 2589 return -EINVAL; 2590 } 2591 2592 return ret; 2593 } 2594 2595 #define RK3328_SCHMITT_BITS_PER_PIN 1 2596 #define RK3328_SCHMITT_PINS_PER_REG 16 2597 #define RK3328_SCHMITT_BANK_STRIDE 8 2598 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2599 2600 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2601 int pin_num, 2602 struct regmap **regmap, 2603 int *reg, u8 *bit) 2604 { 2605 struct rockchip_pinctrl_priv *priv = bank->priv; 2606 2607 *regmap = priv->regmap_base; 2608 *reg = RK3328_SCHMITT_GRF_OFFSET; 2609 2610 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2611 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2612 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2613 2614 return 0; 2615 } 2616 2617 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2618 int pin_num, int enable) 2619 { 2620 struct rockchip_pinctrl_priv *priv = bank->priv; 2621 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2622 struct regmap *regmap; 2623 int reg, ret; 2624 u8 bit; 2625 u32 data; 2626 2627 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 2628 pin_num, enable); 2629 2630 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2631 if (ret) 2632 return ret; 2633 2634 /* enable the write to the equivalent lower bits */ 2635 data = BIT(bit + 16) | (enable << bit); 2636 2637 return regmap_write(regmap, reg, data); 2638 } 2639 2640 #define PX30_SLEW_RATE_PMU_OFFSET 0x30 2641 #define PX30_SLEW_RATE_GRF_OFFSET 0x90 2642 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16 2643 #define PX30_SLEW_RATE_BANK_STRIDE 16 2644 #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8 2645 2646 static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, 2647 int pin_num, 2648 struct regmap **regmap, 2649 int *reg, u8 *bit) 2650 { 2651 struct rockchip_pinctrl_priv *priv = bank->priv; 2652 int pins_per_reg; 2653 2654 if (bank->bank_num == 0) { 2655 *regmap = priv->regmap_pmu; 2656 *reg = PX30_SLEW_RATE_PMU_OFFSET; 2657 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 2658 } else { 2659 *regmap = priv->regmap_base; 2660 *reg = PX30_SCHMITT_GRF_OFFSET; 2661 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 2662 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 2663 } 2664 *reg += ((pin_num / pins_per_reg) * 4); 2665 *bit = pin_num % pins_per_reg; 2666 2667 return 0; 2668 } 2669 2670 static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank, 2671 int pin_num, int speed) 2672 { 2673 struct rockchip_pinctrl_priv *priv = bank->priv; 2674 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2675 struct regmap *regmap; 2676 int reg, ret; 2677 u8 bit; 2678 u32 data; 2679 2680 debug("setting slew rate of GPIO%d-%d to %d\n", bank->bank_num, 2681 pin_num, speed); 2682 2683 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit); 2684 if (ret) 2685 return ret; 2686 2687 /* enable the write to the equivalent lower bits */ 2688 data = BIT(bit + 16) | (speed << bit); 2689 2690 return regmap_write(regmap, reg, data); 2691 } 2692 2693 /* 2694 * Pinconf_ops handling 2695 */ 2696 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2697 unsigned int pull) 2698 { 2699 switch (ctrl->type) { 2700 case RK2928: 2701 case RK3128: 2702 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2703 pull == PIN_CONFIG_BIAS_DISABLE); 2704 case RK3066B: 2705 return pull ? false : true; 2706 case PX30: 2707 case RV1108: 2708 case RV1126: 2709 case RK1808: 2710 case RK3188: 2711 case RK3288: 2712 case RK3308: 2713 case RK3368: 2714 case RK3399: 2715 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2716 } 2717 2718 return false; 2719 } 2720 2721 /* set the pin config settings for a specified pin */ 2722 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 2723 u32 pin, u32 param, u32 arg) 2724 { 2725 struct rockchip_pinctrl_priv *priv = bank->priv; 2726 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2727 int rc; 2728 2729 switch (param) { 2730 case PIN_CONFIG_BIAS_DISABLE: 2731 rc = rockchip_set_pull(bank, pin, param); 2732 if (rc) 2733 return rc; 2734 break; 2735 2736 case PIN_CONFIG_BIAS_PULL_UP: 2737 case PIN_CONFIG_BIAS_PULL_DOWN: 2738 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2739 case PIN_CONFIG_BIAS_BUS_HOLD: 2740 if (!rockchip_pinconf_pull_valid(ctrl, param)) 2741 return -ENOTSUPP; 2742 2743 if (!arg) 2744 return -EINVAL; 2745 2746 rc = rockchip_set_pull(bank, pin, param); 2747 if (rc) 2748 return rc; 2749 break; 2750 2751 case PIN_CONFIG_DRIVE_STRENGTH: 2752 if (!ctrl->drv_calc_reg) 2753 return -ENOTSUPP; 2754 2755 rc = rockchip_set_drive_perpin(bank, pin, arg); 2756 if (rc < 0) 2757 return rc; 2758 break; 2759 2760 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2761 if (!ctrl->schmitt_calc_reg) 2762 return -ENOTSUPP; 2763 2764 rc = rockchip_set_schmitt(bank, pin, arg); 2765 if (rc < 0) 2766 return rc; 2767 break; 2768 2769 case PIN_CONFIG_SLEW_RATE: 2770 if (!ctrl->slew_rate_calc_reg) 2771 return -ENOTSUPP; 2772 2773 rc = rockchip_set_slew_rate(bank, 2774 pin - bank->pin_base, arg); 2775 if (rc < 0) 2776 return rc; 2777 break; 2778 2779 default: 2780 break; 2781 } 2782 2783 return 0; 2784 } 2785 2786 static const struct pinconf_param rockchip_conf_params[] = { 2787 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 2788 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 2789 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 2790 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 2791 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 2792 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 2793 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 2794 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 2795 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 2796 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, 2797 }; 2798 2799 static int rockchip_pinconf_prop_name_to_param(const char *property, 2800 u32 *default_value) 2801 { 2802 const struct pinconf_param *p, *end; 2803 2804 p = rockchip_conf_params; 2805 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 2806 2807 /* See if this pctldev supports this parameter */ 2808 for (; p < end; p++) { 2809 if (!strcmp(property, p->property)) { 2810 *default_value = p->default_value; 2811 return p->param; 2812 } 2813 } 2814 2815 *default_value = 0; 2816 return -EPERM; 2817 } 2818 2819 static int rockchip_pinctrl_set_state(struct udevice *dev, 2820 struct udevice *config) 2821 { 2822 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2823 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2824 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 2825 u32 bank, pin, mux, conf, arg, default_val; 2826 int ret, count, i; 2827 const char *prop_name; 2828 const void *value; 2829 int prop_len, param; 2830 const u32 *data; 2831 ofnode node; 2832 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 2833 const struct device_node *np; 2834 struct property *pp; 2835 #else 2836 int property_offset, pcfg_node; 2837 const void *blob = gd->fdt_blob; 2838 #endif 2839 data = dev_read_prop(config, "rockchip,pins", &count); 2840 if (count < 0) { 2841 debug("%s: bad array size %d\n", __func__, count); 2842 return -EINVAL; 2843 } 2844 2845 count /= sizeof(u32); 2846 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2847 debug("%s: unsupported pins array count %d\n", 2848 __func__, count); 2849 return -EINVAL; 2850 } 2851 2852 for (i = 0; i < count; i++) 2853 cells[i] = fdt32_to_cpu(data[i]); 2854 2855 for (i = 0; i < (count >> 2); i++) { 2856 bank = cells[4 * i + 0]; 2857 pin = cells[4 * i + 1]; 2858 mux = cells[4 * i + 2]; 2859 conf = cells[4 * i + 3]; 2860 2861 ret = rockchip_verify_config(dev, bank, pin); 2862 if (ret) 2863 return ret; 2864 2865 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2866 if (ret) 2867 return ret; 2868 2869 node = ofnode_get_by_phandle(conf); 2870 if (!ofnode_valid(node)) 2871 return -ENODEV; 2872 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 2873 np = ofnode_to_np(node); 2874 for (pp = np->properties; pp; pp = pp->next) { 2875 prop_name = pp->name; 2876 prop_len = pp->length; 2877 value = pp->value; 2878 #else 2879 pcfg_node = ofnode_to_offset(node); 2880 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2881 value = fdt_getprop_by_offset(blob, property_offset, 2882 &prop_name, &prop_len); 2883 if (!value) 2884 return -ENOENT; 2885 #endif 2886 param = rockchip_pinconf_prop_name_to_param(prop_name, 2887 &default_val); 2888 if (param < 0) 2889 break; 2890 2891 if (prop_len >= sizeof(fdt32_t)) 2892 arg = fdt32_to_cpu(*(fdt32_t *)value); 2893 else 2894 arg = default_val; 2895 2896 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2897 param, arg); 2898 if (ret) { 2899 debug("%s: rockchip_pinconf_set fail: %d\n", 2900 __func__, ret); 2901 return ret; 2902 } 2903 } 2904 } 2905 2906 return 0; 2907 } 2908 2909 static struct pinctrl_ops rockchip_pinctrl_ops = { 2910 .set_state = rockchip_pinctrl_set_state, 2911 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2912 }; 2913 2914 /* Ctrl data specially handle */ 2915 static int rk3308b_ctrl_data_re_init(struct rockchip_pin_ctrl *ctrl) 2916 { 2917 /* 2918 * Special for rk3308b, where we need to replace the recalced 2919 * and routed arrays. 2920 */ 2921 if (soc_is_rk3308b()) { 2922 ctrl->iomux_recalced = rk3308b_mux_recalced_data; 2923 ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data); 2924 ctrl->iomux_routes = rk3308b_mux_route_data; 2925 ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data); 2926 } 2927 2928 return 0; 2929 } 2930 2931 /* retrieve the soc specific data */ 2932 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 2933 { 2934 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2935 struct rockchip_pin_ctrl *ctrl = 2936 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 2937 struct rockchip_pin_bank *bank; 2938 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2939 2940 grf_offs = ctrl->grf_mux_offset; 2941 pmu_offs = ctrl->pmu_mux_offset; 2942 drv_pmu_offs = ctrl->pmu_drv_offset; 2943 drv_grf_offs = ctrl->grf_drv_offset; 2944 bank = ctrl->pin_banks; 2945 2946 /* Ctrl data re-initialize for some Socs */ 2947 if (ctrl->ctrl_data_re_init) { 2948 if (ctrl->ctrl_data_re_init(ctrl)) 2949 return NULL; 2950 } 2951 2952 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2953 int bank_pins = 0; 2954 2955 bank->priv = priv; 2956 bank->pin_base = ctrl->nr_pins; 2957 ctrl->nr_pins += bank->nr_pins; 2958 2959 /* calculate iomux and drv offsets */ 2960 for (j = 0; j < 4; j++) { 2961 struct rockchip_iomux *iom = &bank->iomux[j]; 2962 struct rockchip_drv *drv = &bank->drv[j]; 2963 int inc; 2964 2965 if (bank_pins >= bank->nr_pins) 2966 break; 2967 2968 /* preset iomux offset value, set new start value */ 2969 if (iom->offset >= 0) { 2970 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 2971 pmu_offs = iom->offset; 2972 else 2973 grf_offs = iom->offset; 2974 } else { /* set current iomux offset */ 2975 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || 2976 (iom->type & IOMUX_L_SOURCE_PMU)) ? 2977 pmu_offs : grf_offs; 2978 } 2979 2980 /* preset drv offset value, set new start value */ 2981 if (drv->offset >= 0) { 2982 if (iom->type & IOMUX_SOURCE_PMU) 2983 drv_pmu_offs = drv->offset; 2984 else 2985 drv_grf_offs = drv->offset; 2986 } else { /* set current drv offset */ 2987 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2988 drv_pmu_offs : drv_grf_offs; 2989 } 2990 2991 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2992 i, j, iom->offset, drv->offset); 2993 2994 /* 2995 * Increase offset according to iomux width. 2996 * 4bit iomux'es are spread over two registers. 2997 */ 2998 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2999 IOMUX_WIDTH_3BIT | 3000 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 3001 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 3002 pmu_offs += inc; 3003 else 3004 grf_offs += inc; 3005 3006 /* 3007 * Increase offset according to drv width. 3008 * 3bit drive-strenth'es are spread over two registers. 3009 */ 3010 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3011 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3012 inc = 8; 3013 else 3014 inc = 4; 3015 3016 if (iom->type & IOMUX_SOURCE_PMU) 3017 drv_pmu_offs += inc; 3018 else 3019 drv_grf_offs += inc; 3020 3021 bank_pins += 8; 3022 } 3023 3024 /* calculate the per-bank recalced_mask */ 3025 for (j = 0; j < ctrl->niomux_recalced; j++) { 3026 int pin = 0; 3027 3028 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3029 pin = ctrl->iomux_recalced[j].pin; 3030 bank->recalced_mask |= BIT(pin); 3031 } 3032 } 3033 3034 /* calculate the per-bank route_mask */ 3035 for (j = 0; j < ctrl->niomux_routes; j++) { 3036 int pin = 0; 3037 3038 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3039 pin = ctrl->iomux_routes[j].pin; 3040 bank->route_mask |= BIT(pin); 3041 } 3042 } 3043 } 3044 3045 return ctrl; 3046 } 3047 3048 /* SoC data specially handle */ 3049 3050 /* rk3308b SoC data initialize */ 3051 #define RK3308B_GRF_SOC_CON13 0x608 3052 #define RK3308B_GRF_SOC_CON15 0x610 3053 3054 /* RK3308B_GRF_SOC_CON13 */ 3055 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) 3056 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 3057 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 3058 3059 /* RK3308B_GRF_SOC_CON15 */ 3060 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) 3061 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 3062 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 3063 3064 static int rk3308b_soc_data_init(struct rockchip_pinctrl_priv *priv) 3065 { 3066 int ret; 3067 3068 /* 3069 * Enable the special ctrl of selected sources. 3070 */ 3071 if (soc_is_rk3308b()) { 3072 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13, 3073 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | 3074 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | 3075 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); 3076 if (ret) 3077 return ret; 3078 3079 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15, 3080 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | 3081 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | 3082 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); 3083 if (ret) 3084 return ret; 3085 } 3086 3087 return 0; 3088 } 3089 3090 static int rockchip_pinctrl_probe(struct udevice *dev) 3091 { 3092 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 3093 struct rockchip_pin_ctrl *ctrl; 3094 struct udevice *syscon; 3095 struct regmap *regmap; 3096 int ret = 0; 3097 3098 /* get rockchip grf syscon phandle */ 3099 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 3100 &syscon); 3101 if (ret) { 3102 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 3103 return ret; 3104 } 3105 3106 /* get grf-reg base address */ 3107 regmap = syscon_get_regmap(syscon); 3108 if (!regmap) { 3109 debug("unable to find rockchip grf regmap\n"); 3110 return -ENODEV; 3111 } 3112 priv->regmap_base = regmap; 3113 3114 /* option: get pmu-reg base address */ 3115 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 3116 &syscon); 3117 if (!ret) { 3118 /* get pmugrf-reg base address */ 3119 regmap = syscon_get_regmap(syscon); 3120 if (!regmap) { 3121 debug("unable to find rockchip pmu regmap\n"); 3122 return -ENODEV; 3123 } 3124 priv->regmap_pmu = regmap; 3125 } 3126 3127 ctrl = rockchip_pinctrl_get_soc_data(dev); 3128 if (!ctrl) { 3129 debug("driver data not available\n"); 3130 return -EINVAL; 3131 } 3132 3133 /* Special handle for some Socs */ 3134 if (ctrl->soc_data_init) { 3135 ret = ctrl->soc_data_init(priv); 3136 if (ret) 3137 return ret; 3138 } 3139 3140 priv->ctrl = ctrl; 3141 return 0; 3142 } 3143 3144 static struct rockchip_pin_bank px30_pin_banks[] = { 3145 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3146 IOMUX_SOURCE_PMU, 3147 IOMUX_SOURCE_PMU, 3148 IOMUX_SOURCE_PMU 3149 ), 3150 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3151 IOMUX_WIDTH_4BIT, 3152 IOMUX_WIDTH_4BIT, 3153 IOMUX_WIDTH_4BIT 3154 ), 3155 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3156 IOMUX_WIDTH_4BIT, 3157 IOMUX_WIDTH_4BIT, 3158 IOMUX_WIDTH_4BIT 3159 ), 3160 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3161 IOMUX_WIDTH_4BIT, 3162 IOMUX_WIDTH_4BIT, 3163 IOMUX_WIDTH_4BIT 3164 ), 3165 }; 3166 3167 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3168 .pin_banks = px30_pin_banks, 3169 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3170 .label = "PX30-GPIO", 3171 .type = PX30, 3172 .grf_mux_offset = 0x0, 3173 .pmu_mux_offset = 0x0, 3174 .iomux_routes = px30_mux_route_data, 3175 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3176 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3177 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3178 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3179 .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit, 3180 }; 3181 3182 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3183 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3184 IOMUX_SOURCE_PMU, 3185 IOMUX_SOURCE_PMU, 3186 IOMUX_SOURCE_PMU), 3187 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3188 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3189 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3190 }; 3191 3192 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3193 .pin_banks = rv1108_pin_banks, 3194 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3195 .label = "RV1108-GPIO", 3196 .type = RV1108, 3197 .grf_mux_offset = 0x10, 3198 .pmu_mux_offset = 0x0, 3199 .iomux_recalced = rv1108_mux_recalced_data, 3200 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3201 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3202 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3203 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3204 }; 3205 3206 static struct rockchip_pin_bank rv1126_pin_banks[] = { 3207 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3208 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3209 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3210 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 3211 IOMUX_WIDTH_4BIT), 3212 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 3213 IOMUX_WIDTH_4BIT, 3214 IOMUX_WIDTH_4BIT, 3215 IOMUX_WIDTH_4BIT, 3216 IOMUX_WIDTH_4BIT, 3217 0x10010, 0x10018, 0x10020, 0x10028), 3218 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3219 IOMUX_WIDTH_4BIT, 3220 IOMUX_WIDTH_4BIT, 3221 IOMUX_WIDTH_4BIT, 3222 IOMUX_WIDTH_4BIT), 3223 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3224 IOMUX_WIDTH_4BIT, 3225 IOMUX_WIDTH_4BIT, 3226 IOMUX_WIDTH_4BIT, 3227 IOMUX_WIDTH_4BIT), 3228 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 3229 IOMUX_WIDTH_4BIT, 0, 0, 0), 3230 }; 3231 3232 static struct rockchip_pin_ctrl rv1126_pin_ctrl = { 3233 .pin_banks = rv1126_pin_banks, 3234 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 3235 .label = "RV1126-GPIO", 3236 .type = RV1126, 3237 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 3238 .pmu_mux_offset = 0x0, 3239 .iomux_routes = rv1126_mux_route_data, 3240 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), 3241 .iomux_recalced = rv1126_mux_recalced_data, 3242 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 3243 .pull_calc_reg = rv1126_calc_pull_reg_and_bit, 3244 .drv_calc_reg = rv1126_calc_drv_reg_and_bit, 3245 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit, 3246 }; 3247 3248 static struct rockchip_pin_bank rk1808_pin_banks[] = { 3249 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3250 IOMUX_SOURCE_PMU, 3251 IOMUX_SOURCE_PMU, 3252 IOMUX_SOURCE_PMU, 3253 IOMUX_SOURCE_PMU), 3254 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 3255 IOMUX_WIDTH_4BIT, 3256 IOMUX_WIDTH_4BIT, 3257 IOMUX_WIDTH_4BIT, 3258 IOMUX_WIDTH_4BIT), 3259 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3260 IOMUX_WIDTH_4BIT, 3261 IOMUX_WIDTH_4BIT, 3262 IOMUX_WIDTH_4BIT, 3263 IOMUX_WIDTH_4BIT), 3264 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3265 IOMUX_WIDTH_4BIT, 3266 IOMUX_WIDTH_4BIT, 3267 IOMUX_WIDTH_4BIT, 3268 IOMUX_WIDTH_4BIT), 3269 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", 3270 IOMUX_WIDTH_4BIT, 3271 IOMUX_WIDTH_4BIT, 3272 IOMUX_WIDTH_4BIT, 3273 IOMUX_WIDTH_4BIT), 3274 }; 3275 3276 static struct rockchip_pin_ctrl rk1808_pin_ctrl = { 3277 .pin_banks = rk1808_pin_banks, 3278 .nr_banks = ARRAY_SIZE(rk1808_pin_banks), 3279 .label = "RK1808-GPIO", 3280 .type = RK1808, 3281 .iomux_routes = rk1808_mux_route_data, 3282 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data), 3283 .grf_mux_offset = 0x0, 3284 .pmu_mux_offset = 0x0, 3285 .pull_calc_reg = rk1808_calc_pull_reg_and_bit, 3286 .drv_calc_reg = rk1808_calc_drv_reg_and_bit, 3287 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit, 3288 }; 3289 3290 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3291 PIN_BANK(0, 32, "gpio0"), 3292 PIN_BANK(1, 32, "gpio1"), 3293 PIN_BANK(2, 32, "gpio2"), 3294 PIN_BANK(3, 32, "gpio3"), 3295 }; 3296 3297 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3298 .pin_banks = rk2928_pin_banks, 3299 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3300 .label = "RK2928-GPIO", 3301 .type = RK2928, 3302 .grf_mux_offset = 0xa8, 3303 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3304 }; 3305 3306 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3307 PIN_BANK(0, 32, "gpio0"), 3308 PIN_BANK(1, 32, "gpio1"), 3309 PIN_BANK(2, 32, "gpio2"), 3310 }; 3311 3312 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3313 .pin_banks = rk3036_pin_banks, 3314 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3315 .label = "RK3036-GPIO", 3316 .type = RK2928, 3317 .grf_mux_offset = 0xa8, 3318 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3319 }; 3320 3321 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3322 PIN_BANK(0, 32, "gpio0"), 3323 PIN_BANK(1, 32, "gpio1"), 3324 PIN_BANK(2, 32, "gpio2"), 3325 PIN_BANK(3, 32, "gpio3"), 3326 PIN_BANK(4, 32, "gpio4"), 3327 PIN_BANK(6, 16, "gpio6"), 3328 }; 3329 3330 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3331 .pin_banks = rk3066a_pin_banks, 3332 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3333 .label = "RK3066a-GPIO", 3334 .type = RK2928, 3335 .grf_mux_offset = 0xa8, 3336 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3337 }; 3338 3339 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3340 PIN_BANK(0, 32, "gpio0"), 3341 PIN_BANK(1, 32, "gpio1"), 3342 PIN_BANK(2, 32, "gpio2"), 3343 PIN_BANK(3, 32, "gpio3"), 3344 }; 3345 3346 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3347 .pin_banks = rk3066b_pin_banks, 3348 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3349 .label = "RK3066b-GPIO", 3350 .type = RK3066B, 3351 .grf_mux_offset = 0x60, 3352 }; 3353 3354 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3355 PIN_BANK(0, 32, "gpio0"), 3356 PIN_BANK(1, 32, "gpio1"), 3357 PIN_BANK(2, 32, "gpio2"), 3358 PIN_BANK(3, 32, "gpio3"), 3359 }; 3360 3361 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3362 .pin_banks = rk3128_pin_banks, 3363 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3364 .label = "RK3128-GPIO", 3365 .type = RK3128, 3366 .grf_mux_offset = 0xa8, 3367 .iomux_recalced = rk3128_mux_recalced_data, 3368 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3369 .iomux_routes = rk3128_mux_route_data, 3370 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3371 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3372 }; 3373 3374 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3375 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3376 PIN_BANK(1, 32, "gpio1"), 3377 PIN_BANK(2, 32, "gpio2"), 3378 PIN_BANK(3, 32, "gpio3"), 3379 }; 3380 3381 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3382 .pin_banks = rk3188_pin_banks, 3383 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3384 .label = "RK3188-GPIO", 3385 .type = RK3188, 3386 .grf_mux_offset = 0x60, 3387 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3388 }; 3389 3390 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3391 PIN_BANK(0, 32, "gpio0"), 3392 PIN_BANK(1, 32, "gpio1"), 3393 PIN_BANK(2, 32, "gpio2"), 3394 PIN_BANK(3, 32, "gpio3"), 3395 }; 3396 3397 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3398 .pin_banks = rk3228_pin_banks, 3399 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3400 .label = "RK3228-GPIO", 3401 .type = RK3288, 3402 .grf_mux_offset = 0x0, 3403 .iomux_routes = rk3228_mux_route_data, 3404 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3405 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3406 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3407 }; 3408 3409 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3410 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 3411 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3412 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3413 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3414 IOMUX_UNROUTED, 3415 DRV_TYPE_WRITABLE_32BIT, 3416 DRV_TYPE_WRITABLE_32BIT, 3417 DRV_TYPE_WRITABLE_32BIT, 3418 0, 3419 PULL_TYPE_WRITABLE_32BIT, 3420 PULL_TYPE_WRITABLE_32BIT, 3421 PULL_TYPE_WRITABLE_32BIT, 3422 0 3423 ), 3424 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3425 IOMUX_UNROUTED, 3426 IOMUX_UNROUTED, 3427 0 3428 ), 3429 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3430 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3431 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3432 IOMUX_WIDTH_4BIT, 3433 0, 3434 0 3435 ), 3436 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3437 0, 3438 0, 3439 IOMUX_UNROUTED 3440 ), 3441 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3442 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3443 0, 3444 IOMUX_WIDTH_4BIT, 3445 IOMUX_UNROUTED 3446 ), 3447 PIN_BANK(8, 16, "gpio8"), 3448 }; 3449 3450 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3451 .pin_banks = rk3288_pin_banks, 3452 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3453 .label = "RK3288-GPIO", 3454 .type = RK3288, 3455 .grf_mux_offset = 0x0, 3456 .pmu_mux_offset = 0x84, 3457 .iomux_routes = rk3288_mux_route_data, 3458 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3459 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3460 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3461 }; 3462 3463 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3464 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 3465 IOMUX_8WIDTH_2BIT, 3466 IOMUX_8WIDTH_2BIT, 3467 IOMUX_8WIDTH_2BIT), 3468 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 3469 IOMUX_8WIDTH_2BIT, 3470 IOMUX_8WIDTH_2BIT, 3471 IOMUX_8WIDTH_2BIT), 3472 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 3473 IOMUX_8WIDTH_2BIT, 3474 IOMUX_8WIDTH_2BIT, 3475 IOMUX_8WIDTH_2BIT), 3476 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 3477 IOMUX_8WIDTH_2BIT, 3478 IOMUX_8WIDTH_2BIT, 3479 IOMUX_8WIDTH_2BIT), 3480 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 3481 IOMUX_8WIDTH_2BIT, 3482 IOMUX_8WIDTH_2BIT, 3483 IOMUX_8WIDTH_2BIT), 3484 }; 3485 3486 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3487 .pin_banks = rk3308_pin_banks, 3488 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3489 .label = "RK3308-GPIO", 3490 .type = RK3308, 3491 .grf_mux_offset = 0x0, 3492 .iomux_recalced = rk3308_mux_recalced_data, 3493 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3494 .iomux_routes = rk3308_mux_route_data, 3495 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3496 .ctrl_data_re_init = rk3308b_ctrl_data_re_init, 3497 .soc_data_init = rk3308b_soc_data_init, 3498 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3499 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3500 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3501 }; 3502 3503 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3504 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3505 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3506 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3507 IOMUX_WIDTH_3BIT, 3508 IOMUX_WIDTH_3BIT, 3509 0), 3510 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3511 IOMUX_WIDTH_3BIT, 3512 IOMUX_WIDTH_3BIT, 3513 0, 3514 0), 3515 }; 3516 3517 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3518 .pin_banks = rk3328_pin_banks, 3519 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3520 .label = "RK3328-GPIO", 3521 .type = RK3288, 3522 .grf_mux_offset = 0x0, 3523 .iomux_recalced = rk3328_mux_recalced_data, 3524 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3525 .iomux_routes = rk3328_mux_route_data, 3526 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3527 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3528 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3529 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3530 }; 3531 3532 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3533 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3534 IOMUX_SOURCE_PMU, 3535 IOMUX_SOURCE_PMU, 3536 IOMUX_SOURCE_PMU 3537 ), 3538 PIN_BANK(1, 32, "gpio1"), 3539 PIN_BANK(2, 32, "gpio2"), 3540 PIN_BANK(3, 32, "gpio3"), 3541 }; 3542 3543 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3544 .pin_banks = rk3368_pin_banks, 3545 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3546 .label = "RK3368-GPIO", 3547 .type = RK3368, 3548 .grf_mux_offset = 0x0, 3549 .pmu_mux_offset = 0x0, 3550 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3551 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3552 }; 3553 3554 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3555 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3556 IOMUX_SOURCE_PMU, 3557 IOMUX_SOURCE_PMU, 3558 IOMUX_SOURCE_PMU, 3559 IOMUX_SOURCE_PMU, 3560 DRV_TYPE_IO_1V8_ONLY, 3561 DRV_TYPE_IO_1V8_ONLY, 3562 DRV_TYPE_IO_DEFAULT, 3563 DRV_TYPE_IO_DEFAULT, 3564 0x80, 3565 0x88, 3566 -1, 3567 -1, 3568 PULL_TYPE_IO_1V8_ONLY, 3569 PULL_TYPE_IO_1V8_ONLY, 3570 PULL_TYPE_IO_DEFAULT, 3571 PULL_TYPE_IO_DEFAULT 3572 ), 3573 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3574 IOMUX_SOURCE_PMU, 3575 IOMUX_SOURCE_PMU, 3576 IOMUX_SOURCE_PMU, 3577 DRV_TYPE_IO_1V8_OR_3V0, 3578 DRV_TYPE_IO_1V8_OR_3V0, 3579 DRV_TYPE_IO_1V8_OR_3V0, 3580 DRV_TYPE_IO_1V8_OR_3V0, 3581 0xa0, 3582 0xa8, 3583 0xb0, 3584 0xb8 3585 ), 3586 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3587 DRV_TYPE_IO_1V8_OR_3V0, 3588 DRV_TYPE_IO_1V8_ONLY, 3589 DRV_TYPE_IO_1V8_ONLY, 3590 PULL_TYPE_IO_DEFAULT, 3591 PULL_TYPE_IO_DEFAULT, 3592 PULL_TYPE_IO_1V8_ONLY, 3593 PULL_TYPE_IO_1V8_ONLY 3594 ), 3595 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3596 DRV_TYPE_IO_3V3_ONLY, 3597 DRV_TYPE_IO_3V3_ONLY, 3598 DRV_TYPE_IO_1V8_OR_3V0 3599 ), 3600 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3601 DRV_TYPE_IO_1V8_3V0_AUTO, 3602 DRV_TYPE_IO_1V8_OR_3V0, 3603 DRV_TYPE_IO_1V8_OR_3V0 3604 ), 3605 }; 3606 3607 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3608 .pin_banks = rk3399_pin_banks, 3609 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3610 .label = "RK3399-GPIO", 3611 .type = RK3399, 3612 .grf_mux_offset = 0xe000, 3613 .pmu_mux_offset = 0x0, 3614 .grf_drv_offset = 0xe100, 3615 .pmu_drv_offset = 0x80, 3616 .iomux_routes = rk3399_mux_route_data, 3617 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3618 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3619 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3620 }; 3621 3622 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 3623 { .compatible = "rockchip,px30-pinctrl", 3624 .data = (ulong)&px30_pin_ctrl }, 3625 { .compatible = "rockchip,rv1108-pinctrl", 3626 .data = (ulong)&rv1108_pin_ctrl }, 3627 { .compatible = "rockchip,rv1126-pinctrl", 3628 .data = (ulong)&rv1126_pin_ctrl }, 3629 { .compatible = "rockchip,rk1808-pinctrl", 3630 .data = (ulong)&rk1808_pin_ctrl }, 3631 { .compatible = "rockchip,rk2928-pinctrl", 3632 .data = (ulong)&rk2928_pin_ctrl }, 3633 { .compatible = "rockchip,rk3036-pinctrl", 3634 .data = (ulong)&rk3036_pin_ctrl }, 3635 { .compatible = "rockchip,rk3066a-pinctrl", 3636 .data = (ulong)&rk3066a_pin_ctrl }, 3637 { .compatible = "rockchip,rk3066b-pinctrl", 3638 .data = (ulong)&rk3066b_pin_ctrl }, 3639 { .compatible = "rockchip,rk3128-pinctrl", 3640 .data = (ulong)&rk3128_pin_ctrl }, 3641 { .compatible = "rockchip,rk3188-pinctrl", 3642 .data = (ulong)&rk3188_pin_ctrl }, 3643 { .compatible = "rockchip,rk3228-pinctrl", 3644 .data = (ulong)&rk3228_pin_ctrl }, 3645 { .compatible = "rockchip,rk3288-pinctrl", 3646 .data = (ulong)&rk3288_pin_ctrl }, 3647 { .compatible = "rockchip,rk3308-pinctrl", 3648 .data = (ulong)&rk3308_pin_ctrl }, 3649 { .compatible = "rockchip,rk3328-pinctrl", 3650 .data = (ulong)&rk3328_pin_ctrl }, 3651 { .compatible = "rockchip,rk3368-pinctrl", 3652 .data = (ulong)&rk3368_pin_ctrl }, 3653 { .compatible = "rockchip,rk3399-pinctrl", 3654 .data = (ulong)&rk3399_pin_ctrl }, 3655 {}, 3656 }; 3657 3658 U_BOOT_DRIVER(pinctrl_rockchip) = { 3659 .name = "rockchip_pinctrl", 3660 .id = UCLASS_PINCTRL, 3661 .of_match = rockchip_pinctrl_dt_match, 3662 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 3663 .ops = &rockchip_pinctrl_ops, 3664 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 3665 .bind = dm_scan_fdt_dev, 3666 #endif 3667 .probe = rockchip_pinctrl_probe, 3668 }; 3669