1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <linux/bitops.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/arch/cpu.h> 15 #include <dt-bindings/pinctrl/rockchip.h> 16 17 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 18 #define RK_FUNC_GPIO 0 19 #define MAX_ROCKCHIP_PINS_ENTRIES 30 20 21 enum rockchip_pinctrl_type { 22 PX30, 23 RV1108, 24 RV1126, 25 RK1808, 26 RK2928, 27 RK3066B, 28 RK3128, 29 RK3188, 30 RK3288, 31 RK3308, 32 RK3368, 33 RK3399, 34 }; 35 36 #define RK_GENMASK_VAL(h, l, v) \ 37 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 38 39 /** 40 * Encode variants of iomux registers into a type variable 41 */ 42 #define IOMUX_GPIO_ONLY BIT(0) 43 #define IOMUX_WIDTH_4BIT BIT(1) 44 #define IOMUX_SOURCE_PMU BIT(2) 45 #define IOMUX_UNROUTED BIT(3) 46 #define IOMUX_WIDTH_3BIT BIT(4) 47 #define IOMUX_8WIDTH_2BIT BIT(5) 48 #define IOMUX_WRITABLE_32BIT BIT(6) 49 #define IOMUX_L_SOURCE_PMU BIT(7) 50 51 /** 52 * @type: iomux variant using IOMUX_* constants 53 * @offset: if initialized to -1 it will be autocalculated, by specifying 54 * an initial offset value the relevant source offset can be reset 55 * to a new value for autocalculating the following iomux registers. 56 */ 57 struct rockchip_iomux { 58 int type; 59 int offset; 60 }; 61 62 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 63 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 64 65 /** 66 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 67 */ 68 enum rockchip_pin_drv_type { 69 DRV_TYPE_IO_DEFAULT = 0, 70 DRV_TYPE_IO_1V8_OR_3V0, 71 DRV_TYPE_IO_1V8_ONLY, 72 DRV_TYPE_IO_1V8_3V0_AUTO, 73 DRV_TYPE_IO_3V3_ONLY, 74 DRV_TYPE_MAX 75 }; 76 77 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 78 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 79 80 /** 81 * enum type index corresponding to rockchip_pull_list arrays index. 82 */ 83 enum rockchip_pin_pull_type { 84 PULL_TYPE_IO_DEFAULT = 0, 85 PULL_TYPE_IO_1V8_ONLY, 86 PULL_TYPE_MAX 87 }; 88 89 /** 90 * enum mux route register type, should be invalid/default/topgrf/pmugrf. 91 * INVALID: means do not need to set mux route 92 * DEFAULT: means same regmap as pin iomux 93 * TOPGRF: means mux route setting in topgrf 94 * PMUGRF: means mux route setting in pmugrf 95 */ 96 enum rockchip_pin_route_type { 97 ROUTE_TYPE_DEFAULT = 0, 98 ROUTE_TYPE_TOPGRF = 1, 99 ROUTE_TYPE_PMUGRF = 2, 100 101 ROUTE_TYPE_INVALID = -1, 102 }; 103 104 /** 105 * @drv_type: drive strength variant using rockchip_perpin_drv_type 106 * @offset: if initialized to -1 it will be autocalculated, by specifying 107 * an initial offset value the relevant source offset can be reset 108 * to a new value for autocalculating the following drive strength 109 * registers. if used chips own cal_drv func instead to calculate 110 * registers offset, the variant could be ignored. 111 */ 112 struct rockchip_drv { 113 enum rockchip_pin_drv_type drv_type; 114 int offset; 115 }; 116 117 /** 118 * @priv: common pinctrl private basedata 119 * @pin_base: first pin number 120 * @nr_pins: number of pins in this bank 121 * @name: name of the bank 122 * @bank_num: number of the bank, to account for holes 123 * @iomux: array describing the 4 iomux sources of the bank 124 * @drv: array describing the 4 drive strength sources of the bank 125 * @pull_type: array describing the 4 pull type sources of the bank 126 * @recalced_mask: bits describing the mux recalced pins of per bank 127 * @route_mask: bits describing the routing pins of per bank 128 */ 129 struct rockchip_pin_bank { 130 struct rockchip_pinctrl_priv *priv; 131 u32 pin_base; 132 u8 nr_pins; 133 char *name; 134 u8 bank_num; 135 struct rockchip_iomux iomux[4]; 136 struct rockchip_drv drv[4]; 137 enum rockchip_pin_pull_type pull_type[4]; 138 u32 recalced_mask; 139 u32 route_mask; 140 }; 141 142 #define PIN_BANK(id, pins, label) \ 143 { \ 144 .bank_num = id, \ 145 .nr_pins = pins, \ 146 .name = label, \ 147 .iomux = { \ 148 { .offset = -1 }, \ 149 { .offset = -1 }, \ 150 { .offset = -1 }, \ 151 { .offset = -1 }, \ 152 }, \ 153 } 154 155 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 156 { \ 157 .bank_num = id, \ 158 .nr_pins = pins, \ 159 .name = label, \ 160 .iomux = { \ 161 { .type = iom0, .offset = -1 }, \ 162 { .type = iom1, .offset = -1 }, \ 163 { .type = iom2, .offset = -1 }, \ 164 { .type = iom3, .offset = -1 }, \ 165 }, \ 166 } 167 168 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ 169 iom3, offset0, offset1, offset2, \ 170 offset3) \ 171 { \ 172 .bank_num = id, \ 173 .nr_pins = pins, \ 174 .name = label, \ 175 .iomux = { \ 176 { .type = iom0, .offset = offset0 }, \ 177 { .type = iom1, .offset = offset1 }, \ 178 { .type = iom2, .offset = offset2 }, \ 179 { .type = iom3, .offset = offset3 }, \ 180 }, \ 181 } 182 183 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 184 { \ 185 .bank_num = id, \ 186 .nr_pins = pins, \ 187 .name = label, \ 188 .iomux = { \ 189 { .offset = -1 }, \ 190 { .offset = -1 }, \ 191 { .offset = -1 }, \ 192 { .offset = -1 }, \ 193 }, \ 194 .drv = { \ 195 { .drv_type = type0, .offset = -1 }, \ 196 { .drv_type = type1, .offset = -1 }, \ 197 { .drv_type = type2, .offset = -1 }, \ 198 { .drv_type = type3, .offset = -1 }, \ 199 }, \ 200 } 201 202 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 203 drv2, drv3, pull0, pull1, \ 204 pull2, pull3) \ 205 { \ 206 .bank_num = id, \ 207 .nr_pins = pins, \ 208 .name = label, \ 209 .iomux = { \ 210 { .offset = -1 }, \ 211 { .offset = -1 }, \ 212 { .offset = -1 }, \ 213 { .offset = -1 }, \ 214 }, \ 215 .drv = { \ 216 { .drv_type = drv0, .offset = -1 }, \ 217 { .drv_type = drv1, .offset = -1 }, \ 218 { .drv_type = drv2, .offset = -1 }, \ 219 { .drv_type = drv3, .offset = -1 }, \ 220 }, \ 221 .pull_type[0] = pull0, \ 222 .pull_type[1] = pull1, \ 223 .pull_type[2] = pull2, \ 224 .pull_type[3] = pull3, \ 225 } 226 227 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 228 iom2, iom3, drv0, drv1, drv2, \ 229 drv3, offset0, offset1, \ 230 offset2, offset3) \ 231 { \ 232 .bank_num = id, \ 233 .nr_pins = pins, \ 234 .name = label, \ 235 .iomux = { \ 236 { .type = iom0, .offset = -1 }, \ 237 { .type = iom1, .offset = -1 }, \ 238 { .type = iom2, .offset = -1 }, \ 239 { .type = iom3, .offset = -1 }, \ 240 }, \ 241 .drv = { \ 242 { .drv_type = drv0, .offset = offset0 }, \ 243 { .drv_type = drv1, .offset = offset1 }, \ 244 { .drv_type = drv2, .offset = offset2 }, \ 245 { .drv_type = drv3, .offset = offset3 }, \ 246 }, \ 247 } 248 249 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 250 iom2, iom3, drv0, drv1, drv2, \ 251 drv3, pull0, pull1, pull2, \ 252 pull3) \ 253 { \ 254 .bank_num = id, \ 255 .nr_pins = pins, \ 256 .name = label, \ 257 .iomux = { \ 258 { .type = iom0, .offset = -1 }, \ 259 { .type = iom1, .offset = -1 }, \ 260 { .type = iom2, .offset = -1 }, \ 261 { .type = iom3, .offset = -1 }, \ 262 }, \ 263 .drv = { \ 264 { .drv_type = drv0, .offset = -1 }, \ 265 { .drv_type = drv1, .offset = -1 }, \ 266 { .drv_type = drv2, .offset = -1 }, \ 267 { .drv_type = drv3, .offset = -1 }, \ 268 }, \ 269 .pull_type[0] = pull0, \ 270 .pull_type[1] = pull1, \ 271 .pull_type[2] = pull2, \ 272 .pull_type[3] = pull3, \ 273 } 274 275 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 276 label, iom0, iom1, iom2, \ 277 iom3, drv0, drv1, drv2, \ 278 drv3, offset0, offset1, \ 279 offset2, offset3, pull0, \ 280 pull1, pull2, pull3) \ 281 { \ 282 .bank_num = id, \ 283 .nr_pins = pins, \ 284 .name = label, \ 285 .iomux = { \ 286 { .type = iom0, .offset = -1 }, \ 287 { .type = iom1, .offset = -1 }, \ 288 { .type = iom2, .offset = -1 }, \ 289 { .type = iom3, .offset = -1 }, \ 290 }, \ 291 .drv = { \ 292 { .drv_type = drv0, .offset = offset0 }, \ 293 { .drv_type = drv1, .offset = offset1 }, \ 294 { .drv_type = drv2, .offset = offset2 }, \ 295 { .drv_type = drv3, .offset = offset3 }, \ 296 }, \ 297 .pull_type[0] = pull0, \ 298 .pull_type[1] = pull1, \ 299 .pull_type[2] = pull2, \ 300 .pull_type[3] = pull3, \ 301 } 302 303 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 304 { \ 305 .bank_num = ID, \ 306 .pin = PIN, \ 307 .func = FUNC, \ 308 .route_offset = REG, \ 309 .route_val = VAL, \ 310 .route_type = FLAG, \ 311 } 312 313 #define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ 314 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT) 315 316 #define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ 317 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF) 318 319 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ 320 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF) 321 322 /** 323 * struct rockchip_mux_recalced_data: represent a pin iomux data. 324 * @num: bank number. 325 * @pin: pin number. 326 * @bit: index at register. 327 * @reg: register offset. 328 * @mask: mask bit 329 */ 330 struct rockchip_mux_recalced_data { 331 u8 num; 332 u8 pin; 333 u32 reg; 334 u8 bit; 335 u8 mask; 336 }; 337 338 /** 339 * struct rockchip_mux_recalced_data: represent a pin iomux data. 340 * @bank_num: bank number. 341 * @pin: index at register or used to calc index. 342 * @func: the min pin. 343 * @route_type: the register type. 344 * @route_offset: the max pin. 345 * @route_val: the register offset. 346 */ 347 struct rockchip_mux_route_data { 348 u8 bank_num; 349 u8 pin; 350 u8 func; 351 enum rockchip_pin_route_type route_type : 8; 352 u32 route_offset; 353 u32 route_val; 354 }; 355 356 /** 357 */ 358 struct rockchip_pin_ctrl { 359 struct rockchip_pin_bank *pin_banks; 360 u32 nr_banks; 361 u32 nr_pins; 362 char *label; 363 enum rockchip_pinctrl_type type; 364 int grf_mux_offset; 365 int pmu_mux_offset; 366 int grf_drv_offset; 367 int pmu_drv_offset; 368 struct rockchip_mux_recalced_data *iomux_recalced; 369 u32 niomux_recalced; 370 struct rockchip_mux_route_data *iomux_routes; 371 u32 niomux_routes; 372 373 int (*ctrl_data_re_init)(const struct rockchip_pin_ctrl *ctrl); 374 375 int (*soc_data_init)(struct rockchip_pinctrl_priv *info); 376 377 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 378 int pin_num, struct regmap **regmap, 379 int *reg, u8 *bit); 380 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 381 int pin_num, struct regmap **regmap, 382 int *reg, u8 *bit); 383 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 384 int pin_num, struct regmap **regmap, 385 int *reg, u8 *bit); 386 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank, 387 int pin_num, struct regmap **regmap, 388 int *reg, u8 *bit); 389 }; 390 391 /** 392 */ 393 struct rockchip_pinctrl_priv { 394 struct rockchip_pin_ctrl *ctrl; 395 struct regmap *regmap_base; 396 struct regmap *regmap_pmu; 397 398 }; 399 400 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 401 { 402 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 403 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 404 405 if (bank >= ctrl->nr_banks) { 406 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 407 return -EINVAL; 408 } 409 410 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 411 debug("pin conf pin %d >= %d\n", pin, 412 MAX_ROCKCHIP_GPIO_PER_BANK); 413 return -EINVAL; 414 } 415 416 return 0; 417 } 418 419 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 420 { 421 .num = 1, 422 .pin = 0, 423 .reg = 0x418, 424 .bit = 0, 425 .mask = 0x3 426 }, { 427 .num = 1, 428 .pin = 1, 429 .reg = 0x418, 430 .bit = 2, 431 .mask = 0x3 432 }, { 433 .num = 1, 434 .pin = 2, 435 .reg = 0x418, 436 .bit = 4, 437 .mask = 0x3 438 }, { 439 .num = 1, 440 .pin = 3, 441 .reg = 0x418, 442 .bit = 6, 443 .mask = 0x3 444 }, { 445 .num = 1, 446 .pin = 4, 447 .reg = 0x418, 448 .bit = 8, 449 .mask = 0x3 450 }, { 451 .num = 1, 452 .pin = 5, 453 .reg = 0x418, 454 .bit = 10, 455 .mask = 0x3 456 }, { 457 .num = 1, 458 .pin = 6, 459 .reg = 0x418, 460 .bit = 12, 461 .mask = 0x3 462 }, { 463 .num = 1, 464 .pin = 7, 465 .reg = 0x418, 466 .bit = 14, 467 .mask = 0x3 468 }, { 469 .num = 1, 470 .pin = 8, 471 .reg = 0x41c, 472 .bit = 0, 473 .mask = 0x3 474 }, { 475 .num = 1, 476 .pin = 9, 477 .reg = 0x41c, 478 .bit = 2, 479 .mask = 0x3 480 }, 481 }; 482 483 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 484 { 485 .num = 0, 486 .pin = 20, 487 .reg = 0x10000, 488 .bit = 0, 489 .mask = 0xf 490 }, 491 { 492 .num = 0, 493 .pin = 21, 494 .reg = 0x10000, 495 .bit = 4, 496 .mask = 0xf 497 }, 498 { 499 .num = 0, 500 .pin = 22, 501 .reg = 0x10000, 502 .bit = 8, 503 .mask = 0xf 504 }, 505 { 506 .num = 0, 507 .pin = 23, 508 .reg = 0x10000, 509 .bit = 12, 510 .mask = 0xf 511 }, 512 }; 513 514 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 515 { 516 .num = 2, 517 .pin = 20, 518 .reg = 0xe8, 519 .bit = 0, 520 .mask = 0x7 521 }, { 522 .num = 2, 523 .pin = 21, 524 .reg = 0xe8, 525 .bit = 4, 526 .mask = 0x7 527 }, { 528 .num = 2, 529 .pin = 22, 530 .reg = 0xe8, 531 .bit = 8, 532 .mask = 0x7 533 }, { 534 .num = 2, 535 .pin = 23, 536 .reg = 0xe8, 537 .bit = 12, 538 .mask = 0x7 539 }, { 540 .num = 2, 541 .pin = 24, 542 .reg = 0xd4, 543 .bit = 12, 544 .mask = 0x7 545 }, 546 }; 547 548 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 549 { 550 .num = 1, 551 .pin = 14, 552 .reg = 0x28, 553 .bit = 12, 554 .mask = 0x7 555 }, { 556 .num = 1, 557 .pin = 15, 558 .reg = 0x2c, 559 .bit = 0, 560 .mask = 0x3 561 }, { 562 .num = 1, 563 .pin = 18, 564 .reg = 0x30, 565 .bit = 4, 566 .mask = 0x7 567 }, { 568 .num = 1, 569 .pin = 19, 570 .reg = 0x30, 571 .bit = 8, 572 .mask = 0x7 573 }, { 574 .num = 1, 575 .pin = 20, 576 .reg = 0x30, 577 .bit = 12, 578 .mask = 0x7 579 }, { 580 .num = 1, 581 .pin = 21, 582 .reg = 0x34, 583 .bit = 0, 584 .mask = 0x7 585 }, { 586 .num = 1, 587 .pin = 22, 588 .reg = 0x34, 589 .bit = 4, 590 .mask = 0x7 591 }, { 592 .num = 1, 593 .pin = 23, 594 .reg = 0x34, 595 .bit = 8, 596 .mask = 0x7 597 }, { 598 .num = 3, 599 .pin = 12, 600 .reg = 0x68, 601 .bit = 8, 602 .mask = 0x7 603 }, { 604 .num = 3, 605 .pin = 13, 606 .reg = 0x68, 607 .bit = 12, 608 .mask = 0x7 609 }, 610 }; 611 612 static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { 613 { 614 .num = 1, 615 .pin = 14, 616 .reg = 0x28, 617 .bit = 12, 618 .mask = 0xf 619 }, { 620 .num = 1, 621 .pin = 15, 622 .reg = 0x2c, 623 .bit = 0, 624 .mask = 0x3 625 }, { 626 .num = 1, 627 .pin = 18, 628 .reg = 0x30, 629 .bit = 4, 630 .mask = 0xf 631 }, { 632 .num = 1, 633 .pin = 19, 634 .reg = 0x30, 635 .bit = 8, 636 .mask = 0xf 637 }, { 638 .num = 1, 639 .pin = 20, 640 .reg = 0x30, 641 .bit = 12, 642 .mask = 0xf 643 }, { 644 .num = 1, 645 .pin = 21, 646 .reg = 0x34, 647 .bit = 0, 648 .mask = 0xf 649 }, { 650 .num = 1, 651 .pin = 22, 652 .reg = 0x34, 653 .bit = 4, 654 .mask = 0xf 655 }, { 656 .num = 1, 657 .pin = 23, 658 .reg = 0x34, 659 .bit = 8, 660 .mask = 0xf 661 }, { 662 .num = 3, 663 .pin = 12, 664 .reg = 0x68, 665 .bit = 8, 666 .mask = 0xf 667 }, { 668 .num = 3, 669 .pin = 13, 670 .reg = 0x68, 671 .bit = 12, 672 .mask = 0xf 673 }, { 674 .num = 2, 675 .pin = 2, 676 .reg = 0x608, 677 .bit = 0, 678 .mask = 0x7 679 }, { 680 .num = 2, 681 .pin = 3, 682 .reg = 0x608, 683 .bit = 4, 684 .mask = 0x7 685 }, { 686 .num = 2, 687 .pin = 16, 688 .reg = 0x610, 689 .bit = 8, 690 .mask = 0x7 691 }, { 692 .num = 3, 693 .pin = 10, 694 .reg = 0x610, 695 .bit = 0, 696 .mask = 0x7 697 }, { 698 .num = 3, 699 .pin = 11, 700 .reg = 0x610, 701 .bit = 4, 702 .mask = 0x7 703 }, 704 }; 705 706 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 707 { 708 .num = 2, 709 .pin = 12, 710 .reg = 0x24, 711 .bit = 8, 712 .mask = 0x3 713 }, { 714 .num = 2, 715 .pin = 15, 716 .reg = 0x28, 717 .bit = 0, 718 .mask = 0x7 719 }, { 720 .num = 2, 721 .pin = 23, 722 .reg = 0x30, 723 .bit = 14, 724 .mask = 0x3 725 }, 726 }; 727 728 static struct rockchip_mux_route_data rv1126_mux_route_data[] = { 729 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ 730 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ 731 732 MR_TOPGRF(RK_GPIO0, RK_PD4, RK_FUNC_4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ 733 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ 734 MR_TOPGRF(RK_GPIO2, RK_PC7, RK_FUNC_6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ 735 736 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ 737 MR_TOPGRF(RK_GPIO2, RK_PB3, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ 738 739 MR_TOPGRF(RK_GPIO3, RK_PD4, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ 740 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ 741 742 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ 743 MR_TOPGRF(RK_GPIO2, RK_PD1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ 744 745 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ 746 MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ 747 MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ 748 749 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ 750 MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ 751 752 MR_TOPGRF(RK_GPIO2, RK_PA5, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ 753 MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ 754 MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ 755 756 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ 757 MR_TOPGRF(RK_GPIO1, RK_PC6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ 758 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ 759 760 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ 761 MR_TOPGRF(RK_GPIO2, RK_PB7, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ 762 763 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ 764 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ 765 766 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */ 767 MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */ 768 769 MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */ 770 MR_TOPGRF(RK_GPIO2, RK_PD6, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */ 771 772 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */ 773 MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */ 774 775 MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ 776 MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ 777 778 MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ 779 MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ 780 781 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ 782 MR_TOPGRF(RK_GPIO1, RK_PA7, RK_FUNC_2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ 783 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ 784 785 MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ 786 MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ 787 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ 788 789 MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ 790 MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ 791 MR_TOPGRF(RK_GPIO2, RK_PA0, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ 792 793 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */ 794 MR_PMUGRF(RK_GPIO2, RK_PB3, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */ 795 796 MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */ 797 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */ 798 799 MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */ 800 MR_PMUGRF(RK_GPIO2, RK_PB1, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */ 801 802 MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ 803 MR_PMUGRF(RK_GPIO2, RK_PB0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ 804 805 MR_PMUGRF(RK_GPIO0, RK_PC2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */ 806 MR_PMUGRF(RK_GPIO2, RK_PA7, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */ 807 808 MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */ 809 MR_PMUGRF(RK_GPIO2, RK_PA6, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */ 810 811 MR_PMUGRF(RK_GPIO0, RK_PB2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */ 812 MR_PMUGRF(RK_GPIO2, RK_PD4, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */ 813 814 MR_PMUGRF(RK_GPIO0, RK_PB1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ 815 MR_PMUGRF(RK_GPIO3, RK_PA0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ 816 817 MR_PMUGRF(RK_GPIO0, RK_PB0, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ 818 MR_PMUGRF(RK_GPIO2, RK_PA1, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ 819 MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ 820 821 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ 822 MR_PMUGRF(RK_GPIO1, RK_PD0, RK_FUNC_5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ 823 MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */ 824 }; 825 826 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 827 int *reg, u8 *bit, int *mask) 828 { 829 struct rockchip_pinctrl_priv *priv = bank->priv; 830 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 831 struct rockchip_mux_recalced_data *data; 832 int i; 833 834 for (i = 0; i < ctrl->niomux_recalced; i++) { 835 data = &ctrl->iomux_recalced[i]; 836 if (data->num == bank->bank_num && 837 data->pin == pin) 838 break; 839 } 840 841 if (i >= ctrl->niomux_recalced) 842 return; 843 844 *reg = data->reg; 845 *mask = data->mask; 846 *bit = data->bit; 847 } 848 849 static struct rockchip_mux_route_data px30_mux_route_data[] = { 850 { 851 /* cif-d2m0 */ 852 .bank_num = 2, 853 .pin = 0, 854 .func = 1, 855 .route_offset = 0x184, 856 .route_val = BIT(16 + 7), 857 }, { 858 /* cif-d2m1 */ 859 .bank_num = 3, 860 .pin = 3, 861 .func = 3, 862 .route_offset = 0x184, 863 .route_val = BIT(16 + 7) | BIT(7), 864 }, { 865 /* pdm-m0 */ 866 .bank_num = 3, 867 .pin = 22, 868 .func = 2, 869 .route_offset = 0x184, 870 .route_val = BIT(16 + 8), 871 }, { 872 /* pdm-m1 */ 873 .bank_num = 2, 874 .pin = 22, 875 .func = 1, 876 .route_offset = 0x184, 877 .route_val = BIT(16 + 8) | BIT(8), 878 }, { 879 /* uart2-rxm0 */ 880 .bank_num = 1, 881 .pin = 27, 882 .func = 2, 883 .route_offset = 0x184, 884 .route_val = BIT(16 + 10), 885 }, { 886 /* uart2-rxm1 */ 887 .bank_num = 2, 888 .pin = 14, 889 .func = 2, 890 .route_offset = 0x184, 891 .route_val = BIT(16 + 10) | BIT(10), 892 }, { 893 /* uart3-rxm0 */ 894 .bank_num = 0, 895 .pin = 17, 896 .func = 2, 897 .route_offset = 0x184, 898 .route_val = BIT(16 + 9), 899 }, { 900 /* uart3-rxm1 */ 901 .bank_num = 1, 902 .pin = 15, 903 .func = 2, 904 .route_offset = 0x184, 905 .route_val = BIT(16 + 9) | BIT(9), 906 }, 907 }; 908 909 static struct rockchip_mux_route_data rk1808_mux_route_data[] = { 910 { 911 /* i2c2m0_sda */ 912 .bank_num = 3, 913 .pin = 12, 914 .func = 2, 915 .route_offset = 0x190, 916 .route_val = BIT(16 + 3), 917 }, { 918 /* i2c2m1_sda */ 919 .bank_num = 1, 920 .pin = 13, 921 .func = 2, 922 .route_offset = 0x190, 923 .route_val = BIT(16 + 3) | BIT(3), 924 }, { 925 /* uart2_rxm0 */ 926 .bank_num = 4, 927 .pin = 3, 928 .func = 2, 929 .route_offset = 0x190, 930 .route_val = BIT(16 + 14) | BIT(16 + 15), 931 }, { 932 /* uart2_rxm1 */ 933 .bank_num = 2, 934 .pin = 25, 935 .func = 2, 936 .route_offset = 0x190, 937 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15), 938 }, { 939 /* uart2_rxm2 */ 940 .bank_num = 3, 941 .pin = 4, 942 .func = 2, 943 .route_offset = 0x190, 944 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15), 945 }, 946 }; 947 948 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 949 { 950 /* spi-0 */ 951 .bank_num = 1, 952 .pin = 10, 953 .func = 1, 954 .route_offset = 0x144, 955 .route_val = BIT(16 + 3) | BIT(16 + 4), 956 }, { 957 /* spi-1 */ 958 .bank_num = 1, 959 .pin = 27, 960 .func = 3, 961 .route_offset = 0x144, 962 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 963 }, { 964 /* spi-2 */ 965 .bank_num = 0, 966 .pin = 13, 967 .func = 2, 968 .route_offset = 0x144, 969 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 970 }, { 971 /* i2s-0 */ 972 .bank_num = 1, 973 .pin = 5, 974 .func = 1, 975 .route_offset = 0x144, 976 .route_val = BIT(16 + 5), 977 }, { 978 /* i2s-1 */ 979 .bank_num = 0, 980 .pin = 14, 981 .func = 1, 982 .route_offset = 0x144, 983 .route_val = BIT(16 + 5) | BIT(5), 984 }, { 985 /* emmc-0 */ 986 .bank_num = 1, 987 .pin = 22, 988 .func = 2, 989 .route_offset = 0x144, 990 .route_val = BIT(16 + 6), 991 }, { 992 /* emmc-1 */ 993 .bank_num = 2, 994 .pin = 4, 995 .func = 2, 996 .route_offset = 0x144, 997 .route_val = BIT(16 + 6) | BIT(6), 998 }, 999 }; 1000 1001 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 1002 { 1003 /* pwm0-0 */ 1004 .bank_num = 0, 1005 .pin = 26, 1006 .func = 1, 1007 .route_offset = 0x50, 1008 .route_val = BIT(16), 1009 }, { 1010 /* pwm0-1 */ 1011 .bank_num = 3, 1012 .pin = 21, 1013 .func = 1, 1014 .route_offset = 0x50, 1015 .route_val = BIT(16) | BIT(0), 1016 }, { 1017 /* pwm1-0 */ 1018 .bank_num = 0, 1019 .pin = 27, 1020 .func = 1, 1021 .route_offset = 0x50, 1022 .route_val = BIT(16 + 1), 1023 }, { 1024 /* pwm1-1 */ 1025 .bank_num = 0, 1026 .pin = 30, 1027 .func = 2, 1028 .route_offset = 0x50, 1029 .route_val = BIT(16 + 1) | BIT(1), 1030 }, { 1031 /* pwm2-0 */ 1032 .bank_num = 0, 1033 .pin = 28, 1034 .func = 1, 1035 .route_offset = 0x50, 1036 .route_val = BIT(16 + 2), 1037 }, { 1038 /* pwm2-1 */ 1039 .bank_num = 1, 1040 .pin = 12, 1041 .func = 2, 1042 .route_offset = 0x50, 1043 .route_val = BIT(16 + 2) | BIT(2), 1044 }, { 1045 /* pwm3-0 */ 1046 .bank_num = 3, 1047 .pin = 26, 1048 .func = 1, 1049 .route_offset = 0x50, 1050 .route_val = BIT(16 + 3), 1051 }, { 1052 /* pwm3-1 */ 1053 .bank_num = 1, 1054 .pin = 11, 1055 .func = 2, 1056 .route_offset = 0x50, 1057 .route_val = BIT(16 + 3) | BIT(3), 1058 }, { 1059 /* sdio-0_d0 */ 1060 .bank_num = 1, 1061 .pin = 1, 1062 .func = 1, 1063 .route_offset = 0x50, 1064 .route_val = BIT(16 + 4), 1065 }, { 1066 /* sdio-1_d0 */ 1067 .bank_num = 3, 1068 .pin = 2, 1069 .func = 1, 1070 .route_offset = 0x50, 1071 .route_val = BIT(16 + 4) | BIT(4), 1072 }, { 1073 /* spi-0_rx */ 1074 .bank_num = 0, 1075 .pin = 13, 1076 .func = 2, 1077 .route_offset = 0x50, 1078 .route_val = BIT(16 + 5), 1079 }, { 1080 /* spi-1_rx */ 1081 .bank_num = 2, 1082 .pin = 0, 1083 .func = 2, 1084 .route_offset = 0x50, 1085 .route_val = BIT(16 + 5) | BIT(5), 1086 }, { 1087 /* emmc-0_cmd */ 1088 .bank_num = 1, 1089 .pin = 22, 1090 .func = 2, 1091 .route_offset = 0x50, 1092 .route_val = BIT(16 + 7), 1093 }, { 1094 /* emmc-1_cmd */ 1095 .bank_num = 2, 1096 .pin = 4, 1097 .func = 2, 1098 .route_offset = 0x50, 1099 .route_val = BIT(16 + 7) | BIT(7), 1100 }, { 1101 /* uart2-0_rx */ 1102 .bank_num = 1, 1103 .pin = 19, 1104 .func = 2, 1105 .route_offset = 0x50, 1106 .route_val = BIT(16 + 8), 1107 }, { 1108 /* uart2-1_rx */ 1109 .bank_num = 1, 1110 .pin = 10, 1111 .func = 2, 1112 .route_offset = 0x50, 1113 .route_val = BIT(16 + 8) | BIT(8), 1114 }, { 1115 /* uart1-0_rx */ 1116 .bank_num = 1, 1117 .pin = 10, 1118 .func = 1, 1119 .route_offset = 0x50, 1120 .route_val = BIT(16 + 11), 1121 }, { 1122 /* uart1-1_rx */ 1123 .bank_num = 3, 1124 .pin = 13, 1125 .func = 1, 1126 .route_offset = 0x50, 1127 .route_val = BIT(16 + 11) | BIT(11), 1128 }, 1129 }; 1130 1131 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 1132 { 1133 /* edphdmi_cecinoutt1 */ 1134 .bank_num = 7, 1135 .pin = 16, 1136 .func = 2, 1137 .route_offset = 0x264, 1138 .route_val = BIT(16 + 12) | BIT(12), 1139 }, { 1140 /* edphdmi_cecinout */ 1141 .bank_num = 7, 1142 .pin = 23, 1143 .func = 4, 1144 .route_offset = 0x264, 1145 .route_val = BIT(16 + 12), 1146 }, 1147 }; 1148 1149 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 1150 { 1151 /* rtc_clk */ 1152 .bank_num = 0, 1153 .pin = 19, 1154 .func = 1, 1155 .route_offset = 0x314, 1156 .route_val = BIT(16 + 0) | BIT(0), 1157 }, { 1158 /* uart2_rxm0 */ 1159 .bank_num = 1, 1160 .pin = 22, 1161 .func = 2, 1162 .route_offset = 0x314, 1163 .route_val = BIT(16 + 2) | BIT(16 + 3), 1164 }, { 1165 /* uart2_rxm1 */ 1166 .bank_num = 4, 1167 .pin = 26, 1168 .func = 2, 1169 .route_offset = 0x314, 1170 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1171 }, { 1172 /* i2c3_sdam0 */ 1173 .bank_num = 0, 1174 .pin = 23, 1175 .func = 2, 1176 .route_offset = 0x314, 1177 .route_val = BIT(16 + 4), 1178 }, { 1179 /* i2c3_sdam1 */ 1180 .bank_num = 3, 1181 .pin = 12, 1182 .func = 2, 1183 .route_offset = 0x314, 1184 .route_val = BIT(16 + 4) | BIT(4), 1185 }, { 1186 /* i2s-8ch-1-sclktxm0 */ 1187 .bank_num = 1, 1188 .pin = 3, 1189 .func = 2, 1190 .route_offset = 0x308, 1191 .route_val = BIT(16 + 3), 1192 }, { 1193 /* i2s-8ch-1-sclkrxm0 */ 1194 .bank_num = 1, 1195 .pin = 4, 1196 .func = 2, 1197 .route_offset = 0x308, 1198 .route_val = BIT(16 + 3), 1199 }, { 1200 /* i2s-8ch-1-sclktxm1 */ 1201 .bank_num = 1, 1202 .pin = 13, 1203 .func = 2, 1204 .route_offset = 0x308, 1205 .route_val = BIT(16 + 3) | BIT(3), 1206 }, { 1207 /* i2s-8ch-1-sclkrxm1 */ 1208 .bank_num = 1, 1209 .pin = 14, 1210 .func = 2, 1211 .route_offset = 0x308, 1212 .route_val = BIT(16 + 3) | BIT(3), 1213 }, { 1214 /* pdm-clkm0 */ 1215 .bank_num = 1, 1216 .pin = 4, 1217 .func = 3, 1218 .route_offset = 0x308, 1219 .route_val = BIT(16 + 12) | BIT(16 + 13), 1220 }, { 1221 /* pdm-clkm1 */ 1222 .bank_num = 1, 1223 .pin = 14, 1224 .func = 4, 1225 .route_offset = 0x308, 1226 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1227 }, { 1228 /* pdm-clkm2 */ 1229 .bank_num = 2, 1230 .pin = 6, 1231 .func = 2, 1232 .route_offset = 0x308, 1233 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1234 }, { 1235 /* pdm-clkm-m2 */ 1236 .bank_num = 2, 1237 .pin = 4, 1238 .func = 3, 1239 .route_offset = 0x600, 1240 .route_val = BIT(16 + 2) | BIT(2), 1241 }, 1242 }; 1243 1244 static struct rockchip_mux_route_data rk3308b_mux_route_data[] = { 1245 { 1246 /* rtc_clk */ 1247 .bank_num = 0, 1248 .pin = 19, 1249 .func = 1, 1250 .route_offset = 0x314, 1251 .route_val = BIT(16 + 0) | BIT(0), 1252 }, { 1253 /* uart2_rxm0 */ 1254 .bank_num = 1, 1255 .pin = 22, 1256 .func = 2, 1257 .route_offset = 0x314, 1258 .route_val = BIT(16 + 2) | BIT(16 + 3), 1259 }, { 1260 /* uart2_rxm1 */ 1261 .bank_num = 4, 1262 .pin = 26, 1263 .func = 2, 1264 .route_offset = 0x314, 1265 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1266 }, { 1267 /* i2c3_sdam0 */ 1268 .bank_num = 0, 1269 .pin = 15, 1270 .func = 2, 1271 .route_offset = 0x608, 1272 .route_val = BIT(16 + 8) | BIT(16 + 9), 1273 }, { 1274 /* i2c3_sdam1 */ 1275 .bank_num = 3, 1276 .pin = 12, 1277 .func = 2, 1278 .route_offset = 0x608, 1279 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 1280 }, { 1281 /* i2c3_sdam2 */ 1282 .bank_num = 2, 1283 .pin = 0, 1284 .func = 3, 1285 .route_offset = 0x608, 1286 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 1287 }, { 1288 /* i2s-8ch-1-sclktxm0 */ 1289 .bank_num = 1, 1290 .pin = 3, 1291 .func = 2, 1292 .route_offset = 0x308, 1293 .route_val = BIT(16 + 3), 1294 }, { 1295 /* i2s-8ch-1-sclkrxm0 */ 1296 .bank_num = 1, 1297 .pin = 4, 1298 .func = 2, 1299 .route_offset = 0x308, 1300 .route_val = BIT(16 + 3), 1301 }, { 1302 /* i2s-8ch-1-sclktxm1 */ 1303 .bank_num = 1, 1304 .pin = 13, 1305 .func = 2, 1306 .route_offset = 0x308, 1307 .route_val = BIT(16 + 3) | BIT(3), 1308 }, { 1309 /* i2s-8ch-1-sclkrxm1 */ 1310 .bank_num = 1, 1311 .pin = 14, 1312 .func = 2, 1313 .route_offset = 0x308, 1314 .route_val = BIT(16 + 3) | BIT(3), 1315 }, { 1316 /* pdm-clkm0 */ 1317 .bank_num = 1, 1318 .pin = 4, 1319 .func = 3, 1320 .route_offset = 0x308, 1321 .route_val = BIT(16 + 12) | BIT(16 + 13), 1322 }, { 1323 /* pdm-clkm1 */ 1324 .bank_num = 1, 1325 .pin = 14, 1326 .func = 4, 1327 .route_offset = 0x308, 1328 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1329 }, { 1330 /* pdm-clkm2 */ 1331 .bank_num = 2, 1332 .pin = 6, 1333 .func = 2, 1334 .route_offset = 0x308, 1335 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1336 }, { 1337 /* pdm-clkm-m2 */ 1338 .bank_num = 2, 1339 .pin = 4, 1340 .func = 3, 1341 .route_offset = 0x600, 1342 .route_val = BIT(16 + 2) | BIT(2), 1343 }, { 1344 /* spi1_miso */ 1345 .bank_num = 3, 1346 .pin = 10, 1347 .func = 3, 1348 .route_offset = 0x314, 1349 .route_val = BIT(16 + 9), 1350 }, { 1351 /* spi1_miso_m1 */ 1352 .bank_num = 2, 1353 .pin = 4, 1354 .func = 2, 1355 .route_offset = 0x314, 1356 .route_val = BIT(16 + 9) | BIT(9), 1357 }, { 1358 /* owire_m0 */ 1359 .bank_num = 0, 1360 .pin = 11, 1361 .func = 3, 1362 .route_offset = 0x314, 1363 .route_val = BIT(16 + 10) | BIT(16 + 11), 1364 }, { 1365 /* owire_m1 */ 1366 .bank_num = 1, 1367 .pin = 22, 1368 .func = 7, 1369 .route_offset = 0x314, 1370 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1371 }, { 1372 /* owire_m2 */ 1373 .bank_num = 2, 1374 .pin = 2, 1375 .func = 5, 1376 .route_offset = 0x314, 1377 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1378 }, { 1379 /* can_rxd_m0 */ 1380 .bank_num = 0, 1381 .pin = 11, 1382 .func = 2, 1383 .route_offset = 0x314, 1384 .route_val = BIT(16 + 12) | BIT(16 + 13), 1385 }, { 1386 /* can_rxd_m1 */ 1387 .bank_num = 1, 1388 .pin = 22, 1389 .func = 5, 1390 .route_offset = 0x314, 1391 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1392 }, { 1393 /* can_rxd_m2 */ 1394 .bank_num = 2, 1395 .pin = 2, 1396 .func = 4, 1397 .route_offset = 0x314, 1398 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1399 }, { 1400 /* mac_rxd0_m0 */ 1401 .bank_num = 1, 1402 .pin = 20, 1403 .func = 3, 1404 .route_offset = 0x314, 1405 .route_val = BIT(16 + 14), 1406 }, { 1407 /* mac_rxd0_m1 */ 1408 .bank_num = 4, 1409 .pin = 2, 1410 .func = 2, 1411 .route_offset = 0x314, 1412 .route_val = BIT(16 + 14) | BIT(14), 1413 }, { 1414 /* uart3_rx */ 1415 .bank_num = 3, 1416 .pin = 12, 1417 .func = 4, 1418 .route_offset = 0x314, 1419 .route_val = BIT(16 + 15), 1420 }, { 1421 /* uart3_rx_m1 */ 1422 .bank_num = 0, 1423 .pin = 17, 1424 .func = 3, 1425 .route_offset = 0x314, 1426 .route_val = BIT(16 + 15) | BIT(15), 1427 }, 1428 }; 1429 1430 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1431 { 1432 /* uart2dbg_rxm0 */ 1433 .bank_num = 1, 1434 .pin = 1, 1435 .func = 2, 1436 .route_offset = 0x50, 1437 .route_val = BIT(16) | BIT(16 + 1), 1438 }, { 1439 /* uart2dbg_rxm1 */ 1440 .bank_num = 2, 1441 .pin = 1, 1442 .func = 1, 1443 .route_offset = 0x50, 1444 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1445 }, { 1446 /* gmac-m1_rxd0 */ 1447 .bank_num = 1, 1448 .pin = 11, 1449 .func = 2, 1450 .route_offset = 0x50, 1451 .route_val = BIT(16 + 2) | BIT(2), 1452 }, { 1453 /* gmac-m1-optimized_rxd3 */ 1454 .bank_num = 1, 1455 .pin = 14, 1456 .func = 2, 1457 .route_offset = 0x50, 1458 .route_val = BIT(16 + 10) | BIT(10), 1459 }, { 1460 /* pdm_sdi0m0 */ 1461 .bank_num = 2, 1462 .pin = 19, 1463 .func = 2, 1464 .route_offset = 0x50, 1465 .route_val = BIT(16 + 3), 1466 }, { 1467 /* pdm_sdi0m1 */ 1468 .bank_num = 1, 1469 .pin = 23, 1470 .func = 3, 1471 .route_offset = 0x50, 1472 .route_val = BIT(16 + 3) | BIT(3), 1473 }, { 1474 /* spi_rxdm2 */ 1475 .bank_num = 3, 1476 .pin = 2, 1477 .func = 4, 1478 .route_offset = 0x50, 1479 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1480 }, { 1481 /* i2s2_sdim0 */ 1482 .bank_num = 1, 1483 .pin = 24, 1484 .func = 1, 1485 .route_offset = 0x50, 1486 .route_val = BIT(16 + 6), 1487 }, { 1488 /* i2s2_sdim1 */ 1489 .bank_num = 3, 1490 .pin = 2, 1491 .func = 6, 1492 .route_offset = 0x50, 1493 .route_val = BIT(16 + 6) | BIT(6), 1494 }, { 1495 /* card_iom1 */ 1496 .bank_num = 2, 1497 .pin = 22, 1498 .func = 3, 1499 .route_offset = 0x50, 1500 .route_val = BIT(16 + 7) | BIT(7), 1501 }, { 1502 /* tsp_d5m1 */ 1503 .bank_num = 2, 1504 .pin = 16, 1505 .func = 3, 1506 .route_offset = 0x50, 1507 .route_val = BIT(16 + 8) | BIT(8), 1508 }, { 1509 /* cif_data5m1 */ 1510 .bank_num = 2, 1511 .pin = 16, 1512 .func = 4, 1513 .route_offset = 0x50, 1514 .route_val = BIT(16 + 9) | BIT(9), 1515 }, 1516 }; 1517 1518 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1519 { 1520 /* uart2dbga_rx */ 1521 .bank_num = 4, 1522 .pin = 8, 1523 .func = 2, 1524 .route_offset = 0xe21c, 1525 .route_val = BIT(16 + 10) | BIT(16 + 11), 1526 }, { 1527 /* uart2dbgb_rx */ 1528 .bank_num = 4, 1529 .pin = 16, 1530 .func = 2, 1531 .route_offset = 0xe21c, 1532 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1533 }, { 1534 /* uart2dbgc_rx */ 1535 .bank_num = 4, 1536 .pin = 19, 1537 .func = 1, 1538 .route_offset = 0xe21c, 1539 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1540 }, { 1541 /* pcie_clkreqn */ 1542 .bank_num = 2, 1543 .pin = 26, 1544 .func = 2, 1545 .route_offset = 0xe21c, 1546 .route_val = BIT(16 + 14), 1547 }, { 1548 /* pcie_clkreqnb */ 1549 .bank_num = 4, 1550 .pin = 24, 1551 .func = 1, 1552 .route_offset = 0xe21c, 1553 .route_val = BIT(16 + 14) | BIT(14), 1554 }, 1555 }; 1556 1557 static enum rockchip_pin_route_type 1558 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1559 int mux, u32 *reg, u32 *value) 1560 { 1561 struct rockchip_pinctrl_priv *priv = bank->priv; 1562 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1563 struct rockchip_mux_route_data *data; 1564 int i; 1565 1566 for (i = 0; i < ctrl->niomux_routes; i++) { 1567 data = &ctrl->iomux_routes[i]; 1568 if ((data->bank_num == bank->bank_num) && 1569 (data->pin == pin) && (data->func == mux)) 1570 break; 1571 } 1572 1573 if (i >= ctrl->niomux_routes) 1574 return ROUTE_TYPE_INVALID; 1575 1576 *reg = data->route_offset; 1577 *value = data->route_val; 1578 1579 return data->route_type; 1580 } 1581 1582 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1583 { 1584 struct rockchip_pinctrl_priv *priv = bank->priv; 1585 int iomux_num = (pin / 8); 1586 struct regmap *regmap; 1587 unsigned int val; 1588 int reg, ret, mask, mux_type; 1589 u8 bit; 1590 1591 if (iomux_num > 3) 1592 return -EINVAL; 1593 1594 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1595 debug("pin %d is unrouted\n", pin); 1596 return -EINVAL; 1597 } 1598 1599 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1600 return RK_FUNC_GPIO; 1601 1602 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1603 regmap = priv->regmap_pmu; 1604 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1605 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 1606 else 1607 regmap = priv->regmap_base; 1608 1609 /* get basic quadrupel of mux registers and the correct reg inside */ 1610 mux_type = bank->iomux[iomux_num].type; 1611 reg = bank->iomux[iomux_num].offset; 1612 if (mux_type & IOMUX_WIDTH_4BIT) { 1613 if ((pin % 8) >= 4) 1614 reg += 0x4; 1615 bit = (pin % 4) * 4; 1616 mask = 0xf; 1617 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1618 if ((pin % 8) >= 5) 1619 reg += 0x4; 1620 bit = (pin % 8 % 5) * 3; 1621 mask = 0x7; 1622 } else { 1623 bit = (pin % 8) * 2; 1624 mask = 0x3; 1625 } 1626 1627 if (bank->recalced_mask & BIT(pin)) 1628 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1629 1630 ret = regmap_read(regmap, reg, &val); 1631 if (ret) 1632 return ret; 1633 1634 return ((val >> bit) & mask); 1635 } 1636 1637 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1638 int index) 1639 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1640 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1641 1642 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1643 } 1644 1645 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1646 int pin, int mux) 1647 { 1648 int iomux_num = (pin / 8); 1649 1650 if (iomux_num > 3) 1651 return -EINVAL; 1652 1653 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1654 debug("pin %d is unrouted\n", pin); 1655 return -EINVAL; 1656 } 1657 1658 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1659 if (mux != IOMUX_GPIO_ONLY) { 1660 debug("pin %d only supports a gpio mux\n", pin); 1661 return -ENOTSUPP; 1662 } 1663 } 1664 1665 return 0; 1666 } 1667 1668 /* 1669 * Set a new mux function for a pin. 1670 * 1671 * The register is divided into the upper and lower 16 bit. When changing 1672 * a value, the previous register value is not read and changed. Instead 1673 * it seems the changed bits are marked in the upper 16 bit, while the 1674 * changed value gets set in the same offset in the lower 16 bit. 1675 * All pin settings seem to be 2 bit wide in both the upper and lower 1676 * parts. 1677 * @bank: pin bank to change 1678 * @pin: pin to change 1679 * @mux: new mux function to set 1680 */ 1681 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1682 { 1683 struct rockchip_pinctrl_priv *priv = bank->priv; 1684 int iomux_num = (pin / 8); 1685 struct regmap *regmap; 1686 int reg, ret, mask, mux_type; 1687 u8 bit; 1688 u32 data; 1689 1690 ret = rockchip_verify_mux(bank, pin, mux); 1691 if (ret < 0) 1692 return ret; 1693 1694 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1695 return 0; 1696 1697 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1698 1699 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1700 regmap = priv->regmap_pmu; 1701 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1702 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 1703 else 1704 regmap = priv->regmap_base; 1705 1706 /* get basic quadrupel of mux registers and the correct reg inside */ 1707 mux_type = bank->iomux[iomux_num].type; 1708 reg = bank->iomux[iomux_num].offset; 1709 if (mux_type & IOMUX_WIDTH_4BIT) { 1710 if ((pin % 8) >= 4) 1711 reg += 0x4; 1712 bit = (pin % 4) * 4; 1713 mask = 0xf; 1714 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1715 if ((pin % 8) >= 5) 1716 reg += 0x4; 1717 bit = (pin % 8 % 5) * 3; 1718 mask = 0x7; 1719 } else { 1720 bit = (pin % 8) * 2; 1721 mask = 0x3; 1722 } 1723 1724 if (bank->recalced_mask & BIT(pin)) 1725 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1726 1727 if (bank->route_mask & BIT(pin)) { 1728 u32 route_reg = 0, route_val = 0; 1729 1730 ret = rockchip_get_mux_route(bank, pin, mux, 1731 &route_reg, &route_val); 1732 switch (ret) { 1733 case ROUTE_TYPE_DEFAULT: 1734 regmap_write(regmap, route_reg, route_val); 1735 break; 1736 case ROUTE_TYPE_TOPGRF: 1737 regmap_write(priv->regmap_base, route_reg, route_val); 1738 break; 1739 case ROUTE_TYPE_PMUGRF: 1740 regmap_write(priv->regmap_pmu, route_reg, route_val); 1741 break; 1742 case ROUTE_TYPE_INVALID: /* Fall through */ 1743 default: 1744 break; 1745 } 1746 } 1747 1748 if (mux_type & IOMUX_WRITABLE_32BIT) { 1749 regmap_read(regmap, reg, &data); 1750 data &= ~(mask << bit); 1751 } else { 1752 data = (mask << (bit + 16)); 1753 } 1754 1755 data |= (mux & mask) << bit; 1756 ret = regmap_write(regmap, reg, data); 1757 1758 return ret; 1759 } 1760 1761 #define PX30_PULL_PMU_OFFSET 0x10 1762 #define PX30_PULL_GRF_OFFSET 0x60 1763 #define PX30_PULL_BITS_PER_PIN 2 1764 #define PX30_PULL_PINS_PER_REG 8 1765 #define PX30_PULL_BANK_STRIDE 16 1766 1767 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1768 int pin_num, struct regmap **regmap, 1769 int *reg, u8 *bit) 1770 { 1771 struct rockchip_pinctrl_priv *priv = bank->priv; 1772 1773 /* The first 32 pins of the first bank are located in PMU */ 1774 if (bank->bank_num == 0) { 1775 *regmap = priv->regmap_pmu; 1776 *reg = PX30_PULL_PMU_OFFSET; 1777 } else { 1778 *regmap = priv->regmap_base; 1779 *reg = PX30_PULL_GRF_OFFSET; 1780 1781 /* correct the offset, as we're starting with the 2nd bank */ 1782 *reg -= 0x10; 1783 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1784 } 1785 1786 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1787 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1788 *bit *= PX30_PULL_BITS_PER_PIN; 1789 } 1790 1791 #define PX30_DRV_PMU_OFFSET 0x20 1792 #define PX30_DRV_GRF_OFFSET 0xf0 1793 #define PX30_DRV_BITS_PER_PIN 2 1794 #define PX30_DRV_PINS_PER_REG 8 1795 #define PX30_DRV_BANK_STRIDE 16 1796 1797 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1798 int pin_num, struct regmap **regmap, 1799 int *reg, u8 *bit) 1800 { 1801 struct rockchip_pinctrl_priv *priv = bank->priv; 1802 1803 /* The first 32 pins of the first bank are located in PMU */ 1804 if (bank->bank_num == 0) { 1805 *regmap = priv->regmap_pmu; 1806 *reg = PX30_DRV_PMU_OFFSET; 1807 } else { 1808 *regmap = priv->regmap_base; 1809 *reg = PX30_DRV_GRF_OFFSET; 1810 1811 /* correct the offset, as we're starting with the 2nd bank */ 1812 *reg -= 0x10; 1813 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1814 } 1815 1816 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1817 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1818 *bit *= PX30_DRV_BITS_PER_PIN; 1819 } 1820 1821 #define PX30_SCHMITT_PMU_OFFSET 0x38 1822 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1823 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1824 #define PX30_SCHMITT_BANK_STRIDE 16 1825 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1826 1827 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1828 int pin_num, 1829 struct regmap **regmap, 1830 int *reg, u8 *bit) 1831 { 1832 struct rockchip_pinctrl_priv *priv = bank->priv; 1833 int pins_per_reg; 1834 1835 if (bank->bank_num == 0) { 1836 *regmap = priv->regmap_pmu; 1837 *reg = PX30_SCHMITT_PMU_OFFSET; 1838 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1839 } else { 1840 *regmap = priv->regmap_base; 1841 *reg = PX30_SCHMITT_GRF_OFFSET; 1842 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1843 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1844 } 1845 *reg += ((pin_num / pins_per_reg) * 4); 1846 *bit = pin_num % pins_per_reg; 1847 1848 return 0; 1849 } 1850 1851 #define RV1108_PULL_PMU_OFFSET 0x10 1852 #define RV1108_PULL_OFFSET 0x110 1853 #define RV1108_PULL_PINS_PER_REG 8 1854 #define RV1108_PULL_BITS_PER_PIN 2 1855 #define RV1108_PULL_BANK_STRIDE 16 1856 1857 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1858 int pin_num, struct regmap **regmap, 1859 int *reg, u8 *bit) 1860 { 1861 struct rockchip_pinctrl_priv *priv = bank->priv; 1862 1863 /* The first 24 pins of the first bank are located in PMU */ 1864 if (bank->bank_num == 0) { 1865 *regmap = priv->regmap_pmu; 1866 *reg = RV1108_PULL_PMU_OFFSET; 1867 } else { 1868 *reg = RV1108_PULL_OFFSET; 1869 *regmap = priv->regmap_base; 1870 /* correct the offset, as we're starting with the 2nd bank */ 1871 *reg -= 0x10; 1872 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1873 } 1874 1875 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1876 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1877 *bit *= RV1108_PULL_BITS_PER_PIN; 1878 } 1879 1880 #define RV1108_DRV_PMU_OFFSET 0x20 1881 #define RV1108_DRV_GRF_OFFSET 0x210 1882 #define RV1108_DRV_BITS_PER_PIN 2 1883 #define RV1108_DRV_PINS_PER_REG 8 1884 #define RV1108_DRV_BANK_STRIDE 16 1885 1886 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1887 int pin_num, struct regmap **regmap, 1888 int *reg, u8 *bit) 1889 { 1890 struct rockchip_pinctrl_priv *priv = bank->priv; 1891 1892 /* The first 24 pins of the first bank are located in PMU */ 1893 if (bank->bank_num == 0) { 1894 *regmap = priv->regmap_pmu; 1895 *reg = RV1108_DRV_PMU_OFFSET; 1896 } else { 1897 *regmap = priv->regmap_base; 1898 *reg = RV1108_DRV_GRF_OFFSET; 1899 1900 /* correct the offset, as we're starting with the 2nd bank */ 1901 *reg -= 0x10; 1902 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1903 } 1904 1905 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1906 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1907 *bit *= RV1108_DRV_BITS_PER_PIN; 1908 } 1909 1910 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1911 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1912 #define RV1108_SCHMITT_BANK_STRIDE 8 1913 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1914 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1915 1916 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1917 int pin_num, 1918 struct regmap **regmap, 1919 int *reg, u8 *bit) 1920 { 1921 struct rockchip_pinctrl_priv *priv = bank->priv; 1922 int pins_per_reg; 1923 1924 if (bank->bank_num == 0) { 1925 *regmap = priv->regmap_pmu; 1926 *reg = RV1108_SCHMITT_PMU_OFFSET; 1927 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1928 } else { 1929 *regmap = priv->regmap_base; 1930 *reg = RV1108_SCHMITT_GRF_OFFSET; 1931 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1932 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1933 } 1934 *reg += ((pin_num / pins_per_reg) * 4); 1935 *bit = pin_num % pins_per_reg; 1936 1937 return 0; 1938 } 1939 1940 #define RV1126_PULL_PMU_OFFSET 0x40 1941 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 1942 #define RV1126_PULL_PINS_PER_REG 8 1943 #define RV1126_PULL_BITS_PER_PIN 2 1944 #define RV1126_PULL_BANK_STRIDE 16 1945 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 1946 1947 static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1948 int pin_num, struct regmap **regmap, 1949 int *reg, u8 *bit) 1950 { 1951 struct rockchip_pinctrl_priv *priv = bank->priv; 1952 1953 /* The first 24 pins of the first bank are located in PMU */ 1954 if (bank->bank_num == 0) { 1955 if (RV1126_GPIO_C4_D7(pin_num)) { 1956 *regmap = priv->regmap_base; 1957 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1958 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 1959 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 1960 *bit *= RV1126_PULL_BITS_PER_PIN; 1961 return; 1962 } 1963 *regmap = priv->regmap_pmu; 1964 *reg = RV1126_PULL_PMU_OFFSET; 1965 } else { 1966 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1967 *regmap = priv->regmap_base; 1968 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; 1969 } 1970 1971 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 1972 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 1973 *bit *= RV1126_PULL_BITS_PER_PIN; 1974 } 1975 1976 #define RV1126_DRV_PMU_OFFSET 0x20 1977 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 1978 #define RV1126_DRV_BITS_PER_PIN 4 1979 #define RV1126_DRV_PINS_PER_REG 4 1980 #define RV1126_DRV_BANK_STRIDE 32 1981 1982 static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1983 int pin_num, struct regmap **regmap, 1984 int *reg, u8 *bit) 1985 { 1986 struct rockchip_pinctrl_priv *priv = bank->priv; 1987 1988 /* The first 24 pins of the first bank are located in PMU */ 1989 if (bank->bank_num == 0) { 1990 if (RV1126_GPIO_C4_D7(pin_num)) { 1991 *regmap = priv->regmap_base; 1992 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1993 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 1994 *reg -= 0x4; 1995 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1996 *bit *= RV1126_DRV_BITS_PER_PIN; 1997 return; 1998 } 1999 *regmap = priv->regmap_pmu; 2000 *reg = RV1126_DRV_PMU_OFFSET; 2001 } else { 2002 *regmap = priv->regmap_base; 2003 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 2004 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; 2005 } 2006 2007 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 2008 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 2009 *bit *= RV1126_DRV_BITS_PER_PIN; 2010 } 2011 2012 #define RV1126_SCHMITT_PMU_OFFSET 0x60 2013 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 2014 #define RV1126_SCHMITT_BANK_STRIDE 16 2015 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8 2016 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8 2017 2018 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2019 int pin_num, 2020 struct regmap **regmap, 2021 int *reg, u8 *bit) 2022 { 2023 struct rockchip_pinctrl_priv *priv = bank->priv; 2024 int pins_per_reg; 2025 2026 if (bank->bank_num == 0) { 2027 if (RV1126_GPIO_C4_D7(pin_num)) { 2028 *regmap = priv->regmap_base; 2029 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 2030 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 2031 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 2032 return 0; 2033 } 2034 *regmap = priv->regmap_pmu; 2035 *reg = RV1126_SCHMITT_PMU_OFFSET; 2036 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 2037 } else { 2038 *regmap = priv->regmap_base; 2039 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 2040 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 2041 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; 2042 } 2043 *reg += ((pin_num / pins_per_reg) * 4); 2044 *bit = pin_num % pins_per_reg; 2045 2046 return 0; 2047 } 2048 2049 #define RK1808_PULL_PMU_OFFSET 0x10 2050 #define RK1808_PULL_GRF_OFFSET 0x80 2051 #define RK1808_PULL_PINS_PER_REG 8 2052 #define RK1808_PULL_BITS_PER_PIN 2 2053 #define RK1808_PULL_BANK_STRIDE 16 2054 2055 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2056 int pin_num, 2057 struct regmap **regmap, 2058 int *reg, u8 *bit) 2059 { 2060 struct rockchip_pinctrl_priv *priv = bank->priv; 2061 2062 if (bank->bank_num == 0) { 2063 *regmap = priv->regmap_pmu; 2064 *reg = RK1808_PULL_PMU_OFFSET; 2065 } else { 2066 *reg = RK1808_PULL_GRF_OFFSET; 2067 *regmap = priv->regmap_base; 2068 } 2069 2070 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4); 2071 *bit = (pin_num % RK1808_PULL_PINS_PER_REG); 2072 *bit *= RK1808_PULL_BITS_PER_PIN; 2073 } 2074 2075 #define RK1808_DRV_PMU_OFFSET 0x20 2076 #define RK1808_DRV_GRF_OFFSET 0x140 2077 #define RK1808_DRV_BITS_PER_PIN 2 2078 #define RK1808_DRV_PINS_PER_REG 8 2079 #define RK1808_DRV_BANK_STRIDE 16 2080 2081 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2082 int pin_num, 2083 struct regmap **regmap, 2084 int *reg, u8 *bit) 2085 { 2086 struct rockchip_pinctrl_priv *priv = bank->priv; 2087 2088 if (bank->bank_num == 0) { 2089 *regmap = priv->regmap_pmu; 2090 *reg = RK1808_DRV_PMU_OFFSET; 2091 } else { 2092 *regmap = priv->regmap_base; 2093 *reg = RK1808_DRV_GRF_OFFSET; 2094 } 2095 2096 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4); 2097 *bit = pin_num % RK1808_DRV_PINS_PER_REG; 2098 *bit *= RK1808_DRV_BITS_PER_PIN; 2099 } 2100 2101 #define RK1808_SCHMITT_PMU_OFFSET 0x0040 2102 #define RK1808_SCHMITT_GRF_OFFSET 0x0100 2103 #define RK1808_SCHMITT_BANK_STRIDE 16 2104 #define RK1808_SCHMITT_PINS_PER_REG 8 2105 2106 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2107 int pin_num, 2108 struct regmap **regmap, 2109 int *reg, u8 *bit) 2110 { 2111 struct rockchip_pinctrl_priv *priv = bank->priv; 2112 2113 if (bank->bank_num == 0) { 2114 *regmap = priv->regmap_pmu; 2115 *reg = RK1808_SCHMITT_PMU_OFFSET; 2116 } else { 2117 *regmap = priv->regmap_base; 2118 *reg = RK1808_SCHMITT_GRF_OFFSET; 2119 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE; 2120 } 2121 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4); 2122 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG; 2123 2124 return 0; 2125 } 2126 2127 #define RK2928_PULL_OFFSET 0x118 2128 #define RK2928_PULL_PINS_PER_REG 16 2129 #define RK2928_PULL_BANK_STRIDE 8 2130 2131 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2132 int pin_num, struct regmap **regmap, 2133 int *reg, u8 *bit) 2134 { 2135 struct rockchip_pinctrl_priv *priv = bank->priv; 2136 2137 *regmap = priv->regmap_base; 2138 *reg = RK2928_PULL_OFFSET; 2139 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 2140 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 2141 2142 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 2143 }; 2144 2145 #define RK3128_PULL_OFFSET 0x118 2146 2147 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2148 int pin_num, struct regmap **regmap, 2149 int *reg, u8 *bit) 2150 { 2151 struct rockchip_pinctrl_priv *priv = bank->priv; 2152 2153 *regmap = priv->regmap_base; 2154 *reg = RK3128_PULL_OFFSET; 2155 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 2156 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 2157 2158 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 2159 } 2160 2161 #define RK3188_PULL_OFFSET 0x164 2162 #define RK3188_PULL_BITS_PER_PIN 2 2163 #define RK3188_PULL_PINS_PER_REG 8 2164 #define RK3188_PULL_BANK_STRIDE 16 2165 #define RK3188_PULL_PMU_OFFSET 0x64 2166 2167 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2168 int pin_num, struct regmap **regmap, 2169 int *reg, u8 *bit) 2170 { 2171 struct rockchip_pinctrl_priv *priv = bank->priv; 2172 2173 /* The first 12 pins of the first bank are located elsewhere */ 2174 if (bank->bank_num == 0 && pin_num < 12) { 2175 *regmap = priv->regmap_pmu; 2176 *reg = RK3188_PULL_PMU_OFFSET; 2177 2178 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2179 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2180 *bit *= RK3188_PULL_BITS_PER_PIN; 2181 } else { 2182 *regmap = priv->regmap_base; 2183 *reg = RK3188_PULL_OFFSET; 2184 2185 /* correct the offset, as it is the 2nd pull register */ 2186 *reg -= 4; 2187 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2188 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2189 2190 /* 2191 * The bits in these registers have an inverse ordering 2192 * with the lowest pin being in bits 15:14 and the highest 2193 * pin in bits 1:0 2194 */ 2195 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 2196 *bit *= RK3188_PULL_BITS_PER_PIN; 2197 } 2198 } 2199 2200 #define RK3288_PULL_OFFSET 0x140 2201 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2202 int pin_num, struct regmap **regmap, 2203 int *reg, u8 *bit) 2204 { 2205 struct rockchip_pinctrl_priv *priv = bank->priv; 2206 2207 /* The first 24 pins of the first bank are located in PMU */ 2208 if (bank->bank_num == 0) { 2209 *regmap = priv->regmap_pmu; 2210 *reg = RK3188_PULL_PMU_OFFSET; 2211 2212 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2213 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2214 *bit *= RK3188_PULL_BITS_PER_PIN; 2215 } else { 2216 *regmap = priv->regmap_base; 2217 *reg = RK3288_PULL_OFFSET; 2218 2219 /* correct the offset, as we're starting with the 2nd bank */ 2220 *reg -= 0x10; 2221 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2222 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2223 2224 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2225 *bit *= RK3188_PULL_BITS_PER_PIN; 2226 } 2227 } 2228 2229 #define RK3288_DRV_PMU_OFFSET 0x70 2230 #define RK3288_DRV_GRF_OFFSET 0x1c0 2231 #define RK3288_DRV_BITS_PER_PIN 2 2232 #define RK3288_DRV_PINS_PER_REG 8 2233 #define RK3288_DRV_BANK_STRIDE 16 2234 2235 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2236 int pin_num, struct regmap **regmap, 2237 int *reg, u8 *bit) 2238 { 2239 struct rockchip_pinctrl_priv *priv = bank->priv; 2240 2241 /* The first 24 pins of the first bank are located in PMU */ 2242 if (bank->bank_num == 0) { 2243 *regmap = priv->regmap_pmu; 2244 *reg = RK3288_DRV_PMU_OFFSET; 2245 2246 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2247 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2248 *bit *= RK3288_DRV_BITS_PER_PIN; 2249 } else { 2250 *regmap = priv->regmap_base; 2251 *reg = RK3288_DRV_GRF_OFFSET; 2252 2253 /* correct the offset, as we're starting with the 2nd bank */ 2254 *reg -= 0x10; 2255 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2256 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2257 2258 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2259 *bit *= RK3288_DRV_BITS_PER_PIN; 2260 } 2261 } 2262 2263 #define RK3228_PULL_OFFSET 0x100 2264 2265 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2266 int pin_num, struct regmap **regmap, 2267 int *reg, u8 *bit) 2268 { 2269 struct rockchip_pinctrl_priv *priv = bank->priv; 2270 2271 *regmap = priv->regmap_base; 2272 *reg = RK3228_PULL_OFFSET; 2273 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2274 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2275 2276 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2277 *bit *= RK3188_PULL_BITS_PER_PIN; 2278 } 2279 2280 #define RK3228_DRV_GRF_OFFSET 0x200 2281 2282 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2283 int pin_num, struct regmap **regmap, 2284 int *reg, u8 *bit) 2285 { 2286 struct rockchip_pinctrl_priv *priv = bank->priv; 2287 2288 *regmap = priv->regmap_base; 2289 *reg = RK3228_DRV_GRF_OFFSET; 2290 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2291 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2292 2293 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2294 *bit *= RK3288_DRV_BITS_PER_PIN; 2295 } 2296 2297 #define RK3308_PULL_OFFSET 0xa0 2298 2299 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2300 int pin_num, struct regmap **regmap, 2301 int *reg, u8 *bit) 2302 { 2303 struct rockchip_pinctrl_priv *priv = bank->priv; 2304 2305 *regmap = priv->regmap_base; 2306 *reg = RK3308_PULL_OFFSET; 2307 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2308 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2309 2310 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2311 *bit *= RK3188_PULL_BITS_PER_PIN; 2312 } 2313 2314 #define RK3308_DRV_GRF_OFFSET 0x100 2315 2316 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2317 int pin_num, struct regmap **regmap, 2318 int *reg, u8 *bit) 2319 { 2320 struct rockchip_pinctrl_priv *priv = bank->priv; 2321 2322 *regmap = priv->regmap_base; 2323 *reg = RK3308_DRV_GRF_OFFSET; 2324 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2325 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2326 2327 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2328 *bit *= RK3288_DRV_BITS_PER_PIN; 2329 } 2330 2331 #define RK3308_SCHMITT_PINS_PER_REG 8 2332 #define RK3308_SCHMITT_BANK_STRIDE 16 2333 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 2334 2335 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2336 int pin_num, 2337 struct regmap **regmap, 2338 int *reg, u8 *bit) 2339 { 2340 struct rockchip_pinctrl_priv *priv = bank->priv; 2341 2342 *regmap = priv->regmap_base; 2343 *reg = RK3308_SCHMITT_GRF_OFFSET; 2344 2345 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 2346 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 2347 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 2348 2349 return 0; 2350 } 2351 2352 #define RK3368_PULL_GRF_OFFSET 0x100 2353 #define RK3368_PULL_PMU_OFFSET 0x10 2354 2355 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2356 int pin_num, struct regmap **regmap, 2357 int *reg, u8 *bit) 2358 { 2359 struct rockchip_pinctrl_priv *priv = bank->priv; 2360 2361 /* The first 32 pins of the first bank are located in PMU */ 2362 if (bank->bank_num == 0) { 2363 *regmap = priv->regmap_pmu; 2364 *reg = RK3368_PULL_PMU_OFFSET; 2365 2366 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2367 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2368 *bit *= RK3188_PULL_BITS_PER_PIN; 2369 } else { 2370 *regmap = priv->regmap_base; 2371 *reg = RK3368_PULL_GRF_OFFSET; 2372 2373 /* correct the offset, as we're starting with the 2nd bank */ 2374 *reg -= 0x10; 2375 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2376 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2377 2378 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2379 *bit *= RK3188_PULL_BITS_PER_PIN; 2380 } 2381 } 2382 2383 #define RK3368_DRV_PMU_OFFSET 0x20 2384 #define RK3368_DRV_GRF_OFFSET 0x200 2385 2386 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2387 int pin_num, struct regmap **regmap, 2388 int *reg, u8 *bit) 2389 { 2390 struct rockchip_pinctrl_priv *priv = bank->priv; 2391 2392 /* The first 32 pins of the first bank are located in PMU */ 2393 if (bank->bank_num == 0) { 2394 *regmap = priv->regmap_pmu; 2395 *reg = RK3368_DRV_PMU_OFFSET; 2396 2397 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2398 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2399 *bit *= RK3288_DRV_BITS_PER_PIN; 2400 } else { 2401 *regmap = priv->regmap_base; 2402 *reg = RK3368_DRV_GRF_OFFSET; 2403 2404 /* correct the offset, as we're starting with the 2nd bank */ 2405 *reg -= 0x10; 2406 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2407 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2408 2409 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2410 *bit *= RK3288_DRV_BITS_PER_PIN; 2411 } 2412 } 2413 2414 #define RK3399_PULL_GRF_OFFSET 0xe040 2415 #define RK3399_PULL_PMU_OFFSET 0x40 2416 #define RK3399_DRV_3BITS_PER_PIN 3 2417 2418 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2419 int pin_num, struct regmap **regmap, 2420 int *reg, u8 *bit) 2421 { 2422 struct rockchip_pinctrl_priv *priv = bank->priv; 2423 2424 /* The bank0:16 and bank1:32 pins are located in PMU */ 2425 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2426 *regmap = priv->regmap_pmu; 2427 *reg = RK3399_PULL_PMU_OFFSET; 2428 2429 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2430 2431 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2432 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2433 *bit *= RK3188_PULL_BITS_PER_PIN; 2434 } else { 2435 *regmap = priv->regmap_base; 2436 *reg = RK3399_PULL_GRF_OFFSET; 2437 2438 /* correct the offset, as we're starting with the 3rd bank */ 2439 *reg -= 0x20; 2440 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2441 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2442 2443 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2444 *bit *= RK3188_PULL_BITS_PER_PIN; 2445 } 2446 } 2447 2448 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2449 int pin_num, struct regmap **regmap, 2450 int *reg, u8 *bit) 2451 { 2452 struct rockchip_pinctrl_priv *priv = bank->priv; 2453 int drv_num = (pin_num / 8); 2454 2455 /* The bank0:16 and bank1:32 pins are located in PMU */ 2456 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2457 *regmap = priv->regmap_pmu; 2458 else 2459 *regmap = priv->regmap_base; 2460 2461 *reg = bank->drv[drv_num].offset; 2462 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2463 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2464 *bit = (pin_num % 8) * 3; 2465 else 2466 *bit = (pin_num % 8) * 2; 2467 } 2468 2469 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2470 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2471 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2472 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2473 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2474 { 4, 7, 10, 13, 16, 19, 22, 26 } 2475 }; 2476 2477 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2478 int pin_num, int strength) 2479 { 2480 struct rockchip_pinctrl_priv *priv = bank->priv; 2481 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2482 struct regmap *regmap; 2483 int reg, ret, i; 2484 u32 data, rmask_bits, temp; 2485 u8 bit; 2486 /* Where need to clean the special mask for rockchip_perpin_drv_list */ 2487 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); 2488 2489 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 2490 pin_num, strength); 2491 2492 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2493 if (ctrl->type == RV1126) { 2494 rmask_bits = RV1126_DRV_BITS_PER_PIN; 2495 ret = strength; 2496 goto config; 2497 } 2498 2499 ret = -EINVAL; 2500 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2501 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2502 ret = i; 2503 break; 2504 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2505 ret = rockchip_perpin_drv_list[drv_type][i]; 2506 break; 2507 } 2508 } 2509 2510 if (ret < 0) { 2511 debug("unsupported driver strength %d\n", strength); 2512 return ret; 2513 } 2514 2515 switch (drv_type) { 2516 case DRV_TYPE_IO_1V8_3V0_AUTO: 2517 case DRV_TYPE_IO_3V3_ONLY: 2518 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2519 switch (bit) { 2520 case 0 ... 12: 2521 /* regular case, nothing to do */ 2522 break; 2523 case 15: 2524 /* 2525 * drive-strength offset is special, as it is spread 2526 * over 2 registers, the bit data[15] contains bit 0 2527 * of the value while temp[1:0] contains bits 2 and 1 2528 */ 2529 data = (ret & 0x1) << 15; 2530 temp = (ret >> 0x1) & 0x3; 2531 2532 data |= BIT(31); 2533 ret = regmap_write(regmap, reg, data); 2534 if (ret) 2535 return ret; 2536 2537 temp |= (0x3 << 16); 2538 reg += 0x4; 2539 ret = regmap_write(regmap, reg, temp); 2540 2541 return ret; 2542 case 18 ... 21: 2543 /* setting fully enclosed in the second register */ 2544 reg += 4; 2545 bit -= 16; 2546 break; 2547 default: 2548 debug("unsupported bit: %d for pinctrl drive type: %d\n", 2549 bit, drv_type); 2550 return -EINVAL; 2551 } 2552 break; 2553 case DRV_TYPE_IO_DEFAULT: 2554 case DRV_TYPE_IO_1V8_OR_3V0: 2555 case DRV_TYPE_IO_1V8_ONLY: 2556 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2557 break; 2558 default: 2559 debug("unsupported pinctrl drive type: %d\n", 2560 drv_type); 2561 return -EINVAL; 2562 } 2563 2564 config: 2565 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 2566 regmap_read(regmap, reg, &data); 2567 data &= ~(((1 << rmask_bits) - 1) << bit); 2568 } else { 2569 /* enable the write to the equivalent lower bits */ 2570 data = ((1 << rmask_bits) - 1) << (bit + 16); 2571 } 2572 2573 data |= (ret << bit); 2574 ret = regmap_write(regmap, reg, data); 2575 return ret; 2576 } 2577 2578 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2579 { 2580 PIN_CONFIG_BIAS_DISABLE, 2581 PIN_CONFIG_BIAS_PULL_UP, 2582 PIN_CONFIG_BIAS_PULL_DOWN, 2583 PIN_CONFIG_BIAS_BUS_HOLD 2584 }, 2585 { 2586 PIN_CONFIG_BIAS_DISABLE, 2587 PIN_CONFIG_BIAS_PULL_DOWN, 2588 PIN_CONFIG_BIAS_DISABLE, 2589 PIN_CONFIG_BIAS_PULL_UP 2590 }, 2591 }; 2592 2593 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2594 int pin_num, int pull) 2595 { 2596 struct rockchip_pinctrl_priv *priv = bank->priv; 2597 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2598 struct regmap *regmap; 2599 int reg, ret, i, pull_type; 2600 u8 bit; 2601 u32 data; 2602 2603 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 2604 pin_num, pull); 2605 2606 /* rk3066b does support any pulls */ 2607 if (ctrl->type == RK3066B) 2608 return pull ? -EINVAL : 0; 2609 2610 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2611 2612 switch (ctrl->type) { 2613 case RK2928: 2614 case RK3128: 2615 data = BIT(bit + 16); 2616 if (pull == PIN_CONFIG_BIAS_DISABLE) 2617 data |= BIT(bit); 2618 ret = regmap_write(regmap, reg, data); 2619 break; 2620 case PX30: 2621 case RV1108: 2622 case RV1126: 2623 case RK1808: 2624 case RK3188: 2625 case RK3288: 2626 case RK3308: 2627 case RK3368: 2628 case RK3399: 2629 /* 2630 * Where need to clean the special mask for 2631 * rockchip_pull_list. 2632 */ 2633 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); 2634 ret = -EINVAL; 2635 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2636 i++) { 2637 if (rockchip_pull_list[pull_type][i] == pull) { 2638 ret = i; 2639 break; 2640 } 2641 } 2642 2643 if (ret < 0) { 2644 debug("unsupported pull setting %d\n", pull); 2645 return ret; 2646 } 2647 2648 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 2649 regmap_read(regmap, reg, &data); 2650 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); 2651 } else { 2652 /* enable the write to the equivalent lower bits */ 2653 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2654 } 2655 2656 data |= (ret << bit); 2657 ret = regmap_write(regmap, reg, data); 2658 break; 2659 default: 2660 debug("unsupported pinctrl type\n"); 2661 return -EINVAL; 2662 } 2663 2664 return ret; 2665 } 2666 2667 #define RK3328_SCHMITT_BITS_PER_PIN 1 2668 #define RK3328_SCHMITT_PINS_PER_REG 16 2669 #define RK3328_SCHMITT_BANK_STRIDE 8 2670 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2671 2672 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2673 int pin_num, 2674 struct regmap **regmap, 2675 int *reg, u8 *bit) 2676 { 2677 struct rockchip_pinctrl_priv *priv = bank->priv; 2678 2679 *regmap = priv->regmap_base; 2680 *reg = RK3328_SCHMITT_GRF_OFFSET; 2681 2682 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2683 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2684 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2685 2686 return 0; 2687 } 2688 2689 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2690 int pin_num, int enable) 2691 { 2692 struct rockchip_pinctrl_priv *priv = bank->priv; 2693 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2694 struct regmap *regmap; 2695 int reg, ret; 2696 u8 bit; 2697 u32 data; 2698 2699 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 2700 pin_num, enable); 2701 2702 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2703 if (ret) 2704 return ret; 2705 2706 /* enable the write to the equivalent lower bits */ 2707 data = BIT(bit + 16) | (enable << bit); 2708 2709 return regmap_write(regmap, reg, data); 2710 } 2711 2712 #define PX30_SLEW_RATE_PMU_OFFSET 0x30 2713 #define PX30_SLEW_RATE_GRF_OFFSET 0x90 2714 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16 2715 #define PX30_SLEW_RATE_BANK_STRIDE 16 2716 #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8 2717 2718 static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, 2719 int pin_num, 2720 struct regmap **regmap, 2721 int *reg, u8 *bit) 2722 { 2723 struct rockchip_pinctrl_priv *priv = bank->priv; 2724 int pins_per_reg; 2725 2726 if (bank->bank_num == 0) { 2727 *regmap = priv->regmap_pmu; 2728 *reg = PX30_SLEW_RATE_PMU_OFFSET; 2729 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 2730 } else { 2731 *regmap = priv->regmap_base; 2732 *reg = PX30_SCHMITT_GRF_OFFSET; 2733 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 2734 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 2735 } 2736 *reg += ((pin_num / pins_per_reg) * 4); 2737 *bit = pin_num % pins_per_reg; 2738 2739 return 0; 2740 } 2741 2742 static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank, 2743 int pin_num, int speed) 2744 { 2745 struct rockchip_pinctrl_priv *priv = bank->priv; 2746 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2747 struct regmap *regmap; 2748 int reg, ret; 2749 u8 bit; 2750 u32 data; 2751 2752 debug("setting slew rate of GPIO%d-%d to %d\n", bank->bank_num, 2753 pin_num, speed); 2754 2755 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit); 2756 if (ret) 2757 return ret; 2758 2759 /* enable the write to the equivalent lower bits */ 2760 data = BIT(bit + 16) | (speed << bit); 2761 2762 return regmap_write(regmap, reg, data); 2763 } 2764 2765 /* 2766 * Pinconf_ops handling 2767 */ 2768 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2769 unsigned int pull) 2770 { 2771 switch (ctrl->type) { 2772 case RK2928: 2773 case RK3128: 2774 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2775 pull == PIN_CONFIG_BIAS_DISABLE); 2776 case RK3066B: 2777 return pull ? false : true; 2778 case PX30: 2779 case RV1108: 2780 case RV1126: 2781 case RK1808: 2782 case RK3188: 2783 case RK3288: 2784 case RK3308: 2785 case RK3368: 2786 case RK3399: 2787 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2788 } 2789 2790 return false; 2791 } 2792 2793 /* set the pin config settings for a specified pin */ 2794 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 2795 u32 pin, u32 param, u32 arg) 2796 { 2797 struct rockchip_pinctrl_priv *priv = bank->priv; 2798 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2799 int rc; 2800 2801 switch (param) { 2802 case PIN_CONFIG_BIAS_DISABLE: 2803 rc = rockchip_set_pull(bank, pin, param); 2804 if (rc) 2805 return rc; 2806 break; 2807 2808 case PIN_CONFIG_BIAS_PULL_UP: 2809 case PIN_CONFIG_BIAS_PULL_DOWN: 2810 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2811 case PIN_CONFIG_BIAS_BUS_HOLD: 2812 if (!rockchip_pinconf_pull_valid(ctrl, param)) 2813 return -ENOTSUPP; 2814 2815 if (!arg) 2816 return -EINVAL; 2817 2818 rc = rockchip_set_pull(bank, pin, param); 2819 if (rc) 2820 return rc; 2821 break; 2822 2823 case PIN_CONFIG_DRIVE_STRENGTH: 2824 if (!ctrl->drv_calc_reg) 2825 return -ENOTSUPP; 2826 2827 rc = rockchip_set_drive_perpin(bank, pin, arg); 2828 if (rc < 0) 2829 return rc; 2830 break; 2831 2832 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2833 if (!ctrl->schmitt_calc_reg) 2834 return -ENOTSUPP; 2835 2836 rc = rockchip_set_schmitt(bank, pin, arg); 2837 if (rc < 0) 2838 return rc; 2839 break; 2840 2841 case PIN_CONFIG_SLEW_RATE: 2842 if (!ctrl->slew_rate_calc_reg) 2843 return -ENOTSUPP; 2844 2845 rc = rockchip_set_slew_rate(bank, 2846 pin - bank->pin_base, arg); 2847 if (rc < 0) 2848 return rc; 2849 break; 2850 2851 default: 2852 break; 2853 } 2854 2855 return 0; 2856 } 2857 2858 static const struct pinconf_param rockchip_conf_params[] = { 2859 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 2860 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 2861 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 2862 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 2863 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 2864 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 2865 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 2866 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 2867 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 2868 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, 2869 }; 2870 2871 static int rockchip_pinconf_prop_name_to_param(const char *property, 2872 u32 *default_value) 2873 { 2874 const struct pinconf_param *p, *end; 2875 2876 p = rockchip_conf_params; 2877 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 2878 2879 /* See if this pctldev supports this parameter */ 2880 for (; p < end; p++) { 2881 if (!strcmp(property, p->property)) { 2882 *default_value = p->default_value; 2883 return p->param; 2884 } 2885 } 2886 2887 *default_value = 0; 2888 return -EPERM; 2889 } 2890 2891 static int rockchip_pinctrl_set_state(struct udevice *dev, 2892 struct udevice *config) 2893 { 2894 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2895 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2896 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 2897 u32 bank, pin, mux, conf, arg, default_val; 2898 int ret, count, i; 2899 const char *prop_name; 2900 const void *value; 2901 int prop_len, param; 2902 const u32 *data; 2903 ofnode node; 2904 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 2905 const struct device_node *np; 2906 struct property *pp; 2907 #else 2908 int property_offset, pcfg_node; 2909 const void *blob = gd->fdt_blob; 2910 #endif 2911 data = dev_read_prop(config, "rockchip,pins", &count); 2912 if (count < 0) { 2913 debug("%s: bad array size %d\n", __func__, count); 2914 return -EINVAL; 2915 } 2916 2917 count /= sizeof(u32); 2918 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2919 debug("%s: unsupported pins array count %d\n", 2920 __func__, count); 2921 return -EINVAL; 2922 } 2923 2924 for (i = 0; i < count; i++) 2925 cells[i] = fdt32_to_cpu(data[i]); 2926 2927 for (i = 0; i < (count >> 2); i++) { 2928 bank = cells[4 * i + 0]; 2929 pin = cells[4 * i + 1]; 2930 mux = cells[4 * i + 2]; 2931 conf = cells[4 * i + 3]; 2932 2933 ret = rockchip_verify_config(dev, bank, pin); 2934 if (ret) 2935 return ret; 2936 2937 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2938 if (ret) 2939 return ret; 2940 2941 node = ofnode_get_by_phandle(conf); 2942 if (!ofnode_valid(node)) 2943 return -ENODEV; 2944 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 2945 np = ofnode_to_np(node); 2946 for (pp = np->properties; pp; pp = pp->next) { 2947 prop_name = pp->name; 2948 prop_len = pp->length; 2949 value = pp->value; 2950 #else 2951 pcfg_node = ofnode_to_offset(node); 2952 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2953 value = fdt_getprop_by_offset(blob, property_offset, 2954 &prop_name, &prop_len); 2955 if (!value) 2956 return -ENOENT; 2957 #endif 2958 param = rockchip_pinconf_prop_name_to_param(prop_name, 2959 &default_val); 2960 if (param < 0) 2961 break; 2962 2963 if (prop_len >= sizeof(fdt32_t)) 2964 arg = fdt32_to_cpu(*(fdt32_t *)value); 2965 else 2966 arg = default_val; 2967 2968 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2969 param, arg); 2970 if (ret) { 2971 debug("%s: rockchip_pinconf_set fail: %d\n", 2972 __func__, ret); 2973 return ret; 2974 } 2975 } 2976 } 2977 2978 return 0; 2979 } 2980 2981 static int rockchip_pinctrl_get_pins_count(struct udevice *dev) 2982 { 2983 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2984 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2985 2986 return ctrl->nr_pins; 2987 } 2988 2989 static struct pinctrl_ops rockchip_pinctrl_ops = { 2990 .get_pins_count = rockchip_pinctrl_get_pins_count, 2991 .set_state = rockchip_pinctrl_set_state, 2992 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2993 }; 2994 2995 static const struct rockchip_pin_ctrl rk3308b_pin_ctrl; 2996 2997 /* retrieve the soc specific data */ 2998 static const struct rockchip_pin_ctrl * 2999 rockchip_pinctrl_get_soc_data(struct udevice *dev) 3000 { 3001 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 3002 const struct rockchip_pin_ctrl *ctrl = 3003 (const struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 3004 struct rockchip_pin_bank *bank; 3005 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3006 u32 nr_pins; 3007 3008 if (soc_is_rk3308b()) 3009 ctrl = &rk3308b_pin_ctrl; 3010 3011 grf_offs = ctrl->grf_mux_offset; 3012 pmu_offs = ctrl->pmu_mux_offset; 3013 drv_pmu_offs = ctrl->pmu_drv_offset; 3014 drv_grf_offs = ctrl->grf_drv_offset; 3015 bank = ctrl->pin_banks; 3016 3017 /* Ctrl data re-initialize for some Socs */ 3018 if (ctrl->ctrl_data_re_init) { 3019 if (ctrl->ctrl_data_re_init(ctrl)) 3020 return NULL; 3021 } 3022 3023 nr_pins = 0; 3024 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3025 int bank_pins = 0; 3026 3027 bank->priv = priv; 3028 bank->pin_base = nr_pins; 3029 nr_pins += bank->nr_pins; 3030 3031 /* calculate iomux and drv offsets */ 3032 for (j = 0; j < 4; j++) { 3033 struct rockchip_iomux *iom = &bank->iomux[j]; 3034 struct rockchip_drv *drv = &bank->drv[j]; 3035 int inc; 3036 3037 if (bank_pins >= bank->nr_pins) 3038 break; 3039 3040 /* preset iomux offset value, set new start value */ 3041 if (iom->offset >= 0) { 3042 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 3043 pmu_offs = iom->offset; 3044 else 3045 grf_offs = iom->offset; 3046 } else { /* set current iomux offset */ 3047 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || 3048 (iom->type & IOMUX_L_SOURCE_PMU)) ? 3049 pmu_offs : grf_offs; 3050 } 3051 3052 /* preset drv offset value, set new start value */ 3053 if (drv->offset >= 0) { 3054 if (iom->type & IOMUX_SOURCE_PMU) 3055 drv_pmu_offs = drv->offset; 3056 else 3057 drv_grf_offs = drv->offset; 3058 } else { /* set current drv offset */ 3059 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3060 drv_pmu_offs : drv_grf_offs; 3061 } 3062 3063 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3064 i, j, iom->offset, drv->offset); 3065 3066 /* 3067 * Increase offset according to iomux width. 3068 * 4bit iomux'es are spread over two registers. 3069 */ 3070 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3071 IOMUX_WIDTH_3BIT | 3072 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 3073 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 3074 pmu_offs += inc; 3075 else 3076 grf_offs += inc; 3077 3078 /* 3079 * Increase offset according to drv width. 3080 * 3bit drive-strenth'es are spread over two registers. 3081 */ 3082 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3083 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3084 inc = 8; 3085 else 3086 inc = 4; 3087 3088 if (iom->type & IOMUX_SOURCE_PMU) 3089 drv_pmu_offs += inc; 3090 else 3091 drv_grf_offs += inc; 3092 3093 bank_pins += 8; 3094 } 3095 3096 /* calculate the per-bank recalced_mask */ 3097 for (j = 0; j < ctrl->niomux_recalced; j++) { 3098 int pin = 0; 3099 3100 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3101 pin = ctrl->iomux_recalced[j].pin; 3102 bank->recalced_mask |= BIT(pin); 3103 } 3104 } 3105 3106 /* calculate the per-bank route_mask */ 3107 for (j = 0; j < ctrl->niomux_routes; j++) { 3108 int pin = 0; 3109 3110 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3111 pin = ctrl->iomux_routes[j].pin; 3112 bank->route_mask |= BIT(pin); 3113 } 3114 } 3115 } 3116 3117 WARN_ON(nr_pins != ctrl->nr_pins); 3118 3119 return ctrl; 3120 } 3121 3122 /* SoC data specially handle */ 3123 3124 /* rk3308b SoC data initialize */ 3125 #define RK3308B_GRF_SOC_CON13 0x608 3126 #define RK3308B_GRF_SOC_CON15 0x610 3127 3128 /* RK3308B_GRF_SOC_CON13 */ 3129 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) 3130 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 3131 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 3132 3133 /* RK3308B_GRF_SOC_CON15 */ 3134 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) 3135 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 3136 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 3137 3138 static int rk3308b_soc_data_init(struct rockchip_pinctrl_priv *priv) 3139 { 3140 int ret; 3141 3142 /* 3143 * Enable the special ctrl of selected sources. 3144 */ 3145 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13, 3146 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | 3147 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | 3148 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); 3149 if (ret) 3150 return ret; 3151 3152 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15, 3153 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | 3154 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | 3155 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); 3156 if (ret) 3157 return ret; 3158 3159 return 0; 3160 } 3161 3162 static int rockchip_pinctrl_probe(struct udevice *dev) 3163 { 3164 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 3165 const struct rockchip_pin_ctrl *ctrl; 3166 struct udevice *syscon; 3167 struct regmap *regmap; 3168 int ret = 0; 3169 3170 /* get rockchip grf syscon phandle */ 3171 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 3172 &syscon); 3173 if (ret) { 3174 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 3175 return ret; 3176 } 3177 3178 /* get grf-reg base address */ 3179 regmap = syscon_get_regmap(syscon); 3180 if (!regmap) { 3181 debug("unable to find rockchip grf regmap\n"); 3182 return -ENODEV; 3183 } 3184 priv->regmap_base = regmap; 3185 3186 /* option: get pmu-reg base address */ 3187 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 3188 &syscon); 3189 if (!ret) { 3190 /* get pmugrf-reg base address */ 3191 regmap = syscon_get_regmap(syscon); 3192 if (!regmap) { 3193 debug("unable to find rockchip pmu regmap\n"); 3194 return -ENODEV; 3195 } 3196 priv->regmap_pmu = regmap; 3197 } 3198 3199 ctrl = rockchip_pinctrl_get_soc_data(dev); 3200 if (!ctrl) { 3201 debug("driver data not available\n"); 3202 return -EINVAL; 3203 } 3204 3205 /* Special handle for some Socs */ 3206 if (ctrl->soc_data_init) { 3207 ret = ctrl->soc_data_init(priv); 3208 if (ret) 3209 return ret; 3210 } 3211 3212 priv->ctrl = (struct rockchip_pin_ctrl *)ctrl; 3213 return 0; 3214 } 3215 3216 static struct rockchip_pin_bank px30_pin_banks[] = { 3217 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3218 IOMUX_SOURCE_PMU, 3219 IOMUX_SOURCE_PMU, 3220 IOMUX_SOURCE_PMU 3221 ), 3222 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3223 IOMUX_WIDTH_4BIT, 3224 IOMUX_WIDTH_4BIT, 3225 IOMUX_WIDTH_4BIT 3226 ), 3227 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3228 IOMUX_WIDTH_4BIT, 3229 IOMUX_WIDTH_4BIT, 3230 IOMUX_WIDTH_4BIT 3231 ), 3232 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3233 IOMUX_WIDTH_4BIT, 3234 IOMUX_WIDTH_4BIT, 3235 IOMUX_WIDTH_4BIT 3236 ), 3237 }; 3238 3239 static const struct rockchip_pin_ctrl px30_pin_ctrl = { 3240 .pin_banks = px30_pin_banks, 3241 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3242 .nr_pins = 128, 3243 .label = "PX30-GPIO", 3244 .type = PX30, 3245 .grf_mux_offset = 0x0, 3246 .pmu_mux_offset = 0x0, 3247 .iomux_routes = px30_mux_route_data, 3248 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3249 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3250 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3251 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3252 .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit, 3253 }; 3254 3255 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3256 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3257 IOMUX_SOURCE_PMU, 3258 IOMUX_SOURCE_PMU, 3259 IOMUX_SOURCE_PMU), 3260 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3261 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3262 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3263 }; 3264 3265 static const struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3266 .pin_banks = rv1108_pin_banks, 3267 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3268 .nr_pins = 128, 3269 .label = "RV1108-GPIO", 3270 .type = RV1108, 3271 .grf_mux_offset = 0x10, 3272 .pmu_mux_offset = 0x0, 3273 .iomux_recalced = rv1108_mux_recalced_data, 3274 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3275 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3276 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3277 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3278 }; 3279 3280 static struct rockchip_pin_bank rv1126_pin_banks[] = { 3281 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3282 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3283 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3284 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 3285 IOMUX_WIDTH_4BIT), 3286 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 3287 IOMUX_WIDTH_4BIT, 3288 IOMUX_WIDTH_4BIT, 3289 IOMUX_WIDTH_4BIT, 3290 IOMUX_WIDTH_4BIT, 3291 0x10010, 0x10018, 0x10020, 0x10028), 3292 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3293 IOMUX_WIDTH_4BIT, 3294 IOMUX_WIDTH_4BIT, 3295 IOMUX_WIDTH_4BIT, 3296 IOMUX_WIDTH_4BIT), 3297 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3298 IOMUX_WIDTH_4BIT, 3299 IOMUX_WIDTH_4BIT, 3300 IOMUX_WIDTH_4BIT, 3301 IOMUX_WIDTH_4BIT), 3302 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 3303 IOMUX_WIDTH_4BIT, 0, 0, 0), 3304 }; 3305 3306 static const struct rockchip_pin_ctrl rv1126_pin_ctrl = { 3307 .pin_banks = rv1126_pin_banks, 3308 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 3309 .nr_pins = 130, 3310 .label = "RV1126-GPIO", 3311 .type = RV1126, 3312 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 3313 .pmu_mux_offset = 0x0, 3314 .iomux_routes = rv1126_mux_route_data, 3315 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), 3316 .iomux_recalced = rv1126_mux_recalced_data, 3317 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 3318 .pull_calc_reg = rv1126_calc_pull_reg_and_bit, 3319 .drv_calc_reg = rv1126_calc_drv_reg_and_bit, 3320 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit, 3321 }; 3322 3323 static struct rockchip_pin_bank rk1808_pin_banks[] = { 3324 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3325 IOMUX_SOURCE_PMU, 3326 IOMUX_SOURCE_PMU, 3327 IOMUX_SOURCE_PMU, 3328 IOMUX_SOURCE_PMU), 3329 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 3330 IOMUX_WIDTH_4BIT, 3331 IOMUX_WIDTH_4BIT, 3332 IOMUX_WIDTH_4BIT, 3333 IOMUX_WIDTH_4BIT), 3334 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3335 IOMUX_WIDTH_4BIT, 3336 IOMUX_WIDTH_4BIT, 3337 IOMUX_WIDTH_4BIT, 3338 IOMUX_WIDTH_4BIT), 3339 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3340 IOMUX_WIDTH_4BIT, 3341 IOMUX_WIDTH_4BIT, 3342 IOMUX_WIDTH_4BIT, 3343 IOMUX_WIDTH_4BIT), 3344 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", 3345 IOMUX_WIDTH_4BIT, 3346 IOMUX_WIDTH_4BIT, 3347 IOMUX_WIDTH_4BIT, 3348 IOMUX_WIDTH_4BIT), 3349 }; 3350 3351 static const struct rockchip_pin_ctrl rk1808_pin_ctrl = { 3352 .pin_banks = rk1808_pin_banks, 3353 .nr_banks = ARRAY_SIZE(rk1808_pin_banks), 3354 .nr_pins = 160, 3355 .label = "RK1808-GPIO", 3356 .type = RK1808, 3357 .iomux_routes = rk1808_mux_route_data, 3358 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data), 3359 .grf_mux_offset = 0x0, 3360 .pmu_mux_offset = 0x0, 3361 .pull_calc_reg = rk1808_calc_pull_reg_and_bit, 3362 .drv_calc_reg = rk1808_calc_drv_reg_and_bit, 3363 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit, 3364 }; 3365 3366 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3367 PIN_BANK(0, 32, "gpio0"), 3368 PIN_BANK(1, 32, "gpio1"), 3369 PIN_BANK(2, 32, "gpio2"), 3370 PIN_BANK(3, 32, "gpio3"), 3371 }; 3372 3373 static const struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3374 .pin_banks = rk2928_pin_banks, 3375 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3376 .nr_pins = 128, 3377 .label = "RK2928-GPIO", 3378 .type = RK2928, 3379 .grf_mux_offset = 0xa8, 3380 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3381 }; 3382 3383 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3384 PIN_BANK(0, 32, "gpio0"), 3385 PIN_BANK(1, 32, "gpio1"), 3386 PIN_BANK(2, 32, "gpio2"), 3387 }; 3388 3389 static const struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3390 .pin_banks = rk3036_pin_banks, 3391 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3392 .nr_pins = 96, 3393 .label = "RK3036-GPIO", 3394 .type = RK2928, 3395 .grf_mux_offset = 0xa8, 3396 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3397 }; 3398 3399 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3400 PIN_BANK(0, 32, "gpio0"), 3401 PIN_BANK(1, 32, "gpio1"), 3402 PIN_BANK(2, 32, "gpio2"), 3403 PIN_BANK(3, 32, "gpio3"), 3404 PIN_BANK(4, 32, "gpio4"), 3405 PIN_BANK(6, 16, "gpio6"), 3406 }; 3407 3408 static const struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3409 .pin_banks = rk3066a_pin_banks, 3410 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3411 .nr_pins = 176, 3412 .label = "RK3066a-GPIO", 3413 .type = RK2928, 3414 .grf_mux_offset = 0xa8, 3415 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3416 }; 3417 3418 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3419 PIN_BANK(0, 32, "gpio0"), 3420 PIN_BANK(1, 32, "gpio1"), 3421 PIN_BANK(2, 32, "gpio2"), 3422 PIN_BANK(3, 32, "gpio3"), 3423 }; 3424 3425 static const struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3426 .pin_banks = rk3066b_pin_banks, 3427 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3428 .nr_pins = 128, 3429 .label = "RK3066b-GPIO", 3430 .type = RK3066B, 3431 .grf_mux_offset = 0x60, 3432 }; 3433 3434 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3435 PIN_BANK(0, 32, "gpio0"), 3436 PIN_BANK(1, 32, "gpio1"), 3437 PIN_BANK(2, 32, "gpio2"), 3438 PIN_BANK(3, 32, "gpio3"), 3439 }; 3440 3441 static const struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3442 .pin_banks = rk3128_pin_banks, 3443 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3444 .nr_pins = 128, 3445 .label = "RK3128-GPIO", 3446 .type = RK3128, 3447 .grf_mux_offset = 0xa8, 3448 .iomux_recalced = rk3128_mux_recalced_data, 3449 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3450 .iomux_routes = rk3128_mux_route_data, 3451 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3452 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3453 }; 3454 3455 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3456 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3457 PIN_BANK(1, 32, "gpio1"), 3458 PIN_BANK(2, 32, "gpio2"), 3459 PIN_BANK(3, 32, "gpio3"), 3460 }; 3461 3462 static const struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3463 .pin_banks = rk3188_pin_banks, 3464 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3465 .nr_pins = 128, 3466 .label = "RK3188-GPIO", 3467 .type = RK3188, 3468 .grf_mux_offset = 0x60, 3469 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3470 }; 3471 3472 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3473 PIN_BANK(0, 32, "gpio0"), 3474 PIN_BANK(1, 32, "gpio1"), 3475 PIN_BANK(2, 32, "gpio2"), 3476 PIN_BANK(3, 32, "gpio3"), 3477 }; 3478 3479 static const struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3480 .pin_banks = rk3228_pin_banks, 3481 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3482 .nr_pins = 128, 3483 .label = "RK3228-GPIO", 3484 .type = RK3288, 3485 .grf_mux_offset = 0x0, 3486 .iomux_routes = rk3228_mux_route_data, 3487 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3488 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3489 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3490 }; 3491 3492 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3493 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 3494 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3495 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3496 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3497 IOMUX_UNROUTED, 3498 DRV_TYPE_WRITABLE_32BIT, 3499 DRV_TYPE_WRITABLE_32BIT, 3500 DRV_TYPE_WRITABLE_32BIT, 3501 0, 3502 PULL_TYPE_WRITABLE_32BIT, 3503 PULL_TYPE_WRITABLE_32BIT, 3504 PULL_TYPE_WRITABLE_32BIT, 3505 0 3506 ), 3507 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3508 IOMUX_UNROUTED, 3509 IOMUX_UNROUTED, 3510 0 3511 ), 3512 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3513 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3514 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3515 IOMUX_WIDTH_4BIT, 3516 0, 3517 0 3518 ), 3519 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3520 0, 3521 0, 3522 IOMUX_UNROUTED 3523 ), 3524 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3525 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3526 0, 3527 IOMUX_WIDTH_4BIT, 3528 IOMUX_UNROUTED 3529 ), 3530 PIN_BANK(8, 16, "gpio8"), 3531 }; 3532 3533 static const struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3534 .pin_banks = rk3288_pin_banks, 3535 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3536 .nr_pins = 264, 3537 .label = "RK3288-GPIO", 3538 .type = RK3288, 3539 .grf_mux_offset = 0x0, 3540 .pmu_mux_offset = 0x84, 3541 .iomux_routes = rk3288_mux_route_data, 3542 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3543 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3544 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3545 }; 3546 3547 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3548 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 3549 IOMUX_8WIDTH_2BIT, 3550 IOMUX_8WIDTH_2BIT, 3551 IOMUX_8WIDTH_2BIT), 3552 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 3553 IOMUX_8WIDTH_2BIT, 3554 IOMUX_8WIDTH_2BIT, 3555 IOMUX_8WIDTH_2BIT), 3556 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 3557 IOMUX_8WIDTH_2BIT, 3558 IOMUX_8WIDTH_2BIT, 3559 IOMUX_8WIDTH_2BIT), 3560 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 3561 IOMUX_8WIDTH_2BIT, 3562 IOMUX_8WIDTH_2BIT, 3563 IOMUX_8WIDTH_2BIT), 3564 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 3565 IOMUX_8WIDTH_2BIT, 3566 IOMUX_8WIDTH_2BIT, 3567 IOMUX_8WIDTH_2BIT), 3568 }; 3569 3570 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3571 .pin_banks = rk3308_pin_banks, 3572 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3573 .nr_pins = 160, 3574 .label = "RK3308-GPIO", 3575 .type = RK3308, 3576 .grf_mux_offset = 0x0, 3577 .iomux_recalced = rk3308_mux_recalced_data, 3578 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3579 .iomux_routes = rk3308_mux_route_data, 3580 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3581 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3582 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3583 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3584 }; 3585 3586 static const struct rockchip_pin_ctrl rk3308b_pin_ctrl = { 3587 .pin_banks = rk3308_pin_banks, 3588 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3589 .nr_pins = 160, 3590 .label = "RK3308-GPIO", 3591 .type = RK3308, 3592 .grf_mux_offset = 0x0, 3593 .iomux_recalced = rk3308b_mux_recalced_data, 3594 .niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data), 3595 .iomux_routes = rk3308b_mux_route_data, 3596 .niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data), 3597 .soc_data_init = rk3308b_soc_data_init, 3598 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3599 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3600 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3601 }; 3602 3603 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3604 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3605 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3606 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3607 IOMUX_WIDTH_3BIT, 3608 IOMUX_WIDTH_3BIT, 3609 0), 3610 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3611 IOMUX_WIDTH_3BIT, 3612 IOMUX_WIDTH_3BIT, 3613 0, 3614 0), 3615 }; 3616 3617 static const struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3618 .pin_banks = rk3328_pin_banks, 3619 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3620 .nr_pins = 128, 3621 .label = "RK3328-GPIO", 3622 .type = RK3288, 3623 .grf_mux_offset = 0x0, 3624 .iomux_recalced = rk3328_mux_recalced_data, 3625 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3626 .iomux_routes = rk3328_mux_route_data, 3627 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3628 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3629 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3630 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3631 }; 3632 3633 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3634 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3635 IOMUX_SOURCE_PMU, 3636 IOMUX_SOURCE_PMU, 3637 IOMUX_SOURCE_PMU 3638 ), 3639 PIN_BANK(1, 32, "gpio1"), 3640 PIN_BANK(2, 32, "gpio2"), 3641 PIN_BANK(3, 32, "gpio3"), 3642 }; 3643 3644 static const struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3645 .pin_banks = rk3368_pin_banks, 3646 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3647 .nr_pins = 128, 3648 .label = "RK3368-GPIO", 3649 .type = RK3368, 3650 .grf_mux_offset = 0x0, 3651 .pmu_mux_offset = 0x0, 3652 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3653 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3654 }; 3655 3656 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3657 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3658 IOMUX_SOURCE_PMU, 3659 IOMUX_SOURCE_PMU, 3660 IOMUX_SOURCE_PMU, 3661 IOMUX_SOURCE_PMU, 3662 DRV_TYPE_IO_1V8_ONLY, 3663 DRV_TYPE_IO_1V8_ONLY, 3664 DRV_TYPE_IO_DEFAULT, 3665 DRV_TYPE_IO_DEFAULT, 3666 0x80, 3667 0x88, 3668 -1, 3669 -1, 3670 PULL_TYPE_IO_1V8_ONLY, 3671 PULL_TYPE_IO_1V8_ONLY, 3672 PULL_TYPE_IO_DEFAULT, 3673 PULL_TYPE_IO_DEFAULT 3674 ), 3675 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3676 IOMUX_SOURCE_PMU, 3677 IOMUX_SOURCE_PMU, 3678 IOMUX_SOURCE_PMU, 3679 DRV_TYPE_IO_1V8_OR_3V0, 3680 DRV_TYPE_IO_1V8_OR_3V0, 3681 DRV_TYPE_IO_1V8_OR_3V0, 3682 DRV_TYPE_IO_1V8_OR_3V0, 3683 0xa0, 3684 0xa8, 3685 0xb0, 3686 0xb8 3687 ), 3688 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3689 DRV_TYPE_IO_1V8_OR_3V0, 3690 DRV_TYPE_IO_1V8_ONLY, 3691 DRV_TYPE_IO_1V8_ONLY, 3692 PULL_TYPE_IO_DEFAULT, 3693 PULL_TYPE_IO_DEFAULT, 3694 PULL_TYPE_IO_1V8_ONLY, 3695 PULL_TYPE_IO_1V8_ONLY 3696 ), 3697 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3698 DRV_TYPE_IO_3V3_ONLY, 3699 DRV_TYPE_IO_3V3_ONLY, 3700 DRV_TYPE_IO_1V8_OR_3V0 3701 ), 3702 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3703 DRV_TYPE_IO_1V8_3V0_AUTO, 3704 DRV_TYPE_IO_1V8_OR_3V0, 3705 DRV_TYPE_IO_1V8_OR_3V0 3706 ), 3707 }; 3708 3709 static const struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3710 .pin_banks = rk3399_pin_banks, 3711 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3712 .nr_pins = 160, 3713 .label = "RK3399-GPIO", 3714 .type = RK3399, 3715 .grf_mux_offset = 0xe000, 3716 .pmu_mux_offset = 0x0, 3717 .grf_drv_offset = 0xe100, 3718 .pmu_drv_offset = 0x80, 3719 .iomux_routes = rk3399_mux_route_data, 3720 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3721 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3722 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3723 }; 3724 3725 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 3726 { .compatible = "rockchip,px30-pinctrl", 3727 .data = (ulong)&px30_pin_ctrl }, 3728 { .compatible = "rockchip,rv1108-pinctrl", 3729 .data = (ulong)&rv1108_pin_ctrl }, 3730 { .compatible = "rockchip,rv1126-pinctrl-legency", 3731 .data = (ulong)&rv1126_pin_ctrl }, 3732 { .compatible = "rockchip,rk1808-pinctrl", 3733 .data = (ulong)&rk1808_pin_ctrl }, 3734 { .compatible = "rockchip,rk2928-pinctrl", 3735 .data = (ulong)&rk2928_pin_ctrl }, 3736 { .compatible = "rockchip,rk3036-pinctrl", 3737 .data = (ulong)&rk3036_pin_ctrl }, 3738 { .compatible = "rockchip,rk3066a-pinctrl", 3739 .data = (ulong)&rk3066a_pin_ctrl }, 3740 { .compatible = "rockchip,rk3066b-pinctrl", 3741 .data = (ulong)&rk3066b_pin_ctrl }, 3742 { .compatible = "rockchip,rk3128-pinctrl", 3743 .data = (ulong)&rk3128_pin_ctrl }, 3744 { .compatible = "rockchip,rk3188-pinctrl", 3745 .data = (ulong)&rk3188_pin_ctrl }, 3746 { .compatible = "rockchip,rk3228-pinctrl", 3747 .data = (ulong)&rk3228_pin_ctrl }, 3748 { .compatible = "rockchip,rk3288-pinctrl", 3749 .data = (ulong)&rk3288_pin_ctrl }, 3750 { .compatible = "rockchip,rk3308-pinctrl", 3751 .data = (ulong)&rk3308_pin_ctrl }, 3752 { .compatible = "rockchip,rk3328-pinctrl", 3753 .data = (ulong)&rk3328_pin_ctrl }, 3754 { .compatible = "rockchip,rk3368-pinctrl", 3755 .data = (ulong)&rk3368_pin_ctrl }, 3756 { .compatible = "rockchip,rk3399-pinctrl", 3757 .data = (ulong)&rk3399_pin_ctrl }, 3758 {}, 3759 }; 3760 3761 U_BOOT_DRIVER(pinctrl_rockchip) = { 3762 .name = "rockchip_pinctrl", 3763 .id = UCLASS_PINCTRL, 3764 .of_match = rockchip_pinctrl_dt_match, 3765 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 3766 .ops = &rockchip_pinctrl_ops, 3767 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 3768 .bind = dm_scan_fdt_dev, 3769 #endif 3770 .probe = rockchip_pinctrl_probe, 3771 }; 3772