1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <errno.h> 9 #include <i2c.h> 10 #include <max96755f.h> 11 #include <dm/pinctrl.h> 12 13 struct config_desc { 14 u16 reg; 15 u8 mask; 16 u8 val; 17 }; 18 19 struct function_desc { 20 const char *name; 21 const char **group_names; 22 int num_group_names; 23 24 u8 gpio_out_dis:1; 25 u8 gpio_tx_en:1; 26 u8 gpio_rx_en:1; 27 u8 oldi:1; 28 u8 gpio_tx_id; 29 u8 gpio_rx_id; 30 }; 31 32 struct group_desc { 33 const char *name; 34 int *pins; 35 int num_pins; 36 37 const struct config_desc *configs; 38 int num_configs; 39 }; 40 41 struct pin_desc { 42 unsigned int number; 43 const char *name; 44 }; 45 46 static const struct pin_desc max96755f_pins[] = { 47 {0, "gpio0"}, 48 {1, "gpio1"}, 49 {2, "gpio2"}, 50 {3, "gpio3"}, 51 {4, "gpio4"}, 52 {5, "gpio5"}, 53 {6, "gpio6"}, 54 {7, "gpio7"}, 55 {8, "gpio8"}, 56 {9, "gpio9"}, 57 {10, "gpio10"}, 58 {11, "gpio11"}, 59 {12, "gpio12"}, 60 {13, "gpio13"}, 61 {14, "gpio14"}, 62 {15, "gpio15"}, 63 {16, "gpio16"}, 64 {17, "gpio17"}, 65 {18, "gpio18"}, 66 {19, "gpio19"}, 67 {20, "gpio20"}, 68 }; 69 70 static int gpio0_pins[] = {0}; 71 static int gpio1_pins[] = {1}; 72 static int gpio2_pins[] = {2}; 73 static int gpio3_pins[] = {3}; 74 static int gpio4_pins[] = {4}; 75 static int gpio5_pins[] = {5}; 76 static int gpio6_pins[] = {6}; 77 static int gpio7_pins[] = {7}; 78 static int gpio8_pins[] = {8}; 79 static int gpio9_pins[] = {9}; 80 static int gpio10_pins[] = {10}; 81 static int gpio11_pins[] = {11}; 82 static int gpio12_pins[] = {12}; 83 static int gpio13_pins[] = {13}; 84 static int gpio14_pins[] = {14}; 85 static int gpio15_pins[] = {15}; 86 static int gpio16_pins[] = {16}; 87 static int gpio17_pins[] = {17}; 88 static int gpio18_pins[] = {18}; 89 static int gpio19_pins[] = {19}; 90 static int gpio20_pins[] = {20}; 91 static int i2c_pins[] = {19, 20}; 92 static int uart_pins[] = {19, 20}; 93 94 #define GROUP_DESC(nm) \ 95 { \ 96 .name = #nm, \ 97 .pins = nm ## _pins, \ 98 .num_pins = ARRAY_SIZE(nm ## _pins), \ 99 } 100 101 #define GROUP_DESC_CONFIG(nm) \ 102 { \ 103 .name = #nm, \ 104 .pins = nm ## _pins, \ 105 .num_pins = ARRAY_SIZE(nm ## _pins), \ 106 .configs = nm ## _configs, \ 107 .num_configs = ARRAY_SIZE(nm ## _configs), \ 108 } 109 110 static const struct config_desc gpio0_configs[] = { 111 { 0x0005, LOCK_EN, 0 }, 112 { 0x0048, LOC_MS_EN, 0}, 113 }; 114 115 static const struct config_desc gpio1_configs[] = { 116 { 0x0005, ERRB_EN, 0 }, 117 }; 118 119 static const struct config_desc gpio4_configs[] = { 120 { 0x070, SPI_EN, 0 }, 121 }; 122 123 static const struct config_desc gpio5_configs[] = { 124 { 0x006, RCLKEN, 0 }, 125 }; 126 127 static const struct config_desc gpio7_configs[] = { 128 { 0x0002, AUD_TX_EN_X, 0 }, 129 { 0x0002, AUD_TX_EN_Y, 0 } 130 }; 131 132 static const struct config_desc gpio8_configs[] = { 133 { 0x0002, AUD_TX_EN_X, 0 }, 134 { 0x0002, AUD_TX_EN_Y, 0 } 135 }; 136 137 static const struct config_desc gpio9_configs[] = { 138 { 0x0002, AUD_TX_EN_X, 0 }, 139 { 0x0002, AUD_TX_EN_Y, 0 } 140 }; 141 142 static const struct config_desc gpio10_configs[] = { 143 { 0x0001, IIC_2_EN, 0 }, 144 { 0x0003, UART_2_EN, 0 }, 145 { 0x0140, AUD_RX_EN, 0}, 146 }; 147 148 static const struct config_desc gpio11_configs[] = { 149 { 0x0001, IIC_2_EN, 0 }, 150 { 0x0003, UART_2_EN, 0 }, 151 { 0x0140, AUD_RX_EN, 0}, 152 }; 153 154 static const struct config_desc gpio12_configs[] = { 155 { 0x0140, AUD_RX_EN, 0 }, 156 }; 157 158 static const struct config_desc gpio13_configs[] = { 159 { 0x0005, PU_LF0, 0 }, 160 }; 161 162 static const struct config_desc gpio14_configs[] = { 163 { 0x0005, PU_LF1, 0 }, 164 }; 165 166 static const struct config_desc gpio15_configs[] = { 167 { 0x0005, PU_LF2, 0 }, 168 }; 169 170 static const struct config_desc gpio16_configs[] = { 171 { 0x0005, PU_LF3, 0 }, 172 }; 173 174 static const struct config_desc gpio17_configs[] = { 175 { 0x0001, IIC_1_EN, 0 }, 176 { 0x0003, UART_1_EN, 0 }, 177 }; 178 179 static const struct config_desc gpio18_configs[] = { 180 { 0x0001, IIC_1_EN, 0 }, 181 { 0x0003, UART_1_EN, 0 }, 182 }; 183 184 static const struct group_desc max96755f_groups[] = { 185 GROUP_DESC_CONFIG(gpio0), 186 GROUP_DESC_CONFIG(gpio1), 187 GROUP_DESC(gpio2), 188 GROUP_DESC(gpio3), 189 GROUP_DESC_CONFIG(gpio4), 190 GROUP_DESC_CONFIG(gpio5), 191 GROUP_DESC(gpio6), 192 GROUP_DESC_CONFIG(gpio7), 193 GROUP_DESC_CONFIG(gpio8), 194 GROUP_DESC_CONFIG(gpio9), 195 GROUP_DESC_CONFIG(gpio10), 196 GROUP_DESC_CONFIG(gpio11), 197 GROUP_DESC_CONFIG(gpio12), 198 GROUP_DESC_CONFIG(gpio13), 199 GROUP_DESC_CONFIG(gpio14), 200 GROUP_DESC_CONFIG(gpio15), 201 GROUP_DESC_CONFIG(gpio16), 202 GROUP_DESC_CONFIG(gpio17), 203 GROUP_DESC_CONFIG(gpio18), 204 GROUP_DESC(gpio19), 205 GROUP_DESC(gpio20), 206 GROUP_DESC(i2c), 207 GROUP_DESC(uart), 208 }; 209 210 static const char *gpio_groups[] = { 211 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 212 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", 213 "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", 214 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", 215 }; 216 217 static const char *i2c_groups[] = { "i2c" }; 218 static const char *uart_groups[] = { "uart" }; 219 220 #define FUNCTION_DESC(fname, gname) \ 221 { \ 222 .name = #fname, \ 223 .group_names = gname##_groups, \ 224 .num_group_names = ARRAY_SIZE(gname##_groups), \ 225 } \ 226 227 #define FUNCTION_DESC_GPIO_RX(id) \ 228 { \ 229 .name = "GPIO_RX_"#id, \ 230 .group_names = gpio_groups, \ 231 .num_group_names = ARRAY_SIZE(gpio_groups), \ 232 .gpio_rx_en = 1, \ 233 .gpio_rx_id = id, \ 234 } \ 235 236 #define FUNCTION_DESC_GPIO_TX(id) \ 237 { \ 238 .name = "GPIO_TX_"#id, \ 239 .group_names = gpio_groups, \ 240 .num_group_names = ARRAY_SIZE(gpio_groups), \ 241 .gpio_out_dis = 1, \ 242 .gpio_tx_en = 1, \ 243 .gpio_tx_id = id \ 244 } \ 245 246 #define FUNCTION_DESC_GPIO() \ 247 { \ 248 .name = "GPIO", \ 249 .group_names = gpio_groups, \ 250 .num_group_names = ARRAY_SIZE(gpio_groups), \ 251 } \ 252 253 static const struct function_desc max96755f_functions[] = { 254 FUNCTION_DESC_GPIO_TX(0), 255 FUNCTION_DESC_GPIO_TX(1), 256 FUNCTION_DESC_GPIO_TX(2), 257 FUNCTION_DESC_GPIO_TX(3), 258 FUNCTION_DESC_GPIO_TX(4), 259 FUNCTION_DESC_GPIO_TX(5), 260 FUNCTION_DESC_GPIO_TX(6), 261 FUNCTION_DESC_GPIO_TX(7), 262 FUNCTION_DESC_GPIO_TX(8), 263 FUNCTION_DESC_GPIO_TX(9), 264 FUNCTION_DESC_GPIO_TX(10), 265 FUNCTION_DESC_GPIO_TX(11), 266 FUNCTION_DESC_GPIO_TX(12), 267 FUNCTION_DESC_GPIO_TX(13), 268 FUNCTION_DESC_GPIO_TX(14), 269 FUNCTION_DESC_GPIO_TX(15), 270 FUNCTION_DESC_GPIO_TX(16), 271 FUNCTION_DESC_GPIO_TX(17), 272 FUNCTION_DESC_GPIO_TX(18), 273 FUNCTION_DESC_GPIO_TX(19), 274 FUNCTION_DESC_GPIO_TX(20), 275 FUNCTION_DESC_GPIO_RX(0), 276 FUNCTION_DESC_GPIO_RX(1), 277 FUNCTION_DESC_GPIO_RX(2), 278 FUNCTION_DESC_GPIO_RX(3), 279 FUNCTION_DESC_GPIO_RX(4), 280 FUNCTION_DESC_GPIO_RX(5), 281 FUNCTION_DESC_GPIO_RX(6), 282 FUNCTION_DESC_GPIO_RX(7), 283 FUNCTION_DESC_GPIO_RX(8), 284 FUNCTION_DESC_GPIO_RX(9), 285 FUNCTION_DESC_GPIO_RX(10), 286 FUNCTION_DESC_GPIO_RX(11), 287 FUNCTION_DESC_GPIO_RX(12), 288 FUNCTION_DESC_GPIO_RX(13), 289 FUNCTION_DESC_GPIO_RX(14), 290 FUNCTION_DESC_GPIO_RX(15), 291 FUNCTION_DESC_GPIO_RX(16), 292 FUNCTION_DESC_GPIO_RX(17), 293 FUNCTION_DESC_GPIO_RX(18), 294 FUNCTION_DESC_GPIO_RX(19), 295 FUNCTION_DESC_GPIO_RX(20), 296 FUNCTION_DESC_GPIO(), 297 FUNCTION_DESC(I2C, i2c), 298 FUNCTION_DESC(UART, uart), 299 }; 300 301 static int max96755f_get_pins_count(struct udevice *dev) 302 { 303 return ARRAY_SIZE(max96755f_pins); 304 } 305 306 static const char *max96755f_get_pin_name(struct udevice *dev, 307 unsigned int selector) 308 { 309 return max96755f_pins[selector].name; 310 } 311 312 static int max96755f_pinctrl_get_groups_count(struct udevice *dev) 313 { 314 return ARRAY_SIZE(max96755f_groups); 315 } 316 317 static const char *max96755f_pinctrl_get_group_name(struct udevice *dev, 318 unsigned int selector) 319 { 320 return max96755f_groups[selector].name; 321 } 322 323 static int max96755f_pinctrl_get_functions_count(struct udevice *dev) 324 { 325 return ARRAY_SIZE(max96755f_functions); 326 } 327 328 static const char *max96755f_pinctrl_get_function_name(struct udevice *dev, 329 unsigned int selector) 330 { 331 return max96755f_functions[selector].name; 332 } 333 334 static int 335 max96755f_pinmux_set(struct udevice *dev, unsigned int group_selector, 336 unsigned int func_selector) 337 { 338 const struct group_desc *grp = &max96755f_groups[group_selector]; 339 const struct function_desc *func = &max96755f_functions[func_selector]; 340 int i, ret; 341 342 for (i = 0; i < grp->num_configs; i++) { 343 const struct config_desc *config = &grp->configs[i]; 344 345 ret = dm_i2c_reg_clrset(dev->parent, config->reg, config->mask, 346 config->val); 347 if (ret < 0) 348 return ret; 349 } 350 351 for (i = 0; i < grp->num_pins; i++) { 352 ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(grp->pins[i]), 353 GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN, 354 FIELD_PREP(GPIO_OUT_DIS, func->gpio_out_dis) | 355 FIELD_PREP(GPIO_RX_EN, func->gpio_rx_en) | 356 FIELD_PREP(GPIO_TX_EN, func->gpio_tx_en)); 357 if (ret < 0) 358 return ret; 359 360 if (func->gpio_tx_en) { 361 ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(grp->pins[i]), 362 GPIO_TX_ID, 363 FIELD_PREP(GPIO_TX_ID, func->gpio_tx_id)); 364 if (ret < 0) 365 return ret; 366 } 367 368 if (func->gpio_rx_en) { 369 ret = dm_i2c_reg_clrset(dev->parent, 370 GPIO_C_REG(grp->pins[i]), 371 GPIO_RX_ID, 372 FIELD_PREP(GPIO_RX_ID, func->gpio_rx_id)); 373 if (ret < 0) 374 return ret; 375 } 376 } 377 378 return 0; 379 } 380 381 static const struct pinconf_param max96755f_pinconf_params[] = { 382 { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, 383 { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, 384 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 385 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 40000 }, 386 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 40000 }, 387 }; 388 389 static int max96755f_pinconf_set(struct udevice *dev, unsigned int pin, 390 unsigned int param, unsigned int arg) 391 { 392 u8 res_cfg; 393 int ret; 394 395 switch (param) { 396 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 397 ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(pin), OUT_TYPE, 398 FIELD_PREP(OUT_TYPE, 0)); 399 if (ret < 0) 400 return ret; 401 402 break; 403 case PIN_CONFIG_DRIVE_PUSH_PULL: 404 ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(pin), OUT_TYPE, 405 FIELD_PREP(OUT_TYPE, 1)); 406 if (ret < 0) 407 return ret; 408 409 break; 410 case PIN_CONFIG_BIAS_DISABLE: 411 ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin), 412 PULL_UPDN_SEL, 413 FIELD_PREP(PULL_UPDN_SEL, 0)); 414 if (ret < 0) 415 return ret; 416 417 break; 418 case PIN_CONFIG_BIAS_PULL_UP: 419 switch (arg) { 420 case 40000: 421 res_cfg = 0; 422 break; 423 case 1000000: 424 res_cfg = 1; 425 break; 426 default: 427 return -EINVAL; 428 } 429 430 ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin), RES_CFG, 431 FIELD_PREP(RES_CFG, res_cfg)); 432 if (ret < 0) 433 return ret; 434 435 ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin), 436 PULL_UPDN_SEL, 437 FIELD_PREP(PULL_UPDN_SEL, 1)); 438 if (ret < 0) 439 return ret; 440 441 break; 442 case PIN_CONFIG_BIAS_PULL_DOWN: 443 switch (arg) { 444 case 40000: 445 res_cfg = 0; 446 break; 447 case 1000000: 448 res_cfg = 1; 449 break; 450 default: 451 return -EINVAL; 452 } 453 454 ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin), RES_CFG, 455 FIELD_PREP(RES_CFG, res_cfg)); 456 if (ret < 0) 457 return ret; 458 459 ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin), 460 PULL_UPDN_SEL, 461 FIELD_PREP(PULL_UPDN_SEL, 2)); 462 if (ret < 0) 463 return ret; 464 465 break; 466 case PIN_CONFIG_OUTPUT: 467 ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin), 468 GPIO_OUT_DIS | GPIO_OUT, 469 FIELD_PREP(GPIO_OUT_DIS, 0) | 470 FIELD_PREP(GPIO_OUT, arg)); 471 if (ret < 0) 472 return ret; 473 474 break; 475 default: 476 dev_err(dev, "unsupported configuration parameter %u\n", param); 477 return -ENOTSUPP; 478 } 479 480 return 0; 481 } 482 483 static const struct pinctrl_ops max96755f_pinctrl_ops = { 484 .get_pins_count = max96755f_get_pins_count, 485 .get_pin_name = max96755f_get_pin_name, 486 .get_groups_count = max96755f_pinctrl_get_groups_count, 487 .get_group_name = max96755f_pinctrl_get_group_name, 488 .get_functions_count = max96755f_pinctrl_get_functions_count, 489 .get_function_name = max96755f_pinctrl_get_function_name, 490 .set_state = pinctrl_generic_set_state, 491 .pinmux_set = max96755f_pinmux_set, 492 .pinmux_group_set = max96755f_pinmux_set, 493 .pinconf_num_params = ARRAY_SIZE(max96755f_pinconf_params), 494 .pinconf_params = max96755f_pinconf_params, 495 .pinconf_set = max96755f_pinconf_set, 496 }; 497 498 static const struct udevice_id max96755f_pinctrl_of_match[] = { 499 { .compatible = "maxim,max96755f-pinctrl" }, 500 { } 501 }; 502 503 U_BOOT_DRIVER(max96755f_pinctrl) = { 504 .name = "pinctrl-max96755f", 505 .id = UCLASS_PINCTRL, 506 .of_match = max96755f_pinctrl_of_match, 507 .ops = &max96755f_pinctrl_ops, 508 }; 509