xref: /rk3399_rockchip-uboot/drivers/pinctrl/aspeed/pinctrl_ast2500.c (revision 4f66e09bb9fbc47b73f67c3cc08ee2663e8fcdb1)
1*4f0e44e4Smaxims@google.com /*
2*4f0e44e4Smaxims@google.com  * Copyright 2017 Google, Inc
3*4f0e44e4Smaxims@google.com  *
4*4f0e44e4Smaxims@google.com  * SPDX-License-Identifier: GPL-2.0+
5*4f0e44e4Smaxims@google.com  */
6*4f0e44e4Smaxims@google.com 
7*4f0e44e4Smaxims@google.com #include <common.h>
8*4f0e44e4Smaxims@google.com #include <dm.h>
9*4f0e44e4Smaxims@google.com #include <errno.h>
10*4f0e44e4Smaxims@google.com #include <asm/io.h>
11*4f0e44e4Smaxims@google.com #include <asm/arch/pinctrl.h>
12*4f0e44e4Smaxims@google.com #include <asm/arch/scu_ast2500.h>
13*4f0e44e4Smaxims@google.com #include <dm/pinctrl.h>
14*4f0e44e4Smaxims@google.com 
15*4f0e44e4Smaxims@google.com DECLARE_GLOBAL_DATA_PTR;
16*4f0e44e4Smaxims@google.com 
17*4f0e44e4Smaxims@google.com /*
18*4f0e44e4Smaxims@google.com  * This driver works with very simple configuration that has the same name
19*4f0e44e4Smaxims@google.com  * for group and function. This way it is compatible with the Linux Kernel
20*4f0e44e4Smaxims@google.com  * driver.
21*4f0e44e4Smaxims@google.com  */
22*4f0e44e4Smaxims@google.com 
23*4f0e44e4Smaxims@google.com struct ast2500_pinctrl_priv {
24*4f0e44e4Smaxims@google.com 	struct ast2500_scu *scu;
25*4f0e44e4Smaxims@google.com };
26*4f0e44e4Smaxims@google.com 
ast2500_pinctrl_probe(struct udevice * dev)27*4f0e44e4Smaxims@google.com static int ast2500_pinctrl_probe(struct udevice *dev)
28*4f0e44e4Smaxims@google.com {
29*4f0e44e4Smaxims@google.com 	struct ast2500_pinctrl_priv *priv = dev_get_priv(dev);
30*4f0e44e4Smaxims@google.com 
31*4f0e44e4Smaxims@google.com 	priv->scu = ast_get_scu();
32*4f0e44e4Smaxims@google.com 
33*4f0e44e4Smaxims@google.com 	return 0;
34*4f0e44e4Smaxims@google.com }
35*4f0e44e4Smaxims@google.com 
36*4f0e44e4Smaxims@google.com struct ast2500_group_config {
37*4f0e44e4Smaxims@google.com 	char *group_name;
38*4f0e44e4Smaxims@google.com 	/* Control register number (1-10) */
39*4f0e44e4Smaxims@google.com 	unsigned reg_num;
40*4f0e44e4Smaxims@google.com 	/* The mask of control bits in the register */
41*4f0e44e4Smaxims@google.com 	u32 ctrl_bit_mask;
42*4f0e44e4Smaxims@google.com };
43*4f0e44e4Smaxims@google.com 
44*4f0e44e4Smaxims@google.com static const struct ast2500_group_config ast2500_groups[] = {
45*4f0e44e4Smaxims@google.com 	{ "I2C1", 8, (1 << 13) | (1 << 12) },
46*4f0e44e4Smaxims@google.com 	{ "I2C2", 8, (1 << 15) | (1 << 14) },
47*4f0e44e4Smaxims@google.com 	{ "I2C3", 8, (1 << 16) },
48*4f0e44e4Smaxims@google.com 	{ "I2C4", 5, (1 << 17) },
49*4f0e44e4Smaxims@google.com 	{ "I2C4", 5, (1 << 17) },
50*4f0e44e4Smaxims@google.com 	{ "I2C5", 5, (1 << 18) },
51*4f0e44e4Smaxims@google.com 	{ "I2C6", 5, (1 << 19) },
52*4f0e44e4Smaxims@google.com 	{ "I2C7", 5, (1 << 20) },
53*4f0e44e4Smaxims@google.com 	{ "I2C8", 5, (1 << 21) },
54*4f0e44e4Smaxims@google.com 	{ "I2C9", 5, (1 << 22) },
55*4f0e44e4Smaxims@google.com 	{ "I2C10", 5, (1 << 23) },
56*4f0e44e4Smaxims@google.com 	{ "I2C11", 5, (1 << 24) },
57*4f0e44e4Smaxims@google.com 	{ "I2C12", 5, (1 << 25) },
58*4f0e44e4Smaxims@google.com 	{ "I2C13", 5, (1 << 26) },
59*4f0e44e4Smaxims@google.com 	{ "I2C14", 5, (1 << 27) },
60*4f0e44e4Smaxims@google.com 	{ "MAC1LINK", 1, (1 << 0) },
61*4f0e44e4Smaxims@google.com 	{ "MDIO1", 3, (1 << 31) | (1 << 30) },
62*4f0e44e4Smaxims@google.com 	{ "MAC2LINK", 1, (1 << 1) },
63*4f0e44e4Smaxims@google.com 	{ "MDIO2", 5, (1 << 2) },
64*4f0e44e4Smaxims@google.com };
65*4f0e44e4Smaxims@google.com 
ast2500_pinctrl_get_groups_count(struct udevice * dev)66*4f0e44e4Smaxims@google.com static int ast2500_pinctrl_get_groups_count(struct udevice *dev)
67*4f0e44e4Smaxims@google.com {
68*4f0e44e4Smaxims@google.com 	debug("PINCTRL: get_(functions/groups)_count\n");
69*4f0e44e4Smaxims@google.com 
70*4f0e44e4Smaxims@google.com 	return ARRAY_SIZE(ast2500_groups);
71*4f0e44e4Smaxims@google.com }
72*4f0e44e4Smaxims@google.com 
ast2500_pinctrl_get_group_name(struct udevice * dev,unsigned selector)73*4f0e44e4Smaxims@google.com static const char *ast2500_pinctrl_get_group_name(struct udevice *dev,
74*4f0e44e4Smaxims@google.com 						  unsigned selector)
75*4f0e44e4Smaxims@google.com {
76*4f0e44e4Smaxims@google.com 	debug("PINCTRL: get_(function/group)_name %u\n", selector);
77*4f0e44e4Smaxims@google.com 
78*4f0e44e4Smaxims@google.com 	return ast2500_groups[selector].group_name;
79*4f0e44e4Smaxims@google.com }
80*4f0e44e4Smaxims@google.com 
ast2500_pinctrl_group_set(struct udevice * dev,unsigned selector,unsigned func_selector)81*4f0e44e4Smaxims@google.com static int ast2500_pinctrl_group_set(struct udevice *dev, unsigned selector,
82*4f0e44e4Smaxims@google.com 				     unsigned func_selector)
83*4f0e44e4Smaxims@google.com {
84*4f0e44e4Smaxims@google.com 	struct ast2500_pinctrl_priv *priv = dev_get_priv(dev);
85*4f0e44e4Smaxims@google.com 	const struct ast2500_group_config *config;
86*4f0e44e4Smaxims@google.com 	u32 *ctrl_reg;
87*4f0e44e4Smaxims@google.com 
88*4f0e44e4Smaxims@google.com 	debug("PINCTRL: group_set <%u, %u>\n", selector, func_selector);
89*4f0e44e4Smaxims@google.com 	if (selector >= ARRAY_SIZE(ast2500_groups))
90*4f0e44e4Smaxims@google.com 		return -EINVAL;
91*4f0e44e4Smaxims@google.com 
92*4f0e44e4Smaxims@google.com 	config = &ast2500_groups[selector];
93*4f0e44e4Smaxims@google.com 	if (config->reg_num > 6)
94*4f0e44e4Smaxims@google.com 		ctrl_reg = &priv->scu->pinmux_ctrl1[config->reg_num - 7];
95*4f0e44e4Smaxims@google.com 	else
96*4f0e44e4Smaxims@google.com 		ctrl_reg = &priv->scu->pinmux_ctrl[config->reg_num - 1];
97*4f0e44e4Smaxims@google.com 
98*4f0e44e4Smaxims@google.com 	ast_scu_unlock(priv->scu);
99*4f0e44e4Smaxims@google.com 	setbits_le32(ctrl_reg, config->ctrl_bit_mask);
100*4f0e44e4Smaxims@google.com 	ast_scu_lock(priv->scu);
101*4f0e44e4Smaxims@google.com 
102*4f0e44e4Smaxims@google.com 	return 0;
103*4f0e44e4Smaxims@google.com }
104*4f0e44e4Smaxims@google.com 
105*4f0e44e4Smaxims@google.com static struct pinctrl_ops ast2500_pinctrl_ops = {
106*4f0e44e4Smaxims@google.com 	.set_state = pinctrl_generic_set_state,
107*4f0e44e4Smaxims@google.com 	.get_groups_count = ast2500_pinctrl_get_groups_count,
108*4f0e44e4Smaxims@google.com 	.get_group_name = ast2500_pinctrl_get_group_name,
109*4f0e44e4Smaxims@google.com 	.get_functions_count = ast2500_pinctrl_get_groups_count,
110*4f0e44e4Smaxims@google.com 	.get_function_name = ast2500_pinctrl_get_group_name,
111*4f0e44e4Smaxims@google.com 	.pinmux_group_set = ast2500_pinctrl_group_set,
112*4f0e44e4Smaxims@google.com };
113*4f0e44e4Smaxims@google.com 
114*4f0e44e4Smaxims@google.com static const struct udevice_id ast2500_pinctrl_ids[] = {
115*4f0e44e4Smaxims@google.com 	{ .compatible = "aspeed,ast2500-pinctrl" },
116*4f0e44e4Smaxims@google.com 	{ .compatible = "aspeed,g5-pinctrl" },
117*4f0e44e4Smaxims@google.com 	{ }
118*4f0e44e4Smaxims@google.com };
119*4f0e44e4Smaxims@google.com 
120*4f0e44e4Smaxims@google.com U_BOOT_DRIVER(pinctrl_ast2500) = {
121*4f0e44e4Smaxims@google.com 	.name = "aspeed_ast2500_pinctrl",
122*4f0e44e4Smaxims@google.com 	.id = UCLASS_PINCTRL,
123*4f0e44e4Smaxims@google.com 	.of_match = ast2500_pinctrl_ids,
124*4f0e44e4Smaxims@google.com 	.priv_auto_alloc_size = sizeof(struct ast2500_pinctrl_priv),
125*4f0e44e4Smaxims@google.com 	.ops = &ast2500_pinctrl_ops,
126*4f0e44e4Smaxims@google.com 	.probe = ast2500_pinctrl_probe,
127*4f0e44e4Smaxims@google.com };
128