1# 2# PINCTRL infrastructure and drivers 3# 4 5menu "Pin controllers" 6 7config PINCTRL 8 bool "Support pin controllers" 9 depends on DM 10 help 11 This enables the basic support for pinctrl framework. You may want 12 to enable some more options depending on what you want to do. 13 14config PINCTRL_FULL 15 bool "Support full pin controllers" 16 depends on PINCTRL && OF_CONTROL 17 default y 18 help 19 This provides Linux-compatible device tree interface for the pinctrl 20 subsystem. This feature depends on device tree configuration because 21 it parses a device tree to look for the pinctrl device which the 22 peripheral device is associated with. 23 24 If this option is disabled (it is the only possible choice for non-DT 25 boards), the pinctrl core provides no systematic mechanism for 26 identifying peripheral devices, applying needed pinctrl settings. 27 It is totally up to the implementation of each low-level driver. 28 You can save memory footprint in return for some limitations. 29 30config PINCTRL_GENERIC 31 bool "Support generic pin controllers" 32 depends on PINCTRL_FULL 33 default y 34 help 35 Say Y here if you want to use the pinctrl subsystem through the 36 generic DT interface. If enabled, some functions become available 37 to parse common properties such as "pins", "groups", "functions" and 38 some pin configuration parameters. It would be easier if you only 39 need the generic DT interface for pin muxing and pin configuration. 40 If you need to handle vendor-specific DT properties, you can disable 41 this option and implement your own set_state callback in the pinctrl 42 operations. 43 44config PINMUX 45 bool "Support pin multiplexing controllers" 46 depends on PINCTRL_GENERIC 47 default y 48 help 49 This option enables pin multiplexing through the generic pinctrl 50 framework. Most SoCs have their own own multiplexing arrangement 51 where a single pin can be used for several functions. An SoC pinctrl 52 driver allows the required function to be selected for each pin. 53 The driver is typically controlled by the device tree. 54 55config PINCONF 56 bool "Support pin configuration controllers" 57 depends on PINCTRL_GENERIC 58 help 59 This option enables pin configuration through the generic pinctrl 60 framework. 61 62config SPL_PINCTRL 63 bool "Support pin controllers in SPL" 64 depends on SPL && SPL_DM 65 help 66 This option is an SPL-variant of the PINCTRL option. 67 See the help of PINCTRL for details. 68 69config SPL_PINCTRL_FULL 70 bool "Support full pin controllers in SPL" 71 depends on SPL_PINCTRL && SPL_OF_CONTROL 72 default n if TARGET_STM32F746_DISCO 73 default y 74 help 75 This option is an SPL-variant of the PINCTRL_FULL option. 76 See the help of PINCTRL_FULL for details. 77 78config SPL_PINCTRL_GENERIC 79 bool "Support generic pin controllers in SPL" 80 depends on SPL_PINCTRL_FULL 81 default y 82 help 83 This option is an SPL-variant of the PINCTRL_GENERIC option. 84 See the help of PINCTRL_GENERIC for details. 85 86config SPL_PINMUX 87 bool "Support pin multiplexing controllers in SPL" 88 depends on SPL_PINCTRL_GENERIC 89 default y 90 help 91 This option is an SPL-variant of the PINMUX option. 92 See the help of PINMUX for details. 93 The pinctrl subsystem can add a substantial overhead to the SPL 94 image since it typically requires quite a few tables either in the 95 driver or in the device tree. If this is acceptable and you need 96 to adjust pin multiplexing in SPL in order to boot into U-Boot, 97 enable this option. You will need to enable device tree in SPL 98 for this to work. 99 100config SPL_PINCONF 101 bool "Support pin configuration controllers in SPL" 102 depends on SPL_PINCTRL_GENERIC 103 help 104 This option is an SPL-variant of the PINCONF option. 105 See the help of PINCONF for details. 106 107if PINCTRL || SPL_PINCTRL 108 109config PINCTRL_AR933X 110 bool "QCA/Athores ar933x pin control driver" 111 depends on DM && SOC_AR933X 112 help 113 Support pin multiplexing control on QCA/Athores ar933x SoCs. 114 The driver is controlled by a device tree node which contains 115 both the GPIO definitions and pin control functions for each 116 available multiplex function. 117 118config PINCTRL_AT91 119 bool "AT91 pinctrl driver" 120 depends on DM 121 help 122 This option is to enable the AT91 pinctrl driver for AT91 PIO 123 controller. 124 125 AT91 PIO controller is a combined gpio-controller, pin-mux and 126 pin-config module. Each I/O pin may be dedicated as a general-purpose 127 I/O or be assigned to a function of an embedded peripheral. Each I/O 128 pin has a glitch filter providing rejection of glitches lower than 129 one-half of peripheral clock cycle and a debouncing filter providing 130 rejection of unwanted pulses from key or push button operations. You 131 can also control the multi-driver capability, pull-up and pull-down 132 feature on each I/O pin. 133 134config PINCTRL_AT91PIO4 135 bool "AT91 PIO4 pinctrl driver" 136 depends on DM 137 help 138 This option is to enable the AT91 pinctrl driver for AT91 PIO4 139 controller which is available on SAMA5D2 SoC. 140 141config PINCTRL_MAX96752F 142 bool "Maxim MAX96752F pinctrl driver" 143 depends on DM && I2C_MUX_MAX96752F 144 select PINCONF 145 help 146 This option is to enable the pinctrl driver for Maxim 147 MAX96752F. 148 149config PINCTRL_PIC32 150 bool "Microchip PIC32 pin-control and pin-mux driver" 151 depends on DM && MACH_PIC32 152 default y 153 help 154 Supports individual pin selection and configuration for each 155 remappable peripheral available on Microchip PIC32 156 SoCs. This driver is controlled by a device tree node which 157 contains both GPIO defintion and pin control functions. 158 159config PINCTRL_QCA953X 160 bool "QCA/Athores qca953x pin control driver" 161 depends on DM && SOC_QCA953X 162 help 163 Support pin multiplexing control on QCA/Athores qca953x SoCs. 164 165 The driver is controlled by a device tree node which contains both 166 the GPIO definitions and pin control functions for each available 167 multiplex function. 168 169config PINCTRL_ROCKCHIP 170 bool "Rockchip pin control driver" 171 depends on PINCTRL_FULL && ARCH_ROCKCHIP 172 default y 173 help 174 Support pin multiplexing control on Rockchip SoCs. 175 176 The driver is controlled by a device tree node which contains both 177 the GPIO definitions and pin control functions for each available 178 multiplex function. 179 180config SPL_PINCTRL_ROCKCHIP 181 bool "Support Rockchip pin controllers in SPL" 182 depends on SPL_PINCTRL_FULL && ARCH_ROCKCHIP 183 default y 184 help 185 This option is an SPL-variant of the PINCTRL_ROCKCHIP option. 186 See the help of PINCTRL_ROCKCHIP for details. 187 188config PINCTRL_SANDBOX 189 bool "Sandbox pinctrl driver" 190 depends on SANDBOX 191 help 192 This enables pinctrl driver for sandbox. 193 194 Currently, this driver actually does nothing but print debug 195 messages when pinctrl operations are invoked. 196 197config PINCTRL_SINGLE 198 bool "Single register pin-control and pin-multiplex driver" 199 depends on DM 200 help 201 This enables pinctrl driver for systems using a single register for 202 pin configuration and multiplexing. TI's AM335X SoCs are examples of 203 such systems. 204 205 Depending on the platform make sure to also enable OF_TRANSLATE and 206 eventually SPL_OF_TRANSLATE to get correct address translations. 207 208config PINCTRL_STI 209 bool "STMicroelectronics STi pin-control and pin-mux driver" 210 depends on DM && ARCH_STI 211 default y 212 help 213 Support pin multiplexing control on STMicrolectronics STi SoCs. 214 215 The driver is controlled by a device tree node which contains both 216 the GPIO definitions and pin control functions for each available 217 multiplex function. 218 219config PINCTRL_STM32 220 bool "ST STM32 pin control driver" 221 depends on DM 222 help 223 Supports pin multiplexing control on stm32 SoCs. 224 225 The driver is controlled by a device tree node which contains both 226 the GPIO definitions and pin control functions for each available 227 multiplex function. 228 229config ASPEED_AST2500_PINCTRL 230 bool "Aspeed AST2500 pin control driver" 231 depends on DM && PINCTRL_GENERIC && ASPEED_AST2500 232 default y 233 help 234 Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses 235 Generic Pinctrl framework and is compatible with the Linux driver, 236 i.e. it uses the same device tree configuration. 237 238endif 239 240source "drivers/pinctrl/meson/Kconfig" 241source "drivers/pinctrl/nxp/Kconfig" 242source "drivers/pinctrl/uniphier/Kconfig" 243source "drivers/pinctrl/exynos/Kconfig" 244source "drivers/pinctrl/mvebu/Kconfig" 245 246endmenu 247