1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dm/of.h> 13 #include <dm/of_access.h> 14 #include <generic-phy.h> 15 #include <linux/bitfield.h> 16 #include <linux/usb/ch9.h> 17 #include <linux/usb/otg.h> 18 #include <regmap.h> 19 #include <reset.h> 20 #include <syscon.h> 21 #include <asm/arch/clock.h> 22 #include <asm/arch/cpu.h> 23 24 #include <linux/usb/phy-rockchip-usbdp.h> 25 26 #define BIT_WRITEABLE_SHIFT 16 27 28 enum { 29 UDPHY_MODE_NONE = 0, 30 UDPHY_MODE_USB = BIT(0), 31 UDPHY_MODE_DP = BIT(1), 32 UDPHY_MODE_DP_USB = BIT(1) | BIT(0), 33 }; 34 35 struct udphy_grf_reg { 36 unsigned int offset; 37 unsigned int bitend; 38 unsigned int bitstart; 39 unsigned int disable; 40 unsigned int enable; 41 }; 42 43 /** 44 * struct reg_sequence - An individual write from a sequence of writes. 45 * 46 * @reg: Register address. 47 * @def: Register value. 48 * @delay_us: Delay to be applied after the register write in microseconds 49 * 50 * Register/value pairs for sequences of writes with an optional delay in 51 * microseconds to be applied after each write. 52 */ 53 struct reg_sequence { 54 unsigned int reg; 55 unsigned int def; 56 unsigned int delay_us; 57 }; 58 59 struct udphy_grf_cfg { 60 /* u2phy-grf */ 61 struct udphy_grf_reg bvalid_phy_con; 62 struct udphy_grf_reg bvalid_grf_con; 63 64 /* usb-grf */ 65 struct udphy_grf_reg usb3otg0_cfg; 66 struct udphy_grf_reg usb3otg1_cfg; 67 68 /* usbdpphy-grf */ 69 struct udphy_grf_reg low_pwrn; 70 struct udphy_grf_reg rx_lfps; 71 }; 72 73 struct rockchip_udphy; 74 75 struct rockchip_udphy_cfg { 76 /* resets to be requested */ 77 const char * const *rst_list; 78 int num_rsts; 79 80 struct udphy_grf_cfg grfcfg; 81 int (*combophy_init)(struct rockchip_udphy *udphy); 82 }; 83 84 struct rockchip_udphy { 85 struct udevice *dev; 86 struct regmap *pma_regmap; 87 struct regmap *u2phygrf; 88 struct regmap *udphygrf; 89 struct regmap *usbgrf; 90 struct regmap *vogrf; 91 // struct typec_switch *sw; 92 // struct typec_mux *mux; 93 94 /* clocks and rests */ 95 struct reset_ctl *rsts; 96 97 /* PHY status management */ 98 bool flip; 99 bool mode_change; 100 u8 mode; 101 u8 status; 102 103 /* utilized for USB */ 104 bool hs; /* flag for high-speed */ 105 106 /* utilized for DP */ 107 struct gpio_desc *sbu1_dc_gpio; 108 struct gpio_desc *sbu2_dc_gpio; 109 u32 lane_mux_sel[4]; 110 u32 dp_lane_sel[4]; 111 u32 dp_aux_dout_sel; 112 u32 dp_aux_din_sel; 113 int id; 114 115 /* PHY const config */ 116 const struct rockchip_udphy_cfg *cfgs; 117 }; 118 119 static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = { 120 {0x0090, 0x68}, {0x0094, 0x68}, 121 {0x0128, 0x24}, {0x012c, 0x44}, 122 {0x0130, 0x3f}, {0x0134, 0x44}, 123 {0x015c, 0xa9}, {0x0160, 0x71}, 124 {0x0164, 0x71}, {0x0168, 0xa9}, 125 {0x0174, 0xa9}, {0x0178, 0x71}, 126 {0x017c, 0x71}, {0x0180, 0xa9}, 127 {0x018c, 0x41}, {0x0190, 0x00}, 128 {0x0194, 0x05}, {0x01ac, 0x2a}, 129 {0x01b0, 0x17}, {0x01b4, 0x17}, 130 {0x01b8, 0x2a}, {0x01c8, 0x04}, 131 {0x01cc, 0x08}, {0x01d0, 0x08}, 132 {0x01d4, 0x04}, {0x01d8, 0x20}, 133 {0x01dc, 0x01}, {0x01e0, 0x09}, 134 {0x01e4, 0x03}, {0x01f0, 0x29}, 135 {0x01f4, 0x02}, {0x01f8, 0x02}, 136 {0x01fc, 0x29}, {0x0208, 0x2a}, 137 {0x020c, 0x17}, {0x0210, 0x17}, 138 {0x0214, 0x2a}, {0x0224, 0x20}, 139 {0x03f0, 0x0d}, {0x03f4, 0x09}, 140 {0x03f8, 0x09}, {0x03fc, 0x0d}, 141 {0x0404, 0x0e}, {0x0408, 0x14}, 142 {0x040c, 0x14}, {0x0410, 0x3b}, 143 {0x0ce0, 0x68}, {0x0ce8, 0xd0}, 144 {0x0cf0, 0x87}, {0x0cf8, 0x70}, 145 {0x0d00, 0x70}, {0x0d08, 0xa9}, 146 {0x1ce0, 0x68}, {0x1ce8, 0xd0}, 147 {0x1cf0, 0x87}, {0x1cf8, 0x70}, 148 {0x1d00, 0x70}, {0x1d08, 0xa9}, 149 {0x0a3c, 0xd0}, {0x0a44, 0xd0}, 150 {0x0a48, 0x01}, {0x0a4c, 0x0d}, 151 {0x0a54, 0xe0}, {0x0a5c, 0xe0}, 152 {0x0a64, 0xa8}, {0x1a3c, 0xd0}, 153 {0x1a44, 0xd0}, {0x1a48, 0x01}, 154 {0x1a4c, 0x0d}, {0x1a54, 0xe0}, 155 {0x1a5c, 0xe0}, {0x1a64, 0xa8} 156 }; 157 158 static const struct reg_sequence rk3588_udphy_init_sequence[] = { 159 {0x0104, 0x44}, {0x0234, 0xE8}, 160 {0x0248, 0x44}, {0x028C, 0x18}, 161 {0x081C, 0xE5}, {0x0878, 0x00}, 162 {0x0994, 0x1C}, {0x0AF0, 0x00}, 163 {0x181C, 0xE5}, {0x1878, 0x00}, 164 {0x1994, 0x1C}, {0x1AF0, 0x00}, 165 {0x0428, 0x60}, {0x0D58, 0x33}, 166 {0x1D58, 0x33}, {0x0990, 0x74}, 167 {0x0D64, 0x17}, {0x08C8, 0x13}, 168 {0x1990, 0x74}, {0x1D64, 0x17}, 169 {0x18C8, 0x13}, {0x0D90, 0x40}, 170 {0x0DA8, 0x40}, {0x0DC0, 0x40}, 171 {0x0DD8, 0x40}, {0x1D90, 0x40}, 172 {0x1DA8, 0x40}, {0x1DC0, 0x40}, 173 {0x1DD8, 0x40}, {0x03C0, 0x30}, 174 {0x03C4, 0x06}, {0x0E10, 0x00}, 175 {0x1E10, 0x00}, {0x043C, 0x0F}, 176 {0x0D2C, 0xFF}, {0x1D2C, 0xFF}, 177 {0x0D34, 0x0F}, {0x1D34, 0x0F}, 178 {0x08FC, 0x2A}, {0x0914, 0x28}, 179 {0x0A30, 0x03}, {0x0E38, 0x05}, 180 {0x0ECC, 0x27}, {0x0ED0, 0x22}, 181 {0x0ED4, 0x26}, {0x18FC, 0x2A}, 182 {0x1914, 0x28}, {0x1A30, 0x03}, 183 {0x1E38, 0x05}, {0x1ECC, 0x27}, 184 {0x1ED0, 0x22}, {0x1ED4, 0x26}, 185 {0x0048, 0x0F}, {0x0060, 0x3C}, 186 {0x0064, 0xF7}, {0x006C, 0x20}, 187 {0x0070, 0x7D}, {0x0074, 0x68}, 188 {0x0AF4, 0x1A}, {0x1AF4, 0x1A}, 189 {0x0440, 0x3F}, {0x10D4, 0x08}, 190 {0x20D4, 0x08}, {0x00D4, 0x30}, 191 {0x0024, 0x6e}, 192 }; 193 194 static inline int grfreg_write(struct regmap *base, 195 const struct udphy_grf_reg *reg, bool en) 196 { 197 u32 val, mask, tmp; 198 199 tmp = en ? reg->enable : reg->disable; 200 mask = GENMASK(reg->bitend, reg->bitstart); 201 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 202 203 return regmap_write(base, reg->offset, val); 204 } 205 206 static int __regmap_multi_reg_write(struct regmap *map, 207 const struct reg_sequence *regs, int num_regs) 208 { 209 int i, ret = 0; 210 211 for (i = 0; i < num_regs; i++) { 212 ret = regmap_write(map, regs[i].reg, regs[i].def); 213 214 if (regs[i].delay_us) 215 udelay(regs[i].delay_us); 216 } 217 218 return ret; 219 } 220 221 static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev) 222 { 223 return 0; 224 } 225 226 static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev) 227 { 228 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 229 int idx; 230 int ret; 231 232 udphy->rsts = devm_kcalloc(dev, cfg->num_rsts, 233 sizeof(*udphy->rsts), GFP_KERNEL); 234 if (!udphy->rsts) 235 return -ENOMEM; 236 237 for (idx = 0; idx < cfg->num_rsts; idx++) { 238 const char *name = cfg->rst_list[idx]; 239 240 ret = reset_get_by_name(dev, name, &udphy->rsts[idx]); 241 if (ret) { 242 dev_err(dev, "failed to get %s reset\n", name); 243 goto err; 244 } 245 246 reset_assert(&udphy->rsts[idx]); 247 } 248 249 return 0; 250 251 err: 252 devm_kfree(dev, udphy->rsts); 253 return ret; 254 } 255 256 static int udphy_get_rst_idx(const char * const *list, int num, char *name) 257 { 258 int idx; 259 260 for (idx = 0; idx < num; idx++) { 261 if (!strcmp(list[idx], name)) 262 return idx; 263 } 264 265 return -EINVAL; 266 } 267 268 static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name) 269 { 270 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 271 int idx; 272 273 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); 274 if (idx < 0) 275 return idx; 276 277 return reset_assert(&udphy->rsts[idx]); 278 } 279 280 static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name) 281 { 282 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 283 int idx; 284 285 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); 286 if (idx < 0) 287 return idx; 288 289 return reset_deassert(&udphy->rsts[idx]); 290 } 291 292 static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable) 293 { 294 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 295 const struct udphy_grf_reg *preg; 296 297 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; 298 grfreg_write(udphy->usbgrf, preg, disable); 299 } 300 301 __maybe_unused 302 static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable) 303 { 304 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 305 306 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); 307 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); 308 } 309 310 /* 311 * In usb/dp combo phy driver, here are 2 ways to mapping lanes. 312 * 313 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) 314 * --------------------------------------------------------------------------- 315 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 316 * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 317 * C/E(Normal) dpln3 dpln2 dpln0 dpln1 318 * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 319 * D/F(Normal) usbrx usbtx dpln0 dpln1 320 * D/F(Flip ) dpln0 dpln1 usbrx usbtx 321 * A(Normal ) dpln3 dpln1 dpln2 dpln0 322 * A(Flip ) dpln2 dpln0 dpln3 dpln1 323 * B(Normal ) usbrx usbtx dpln1 dpln0 324 * B(Flip ) dpln1 dpln0 usbrx usbtx 325 * --------------------------------------------------------------------------- 326 * 327 * 2 Mapping the lanes in dtsi 328 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>; 329 * sample as follow: 330 * --------------------------------------------------------------------------- 331 * B11-B10 A2-A3 A11-A10 B2-B3 332 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 333 * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 334 * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 335 * --------------------------------------------------------------------------- 336 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>; 337 * sample as follow: 338 * --------------------------------------------------------------------------- 339 * B11-B10 A2-A3 A11-A10 B2-B3 340 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 341 * <0 1> dpln0 dpln1 usbrx usbtx 342 * <2 3> usbrx usbtx dpln0 dpln1 343 * --------------------------------------------------------------------------- 344 */ 345 346 __maybe_unused 347 static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy) 348 { 349 if (udphy->flip) { 350 udphy->dp_lane_sel[0] = 0; 351 udphy->dp_lane_sel[1] = 1; 352 udphy->dp_lane_sel[2] = 3; 353 udphy->dp_lane_sel[3] = 2; 354 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; 355 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; 356 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; 357 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; 358 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; 359 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; 360 } else { 361 udphy->dp_lane_sel[0] = 2; 362 udphy->dp_lane_sel[1] = 3; 363 udphy->dp_lane_sel[2] = 1; 364 udphy->dp_lane_sel[3] = 0; 365 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; 366 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; 367 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; 368 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; 369 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; 370 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; 371 } 372 373 udphy->mode = UDPHY_MODE_DP_USB; 374 375 return 0; 376 } 377 378 static int udphy_setup(struct rockchip_udphy *udphy) 379 { 380 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 381 int ret = 0; 382 383 if (cfg->combophy_init) { 384 ret = cfg->combophy_init(udphy); 385 if (ret) 386 dev_err(udphy->dev, "failed to init combophy\n"); 387 } 388 389 return ret; 390 } 391 392 static int udphy_disable(struct rockchip_udphy *udphy) 393 { 394 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 395 int i; 396 397 for (i = 0; i < cfg->num_rsts; i++) 398 reset_assert(&udphy->rsts[i]); 399 400 return 0; 401 } 402 403 static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, const struct device_node *np) 404 { 405 struct property *prop; 406 int ret, i, len, num_lanes; 407 408 prop = of_find_property(np, "rockchip,dp-lane-mux", &len); 409 if (!prop) { 410 dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n"); 411 udphy->mode = UDPHY_MODE_USB; 412 return 0; 413 } 414 415 num_lanes = len / sizeof(u32); 416 417 if (num_lanes != 2 && num_lanes != 4) { 418 dev_err(udphy->dev, "invalid number of lane mux\n"); 419 return -EINVAL; 420 } 421 422 ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes); 423 if (ret) { 424 dev_err(udphy->dev, "get dp lane mux failed\n"); 425 return -EINVAL; 426 } 427 428 for (i = 0; i < num_lanes; i++) { 429 int j; 430 431 if (udphy->dp_lane_sel[i] > 3) { 432 dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n"); 433 return -EINVAL; 434 } 435 436 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; 437 438 for (j = i + 1; j < num_lanes; j++) { 439 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) { 440 dev_err(udphy->dev, "set repeat lane mux value\n"); 441 return -EINVAL; 442 } 443 } 444 } 445 446 udphy->mode = UDPHY_MODE_DP; 447 if (num_lanes == 2) 448 udphy->mode |= UDPHY_MODE_USB; 449 450 return 0; 451 } 452 453 static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev) 454 { 455 const struct device_node *np = ofnode_to_np(dev->node); 456 enum usb_device_speed maximum_speed; 457 int ret; 458 459 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,u2phy-grf"); 460 if (IS_ERR(udphy->u2phygrf)) { 461 if (PTR_ERR(udphy->u2phygrf) == -ENODEV) { 462 dev_warn(dev, "missing u2phy-grf dt node\n"); 463 udphy->u2phygrf = NULL; 464 } else { 465 return PTR_ERR(udphy->u2phygrf); 466 } 467 } 468 469 udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usbdpphy-grf"); 470 if (IS_ERR(udphy->udphygrf)) { 471 if (PTR_ERR(udphy->udphygrf) == -ENODEV) { 472 dev_warn(dev, "missing usbdpphy-grf dt node\n"); 473 udphy->udphygrf = NULL; 474 } else { 475 return PTR_ERR(udphy->udphygrf); 476 } 477 } 478 479 udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usb-grf"); 480 if (IS_ERR(udphy->usbgrf)) { 481 if (PTR_ERR(udphy->usbgrf) == -ENODEV) { 482 dev_warn(dev, "missing usb-grf dt node\n"); 483 udphy->usbgrf = NULL; 484 } else { 485 return PTR_ERR(udphy->usbgrf); 486 } 487 } 488 489 udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf"); 490 if (IS_ERR(udphy->vogrf)) { 491 if (PTR_ERR(udphy->vogrf) == -ENODEV) { 492 dev_warn(dev, "missing vo-grf dt node\n"); 493 udphy->vogrf = NULL; 494 } else { 495 return PTR_ERR(udphy->vogrf); 496 } 497 } 498 499 ret = udphy_parse_lane_mux_data(udphy, np); 500 if (ret) 501 return ret; 502 503 if (dev_read_prop(dev, "maximum-speed", NULL)) { 504 maximum_speed = usb_get_maximum_speed(dev->node); 505 udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false; 506 } 507 508 ret = udphy_clk_init(udphy, dev); 509 if (ret) 510 return ret; 511 512 ret = udphy_reset_init(udphy, dev); 513 if (ret) 514 return ret; 515 516 return 0; 517 } 518 519 static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) 520 { 521 int ret; 522 523 if (!(udphy->mode & mode)) { 524 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); 525 return 0; 526 } 527 528 if (udphy->status == UDPHY_MODE_NONE) { 529 udphy->mode_change = false; 530 ret = udphy_setup(udphy); 531 if (ret) 532 return ret; 533 534 if (udphy->mode & UDPHY_MODE_USB) 535 udphy_u3_port_disable(udphy, false); 536 } else if (udphy->mode_change) { 537 udphy->mode_change = false; 538 udphy->status = UDPHY_MODE_NONE; 539 if (udphy->mode == UDPHY_MODE_DP) 540 udphy_u3_port_disable(udphy, true); 541 542 ret = udphy_disable(udphy); 543 if (ret) 544 return ret; 545 ret = udphy_setup(udphy); 546 if (ret) 547 return ret; 548 } 549 550 udphy->status |= mode; 551 552 return 0; 553 } 554 555 static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) 556 { 557 int ret; 558 559 if (!(udphy->mode & mode)) { 560 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); 561 return 0; 562 } 563 564 if (!udphy->status) 565 return 0; 566 567 udphy->status &= ~mode; 568 569 if (udphy->status == UDPHY_MODE_NONE) { 570 ret = udphy_disable(udphy); 571 if (ret) 572 return ret; 573 } 574 575 return 0; 576 } 577 578 static int rockchip_u3phy_init(struct phy *phy) 579 { 580 struct udevice *parent = phy->dev->parent; 581 struct rockchip_udphy *udphy = dev_get_priv(parent); 582 583 /* DP only or high-speed, disable U3 port */ 584 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { 585 udphy_u3_port_disable(udphy, true); 586 return 0; 587 } 588 589 return udphy_power_on(udphy, UDPHY_MODE_USB); 590 } 591 592 static int rockchip_u3phy_exit(struct phy *phy) 593 { 594 struct udevice *parent = phy->dev->parent; 595 struct rockchip_udphy *udphy = dev_get_priv(parent); 596 597 /* DP only or high-speed */ 598 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) 599 return 0; 600 601 return udphy_power_off(udphy, UDPHY_MODE_USB); 602 } 603 604 static const struct phy_ops rockchip_u3phy_ops = { 605 .init = rockchip_u3phy_init, 606 .exit = rockchip_u3phy_exit, 607 }; 608 609 int rockchip_u3phy_uboot_init(void) 610 { 611 struct udevice *udev; 612 struct rockchip_udphy *udphy; 613 int ret; 614 615 ret = uclass_get_device_by_driver(UCLASS_PHY, 616 DM_GET_DRIVER(rockchip_udphy_u3_port), 617 &udev); 618 if (ret) { 619 pr_err("%s: get u3-port failed: %d\n", __func__, ret); 620 return ret; 621 } 622 623 /* DP only or high-speed, disable U3 port */ 624 udphy = dev_get_priv(udev->parent); 625 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { 626 udphy_u3_port_disable(udphy, true); 627 return 0; 628 } 629 630 return udphy_power_on(udphy, UDPHY_MODE_USB); 631 } 632 633 static int rockchip_udphy_probe(struct udevice *dev) 634 { 635 const struct device_node *np = ofnode_to_np(dev->node); 636 struct rockchip_udphy *udphy = dev_get_priv(dev); 637 const struct rockchip_udphy_cfg *phy_cfgs; 638 int id, ret; 639 640 udphy->dev = dev; 641 642 id = of_alias_get_id(np, "usbdp"); 643 if (id < 0) 644 id = 0; 645 udphy->id = id; 646 647 phy_cfgs = (const struct rockchip_udphy_cfg *) dev_get_driver_data(dev); 648 if (!phy_cfgs) { 649 dev_err(dev, "unable to get phy_cfgs\n"); 650 return -EINVAL; 651 } 652 udphy->cfgs = phy_cfgs; 653 654 ret = regmap_init_mem(dev, &udphy->pma_regmap); 655 if (ret) 656 return ret; 657 udphy->pma_regmap->base += UDPHY_PMA; 658 659 ret = udphy_parse_dt(udphy, dev); 660 if (ret) 661 return ret; 662 663 return 0; 664 } 665 666 static int rockchip_udphy_bind(struct udevice *parent) 667 { 668 struct udevice *child; 669 ofnode subnode; 670 const char *node_name; 671 int ret; 672 673 dev_for_each_subnode(subnode, parent) { 674 if (!ofnode_valid(subnode)) { 675 printf("%s: no subnode for %s", __func__, parent->name); 676 return -ENXIO; 677 } 678 679 node_name = ofnode_get_name(subnode); 680 debug("%s: subnode %s\n", __func__, node_name); 681 682 if (!strcasecmp(node_name, "u3-port")) { 683 ret = device_bind_driver_to_node(parent, 684 "rockchip_udphy_u3_port", 685 node_name, subnode, &child); 686 if (ret) { 687 printf("%s: '%s' cannot bind its driver\n", 688 __func__, node_name); 689 return ret; 690 } 691 } 692 } 693 694 return 0; 695 } 696 697 static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy) 698 { 699 int ret; 700 701 /* configure phy reference clock */ 702 ret = __regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_24m_refclk_cfg, 703 ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg)); 704 if (ret) 705 return ret; 706 707 return 0; 708 } 709 710 static int rk3588_udphy_status_check(struct rockchip_udphy *udphy) 711 { 712 unsigned int val; 713 int ret; 714 715 /* LCPLL check */ 716 if (udphy->mode & UDPHY_MODE_USB) { 717 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, 718 val, (val & CMN_ANA_LCPLL_AFC_DONE) && 719 (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100); 720 if (ret) { 721 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); 722 return ret; 723 } 724 } 725 726 if (udphy->mode & UDPHY_MODE_USB) { 727 if (!udphy->flip) { 728 ret = regmap_read_poll_timeout(udphy->pma_regmap, 729 TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, 730 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, 731 200, 100); 732 if (ret) 733 dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); 734 } else { 735 ret = regmap_read_poll_timeout(udphy->pma_regmap, 736 TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val, 737 val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, 738 200, 100); 739 if (ret) 740 dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); 741 } 742 } 743 744 return 0; 745 } 746 747 static int rk3588_udphy_init(struct rockchip_udphy *udphy) 748 { 749 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 750 int ret; 751 752 /* enable rx lfps for usb */ 753 if (udphy->mode & UDPHY_MODE_USB) 754 grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); 755 756 /* Step 1: power on pma and deassert apb rstn */ 757 grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); 758 759 udphy_reset_deassert(udphy, "pma_apb"); 760 udphy_reset_deassert(udphy, "pcs_apb"); 761 762 /* Step 2: set init sequence and phy refclk */ 763 ret = __regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_init_sequence, 764 ARRAY_SIZE(rk3588_udphy_init_sequence)); 765 if (ret) { 766 dev_err(udphy->dev, "init sequence set error %d\n", ret); 767 goto assert_apb; 768 } 769 770 ret = rk3588_udphy_refclk_set(udphy); 771 if (ret) { 772 dev_err(udphy->dev, "refclk set error %d\n", ret); 773 goto assert_apb; 774 } 775 776 /* Step 3: configure lane mux */ 777 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, 778 CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, 779 FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | 780 FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | 781 FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | 782 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | 783 FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); 784 785 /* Step 4: deassert init rstn and wait for 200ns from datasheet */ 786 if (udphy->mode & UDPHY_MODE_USB) 787 udphy_reset_deassert(udphy, "init"); 788 789 if (udphy->mode & UDPHY_MODE_DP) { 790 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 791 CMN_DP_INIT_RSTN, 792 FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); 793 } 794 795 udelay(1); 796 797 /* Step 5: deassert cmn/lane rstn */ 798 if (udphy->mode & UDPHY_MODE_USB) { 799 udphy_reset_deassert(udphy, "cmn"); 800 udphy_reset_deassert(udphy, "lane"); 801 } 802 803 /* Step 6: wait for lock done of pll */ 804 ret = rk3588_udphy_status_check(udphy); 805 if (ret) 806 goto assert_phy; 807 808 return 0; 809 810 assert_phy: 811 udphy_reset_assert(udphy, "init"); 812 udphy_reset_assert(udphy, "cmn"); 813 udphy_reset_assert(udphy, "lane"); 814 815 assert_apb: 816 udphy_reset_assert(udphy, "pma_apb"); 817 udphy_reset_assert(udphy, "pcs_apb"); 818 return ret; 819 } 820 821 static const char * const rk3588_udphy_rst_l[] = { 822 "init", "cmn", "lane", "pcs_apb", "pma_apb" 823 }; 824 825 static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { 826 .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l), 827 .rst_list = rk3588_udphy_rst_l, 828 .grfcfg = { 829 /* u2phy-grf */ 830 .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 }, 831 .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 }, 832 833 /* usb-grf */ 834 .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 }, 835 .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 }, 836 837 /* usbdpphy-grf */ 838 .low_pwrn = { 0x0004, 13, 13, 0, 1 }, 839 .rx_lfps = { 0x0004, 14, 14, 0, 1 }, 840 }, 841 .combophy_init = rk3588_udphy_init, 842 }; 843 844 static const struct udevice_id rockchip_udphy_dt_match[] = { 845 { 846 .compatible = "rockchip,rk3588-usbdp-phy", 847 .data = (ulong)&rk3588_udphy_cfgs 848 }, 849 { /* sentinel */ } 850 }; 851 852 U_BOOT_DRIVER(rockchip_udphy_u3_port) = { 853 .name = "rockchip_udphy_u3_port", 854 .id = UCLASS_PHY, 855 .ops = &rockchip_u3phy_ops, 856 }; 857 858 U_BOOT_DRIVER(rockchip_udphy) = { 859 .name = "rockchip_udphy", 860 .id = UCLASS_PHY, 861 .of_match = rockchip_udphy_dt_match, 862 .probe = rockchip_udphy_probe, 863 .bind = rockchip_udphy_bind, 864 .priv_auto_alloc_size = sizeof(struct rockchip_udphy), 865 }; 866