1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dm/of.h> 13 #include <dm/of_access.h> 14 #include <generic-phy.h> 15 #include <linux/bitfield.h> 16 #include <linux/usb/ch9.h> 17 #include <linux/usb/otg.h> 18 #include <regmap.h> 19 #include <reset.h> 20 #include <syscon.h> 21 #include <asm/arch/clock.h> 22 #include <asm/arch/cpu.h> 23 24 #include <linux/usb/phy-rockchip-usbdp.h> 25 26 #define BIT_WRITEABLE_SHIFT 16 27 28 enum { 29 DP_BW_RBR, 30 DP_BW_HBR, 31 DP_BW_HBR2, 32 DP_BW_HBR3, 33 }; 34 35 enum { 36 UDPHY_MODE_NONE = 0, 37 UDPHY_MODE_USB = BIT(0), 38 UDPHY_MODE_DP = BIT(1), 39 UDPHY_MODE_DP_USB = BIT(1) | BIT(0), 40 }; 41 42 struct udphy_grf_reg { 43 unsigned int offset; 44 unsigned int bitend; 45 unsigned int bitstart; 46 unsigned int disable; 47 unsigned int enable; 48 }; 49 50 /** 51 * struct reg_sequence - An individual write from a sequence of writes. 52 * 53 * @reg: Register address. 54 * @def: Register value. 55 * @delay_us: Delay to be applied after the register write in microseconds 56 * 57 * Register/value pairs for sequences of writes with an optional delay in 58 * microseconds to be applied after each write. 59 */ 60 struct reg_sequence { 61 unsigned int reg; 62 unsigned int def; 63 unsigned int delay_us; 64 }; 65 66 struct udphy_grf_cfg { 67 /* u2phy-grf */ 68 struct udphy_grf_reg bvalid_phy_con; 69 struct udphy_grf_reg bvalid_grf_con; 70 71 /* usb-grf */ 72 struct udphy_grf_reg usb3otg0_cfg; 73 struct udphy_grf_reg usb3otg1_cfg; 74 75 /* usbdpphy-grf */ 76 struct udphy_grf_reg low_pwrn; 77 struct udphy_grf_reg rx_lfps; 78 }; 79 80 struct dp_tx_drv_ctrl { 81 u32 trsv_reg0204; 82 u32 trsv_reg0205; 83 u32 trsv_reg0206; 84 u32 trsv_reg0207; 85 }; 86 87 struct rockchip_udphy; 88 89 struct rockchip_udphy_cfg { 90 /* resets to be requested */ 91 const char * const *rst_list; 92 int num_rsts; 93 94 struct udphy_grf_cfg grfcfg; 95 const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4]; 96 int (*combophy_init)(struct rockchip_udphy *udphy); 97 int (*dp_phy_set_rate)(struct rockchip_udphy *udphy, 98 struct phy_configure_opts_dp *dp); 99 int (*dp_phy_set_voltages)(struct rockchip_udphy *udphy, 100 struct phy_configure_opts_dp *dp); 101 int (*dplane_enable)(struct rockchip_udphy *udphy, int dp_lanes); 102 int (*dplane_select)(struct rockchip_udphy *udphy); 103 }; 104 105 struct rockchip_udphy { 106 struct udevice *dev; 107 struct regmap *pma_regmap; 108 struct regmap *u2phygrf; 109 struct regmap *udphygrf; 110 struct regmap *usbgrf; 111 struct regmap *vogrf; 112 // struct typec_switch *sw; 113 // struct typec_mux *mux; 114 115 /* clocks and rests */ 116 struct reset_ctl *rsts; 117 118 /* PHY status management */ 119 bool flip; 120 bool mode_change; 121 u8 mode; 122 u8 status; 123 124 /* utilized for USB */ 125 bool hs; /* flag for high-speed */ 126 127 /* utilized for DP */ 128 struct gpio_desc *sbu1_dc_gpio; 129 struct gpio_desc *sbu2_dc_gpio; 130 u32 lane_mux_sel[4]; 131 u32 dp_lane_sel[4]; 132 u32 dp_aux_dout_sel; 133 u32 dp_aux_din_sel; 134 u32 max_link_rate; 135 u8 bw; /* dp bandwidth */ 136 int id; 137 138 /* PHY const config */ 139 const struct rockchip_udphy_cfg *cfgs; 140 }; 141 142 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = { 143 /* voltage swing 0, pre-emphasis 0->3 */ 144 { 145 { 0x20, 0x10, 0x42, 0xe5 }, 146 { 0x26, 0x14, 0x42, 0xe5 }, 147 { 0x29, 0x18, 0x42, 0xe5 }, 148 { 0x2b, 0x1c, 0x43, 0xe7 }, 149 }, 150 151 /* voltage swing 1, pre-emphasis 0->2 */ 152 { 153 { 0x23, 0x10, 0x42, 0xe7 }, 154 { 0x2a, 0x17, 0x43, 0xe7 }, 155 { 0x2b, 0x1a, 0x43, 0xe7 }, 156 }, 157 158 /* voltage swing 2, pre-emphasis 0->1 */ 159 { 160 { 0x27, 0x10, 0x42, 0xe7 }, 161 { 0x2b, 0x17, 0x43, 0xe7 }, 162 }, 163 164 /* voltage swing 3, pre-emphasis 0 */ 165 { 166 { 0x29, 0x10, 0x43, 0xe7 }, 167 }, 168 }; 169 170 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = { 171 /* voltage swing 0, pre-emphasis 0->3 */ 172 { 173 { 0x21, 0x10, 0x42, 0xe5 }, 174 { 0x26, 0x14, 0x42, 0xe5 }, 175 { 0x26, 0x16, 0x43, 0xe5 }, 176 { 0x2a, 0x19, 0x43, 0xe7 }, 177 }, 178 179 /* voltage swing 1, pre-emphasis 0->2 */ 180 { 181 { 0x24, 0x10, 0x42, 0xe7 }, 182 { 0x2a, 0x17, 0x43, 0xe7 }, 183 { 0x2b, 0x1a, 0x43, 0xe7 }, 184 }, 185 186 /* voltage swing 2, pre-emphasis 0->1 */ 187 { 188 { 0x28, 0x10, 0x42, 0xe7 }, 189 { 0x2b, 0x17, 0x43, 0xe7 }, 190 }, 191 192 /* voltage swing 3, pre-emphasis 0 */ 193 { 194 { 0x28, 0x10, 0x43, 0xe7 }, 195 }, 196 }; 197 198 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = { 199 /* voltage swing 0, pre-emphasis 0->3 */ 200 { 201 { 0x21, 0x10, 0x42, 0xe5 }, 202 { 0x26, 0x14, 0x42, 0xe5 }, 203 { 0x26, 0x16, 0x43, 0xe5 }, 204 { 0x29, 0x18, 0x43, 0xe7 }, 205 }, 206 207 /* voltage swing 1, pre-emphasis 0->2 */ 208 { 209 { 0x24, 0x10, 0x42, 0xe7 }, 210 { 0x2a, 0x18, 0x43, 0xe7 }, 211 { 0x2b, 0x1b, 0x43, 0xe7 } 212 }, 213 214 /* voltage swing 2, pre-emphasis 0->1 */ 215 { 216 { 0x27, 0x10, 0x42, 0xe7 }, 217 { 0x2b, 0x18, 0x43, 0xe7 } 218 }, 219 220 /* voltage swing 3, pre-emphasis 0 */ 221 { 222 { 0x28, 0x10, 0x43, 0xe7 }, 223 }, 224 }; 225 226 static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = { 227 {0x0090, 0x68}, {0x0094, 0x68}, 228 {0x0128, 0x24}, {0x012c, 0x44}, 229 {0x0130, 0x3f}, {0x0134, 0x44}, 230 {0x015c, 0xa9}, {0x0160, 0x71}, 231 {0x0164, 0x71}, {0x0168, 0xa9}, 232 {0x0174, 0xa9}, {0x0178, 0x71}, 233 {0x017c, 0x71}, {0x0180, 0xa9}, 234 {0x018c, 0x41}, {0x0190, 0x00}, 235 {0x0194, 0x05}, {0x01ac, 0x2a}, 236 {0x01b0, 0x17}, {0x01b4, 0x17}, 237 {0x01b8, 0x2a}, {0x01c8, 0x04}, 238 {0x01cc, 0x08}, {0x01d0, 0x08}, 239 {0x01d4, 0x04}, {0x01d8, 0x20}, 240 {0x01dc, 0x01}, {0x01e0, 0x09}, 241 {0x01e4, 0x03}, {0x01f0, 0x29}, 242 {0x01f4, 0x02}, {0x01f8, 0x02}, 243 {0x01fc, 0x29}, {0x0208, 0x2a}, 244 {0x020c, 0x17}, {0x0210, 0x17}, 245 {0x0214, 0x2a}, {0x0224, 0x20}, 246 {0x03f0, 0x0a}, {0x03f4, 0x07}, 247 {0x03f8, 0x07}, {0x03fc, 0x0c}, 248 {0x0404, 0x12}, {0x0408, 0x1a}, 249 {0x040c, 0x1a}, {0x0410, 0x3f}, 250 {0x0ce0, 0x68}, {0x0ce8, 0xd0}, 251 {0x0cf0, 0x87}, {0x0cf8, 0x70}, 252 {0x0d00, 0x70}, {0x0d08, 0xa9}, 253 {0x1ce0, 0x68}, {0x1ce8, 0xd0}, 254 {0x1cf0, 0x87}, {0x1cf8, 0x70}, 255 {0x1d00, 0x70}, {0x1d08, 0xa9}, 256 {0x0a3c, 0xd0}, {0x0a44, 0xd0}, 257 {0x0a48, 0x01}, {0x0a4c, 0x0d}, 258 {0x0a54, 0xe0}, {0x0a5c, 0xe0}, 259 {0x0a64, 0xa8}, {0x1a3c, 0xd0}, 260 {0x1a44, 0xd0}, {0x1a48, 0x01}, 261 {0x1a4c, 0x0d}, {0x1a54, 0xe0}, 262 {0x1a5c, 0xe0}, {0x1a64, 0xa8} 263 }; 264 265 static const struct reg_sequence rk3588_udphy_init_sequence[] = { 266 {0x0104, 0x44}, {0x0234, 0xE8}, 267 {0x0248, 0x44}, {0x028C, 0x18}, 268 {0x081C, 0xE5}, {0x0878, 0x00}, 269 {0x0994, 0x1C}, {0x0AF0, 0x00}, 270 {0x181C, 0xE5}, {0x1878, 0x00}, 271 {0x1994, 0x1C}, {0x1AF0, 0x00}, 272 {0x0428, 0x60}, {0x0D58, 0x33}, 273 {0x1D58, 0x33}, {0x0990, 0x74}, 274 {0x0D64, 0x17}, {0x08C8, 0x13}, 275 {0x1990, 0x74}, {0x1D64, 0x17}, 276 {0x18C8, 0x13}, {0x0D90, 0x40}, 277 {0x0DA8, 0x40}, {0x0DC0, 0x40}, 278 {0x0DD8, 0x40}, {0x1D90, 0x40}, 279 {0x1DA8, 0x40}, {0x1DC0, 0x40}, 280 {0x1DD8, 0x40}, {0x03C0, 0x30}, 281 {0x03C4, 0x06}, {0x0E10, 0x00}, 282 {0x1E10, 0x00}, {0x043C, 0x0F}, 283 {0x0D2C, 0xFF}, {0x1D2C, 0xFF}, 284 {0x0D34, 0x0F}, {0x1D34, 0x0F}, 285 {0x08FC, 0x2A}, {0x0914, 0x28}, 286 {0x0A30, 0x03}, {0x0E38, 0x03}, 287 {0x0ECC, 0x27}, {0x0ED0, 0x22}, 288 {0x0ED4, 0x26}, {0x18FC, 0x2A}, 289 {0x1914, 0x28}, {0x1A30, 0x03}, 290 {0x1E38, 0x03}, {0x1ECC, 0x27}, 291 {0x1ED0, 0x22}, {0x1ED4, 0x26}, 292 {0x0048, 0x0F}, {0x0060, 0x3C}, 293 {0x0064, 0xF7}, {0x006C, 0x20}, 294 {0x0070, 0x7D}, {0x0074, 0x68}, 295 {0x0AF4, 0x1A}, {0x1AF4, 0x1A}, 296 {0x0440, 0x3F}, {0x10D4, 0x08}, 297 {0x20D4, 0x08}, {0x00D4, 0x30}, 298 {0x0024, 0x6e}, 299 }; 300 301 static inline int grfreg_write(struct regmap *base, 302 const struct udphy_grf_reg *reg, bool en) 303 { 304 u32 val, mask, tmp; 305 306 tmp = en ? reg->enable : reg->disable; 307 mask = GENMASK(reg->bitend, reg->bitstart); 308 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 309 310 return regmap_write(base, reg->offset, val); 311 } 312 313 static int __regmap_multi_reg_write(struct regmap *map, 314 const struct reg_sequence *regs, int num_regs) 315 { 316 int i, ret = 0; 317 318 for (i = 0; i < num_regs; i++) { 319 ret = regmap_write(map, regs[i].reg, regs[i].def); 320 321 if (regs[i].delay_us) 322 udelay(regs[i].delay_us); 323 } 324 325 return ret; 326 } 327 328 static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev) 329 { 330 return 0; 331 } 332 333 static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev) 334 { 335 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 336 int idx; 337 int ret; 338 339 udphy->rsts = devm_kcalloc(dev, cfg->num_rsts, 340 sizeof(*udphy->rsts), GFP_KERNEL); 341 if (!udphy->rsts) 342 return -ENOMEM; 343 344 for (idx = 0; idx < cfg->num_rsts; idx++) { 345 const char *name = cfg->rst_list[idx]; 346 347 ret = reset_get_by_name(dev, name, &udphy->rsts[idx]); 348 if (ret) { 349 dev_err(dev, "failed to get %s reset\n", name); 350 goto err; 351 } 352 353 reset_assert(&udphy->rsts[idx]); 354 } 355 356 return 0; 357 358 err: 359 devm_kfree(dev, udphy->rsts); 360 return ret; 361 } 362 363 static int udphy_get_rst_idx(const char * const *list, int num, char *name) 364 { 365 int idx; 366 367 for (idx = 0; idx < num; idx++) { 368 if (!strcmp(list[idx], name)) 369 return idx; 370 } 371 372 return -EINVAL; 373 } 374 375 static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name) 376 { 377 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 378 int idx; 379 380 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); 381 if (idx < 0) 382 return idx; 383 384 return reset_assert(&udphy->rsts[idx]); 385 } 386 387 static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name) 388 { 389 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 390 int idx; 391 392 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); 393 if (idx < 0) 394 return idx; 395 396 return reset_deassert(&udphy->rsts[idx]); 397 } 398 399 static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable) 400 { 401 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 402 const struct udphy_grf_reg *preg; 403 404 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; 405 grfreg_write(udphy->usbgrf, preg, disable); 406 } 407 408 __maybe_unused 409 static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable) 410 { 411 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 412 413 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); 414 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); 415 } 416 417 /* 418 * In usb/dp combo phy driver, here are 2 ways to mapping lanes. 419 * 420 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) 421 * --------------------------------------------------------------------------- 422 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 423 * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 424 * C/E(Normal) dpln3 dpln2 dpln0 dpln1 425 * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 426 * D/F(Normal) usbrx usbtx dpln0 dpln1 427 * D/F(Flip ) dpln0 dpln1 usbrx usbtx 428 * A(Normal ) dpln3 dpln1 dpln2 dpln0 429 * A(Flip ) dpln2 dpln0 dpln3 dpln1 430 * B(Normal ) usbrx usbtx dpln1 dpln0 431 * B(Flip ) dpln1 dpln0 usbrx usbtx 432 * --------------------------------------------------------------------------- 433 * 434 * 2 Mapping the lanes in dtsi 435 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>; 436 * sample as follow: 437 * --------------------------------------------------------------------------- 438 * B11-B10 A2-A3 A11-A10 B2-B3 439 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 440 * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 441 * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 442 * --------------------------------------------------------------------------- 443 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>; 444 * sample as follow: 445 * --------------------------------------------------------------------------- 446 * B11-B10 A2-A3 A11-A10 B2-B3 447 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 448 * <0 1> dpln0 dpln1 usbrx usbtx 449 * <2 3> usbrx usbtx dpln0 dpln1 450 * --------------------------------------------------------------------------- 451 */ 452 static int udphy_dplane_select(struct rockchip_udphy *udphy) 453 { 454 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 455 456 if (cfg->dplane_select) 457 return cfg->dplane_select(udphy); 458 459 return 0; 460 } 461 462 static int udphy_dplane_get(struct rockchip_udphy *udphy) 463 { 464 int dp_lanes; 465 466 switch (udphy->mode) { 467 case UDPHY_MODE_DP: 468 dp_lanes = 4; 469 break; 470 case UDPHY_MODE_DP_USB: 471 dp_lanes = 2; 472 break; 473 case UDPHY_MODE_USB: 474 /* fallthrough; */ 475 default: 476 dp_lanes = 0; 477 break; 478 } 479 480 return dp_lanes; 481 } 482 483 static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes) 484 { 485 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 486 int ret = 0; 487 488 if (cfg->dplane_enable) 489 ret = cfg->dplane_enable(udphy, dp_lanes); 490 491 return ret; 492 } 493 494 495 __maybe_unused 496 static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy) 497 { 498 if (udphy->flip) { 499 udphy->dp_lane_sel[0] = 0; 500 udphy->dp_lane_sel[1] = 1; 501 udphy->dp_lane_sel[2] = 3; 502 udphy->dp_lane_sel[3] = 2; 503 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; 504 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; 505 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; 506 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; 507 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; 508 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; 509 } else { 510 udphy->dp_lane_sel[0] = 2; 511 udphy->dp_lane_sel[1] = 3; 512 udphy->dp_lane_sel[2] = 1; 513 udphy->dp_lane_sel[3] = 0; 514 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; 515 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; 516 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; 517 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; 518 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; 519 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; 520 } 521 522 udphy->mode = UDPHY_MODE_DP_USB; 523 524 return 0; 525 } 526 527 static int udphy_setup(struct rockchip_udphy *udphy) 528 { 529 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 530 int ret = 0; 531 532 if (cfg->combophy_init) { 533 ret = cfg->combophy_init(udphy); 534 if (ret) 535 dev_err(udphy->dev, "failed to init combophy\n"); 536 } 537 538 return ret; 539 } 540 541 static int udphy_disable(struct rockchip_udphy *udphy) 542 { 543 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 544 int i; 545 546 for (i = 0; i < cfg->num_rsts; i++) 547 reset_assert(&udphy->rsts[i]); 548 549 return 0; 550 } 551 552 static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct udevice *dev) 553 { 554 const void *prop; 555 int ret, i, len, num_lanes; 556 557 prop = dev_read_prop(dev, "rockchip,dp-lane-mux", &len); 558 if (!prop) { 559 dev_dbg(dev, "failed to find dp lane mux, following dp alt mode\n"); 560 udphy->mode = UDPHY_MODE_USB; 561 return 0; 562 } 563 564 num_lanes = len / sizeof(u32); 565 566 if (num_lanes != 2 && num_lanes != 4) { 567 dev_err(dev, "invalid number of lane mux\n"); 568 return -EINVAL; 569 } 570 571 ret = dev_read_u32_array(dev, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes); 572 if (ret) { 573 dev_err(dev, "get dp lane mux failed\n"); 574 return -EINVAL; 575 } 576 577 for (i = 0; i < num_lanes; i++) { 578 int j; 579 580 if (udphy->dp_lane_sel[i] > 3) { 581 dev_err(dev, "lane mux between 0 and 3, exceeding the range\n"); 582 return -EINVAL; 583 } 584 585 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; 586 587 for (j = i + 1; j < num_lanes; j++) { 588 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) { 589 dev_err(dev, "set repeat lane mux value\n"); 590 return -EINVAL; 591 } 592 } 593 } 594 595 udphy->mode = UDPHY_MODE_DP; 596 if (num_lanes == 2) { 597 udphy->mode |= UDPHY_MODE_USB; 598 udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false; 599 } 600 601 return 0; 602 } 603 604 static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev) 605 { 606 enum usb_device_speed maximum_speed; 607 int ret; 608 609 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,u2phy-grf"); 610 if (IS_ERR(udphy->u2phygrf)) { 611 if (PTR_ERR(udphy->u2phygrf) == -ENODEV) { 612 dev_warn(dev, "missing u2phy-grf dt node\n"); 613 udphy->u2phygrf = NULL; 614 } else { 615 return PTR_ERR(udphy->u2phygrf); 616 } 617 } 618 619 udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usbdpphy-grf"); 620 if (IS_ERR(udphy->udphygrf)) { 621 if (PTR_ERR(udphy->udphygrf) == -ENODEV) { 622 dev_warn(dev, "missing usbdpphy-grf dt node\n"); 623 udphy->udphygrf = NULL; 624 } else { 625 return PTR_ERR(udphy->udphygrf); 626 } 627 } 628 629 udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usb-grf"); 630 if (IS_ERR(udphy->usbgrf)) { 631 if (PTR_ERR(udphy->usbgrf) == -ENODEV) { 632 dev_warn(dev, "missing usb-grf dt node\n"); 633 udphy->usbgrf = NULL; 634 } else { 635 return PTR_ERR(udphy->usbgrf); 636 } 637 } 638 639 udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf"); 640 if (IS_ERR(udphy->vogrf)) { 641 if (PTR_ERR(udphy->vogrf) == -ENODEV) { 642 dev_warn(dev, "missing vo-grf dt node\n"); 643 udphy->vogrf = NULL; 644 } else { 645 return PTR_ERR(udphy->vogrf); 646 } 647 } 648 649 ret = udphy_parse_lane_mux_data(udphy, dev); 650 if (ret) 651 return ret; 652 653 if (dev_read_prop(dev, "maximum-speed", NULL)) { 654 maximum_speed = usb_get_maximum_speed(dev->node); 655 udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false; 656 } 657 658 ret = udphy_clk_init(udphy, dev); 659 if (ret) 660 return ret; 661 662 ret = udphy_reset_init(udphy, dev); 663 if (ret) 664 return ret; 665 666 return 0; 667 } 668 669 static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) 670 { 671 int ret; 672 673 if (!(udphy->mode & mode)) { 674 printf("%s: mode 0x%02x is not support\n", udphy->dev->name, 675 mode); 676 return -EINVAL; 677 } 678 679 if (udphy->status == UDPHY_MODE_NONE) { 680 udphy->mode_change = false; 681 ret = udphy_setup(udphy); 682 if (ret) 683 return ret; 684 685 if (udphy->mode & UDPHY_MODE_USB) 686 udphy_u3_port_disable(udphy, false); 687 } else if (udphy->mode_change) { 688 udphy->mode_change = false; 689 udphy->status = UDPHY_MODE_NONE; 690 if (udphy->mode == UDPHY_MODE_DP) 691 udphy_u3_port_disable(udphy, true); 692 693 ret = udphy_disable(udphy); 694 if (ret) 695 return ret; 696 ret = udphy_setup(udphy); 697 if (ret) 698 return ret; 699 } 700 701 udphy->status |= mode; 702 703 return 0; 704 } 705 706 static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) 707 { 708 int ret; 709 710 if (!(udphy->mode & mode)) { 711 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); 712 return 0; 713 } 714 715 if (!udphy->status) 716 return 0; 717 718 udphy->status &= ~mode; 719 720 if (udphy->status == UDPHY_MODE_NONE) { 721 ret = udphy_disable(udphy); 722 if (ret) 723 return ret; 724 } 725 726 return 0; 727 } 728 729 static int rockchip_dpphy_power_on(struct phy *phy) 730 { 731 struct udevice *parent = phy->dev->parent; 732 struct rockchip_udphy *udphy = dev_get_priv(parent); 733 int ret, dp_lanes; 734 735 dp_lanes = udphy_dplane_get(udphy); 736 phy->attrs.bus_width = dp_lanes; 737 phy->attrs.max_link_rate = udphy->max_link_rate; 738 739 ret = udphy_power_on(udphy, UDPHY_MODE_DP); 740 if (ret) 741 return ret; 742 743 ret = udphy_dplane_enable(udphy, dp_lanes); 744 if (ret) 745 return ret; 746 747 return udphy_dplane_select(udphy); 748 } 749 750 static int rockchip_dpphy_power_off(struct phy *phy) 751 { 752 struct udevice *parent = phy->dev->parent; 753 struct rockchip_udphy *udphy = dev_get_priv(parent); 754 int ret; 755 756 ret = udphy_dplane_enable(udphy, 0); 757 if (ret) 758 return ret; 759 760 return udphy_power_off(udphy, UDPHY_MODE_DP); 761 } 762 763 static int rockchip_dpphy_verify_config(struct rockchip_udphy *udphy, 764 struct phy_configure_opts_dp *dp) 765 { 766 int i; 767 768 /* If changing link rate was required, verify it's supported. */ 769 if (dp->set_rate) { 770 switch (dp->link_rate) { 771 case 1620: 772 case 2700: 773 case 5400: 774 case 8100: 775 /* valid bit rate */ 776 break; 777 default: 778 return -EINVAL; 779 } 780 } 781 782 /* Verify lane count. */ 783 switch (dp->lanes) { 784 case 1: 785 case 2: 786 case 4: 787 /* valid lane count. */ 788 break; 789 default: 790 return -EINVAL; 791 } 792 793 /* 794 * If changing voltages is required, check swing and pre-emphasis 795 * levels, per-lane. 796 */ 797 if (dp->set_voltages) { 798 /* Lane count verified previously. */ 799 for (i = 0; i < dp->lanes; i++) { 800 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 801 return -EINVAL; 802 803 /* 804 * Sum of voltage swing and pre-emphasis levels cannot 805 * exceed 3. 806 */ 807 if (dp->voltage[i] + dp->pre[i] > 3) 808 return -EINVAL; 809 } 810 } 811 812 return 0; 813 } 814 815 static int rockchip_dpphy_configure(struct phy *phy, 816 union phy_configure_opts *opts) 817 { 818 struct udevice *parent = phy->dev->parent; 819 struct rockchip_udphy *udphy = dev_get_priv(parent); 820 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 821 int ret; 822 823 ret = rockchip_dpphy_verify_config(udphy, &opts->dp); 824 if (ret) 825 return ret; 826 827 if (opts->dp.set_rate && cfg->dp_phy_set_rate) { 828 ret = cfg->dp_phy_set_rate(udphy, &opts->dp); 829 if (ret) { 830 printf("%s: rockchip_hdptx_phy_set_rate failed\n", 831 udphy->dev->name); 832 return ret; 833 } 834 } 835 836 if (opts->dp.set_voltages && cfg->dp_phy_set_voltages) { 837 ret = cfg->dp_phy_set_voltages(udphy, &opts->dp); 838 if (ret) { 839 printf("%s: rockchip_dp_phy_set_voltages failed\n", 840 udphy->dev->name); 841 return ret; 842 } 843 } 844 845 return 0; 846 } 847 848 static const struct phy_ops rockchip_dpphy_ops = { 849 .power_on = rockchip_dpphy_power_on, 850 .power_off = rockchip_dpphy_power_off, 851 .configure = rockchip_dpphy_configure, 852 }; 853 854 static int rockchip_u3phy_init(struct phy *phy) 855 { 856 struct udevice *parent = phy->dev->parent; 857 struct rockchip_udphy *udphy = dev_get_priv(parent); 858 859 /* DP only or high-speed, disable U3 port */ 860 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { 861 udphy_u3_port_disable(udphy, true); 862 return 0; 863 } 864 865 return udphy_power_on(udphy, UDPHY_MODE_USB); 866 } 867 868 static int rockchip_u3phy_exit(struct phy *phy) 869 { 870 struct udevice *parent = phy->dev->parent; 871 struct rockchip_udphy *udphy = dev_get_priv(parent); 872 873 /* DP only or high-speed */ 874 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) 875 return 0; 876 877 return udphy_power_off(udphy, UDPHY_MODE_USB); 878 } 879 880 static const struct phy_ops rockchip_u3phy_ops = { 881 .init = rockchip_u3phy_init, 882 .exit = rockchip_u3phy_exit, 883 }; 884 885 int rockchip_u3phy_uboot_init(void) 886 { 887 struct udevice *udev; 888 struct rockchip_udphy *udphy; 889 unsigned int val; 890 int ret; 891 892 ret = uclass_get_device_by_driver(UCLASS_PHY, 893 DM_GET_DRIVER(rockchip_udphy_u3_port), 894 &udev); 895 if (ret) { 896 pr_err("%s: get u3-port failed: %d\n", __func__, ret); 897 return ret; 898 } 899 900 /* DP only or high-speed, disable U3 port */ 901 udphy = dev_get_priv(udev->parent); 902 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { 903 pr_err("%s: udphy mode not support usb3\n", __func__); 904 goto disable_u3; 905 } 906 907 udphy->flip = false; 908 upphy_set_typec_default_mapping(udphy); 909 910 ret = udphy_power_on(udphy, UDPHY_MODE_USB); 911 if (ret) { 912 pr_err("%s: udphy power on failed: %d\n", __func__, ret); 913 goto disable_u3; 914 } 915 916 ret = regmap_read_poll_timeout(udphy->pma_regmap, 917 TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, 918 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, 919 200, 100); 920 if (ret) { 921 pr_err("%s: udphy rx cdr lock timeout\n", __func__); 922 goto disable_u3; 923 } 924 925 return 0; 926 927 disable_u3: 928 udphy_u3_port_disable(udphy, true); 929 930 return -EOPNOTSUPP; 931 } 932 933 static int rockchip_udphy_probe(struct udevice *dev) 934 { 935 struct rockchip_udphy *udphy = dev_get_priv(dev); 936 const struct rockchip_udphy_cfg *phy_cfgs; 937 int id, ret; 938 939 udphy->dev = dev; 940 941 dev_read_alias_seq(dev, &id); 942 if (id < 0) 943 id = 0; 944 udphy->id = id; 945 946 phy_cfgs = (const struct rockchip_udphy_cfg *) dev_get_driver_data(dev); 947 if (!phy_cfgs) { 948 dev_err(dev, "unable to get phy_cfgs\n"); 949 return -EINVAL; 950 } 951 udphy->cfgs = phy_cfgs; 952 953 ret = regmap_init_mem(dev, &udphy->pma_regmap); 954 if (ret) 955 return ret; 956 udphy->pma_regmap->base += UDPHY_PMA; 957 958 ret = udphy_parse_dt(udphy, dev); 959 if (ret) 960 return ret; 961 962 return 0; 963 } 964 965 static int rockchip_udphy_bind(struct udevice *parent) 966 { 967 struct udevice *child; 968 ofnode subnode; 969 const char *node_name; 970 int ret; 971 972 dev_for_each_subnode(subnode, parent) { 973 if (!ofnode_valid(subnode)) { 974 printf("%s: no subnode for %s\n", __func__, parent->name); 975 return -ENXIO; 976 } 977 978 node_name = ofnode_get_name(subnode); 979 debug("%s: subnode %s\n", __func__, node_name); 980 981 if (!strcasecmp(node_name, "u3-port")) { 982 ret = device_bind_driver_to_node(parent, 983 "rockchip_udphy_u3_port", 984 node_name, subnode, &child); 985 if (ret) { 986 printf("%s: '%s' cannot bind its driver\n", 987 __func__, node_name); 988 return ret; 989 } 990 } else if (!strcasecmp(node_name, "dp-port")) { 991 ret = device_bind_driver_to_node(parent, 992 "rockchip_udphy_dp_port", 993 node_name, subnode, &child); 994 if (ret) { 995 printf("%s: '%s' cannot bind its driver\n", 996 __func__, node_name); 997 return ret; 998 } 999 } 1000 } 1001 1002 return 0; 1003 } 1004 1005 static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy) 1006 { 1007 int ret; 1008 1009 /* configure phy reference clock */ 1010 ret = __regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_24m_refclk_cfg, 1011 ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg)); 1012 if (ret) 1013 return ret; 1014 1015 return 0; 1016 } 1017 1018 static int rk3588_udphy_status_check(struct rockchip_udphy *udphy) 1019 { 1020 unsigned int val; 1021 int ret; 1022 1023 /* LCPLL check */ 1024 if (udphy->mode & UDPHY_MODE_USB) { 1025 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, 1026 val, (val & CMN_ANA_LCPLL_AFC_DONE) && 1027 (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100); 1028 if (ret) { 1029 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); 1030 return ret; 1031 } 1032 } 1033 1034 if (udphy->mode & UDPHY_MODE_USB) { 1035 if (!udphy->flip) { 1036 ret = regmap_read_poll_timeout(udphy->pma_regmap, 1037 TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, 1038 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, 1039 200, 100); 1040 if (ret) 1041 dev_notice(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); 1042 } else { 1043 ret = regmap_read_poll_timeout(udphy->pma_regmap, 1044 TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val, 1045 val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, 1046 200, 100); 1047 if (ret) 1048 dev_notice(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); 1049 } 1050 } 1051 1052 return 0; 1053 } 1054 1055 static int rk3588_udphy_init(struct rockchip_udphy *udphy) 1056 { 1057 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 1058 int ret; 1059 1060 /* enable rx lfps for usb */ 1061 if (udphy->mode & UDPHY_MODE_USB) 1062 grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); 1063 1064 /* Step 1: power on pma and deassert apb rstn */ 1065 grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); 1066 1067 udphy_reset_deassert(udphy, "pma_apb"); 1068 udphy_reset_deassert(udphy, "pcs_apb"); 1069 1070 /* Step 2: set init sequence and phy refclk */ 1071 ret = __regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_init_sequence, 1072 ARRAY_SIZE(rk3588_udphy_init_sequence)); 1073 if (ret) { 1074 dev_err(udphy->dev, "init sequence set error %d\n", ret); 1075 goto assert_apb; 1076 } 1077 1078 ret = rk3588_udphy_refclk_set(udphy); 1079 if (ret) { 1080 dev_err(udphy->dev, "refclk set error %d\n", ret); 1081 goto assert_apb; 1082 } 1083 1084 /* Step 3: configure lane mux */ 1085 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, 1086 CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, 1087 FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | 1088 FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | 1089 FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | 1090 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | 1091 FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); 1092 1093 /* Step 4: deassert init rstn and wait for 200ns from datasheet */ 1094 if (udphy->mode & UDPHY_MODE_USB) 1095 udphy_reset_deassert(udphy, "init"); 1096 1097 if (udphy->mode & UDPHY_MODE_DP) { 1098 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 1099 CMN_DP_INIT_RSTN, 1100 FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); 1101 } 1102 1103 udelay(1); 1104 1105 /* Step 5: deassert cmn/lane rstn */ 1106 if (udphy->mode & UDPHY_MODE_USB) { 1107 udphy_reset_deassert(udphy, "cmn"); 1108 udphy_reset_deassert(udphy, "lane"); 1109 } 1110 1111 /* Step 6: wait for lock done of pll */ 1112 ret = rk3588_udphy_status_check(udphy); 1113 if (ret) 1114 goto assert_phy; 1115 1116 return 0; 1117 1118 assert_phy: 1119 udphy_reset_assert(udphy, "init"); 1120 udphy_reset_assert(udphy, "cmn"); 1121 udphy_reset_assert(udphy, "lane"); 1122 1123 assert_apb: 1124 udphy_reset_assert(udphy, "pma_apb"); 1125 udphy_reset_assert(udphy, "pcs_apb"); 1126 return ret; 1127 } 1128 1129 static int rk3588_udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes) 1130 { 1131 int i; 1132 u32 val = 0; 1133 1134 for (i = 0; i < dp_lanes; i++) 1135 val |= BIT(udphy->dp_lane_sel[i]); 1136 1137 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, 1138 FIELD_PREP(CMN_DP_LANE_EN_ALL, val)); 1139 1140 if (!dp_lanes) 1141 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 1142 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); 1143 1144 return 0; 1145 } 1146 1147 static int rk3588_udphy_dplane_select(struct rockchip_udphy *udphy) 1148 { 1149 u32 value = 0; 1150 1151 switch (udphy->mode) { 1152 case UDPHY_MODE_DP: 1153 value |= 2 << udphy->dp_lane_sel[2] * 2; 1154 value |= 3 << udphy->dp_lane_sel[3] * 2; 1155 case UDPHY_MODE_DP_USB: 1156 value |= 0 << udphy->dp_lane_sel[0] * 2; 1157 value |= 1 << udphy->dp_lane_sel[1] * 2; 1158 break; 1159 case UDPHY_MODE_USB: 1160 break; 1161 default: 1162 break; 1163 } 1164 1165 regmap_write(udphy->vogrf, udphy->id ? RK3588_GRF_VO0_CON2 : RK3588_GRF_VO0_CON0, 1166 ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) | 1167 FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | 1168 FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); 1169 1170 return 0; 1171 } 1172 1173 static int rk3588_dp_phy_set_rate(struct rockchip_udphy *udphy, 1174 struct phy_configure_opts_dp *dp) 1175 { 1176 u32 val; 1177 int ret; 1178 1179 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 1180 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); 1181 1182 switch (dp->link_rate) { 1183 case 1620: 1184 udphy->bw = DP_BW_RBR; 1185 break; 1186 case 2700: 1187 udphy->bw = DP_BW_HBR; 1188 break; 1189 case 5400: 1190 udphy->bw = DP_BW_HBR2; 1191 break; 1192 case 8100: 1193 udphy->bw = DP_BW_HBR3; 1194 break; 1195 default: 1196 return -EINVAL; 1197 } 1198 1199 regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, 1200 FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); 1201 regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, 1202 FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); 1203 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, 1204 FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); 1205 1206 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, 1207 FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) && 1208 FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val), 1209 0, 1000); 1210 if (ret) { 1211 printf("ROPLL is not lock\n"); 1212 return ret; 1213 } 1214 1215 return 0; 1216 } 1217 1218 static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw, 1219 u32 voltage, u32 pre, u32 lane) 1220 { 1221 u32 offset = 0x800 * lane; 1222 u32 val; 1223 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 1224 const struct dp_tx_drv_ctrl (*dp_ctrl)[4]; 1225 1226 dp_ctrl = cfg->dp_tx_ctrl_cfg[bw]; 1227 val = dp_ctrl[voltage][pre].trsv_reg0204; 1228 regmap_write(udphy->pma_regmap, 0x0810 + offset, val); 1229 1230 val = dp_ctrl[voltage][pre].trsv_reg0205; 1231 regmap_write(udphy->pma_regmap, 0x0814 + offset, val); 1232 1233 val = dp_ctrl[voltage][pre].trsv_reg0206; 1234 regmap_write(udphy->pma_regmap, 0x0818 + offset, val); 1235 1236 val = dp_ctrl[voltage][pre].trsv_reg0207; 1237 regmap_write(udphy->pma_regmap, 0x081c + offset, val); 1238 } 1239 1240 static int rk3588_dp_phy_set_voltages(struct rockchip_udphy *udphy, 1241 struct phy_configure_opts_dp *dp) 1242 { 1243 u32 i, lane; 1244 1245 for (i = 0; i < dp->lanes; i++) { 1246 lane = udphy->dp_lane_sel[i]; 1247 switch (dp->link_rate) { 1248 case 1620: 1249 case 2700: 1250 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), 1251 LN_ANA_TX_SER_TXCLK_INV, 1252 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 1253 udphy->lane_mux_sel[lane])); 1254 break; 1255 case 5400: 1256 case 8100: 1257 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), 1258 LN_ANA_TX_SER_TXCLK_INV, 1259 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); 1260 break; 1261 } 1262 1263 rk3588_dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane); 1264 } 1265 1266 return 0; 1267 } 1268 1269 static int rockchip_dpphy_probe(struct udevice *dev) 1270 { 1271 struct rockchip_udphy *udphy = dev_get_priv(dev->parent); 1272 u32 max_link_rate; 1273 1274 max_link_rate = dev_read_u32_default(dev, "max-link-rate", 8100); 1275 switch (max_link_rate) { 1276 case 1620: 1277 case 2700: 1278 case 5400: 1279 case 8100: 1280 break; 1281 default: 1282 dev_warn(dev, "invalid max-link-rate %d, using 8100\n", max_link_rate); 1283 max_link_rate = 8100; 1284 break; 1285 } 1286 1287 udphy->max_link_rate = max_link_rate; 1288 1289 return 0; 1290 } 1291 1292 static const char * const rk3588_udphy_rst_l[] = { 1293 "init", "cmn", "lane", "pcs_apb", "pma_apb" 1294 }; 1295 1296 static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { 1297 .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l), 1298 .rst_list = rk3588_udphy_rst_l, 1299 .grfcfg = { 1300 /* u2phy-grf */ 1301 .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 }, 1302 .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 }, 1303 1304 /* usb-grf */ 1305 .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 }, 1306 .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 }, 1307 1308 /* usbdpphy-grf */ 1309 .low_pwrn = { 0x0004, 13, 13, 0, 1 }, 1310 .rx_lfps = { 0x0004, 14, 14, 0, 1 }, 1311 }, 1312 .dp_tx_ctrl_cfg = { 1313 rk3588_dp_tx_drv_ctrl_rbr_hbr, 1314 rk3588_dp_tx_drv_ctrl_rbr_hbr, 1315 rk3588_dp_tx_drv_ctrl_hbr2, 1316 rk3588_dp_tx_drv_ctrl_hbr3, 1317 }, 1318 .combophy_init = rk3588_udphy_init, 1319 .dp_phy_set_rate = rk3588_dp_phy_set_rate, 1320 .dp_phy_set_voltages = rk3588_dp_phy_set_voltages, 1321 .dplane_enable = rk3588_udphy_dplane_enable, 1322 .dplane_select = rk3588_udphy_dplane_select, 1323 }; 1324 1325 static const struct udevice_id rockchip_udphy_dt_match[] = { 1326 { 1327 .compatible = "rockchip,rk3588-usbdp-phy", 1328 .data = (ulong)&rk3588_udphy_cfgs 1329 }, 1330 { /* sentinel */ } 1331 }; 1332 1333 U_BOOT_DRIVER(rockchip_udphy_u3_port) = { 1334 .name = "rockchip_udphy_u3_port", 1335 .id = UCLASS_PHY, 1336 .ops = &rockchip_u3phy_ops, 1337 }; 1338 1339 U_BOOT_DRIVER(rockchip_udphy_dp_port) = { 1340 .name = "rockchip_udphy_dp_port", 1341 .id = UCLASS_PHY, 1342 .ops = &rockchip_dpphy_ops, 1343 .probe = rockchip_dpphy_probe, 1344 }; 1345 1346 U_BOOT_DRIVER(rockchip_udphy) = { 1347 .name = "rockchip_udphy", 1348 .id = UCLASS_PHY, 1349 .of_match = rockchip_udphy_dt_match, 1350 .probe = rockchip_udphy_probe, 1351 .bind = rockchip_udphy_bind, 1352 .priv_auto_alloc_size = sizeof(struct rockchip_udphy), 1353 }; 1354