1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dm/of.h> 13 #include <dm/of_access.h> 14 #include <generic-phy.h> 15 #include <linux/bitfield.h> 16 #include <linux/usb/ch9.h> 17 #include <linux/usb/otg.h> 18 #include <regmap.h> 19 #include <reset.h> 20 #include <syscon.h> 21 #include <asm/arch/clock.h> 22 #include <asm/arch/cpu.h> 23 24 #include <linux/usb/phy-rockchip-usbdp.h> 25 26 #define BIT_WRITEABLE_SHIFT 16 27 28 enum { 29 DP_BW_RBR, 30 DP_BW_HBR, 31 DP_BW_HBR2, 32 DP_BW_HBR3, 33 }; 34 35 enum { 36 UDPHY_MODE_NONE = 0, 37 UDPHY_MODE_USB = BIT(0), 38 UDPHY_MODE_DP = BIT(1), 39 UDPHY_MODE_DP_USB = BIT(1) | BIT(0), 40 }; 41 42 struct udphy_grf_reg { 43 unsigned int offset; 44 unsigned int bitend; 45 unsigned int bitstart; 46 unsigned int disable; 47 unsigned int enable; 48 }; 49 50 /** 51 * struct reg_sequence - An individual write from a sequence of writes. 52 * 53 * @reg: Register address. 54 * @def: Register value. 55 * @delay_us: Delay to be applied after the register write in microseconds 56 * 57 * Register/value pairs for sequences of writes with an optional delay in 58 * microseconds to be applied after each write. 59 */ 60 struct reg_sequence { 61 unsigned int reg; 62 unsigned int def; 63 unsigned int delay_us; 64 }; 65 66 struct udphy_grf_cfg { 67 /* u2phy-grf */ 68 struct udphy_grf_reg bvalid_phy_con; 69 struct udphy_grf_reg bvalid_grf_con; 70 71 /* usb-grf */ 72 struct udphy_grf_reg usb3otg0_cfg; 73 struct udphy_grf_reg usb3otg1_cfg; 74 75 /* usbdpphy-grf */ 76 struct udphy_grf_reg low_pwrn; 77 struct udphy_grf_reg rx_lfps; 78 }; 79 80 struct dp_tx_drv_ctrl { 81 u32 trsv_reg0204; 82 u32 trsv_reg0205; 83 u32 trsv_reg0206; 84 u32 trsv_reg0207; 85 }; 86 87 struct rockchip_udphy; 88 89 struct rockchip_udphy_cfg { 90 /* resets to be requested */ 91 const char * const *rst_list; 92 int num_rsts; 93 94 struct udphy_grf_cfg grfcfg; 95 const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4]; 96 int (*combophy_init)(struct rockchip_udphy *udphy); 97 int (*dp_phy_set_rate)(struct rockchip_udphy *udphy, 98 struct phy_configure_opts_dp *dp); 99 int (*dp_phy_set_voltages)(struct rockchip_udphy *udphy, 100 struct phy_configure_opts_dp *dp); 101 int (*dplane_enable)(struct rockchip_udphy *udphy, int dp_lanes); 102 int (*dplane_select)(struct rockchip_udphy *udphy); 103 }; 104 105 struct rockchip_udphy { 106 struct udevice *dev; 107 struct regmap *pma_regmap; 108 struct regmap *u2phygrf; 109 struct regmap *udphygrf; 110 struct regmap *usbgrf; 111 struct regmap *vogrf; 112 // struct typec_switch *sw; 113 // struct typec_mux *mux; 114 115 /* clocks and rests */ 116 struct reset_ctl *rsts; 117 118 /* PHY status management */ 119 bool flip; 120 bool mode_change; 121 u8 mode; 122 u8 status; 123 124 /* utilized for USB */ 125 bool hs; /* flag for high-speed */ 126 127 /* utilized for DP */ 128 struct gpio_desc *sbu1_dc_gpio; 129 struct gpio_desc *sbu2_dc_gpio; 130 u32 lane_mux_sel[4]; 131 u32 dp_lane_sel[4]; 132 u32 dp_aux_dout_sel; 133 u32 dp_aux_din_sel; 134 u32 max_link_rate; 135 u8 bw; /* dp bandwidth */ 136 int id; 137 138 /* PHY const config */ 139 const struct rockchip_udphy_cfg *cfgs; 140 }; 141 142 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = { 143 /* voltage swing 0, pre-emphasis 0->3 */ 144 { 145 { 0x20, 0x10, 0x42, 0xe5 }, 146 { 0x26, 0x14, 0x42, 0xe5 }, 147 { 0x29, 0x18, 0x42, 0xe5 }, 148 { 0x2b, 0x1c, 0x43, 0xe7 }, 149 }, 150 151 /* voltage swing 1, pre-emphasis 0->2 */ 152 { 153 { 0x23, 0x10, 0x42, 0xe7 }, 154 { 0x2a, 0x17, 0x43, 0xe7 }, 155 { 0x2b, 0x1a, 0x43, 0xe7 }, 156 }, 157 158 /* voltage swing 2, pre-emphasis 0->1 */ 159 { 160 { 0x27, 0x10, 0x42, 0xe7 }, 161 { 0x2b, 0x17, 0x43, 0xe7 }, 162 }, 163 164 /* voltage swing 3, pre-emphasis 0 */ 165 { 166 { 0x29, 0x10, 0x43, 0xe7 }, 167 }, 168 }; 169 170 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = { 171 /* voltage swing 0, pre-emphasis 0->3 */ 172 { 173 { 0x21, 0x10, 0x42, 0xe5 }, 174 { 0x26, 0x14, 0x42, 0xe5 }, 175 { 0x26, 0x16, 0x43, 0xe5 }, 176 { 0x2a, 0x19, 0x43, 0xe7 }, 177 }, 178 179 /* voltage swing 1, pre-emphasis 0->2 */ 180 { 181 { 0x24, 0x10, 0x42, 0xe7 }, 182 { 0x2a, 0x17, 0x43, 0xe7 }, 183 { 0x2b, 0x1a, 0x43, 0xe7 }, 184 }, 185 186 /* voltage swing 2, pre-emphasis 0->1 */ 187 { 188 { 0x28, 0x10, 0x42, 0xe7 }, 189 { 0x2b, 0x17, 0x43, 0xe7 }, 190 }, 191 192 /* voltage swing 3, pre-emphasis 0 */ 193 { 194 { 0x28, 0x10, 0x43, 0xe7 }, 195 }, 196 }; 197 198 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = { 199 /* voltage swing 0, pre-emphasis 0->3 */ 200 { 201 { 0x21, 0x10, 0x42, 0xe5 }, 202 { 0x26, 0x14, 0x42, 0xe5 }, 203 { 0x26, 0x16, 0x43, 0xe5 }, 204 { 0x29, 0x18, 0x43, 0xe7 }, 205 }, 206 207 /* voltage swing 1, pre-emphasis 0->2 */ 208 { 209 { 0x24, 0x10, 0x42, 0xe7 }, 210 { 0x2a, 0x18, 0x43, 0xe7 }, 211 { 0x2b, 0x1b, 0x43, 0xe7 } 212 }, 213 214 /* voltage swing 2, pre-emphasis 0->1 */ 215 { 216 { 0x27, 0x10, 0x42, 0xe7 }, 217 { 0x2b, 0x18, 0x43, 0xe7 } 218 }, 219 220 /* voltage swing 3, pre-emphasis 0 */ 221 { 222 { 0x28, 0x10, 0x43, 0xe7 }, 223 }, 224 }; 225 226 static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = { 227 {0x0090, 0x68}, {0x0094, 0x68}, 228 {0x0128, 0x24}, {0x012c, 0x44}, 229 {0x0130, 0x3f}, {0x0134, 0x44}, 230 {0x015c, 0xa9}, {0x0160, 0x71}, 231 {0x0164, 0x71}, {0x0168, 0xa9}, 232 {0x0174, 0xa9}, {0x0178, 0x71}, 233 {0x017c, 0x71}, {0x0180, 0xa9}, 234 {0x018c, 0x41}, {0x0190, 0x00}, 235 {0x0194, 0x05}, {0x01ac, 0x2a}, 236 {0x01b0, 0x17}, {0x01b4, 0x17}, 237 {0x01b8, 0x2a}, {0x01c8, 0x04}, 238 {0x01cc, 0x08}, {0x01d0, 0x08}, 239 {0x01d4, 0x04}, {0x01d8, 0x20}, 240 {0x01dc, 0x01}, {0x01e0, 0x09}, 241 {0x01e4, 0x03}, {0x01f0, 0x29}, 242 {0x01f4, 0x02}, {0x01f8, 0x02}, 243 {0x01fc, 0x29}, {0x0208, 0x2a}, 244 {0x020c, 0x17}, {0x0210, 0x17}, 245 {0x0214, 0x2a}, {0x0224, 0x20}, 246 {0x03f0, 0x0a}, {0x03f4, 0x07}, 247 {0x03f8, 0x07}, {0x03fc, 0x0c}, 248 {0x0404, 0x12}, {0x0408, 0x1a}, 249 {0x040c, 0x1a}, {0x0410, 0x3f}, 250 {0x0ce0, 0x68}, {0x0ce8, 0xd0}, 251 {0x0cf0, 0x87}, {0x0cf8, 0x70}, 252 {0x0d00, 0x70}, {0x0d08, 0xa9}, 253 {0x1ce0, 0x68}, {0x1ce8, 0xd0}, 254 {0x1cf0, 0x87}, {0x1cf8, 0x70}, 255 {0x1d00, 0x70}, {0x1d08, 0xa9}, 256 {0x0a3c, 0xd0}, {0x0a44, 0xd0}, 257 {0x0a48, 0x01}, {0x0a4c, 0x0d}, 258 {0x0a54, 0xe0}, {0x0a5c, 0xe0}, 259 {0x0a64, 0xa8}, {0x1a3c, 0xd0}, 260 {0x1a44, 0xd0}, {0x1a48, 0x01}, 261 {0x1a4c, 0x0d}, {0x1a54, 0xe0}, 262 {0x1a5c, 0xe0}, {0x1a64, 0xa8} 263 }; 264 265 static const struct reg_sequence rk3588_udphy_init_sequence[] = { 266 {0x0104, 0x44}, {0x0234, 0xE8}, 267 {0x0248, 0x44}, {0x028C, 0x18}, 268 {0x081C, 0xE5}, {0x0878, 0x00}, 269 {0x0994, 0x1C}, {0x0AF0, 0x00}, 270 {0x181C, 0xE5}, {0x1878, 0x00}, 271 {0x1994, 0x1C}, {0x1AF0, 0x00}, 272 {0x0428, 0x60}, {0x0D58, 0x33}, 273 {0x1D58, 0x33}, {0x0990, 0x74}, 274 {0x0D64, 0x17}, {0x08C8, 0x13}, 275 {0x1990, 0x74}, {0x1D64, 0x17}, 276 {0x18C8, 0x13}, {0x0D90, 0x40}, 277 {0x0DA8, 0x40}, {0x0DC0, 0x40}, 278 {0x0DD8, 0x40}, {0x1D90, 0x40}, 279 {0x1DA8, 0x40}, {0x1DC0, 0x40}, 280 {0x1DD8, 0x40}, {0x03C0, 0x30}, 281 {0x03C4, 0x06}, {0x0E10, 0x00}, 282 {0x1E10, 0x00}, {0x043C, 0x0F}, 283 {0x0D2C, 0xFF}, {0x1D2C, 0xFF}, 284 {0x0D34, 0x0F}, {0x1D34, 0x0F}, 285 {0x08FC, 0x2A}, {0x0914, 0x28}, 286 {0x0A30, 0x03}, {0x0E38, 0x05}, 287 {0x0ECC, 0x27}, {0x0ED0, 0x22}, 288 {0x0ED4, 0x26}, {0x18FC, 0x2A}, 289 {0x1914, 0x28}, {0x1A30, 0x03}, 290 {0x1E38, 0x05}, {0x1ECC, 0x27}, 291 {0x1ED0, 0x22}, {0x1ED4, 0x26}, 292 {0x0048, 0x0F}, {0x0060, 0x3C}, 293 {0x0064, 0xF7}, {0x006C, 0x20}, 294 {0x0070, 0x7D}, {0x0074, 0x68}, 295 {0x0AF4, 0x1A}, {0x1AF4, 0x1A}, 296 {0x0440, 0x3F}, {0x10D4, 0x08}, 297 {0x20D4, 0x08}, {0x00D4, 0x30}, 298 {0x0024, 0x6e}, 299 }; 300 301 static inline int grfreg_write(struct regmap *base, 302 const struct udphy_grf_reg *reg, bool en) 303 { 304 u32 val, mask, tmp; 305 306 tmp = en ? reg->enable : reg->disable; 307 mask = GENMASK(reg->bitend, reg->bitstart); 308 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 309 310 return regmap_write(base, reg->offset, val); 311 } 312 313 static int __regmap_multi_reg_write(struct regmap *map, 314 const struct reg_sequence *regs, int num_regs) 315 { 316 int i, ret = 0; 317 318 for (i = 0; i < num_regs; i++) { 319 ret = regmap_write(map, regs[i].reg, regs[i].def); 320 321 if (regs[i].delay_us) 322 udelay(regs[i].delay_us); 323 } 324 325 return ret; 326 } 327 328 static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev) 329 { 330 return 0; 331 } 332 333 static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev) 334 { 335 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 336 int idx; 337 int ret; 338 339 udphy->rsts = devm_kcalloc(dev, cfg->num_rsts, 340 sizeof(*udphy->rsts), GFP_KERNEL); 341 if (!udphy->rsts) 342 return -ENOMEM; 343 344 for (idx = 0; idx < cfg->num_rsts; idx++) { 345 const char *name = cfg->rst_list[idx]; 346 347 ret = reset_get_by_name(dev, name, &udphy->rsts[idx]); 348 if (ret) { 349 dev_err(dev, "failed to get %s reset\n", name); 350 goto err; 351 } 352 353 reset_assert(&udphy->rsts[idx]); 354 } 355 356 return 0; 357 358 err: 359 devm_kfree(dev, udphy->rsts); 360 return ret; 361 } 362 363 static int udphy_get_rst_idx(const char * const *list, int num, char *name) 364 { 365 int idx; 366 367 for (idx = 0; idx < num; idx++) { 368 if (!strcmp(list[idx], name)) 369 return idx; 370 } 371 372 return -EINVAL; 373 } 374 375 static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name) 376 { 377 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 378 int idx; 379 380 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); 381 if (idx < 0) 382 return idx; 383 384 return reset_assert(&udphy->rsts[idx]); 385 } 386 387 static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name) 388 { 389 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 390 int idx; 391 392 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); 393 if (idx < 0) 394 return idx; 395 396 return reset_deassert(&udphy->rsts[idx]); 397 } 398 399 static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable) 400 { 401 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 402 const struct udphy_grf_reg *preg; 403 404 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; 405 grfreg_write(udphy->usbgrf, preg, disable); 406 } 407 408 __maybe_unused 409 static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable) 410 { 411 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 412 413 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); 414 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); 415 } 416 417 /* 418 * In usb/dp combo phy driver, here are 2 ways to mapping lanes. 419 * 420 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) 421 * --------------------------------------------------------------------------- 422 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 423 * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 424 * C/E(Normal) dpln3 dpln2 dpln0 dpln1 425 * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 426 * D/F(Normal) usbrx usbtx dpln0 dpln1 427 * D/F(Flip ) dpln0 dpln1 usbrx usbtx 428 * A(Normal ) dpln3 dpln1 dpln2 dpln0 429 * A(Flip ) dpln2 dpln0 dpln3 dpln1 430 * B(Normal ) usbrx usbtx dpln1 dpln0 431 * B(Flip ) dpln1 dpln0 usbrx usbtx 432 * --------------------------------------------------------------------------- 433 * 434 * 2 Mapping the lanes in dtsi 435 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>; 436 * sample as follow: 437 * --------------------------------------------------------------------------- 438 * B11-B10 A2-A3 A11-A10 B2-B3 439 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 440 * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 441 * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 442 * --------------------------------------------------------------------------- 443 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>; 444 * sample as follow: 445 * --------------------------------------------------------------------------- 446 * B11-B10 A2-A3 A11-A10 B2-B3 447 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 448 * <0 1> dpln0 dpln1 usbrx usbtx 449 * <2 3> usbrx usbtx dpln0 dpln1 450 * --------------------------------------------------------------------------- 451 */ 452 static int udphy_dplane_select(struct rockchip_udphy *udphy) 453 { 454 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 455 456 if (cfg->dplane_select) 457 return cfg->dplane_select(udphy); 458 459 return 0; 460 } 461 462 static int udphy_dplane_get(struct rockchip_udphy *udphy) 463 { 464 int dp_lanes; 465 466 switch (udphy->mode) { 467 case UDPHY_MODE_DP: 468 dp_lanes = 4; 469 break; 470 case UDPHY_MODE_DP_USB: 471 dp_lanes = 2; 472 break; 473 case UDPHY_MODE_USB: 474 /* fallthrough; */ 475 default: 476 dp_lanes = 0; 477 break; 478 } 479 480 return dp_lanes; 481 } 482 483 static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes) 484 { 485 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 486 int ret = 0; 487 488 if (cfg->dplane_enable) 489 ret = cfg->dplane_enable(udphy, dp_lanes); 490 491 return ret; 492 } 493 494 495 __maybe_unused 496 static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy) 497 { 498 if (udphy->flip) { 499 udphy->dp_lane_sel[0] = 0; 500 udphy->dp_lane_sel[1] = 1; 501 udphy->dp_lane_sel[2] = 3; 502 udphy->dp_lane_sel[3] = 2; 503 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; 504 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; 505 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; 506 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; 507 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; 508 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; 509 } else { 510 udphy->dp_lane_sel[0] = 2; 511 udphy->dp_lane_sel[1] = 3; 512 udphy->dp_lane_sel[2] = 1; 513 udphy->dp_lane_sel[3] = 0; 514 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; 515 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; 516 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; 517 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; 518 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; 519 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; 520 } 521 522 udphy->mode = UDPHY_MODE_DP_USB; 523 524 return 0; 525 } 526 527 static int udphy_setup(struct rockchip_udphy *udphy) 528 { 529 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 530 int ret = 0; 531 532 if (cfg->combophy_init) { 533 ret = cfg->combophy_init(udphy); 534 if (ret) 535 dev_err(udphy->dev, "failed to init combophy\n"); 536 } 537 538 return ret; 539 } 540 541 static int udphy_disable(struct rockchip_udphy *udphy) 542 { 543 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 544 int i; 545 546 for (i = 0; i < cfg->num_rsts; i++) 547 reset_assert(&udphy->rsts[i]); 548 549 return 0; 550 } 551 552 static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, const struct device_node *np) 553 { 554 struct property *prop; 555 int ret, i, len, num_lanes; 556 557 prop = of_find_property(np, "rockchip,dp-lane-mux", &len); 558 if (!prop) { 559 dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n"); 560 udphy->mode = UDPHY_MODE_USB; 561 return 0; 562 } 563 564 num_lanes = len / sizeof(u32); 565 566 if (num_lanes != 2 && num_lanes != 4) { 567 dev_err(udphy->dev, "invalid number of lane mux\n"); 568 return -EINVAL; 569 } 570 571 ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes); 572 if (ret) { 573 dev_err(udphy->dev, "get dp lane mux failed\n"); 574 return -EINVAL; 575 } 576 577 for (i = 0; i < num_lanes; i++) { 578 int j; 579 580 if (udphy->dp_lane_sel[i] > 3) { 581 dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n"); 582 return -EINVAL; 583 } 584 585 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; 586 587 for (j = i + 1; j < num_lanes; j++) { 588 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) { 589 dev_err(udphy->dev, "set repeat lane mux value\n"); 590 return -EINVAL; 591 } 592 } 593 } 594 595 udphy->mode = UDPHY_MODE_DP; 596 if (num_lanes == 2) 597 udphy->mode |= UDPHY_MODE_USB; 598 599 return 0; 600 } 601 602 static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev) 603 { 604 const struct device_node *np = ofnode_to_np(dev->node); 605 enum usb_device_speed maximum_speed; 606 int ret; 607 608 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,u2phy-grf"); 609 if (IS_ERR(udphy->u2phygrf)) { 610 if (PTR_ERR(udphy->u2phygrf) == -ENODEV) { 611 dev_warn(dev, "missing u2phy-grf dt node\n"); 612 udphy->u2phygrf = NULL; 613 } else { 614 return PTR_ERR(udphy->u2phygrf); 615 } 616 } 617 618 udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usbdpphy-grf"); 619 if (IS_ERR(udphy->udphygrf)) { 620 if (PTR_ERR(udphy->udphygrf) == -ENODEV) { 621 dev_warn(dev, "missing usbdpphy-grf dt node\n"); 622 udphy->udphygrf = NULL; 623 } else { 624 return PTR_ERR(udphy->udphygrf); 625 } 626 } 627 628 udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usb-grf"); 629 if (IS_ERR(udphy->usbgrf)) { 630 if (PTR_ERR(udphy->usbgrf) == -ENODEV) { 631 dev_warn(dev, "missing usb-grf dt node\n"); 632 udphy->usbgrf = NULL; 633 } else { 634 return PTR_ERR(udphy->usbgrf); 635 } 636 } 637 638 udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf"); 639 if (IS_ERR(udphy->vogrf)) { 640 if (PTR_ERR(udphy->vogrf) == -ENODEV) { 641 dev_warn(dev, "missing vo-grf dt node\n"); 642 udphy->vogrf = NULL; 643 } else { 644 return PTR_ERR(udphy->vogrf); 645 } 646 } 647 648 ret = udphy_parse_lane_mux_data(udphy, np); 649 if (ret) 650 return ret; 651 652 if (dev_read_prop(dev, "maximum-speed", NULL)) { 653 maximum_speed = usb_get_maximum_speed(dev->node); 654 udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false; 655 } 656 657 ret = udphy_clk_init(udphy, dev); 658 if (ret) 659 return ret; 660 661 ret = udphy_reset_init(udphy, dev); 662 if (ret) 663 return ret; 664 665 return 0; 666 } 667 668 static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) 669 { 670 int ret; 671 672 if (!(udphy->mode & mode)) { 673 printf("%s: mode 0x%02x is not support\n", udphy->dev->name, 674 mode); 675 return -EINVAL; 676 } 677 678 if (udphy->status == UDPHY_MODE_NONE) { 679 udphy->mode_change = false; 680 ret = udphy_setup(udphy); 681 if (ret) 682 return ret; 683 684 if (udphy->mode & UDPHY_MODE_USB) 685 udphy_u3_port_disable(udphy, false); 686 } else if (udphy->mode_change) { 687 udphy->mode_change = false; 688 udphy->status = UDPHY_MODE_NONE; 689 if (udphy->mode == UDPHY_MODE_DP) 690 udphy_u3_port_disable(udphy, true); 691 692 ret = udphy_disable(udphy); 693 if (ret) 694 return ret; 695 ret = udphy_setup(udphy); 696 if (ret) 697 return ret; 698 } 699 700 udphy->status |= mode; 701 702 return 0; 703 } 704 705 static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) 706 { 707 int ret; 708 709 if (!(udphy->mode & mode)) { 710 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); 711 return 0; 712 } 713 714 if (!udphy->status) 715 return 0; 716 717 udphy->status &= ~mode; 718 719 if (udphy->status == UDPHY_MODE_NONE) { 720 ret = udphy_disable(udphy); 721 if (ret) 722 return ret; 723 } 724 725 return 0; 726 } 727 728 static int rockchip_dpphy_power_on(struct phy *phy) 729 { 730 struct udevice *parent = phy->dev->parent; 731 struct rockchip_udphy *udphy = dev_get_priv(parent); 732 int ret, dp_lanes; 733 734 dp_lanes = udphy_dplane_get(udphy); 735 phy->attrs.bus_width = dp_lanes; 736 phy->attrs.max_link_rate = udphy->max_link_rate; 737 738 ret = udphy_power_on(udphy, UDPHY_MODE_DP); 739 if (ret) 740 return ret; 741 742 ret = udphy_dplane_enable(udphy, dp_lanes); 743 if (ret) 744 return ret; 745 746 return udphy_dplane_select(udphy); 747 } 748 749 static int rockchip_dpphy_power_off(struct phy *phy) 750 { 751 struct udevice *parent = phy->dev->parent; 752 struct rockchip_udphy *udphy = dev_get_priv(parent); 753 int ret; 754 755 ret = udphy_dplane_enable(udphy, 0); 756 if (ret) 757 return ret; 758 759 return udphy_power_off(udphy, UDPHY_MODE_DP); 760 } 761 762 static int rockchip_dpphy_verify_config(struct rockchip_udphy *udphy, 763 struct phy_configure_opts_dp *dp) 764 { 765 int i; 766 767 /* If changing link rate was required, verify it's supported. */ 768 if (dp->set_rate) { 769 switch (dp->link_rate) { 770 case 1620: 771 case 2700: 772 case 5400: 773 case 8100: 774 /* valid bit rate */ 775 break; 776 default: 777 return -EINVAL; 778 } 779 } 780 781 /* Verify lane count. */ 782 switch (dp->lanes) { 783 case 1: 784 case 2: 785 case 4: 786 /* valid lane count. */ 787 break; 788 default: 789 return -EINVAL; 790 } 791 792 /* 793 * If changing voltages is required, check swing and pre-emphasis 794 * levels, per-lane. 795 */ 796 if (dp->set_voltages) { 797 /* Lane count verified previously. */ 798 for (i = 0; i < dp->lanes; i++) { 799 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 800 return -EINVAL; 801 802 /* 803 * Sum of voltage swing and pre-emphasis levels cannot 804 * exceed 3. 805 */ 806 if (dp->voltage[i] + dp->pre[i] > 3) 807 return -EINVAL; 808 } 809 } 810 811 return 0; 812 } 813 814 static int rockchip_dpphy_configure(struct phy *phy, 815 union phy_configure_opts *opts) 816 { 817 struct udevice *parent = phy->dev->parent; 818 struct rockchip_udphy *udphy = dev_get_priv(parent); 819 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 820 int ret; 821 822 ret = rockchip_dpphy_verify_config(udphy, &opts->dp); 823 if (ret) 824 return ret; 825 826 if (opts->dp.set_rate && cfg->dp_phy_set_rate) { 827 ret = cfg->dp_phy_set_rate(udphy, &opts->dp); 828 if (ret) { 829 printf("%s: rockchip_hdptx_phy_set_rate failed\n", 830 udphy->dev->name); 831 return ret; 832 } 833 } 834 835 if (opts->dp.set_voltages && cfg->dp_phy_set_voltages) { 836 ret = cfg->dp_phy_set_voltages(udphy, &opts->dp); 837 if (ret) { 838 printf("%s: rockchip_dp_phy_set_voltages failed\n", 839 udphy->dev->name); 840 return ret; 841 } 842 } 843 844 return 0; 845 } 846 847 static const struct phy_ops rockchip_dpphy_ops = { 848 .power_on = rockchip_dpphy_power_on, 849 .power_off = rockchip_dpphy_power_off, 850 .configure = rockchip_dpphy_configure, 851 }; 852 853 static int rockchip_u3phy_init(struct phy *phy) 854 { 855 struct udevice *parent = phy->dev->parent; 856 struct rockchip_udphy *udphy = dev_get_priv(parent); 857 858 /* DP only or high-speed, disable U3 port */ 859 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { 860 udphy_u3_port_disable(udphy, true); 861 return 0; 862 } 863 864 return udphy_power_on(udphy, UDPHY_MODE_USB); 865 } 866 867 static int rockchip_u3phy_exit(struct phy *phy) 868 { 869 struct udevice *parent = phy->dev->parent; 870 struct rockchip_udphy *udphy = dev_get_priv(parent); 871 872 /* DP only or high-speed */ 873 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) 874 return 0; 875 876 return udphy_power_off(udphy, UDPHY_MODE_USB); 877 } 878 879 static const struct phy_ops rockchip_u3phy_ops = { 880 .init = rockchip_u3phy_init, 881 .exit = rockchip_u3phy_exit, 882 }; 883 884 int rockchip_u3phy_uboot_init(void) 885 { 886 struct udevice *udev; 887 struct rockchip_udphy *udphy; 888 int ret; 889 890 ret = uclass_get_device_by_driver(UCLASS_PHY, 891 DM_GET_DRIVER(rockchip_udphy_u3_port), 892 &udev); 893 if (ret) { 894 pr_err("%s: get u3-port failed: %d\n", __func__, ret); 895 return ret; 896 } 897 898 /* DP only or high-speed, disable U3 port */ 899 udphy = dev_get_priv(udev->parent); 900 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { 901 udphy_u3_port_disable(udphy, true); 902 return 0; 903 } 904 905 return udphy_power_on(udphy, UDPHY_MODE_USB); 906 } 907 908 static int rockchip_udphy_probe(struct udevice *dev) 909 { 910 const struct device_node *np = ofnode_to_np(dev->node); 911 struct rockchip_udphy *udphy = dev_get_priv(dev); 912 const struct rockchip_udphy_cfg *phy_cfgs; 913 int id, ret; 914 915 udphy->dev = dev; 916 917 id = of_alias_get_id(np, "usbdp"); 918 if (id < 0) 919 id = 0; 920 udphy->id = id; 921 922 phy_cfgs = (const struct rockchip_udphy_cfg *) dev_get_driver_data(dev); 923 if (!phy_cfgs) { 924 dev_err(dev, "unable to get phy_cfgs\n"); 925 return -EINVAL; 926 } 927 udphy->cfgs = phy_cfgs; 928 929 ret = regmap_init_mem(dev, &udphy->pma_regmap); 930 if (ret) 931 return ret; 932 udphy->pma_regmap->base += UDPHY_PMA; 933 934 ret = udphy_parse_dt(udphy, dev); 935 if (ret) 936 return ret; 937 938 return 0; 939 } 940 941 static int rockchip_udphy_bind(struct udevice *parent) 942 { 943 struct udevice *child; 944 ofnode subnode; 945 const char *node_name; 946 int ret; 947 948 dev_for_each_subnode(subnode, parent) { 949 if (!ofnode_valid(subnode)) { 950 printf("%s: no subnode for %s", __func__, parent->name); 951 return -ENXIO; 952 } 953 954 node_name = ofnode_get_name(subnode); 955 debug("%s: subnode %s\n", __func__, node_name); 956 957 if (!strcasecmp(node_name, "u3-port")) { 958 ret = device_bind_driver_to_node(parent, 959 "rockchip_udphy_u3_port", 960 node_name, subnode, &child); 961 if (ret) { 962 printf("%s: '%s' cannot bind its driver\n", 963 __func__, node_name); 964 return ret; 965 } 966 } else if (!strcasecmp(node_name, "dp-port")) { 967 ret = device_bind_driver_to_node(parent, 968 "rockchip_udphy_dp_port", 969 node_name, subnode, &child); 970 if (ret) { 971 printf("%s: '%s' cannot bind its driver\n", 972 __func__, node_name); 973 return ret; 974 } 975 } 976 } 977 978 return 0; 979 } 980 981 static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy) 982 { 983 int ret; 984 985 /* configure phy reference clock */ 986 ret = __regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_24m_refclk_cfg, 987 ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg)); 988 if (ret) 989 return ret; 990 991 return 0; 992 } 993 994 static int rk3588_udphy_status_check(struct rockchip_udphy *udphy) 995 { 996 unsigned int val; 997 int ret; 998 999 /* LCPLL check */ 1000 if (udphy->mode & UDPHY_MODE_USB) { 1001 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, 1002 val, (val & CMN_ANA_LCPLL_AFC_DONE) && 1003 (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100); 1004 if (ret) { 1005 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); 1006 return ret; 1007 } 1008 } 1009 1010 if (udphy->mode & UDPHY_MODE_USB) { 1011 if (!udphy->flip) { 1012 ret = regmap_read_poll_timeout(udphy->pma_regmap, 1013 TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, 1014 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, 1015 200, 100); 1016 if (ret) 1017 dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); 1018 } else { 1019 ret = regmap_read_poll_timeout(udphy->pma_regmap, 1020 TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val, 1021 val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, 1022 200, 100); 1023 if (ret) 1024 dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); 1025 } 1026 } 1027 1028 return 0; 1029 } 1030 1031 static int rk3588_udphy_init(struct rockchip_udphy *udphy) 1032 { 1033 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 1034 int ret; 1035 1036 /* enable rx lfps for usb */ 1037 if (udphy->mode & UDPHY_MODE_USB) 1038 grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); 1039 1040 /* Step 1: power on pma and deassert apb rstn */ 1041 grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); 1042 1043 udphy_reset_deassert(udphy, "pma_apb"); 1044 udphy_reset_deassert(udphy, "pcs_apb"); 1045 1046 /* Step 2: set init sequence and phy refclk */ 1047 ret = __regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_init_sequence, 1048 ARRAY_SIZE(rk3588_udphy_init_sequence)); 1049 if (ret) { 1050 dev_err(udphy->dev, "init sequence set error %d\n", ret); 1051 goto assert_apb; 1052 } 1053 1054 ret = rk3588_udphy_refclk_set(udphy); 1055 if (ret) { 1056 dev_err(udphy->dev, "refclk set error %d\n", ret); 1057 goto assert_apb; 1058 } 1059 1060 /* Step 3: configure lane mux */ 1061 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, 1062 CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, 1063 FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | 1064 FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | 1065 FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | 1066 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | 1067 FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); 1068 1069 /* Step 4: deassert init rstn and wait for 200ns from datasheet */ 1070 if (udphy->mode & UDPHY_MODE_USB) 1071 udphy_reset_deassert(udphy, "init"); 1072 1073 if (udphy->mode & UDPHY_MODE_DP) { 1074 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 1075 CMN_DP_INIT_RSTN, 1076 FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); 1077 } 1078 1079 udelay(1); 1080 1081 /* Step 5: deassert cmn/lane rstn */ 1082 if (udphy->mode & UDPHY_MODE_USB) { 1083 udphy_reset_deassert(udphy, "cmn"); 1084 udphy_reset_deassert(udphy, "lane"); 1085 } 1086 1087 /* Step 6: wait for lock done of pll */ 1088 ret = rk3588_udphy_status_check(udphy); 1089 if (ret) 1090 goto assert_phy; 1091 1092 return 0; 1093 1094 assert_phy: 1095 udphy_reset_assert(udphy, "init"); 1096 udphy_reset_assert(udphy, "cmn"); 1097 udphy_reset_assert(udphy, "lane"); 1098 1099 assert_apb: 1100 udphy_reset_assert(udphy, "pma_apb"); 1101 udphy_reset_assert(udphy, "pcs_apb"); 1102 return ret; 1103 } 1104 1105 static int rk3588_udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes) 1106 { 1107 int i; 1108 u32 val = 0; 1109 1110 for (i = 0; i < dp_lanes; i++) 1111 val |= BIT(udphy->dp_lane_sel[i]); 1112 1113 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, 1114 FIELD_PREP(CMN_DP_LANE_EN_ALL, val)); 1115 1116 if (!dp_lanes) 1117 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 1118 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); 1119 1120 return 0; 1121 } 1122 1123 static int rk3588_udphy_dplane_select(struct rockchip_udphy *udphy) 1124 { 1125 u32 value = 0; 1126 1127 switch (udphy->mode) { 1128 case UDPHY_MODE_DP: 1129 value |= 2 << udphy->dp_lane_sel[2] * 2; 1130 value |= 3 << udphy->dp_lane_sel[3] * 2; 1131 case UDPHY_MODE_DP_USB: 1132 value |= 0 << udphy->dp_lane_sel[0] * 2; 1133 value |= 1 << udphy->dp_lane_sel[1] * 2; 1134 break; 1135 case UDPHY_MODE_USB: 1136 break; 1137 default: 1138 break; 1139 } 1140 1141 regmap_write(udphy->vogrf, udphy->id ? RK3588_GRF_VO0_CON2 : RK3588_GRF_VO0_CON0, 1142 ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) | 1143 FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | 1144 FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); 1145 1146 return 0; 1147 } 1148 1149 static int rk3588_dp_phy_set_rate(struct rockchip_udphy *udphy, 1150 struct phy_configure_opts_dp *dp) 1151 { 1152 u32 val; 1153 int ret; 1154 1155 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 1156 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); 1157 1158 switch (dp->link_rate) { 1159 case 1620: 1160 udphy->bw = DP_BW_RBR; 1161 break; 1162 case 2700: 1163 udphy->bw = DP_BW_HBR; 1164 break; 1165 case 5400: 1166 udphy->bw = DP_BW_HBR2; 1167 break; 1168 case 8100: 1169 udphy->bw = DP_BW_HBR3; 1170 break; 1171 default: 1172 return -EINVAL; 1173 } 1174 1175 regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, 1176 FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); 1177 regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, 1178 FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); 1179 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, 1180 FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); 1181 1182 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, 1183 FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) && 1184 FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val), 1185 0, 1000); 1186 if (ret) { 1187 printf("ROPLL is not lock\n"); 1188 return ret; 1189 } 1190 1191 return 0; 1192 } 1193 1194 static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw, 1195 u32 voltage, u32 pre, u32 lane) 1196 { 1197 u32 offset = 0x800 * lane; 1198 u32 val; 1199 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; 1200 const struct dp_tx_drv_ctrl (*dp_ctrl)[4]; 1201 1202 dp_ctrl = cfg->dp_tx_ctrl_cfg[bw]; 1203 val = dp_ctrl[voltage][pre].trsv_reg0204; 1204 regmap_write(udphy->pma_regmap, 0x0810 + offset, val); 1205 1206 val = dp_ctrl[voltage][pre].trsv_reg0205; 1207 regmap_write(udphy->pma_regmap, 0x0814 + offset, val); 1208 1209 val = dp_ctrl[voltage][pre].trsv_reg0206; 1210 regmap_write(udphy->pma_regmap, 0x0818 + offset, val); 1211 1212 val = dp_ctrl[voltage][pre].trsv_reg0207; 1213 regmap_write(udphy->pma_regmap, 0x081c + offset, val); 1214 } 1215 1216 static int rk3588_dp_phy_set_voltages(struct rockchip_udphy *udphy, 1217 struct phy_configure_opts_dp *dp) 1218 { 1219 u32 i, lane; 1220 1221 for (i = 0; i < dp->lanes; i++) { 1222 lane = udphy->dp_lane_sel[i]; 1223 switch (dp->link_rate) { 1224 case 1620: 1225 case 2700: 1226 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), 1227 LN_ANA_TX_SER_TXCLK_INV, 1228 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 1229 udphy->lane_mux_sel[lane])); 1230 break; 1231 case 5400: 1232 case 8100: 1233 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), 1234 LN_ANA_TX_SER_TXCLK_INV, 1235 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); 1236 break; 1237 } 1238 1239 rk3588_dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane); 1240 } 1241 1242 return 0; 1243 } 1244 1245 static int rockchip_dpphy_probe(struct udevice *dev) 1246 { 1247 struct rockchip_udphy *udphy = dev_get_priv(dev->parent); 1248 u32 max_link_rate; 1249 1250 max_link_rate = dev_read_u32_default(dev, "max-link-rate", 8100); 1251 switch (max_link_rate) { 1252 case 1620: 1253 case 2700: 1254 case 5400: 1255 case 8100: 1256 break; 1257 default: 1258 dev_warn(dev, "invalid max-link-rate %d, using 8100\n", max_link_rate); 1259 max_link_rate = 8100; 1260 break; 1261 } 1262 1263 udphy->max_link_rate = max_link_rate; 1264 1265 return 0; 1266 } 1267 1268 static const char * const rk3588_udphy_rst_l[] = { 1269 "init", "cmn", "lane", "pcs_apb", "pma_apb" 1270 }; 1271 1272 static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { 1273 .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l), 1274 .rst_list = rk3588_udphy_rst_l, 1275 .grfcfg = { 1276 /* u2phy-grf */ 1277 .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 }, 1278 .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 }, 1279 1280 /* usb-grf */ 1281 .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 }, 1282 .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 }, 1283 1284 /* usbdpphy-grf */ 1285 .low_pwrn = { 0x0004, 13, 13, 0, 1 }, 1286 .rx_lfps = { 0x0004, 14, 14, 0, 1 }, 1287 }, 1288 .dp_tx_ctrl_cfg = { 1289 rk3588_dp_tx_drv_ctrl_rbr_hbr, 1290 rk3588_dp_tx_drv_ctrl_rbr_hbr, 1291 rk3588_dp_tx_drv_ctrl_hbr2, 1292 rk3588_dp_tx_drv_ctrl_hbr3, 1293 }, 1294 .combophy_init = rk3588_udphy_init, 1295 .dp_phy_set_rate = rk3588_dp_phy_set_rate, 1296 .dp_phy_set_voltages = rk3588_dp_phy_set_voltages, 1297 .dplane_enable = rk3588_udphy_dplane_enable, 1298 .dplane_select = rk3588_udphy_dplane_select, 1299 }; 1300 1301 static const struct udevice_id rockchip_udphy_dt_match[] = { 1302 { 1303 .compatible = "rockchip,rk3588-usbdp-phy", 1304 .data = (ulong)&rk3588_udphy_cfgs 1305 }, 1306 { /* sentinel */ } 1307 }; 1308 1309 U_BOOT_DRIVER(rockchip_udphy_u3_port) = { 1310 .name = "rockchip_udphy_u3_port", 1311 .id = UCLASS_PHY, 1312 .ops = &rockchip_u3phy_ops, 1313 }; 1314 1315 U_BOOT_DRIVER(rockchip_udphy_dp_port) = { 1316 .name = "rockchip_udphy_dp_port", 1317 .id = UCLASS_PHY, 1318 .ops = &rockchip_dpphy_ops, 1319 .probe = rockchip_dpphy_probe, 1320 }; 1321 1322 U_BOOT_DRIVER(rockchip_udphy) = { 1323 .name = "rockchip_udphy", 1324 .id = UCLASS_PHY, 1325 .of_match = rockchip_udphy_dt_match, 1326 .probe = rockchip_udphy_probe, 1327 .bind = rockchip_udphy_bind, 1328 .priv_auto_alloc_size = sizeof(struct rockchip_udphy), 1329 }; 1330