1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip HDMI/DP Combo PHY with Samsung IP block 4 * 5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <generic-phy.h> 11 #include <reset.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <linux/bitfield.h> 16 #include <linux/iopoll.h> 17 #include <asm/arch/clock.h> 18 19 #define HDPTXPHY_GRF_CON0 0x0000 20 #define RO_REF_CLK_SEL GENMASK(11, 10) 21 #define LC_REF_CLK_SEL GENMASK(9, 8) 22 #define PLL_EN BIT(7) 23 #define BIAS_EN BIT(6) 24 #define BGR_EN BIT(5) 25 #define HDPTX_MODE_SEL BIT(0) 26 #define HDPTXPHY_GRF_STATUS0 0x0080 27 #define PLL_LOCK_DONE BIT(3) 28 #define PHY_CLK_RDY BIT(2) 29 #define PHY_RDY BIT(1) 30 #define SB_RDY BIT(0) 31 32 /* cmn_reg0008 */ 33 #define OVRD_LCPLL_EN BIT(7) 34 #define LCPLL_EN BIT(6) 35 36 /* cmn_reg003C */ 37 #define ANA_LCPLL_RESERVED7 BIT(7) 38 39 /* cmn_reg003D */ 40 #define OVRD_ROPLL_EN BIT(7) 41 #define ROPLL_EN BIT(6) 42 43 /* cmn_reg0046 */ 44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4) 45 #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0) 46 47 /* cmn_reg0047 */ 48 #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3) 49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0) 50 51 /* cmn_reg004E */ 52 #define ANA_ROPLL_PI_EN BIT(5) 53 54 /* cmn_reg0051 */ 55 #define ROPLL_PMS_MDIV GENMASK(7, 0) 56 57 /* cmn_reg0055 */ 58 #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0) 59 60 /* cmn_reg0059 */ 61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4) 62 #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0) 63 64 /* cmn_reg005A */ 65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4) 66 #define ROPLL_PMS_SDIV_HBR GENMASK(3, 0) 67 68 /* cmn_reg005B */ 69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4) 70 #define ROPLL_PMS_SDIV_HBR3 GENMASK(3, 0) 71 72 /* cmn_reg005D */ 73 #define OVRD_ROPLL_REF_CLK_SEL BIT(5) 74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3) 75 76 /* cmn_reg005E */ 77 #define ANA_ROPLL_SDM_EN BIT(6) 78 #define OVRD_ROPLL_SDM_RSTN BIT(5) 79 #define ROPLL_SDM_RSTN BIT(4) 80 #define ROPLL_SDC_FRACTIONAL_EN_RBR BIT(3) 81 #define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2) 82 #define ROPLL_SDC_FRACTIONAL_EN_HBR2 BIT(1) 83 #define ROPLL_SDC_FRACTIONAL_EN_HBR3 BIT(0) 84 85 /* cmn_reg005F */ 86 #define OVRD_ROPLL_SDC_RSTN BIT(5) 87 #define ROPLL_SDC_RSTN BIT(4) 88 89 /* cmn_reg0060 */ 90 #define ROPLL_SDM_DENOMINATOR GENMASK(7, 0) 91 92 /* cmn_reg0064 */ 93 #define ROPLL_SDM_NUMERATOR_SIGN_RBR BIT(3) 94 #define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2) 95 #define ROPLL_SDM_NUMERATOR_SIGN_HBR2 BIT(1) 96 #define ROPLL_SDM_NUMERATOR_SIGN_HBR3 BIT(0) 97 98 /* cmn_reg0065 */ 99 #define ROPLL_SDM_NUMERATOR GENMASK(7, 0) 100 101 /* cmn_reg0069 */ 102 #define ROPLL_SDC_N_RBR GENMASK(2, 0) 103 104 /* cmn_reg006A */ 105 #define ROPLL_SDC_N_HBR GENMASK(5, 3) 106 #define ROPLL_SDC_N_HBR2 GENMASK(2, 0) 107 108 /* cmn_reg006B */ 109 #define ROPLL_SDC_N_HBR3 GENMASK(3, 1) 110 111 /* cmn_reg006C */ 112 #define ROPLL_SDC_NUMERATOR GENMASK(5, 0) 113 114 /* cmn_reg0070 */ 115 #define ROPLL_SDC_DENOMINATOR GENMASK(5, 0) 116 117 /* cmn_reg0074 */ 118 #define OVRD_ROPLL_SDC_NDIV_RSTN BIT(3) 119 #define ROPLL_SDC_NDIV_RSTN BIT(2) 120 #define OVRD_ROPLL_SSC_EN BIT(1) 121 #define ROPLL_SSC_EN BIT(0) 122 123 /* cmn_reg0075 */ 124 #define ANA_ROPLL_SSC_FM_DEVIATION GENMASK(5, 0) 125 126 /* cmn_reg0076 */ 127 #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2) 128 129 /* cmn_reg0077 */ 130 #define ANA_ROPLL_SSC_CLK_DIV_SEL GENMASK(6, 3) 131 132 /* cmn_reg0081 */ 133 #define ANA_PLL_CD_TX_SER_RATE_SEL BIT(3) 134 #define ANA_PLL_CD_HSCLK_WEST_EN BIT(1) 135 #define ANA_PLL_CD_HSCLK_EAST_EN BIT(0) 136 137 /* cmn_reg0082 */ 138 #define ANA_PLL_CD_VREG_GAIN_CTRL GENMASK(3, 0) 139 140 /* cmn_reg0083 */ 141 #define ANA_PLL_CD_VREG_ICTRL GENMASK(6, 5) 142 143 /* cmn_reg0084 */ 144 #define PLL_LCRO_CLK_SEL BIT(5) 145 146 /* cmn_reg0085 */ 147 #define ANA_PLL_SYNC_LOSS_DET_MODE GENMASK(1, 0) 148 149 /* cmn_reg0087 */ 150 #define ANA_PLL_TX_HS_CLK_EN BIT(2) 151 152 /* cmn_reg0095 */ 153 #define DP_TX_LINK_BW GENMASK(1, 0) 154 155 /* cmn_reg0097 */ 156 #define DIG_CLK_SEL BIT(1) 157 158 /* cmn_reg0099 */ 159 #define SSC_EN GENMASK(7, 6) 160 #define CMN_ROPLL_ALONE_MODE BIT(2) 161 162 /* cmn_reg009A */ 163 #define HS_SPEED_SEL BIT(0) 164 165 /* cmn_reg009B */ 166 #define LS_SPEED_SEL BIT(4) 167 168 /* sb_reg0102 */ 169 #define OVRD_SB_RXTERM_EN BIT(5) 170 #define SB_RXRERM_EN BIT(4) 171 #define ANA_SB_RXTERM_OFFSP GENMASK(3, 0) 172 173 /* sb_reg0103 */ 174 #define ANA_SB_RXTERM_OFFSN GENMASK(6, 3) 175 #define OVRD_SB_RX_RESCAL_DONE BIT(1) 176 #define SB_RX_RESCAL_DONE BIT(0) 177 178 /* sb_reg0104 */ 179 #define OVRD_SB_EN BIT(5) 180 #define SB_EN BIT(4) 181 #define OVRD_SB_AUX_EN BIT(1) 182 #define SB_AUX_EN BIT(0) 183 184 /* sb_reg0105 */ 185 #define ANA_SB_TX_HLVL_PROG GENMASK(2, 0) 186 187 /* sb_reg0106 */ 188 #define ANA_SB_TX_LLVL_PROG GENMASK(6, 4) 189 190 /* sb_reg010D */ 191 #define ANA_SB_DMRX_LPBK_DATA BIT(4) 192 193 /* sb_reg010F */ 194 #define OVRD_SB_VREG_EN BIT(7) 195 #define SB_VREG_EN BIT(6) 196 #define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0) 197 198 /* sb_reg0110 */ 199 #define ANA_SB_VREG_OUT_SEL BIT(1) 200 #define ANA_SB_VREG_REF_SEL BIT(0) 201 202 /* sb_reg0113 */ 203 #define SB_RX_RCAL_OPT_CODE GENMASK(5, 4) 204 #define SB_RX_RTERM_CTRL GENMASK(3, 0) 205 206 /* sb_reg0114 */ 207 #define SB_TG_SB_EN_DELAY_TIME GENMASK(5, 3) 208 #define SB_TG_RXTERN_EN_DELAY_TIME GENMASK(2, 0) 209 210 /* sb_reg0115 */ 211 #define SB_READY_DELAY_TIME GENMASK(5, 3) 212 #define SB_TG_OSC_EN_DELAY_TIME GENMASK(2, 0) 213 214 /* sb_reg0116 */ 215 #define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4) 216 217 /* sb_reg0117 */ 218 #define SB_TG_PLL_CD_VREG_FAST_PULSE_TIME GENMASK(3, 0) 219 220 /* sb_reg0118 */ 221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT GENMASK(7, 0) 222 223 /* sb_reg011A */ 224 #define SB_TG_CNT_RUN_NO_7_0 GENMASK(7, 0) 225 226 /* sb_reg011B */ 227 #define SB_EARC_SIG_DET_BYPASS BIT(4) 228 #define SB_AFC_TOL GENMASK(3, 0) 229 230 /* sb_reg011C */ 231 #define SB_AFC_STB_NUM GENMASK(3, 0) 232 233 /* sb_reg011D */ 234 #define SB_TG_OSC_CNT_MIN GENMASK(7, 0) 235 236 /* sb_reg011E */ 237 #define SB_TG_OSC_CNT_MAX GENMASK(7, 0) 238 239 /* sb_reg011F */ 240 #define SB_PWM_AFC_CTRL GENMASK(7, 2) 241 #define SB_RCAL_RSTN BIT(1) 242 243 /* sb_reg0120 */ 244 #define SB_AUX_EN_IN BIT(7) 245 246 /* sb_reg0123 */ 247 #define OVRD_SB_READY BIT(5) 248 #define SB_READY BIT(4) 249 250 /* lntop_reg0200 */ 251 #define PROTOCOL_SEL BIT(2) 252 253 /* lntop_reg0206 */ 254 #define DATA_BUS_WIDTH GENMASK(2, 1) 255 #define BUS_WIDTH_SEL BIT(0) 256 257 /* lntop_reg0207 */ 258 #define LANE_EN GENMASK(3, 0) 259 260 /* lane_reg0301 */ 261 #define OVRD_LN_TX_DRV_EI_EN BIT(7) 262 #define LN_TX_DRV_EI_EN BIT(6) 263 264 /* lane_reg0303 */ 265 #define OVRD_LN_TX_DRV_LVL_CTRL BIT(5) 266 #define LN_TX_DRV_LVL_CTRL GENMASK(4, 0) 267 268 /* lane_reg0304 */ 269 #define OVRD_LN_TX_DRV_POST_LVL_CTRL BIT(4) 270 #define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0) 271 272 /* lane_reg0305 */ 273 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL BIT(6) 274 #define LN_TX_DRV_PRE_LVL_CTRL GENMASK(5, 2) 275 276 /* lane_reg0306 */ 277 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL GENMASK(7, 5) 278 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL GENMASK(4, 2) 279 #define LN_ANA_TX_DRV_ACCDRV_EN BIT(0) 280 281 /* lane_reg0307 */ 282 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL BIT(6) 283 #define LN_ANA_TX_DRV_ACCDRV_CTRL GENMASK(5, 3) 284 285 /* lane_reg030A */ 286 #define LN_ANA_TX_JEQ_EN BIT(4) 287 #define LN_TX_JEQ_EVEN_CTRL_RBR GENMASK(3, 0) 288 289 /* lane_reg030B */ 290 #define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4) 291 #define LN_TX_JEQ_EVEN_CTRL_HBR2 GENMASK(3, 0) 292 293 /* lane_reg030C */ 294 #define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4) 295 #define LN_TX_JEQ_ODD_CTRL_RBR GENMASK(3, 0) 296 297 /* lane_reg030D */ 298 #define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4) 299 #define LN_TX_JEQ_ODD_CTRL_HBR2 GENMASK(3, 0) 300 301 /* lane_reg030E */ 302 #define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4) 303 304 /* lane_reg0310 */ 305 #define LN_ANA_TX_SYNC_LOSS_DET_MODE GENMASK(1, 0) 306 307 /* lane_reg0311 */ 308 #define LN_TX_SER_40BIT_EN_RBR BIT(3) 309 #define LN_TX_SER_40BIT_EN_HBR BIT(2) 310 #define LN_TX_SER_40BIT_EN_HBR2 BIT(1) 311 #define LN_TX_SER_40BIT_EN_HBR3 BIT(0) 312 313 /* lane_reg0316 */ 314 #define LN_ANA_TX_SER_VREG_GAIN_CTRL GENMASK(3, 0) 315 316 /* lane_reg031B */ 317 #define LN_ANA_TX_RESERVED GENMASK(7, 0) 318 319 /* lane_reg031E */ 320 #define LN_POLARITY_INV BIT(2) 321 322 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset)) 323 324 struct rockchip_hdptx_phy { 325 struct udevice *dev; 326 void __iomem *base; 327 struct regmap *grf; 328 329 struct reset_ctl apb_reset; 330 struct reset_ctl cmn_reset; 331 struct reset_ctl init_reset; 332 struct reset_ctl lane_reset; 333 u32 lane_polarity_invert[4]; 334 }; 335 336 enum { 337 DP_BW_RBR, 338 DP_BW_HBR, 339 DP_BW_HBR2, 340 DP_BW_HBR3, 341 }; 342 343 struct tx_drv_ctrl { 344 u8 tx_drv_lvl_ctrl; 345 u8 tx_drv_post_lvl_ctrl; 346 u8 ana_tx_drv_idrv_idn_ctrl; 347 u8 ana_tx_drv_idrv_iup_ctrl; 348 u8 ana_tx_drv_accdrv_en; 349 u8 ana_tx_drv_accdrv_ctrl; 350 }; 351 352 static const struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = { 353 /* voltage swing 0, pre-emphasis 0->3 */ 354 { 355 { 0x1, 0x0, 0x4, 0x6, 0x0, 0x4 }, 356 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4 }, 357 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4 }, 358 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 359 }, 360 361 /* voltage swing 1, pre-emphasis 0->2 */ 362 { 363 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4 }, 364 { 0xa, 0x5, 0x4, 0x6, 0x0, 0x4 }, 365 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 366 }, 367 368 /* voltage swing 2, pre-emphasis 0->1 */ 369 { 370 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4 }, 371 { 0xd, 0x5, 0x7, 0x7, 0x1, 0x7 }, 372 }, 373 374 /* voltage swing 3, pre-emphasis 0 */ 375 { 376 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 }, 377 } 378 }; 379 380 static const struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = { 381 /* voltage swing 0, pre-emphasis 0->3 */ 382 { 383 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 }, 384 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 }, 385 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4 }, 386 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 387 }, 388 389 /* voltage swing 1, pre-emphasis 0->2 */ 390 { 391 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 }, 392 { 0xb, 0x6, 0x4, 0x6, 0x0, 0x4 }, 393 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 394 }, 395 396 /* voltage swing 2, pre-emphasis 0->1 */ 397 { 398 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 }, 399 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 }, 400 }, 401 402 /* voltage swing 3, pre-emphasis 0 */ 403 { 404 { 0xd, 0x1, 0x7, 0x7, 0x1, 0x4 }, 405 } 406 }; 407 408 static const struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = { 409 /* voltage swing 0, pre-emphasis 0->3 */ 410 { 411 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 }, 412 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 }, 413 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4 }, 414 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 415 }, 416 417 /* voltage swing 1, pre-emphasis 0->2 */ 418 { 419 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 }, 420 { 0xc, 0x7, 0x4, 0x6, 0x0, 0x4 }, 421 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 422 }, 423 424 /* voltage swing 2, pre-emphasis 0->1 */ 425 { 426 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 }, 427 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 }, 428 }, 429 430 /* voltage swing 3, pre-emphasis 0 */ 431 { 432 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 }, 433 } 434 }; 435 436 static inline void phy_write(struct rockchip_hdptx_phy *hdptx, uint reg, 437 uint val) 438 { 439 writel(val, hdptx->base + reg); 440 } 441 442 static inline uint phy_read(struct rockchip_hdptx_phy *hdptx, uint reg) 443 { 444 return readl(hdptx->base + reg); 445 } 446 447 static void phy_update_bits(struct rockchip_hdptx_phy *hdptx, uint reg, 448 uint mask, uint val) 449 { 450 uint orig, tmp; 451 452 orig = phy_read(hdptx, reg); 453 tmp = orig & ~mask; 454 tmp |= val & mask; 455 phy_write(hdptx, reg, tmp); 456 } 457 458 static void grf_write(struct rockchip_hdptx_phy *hdptx, uint reg, 459 uint mask, uint val) 460 { 461 regmap_write(hdptx->grf, reg, (mask << 16) | (val & mask)); 462 } 463 464 static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, 465 int submode) 466 { 467 return 0; 468 } 469 470 static int rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy *hdptx, 471 struct phy_configure_opts_dp *dp) 472 { 473 int i; 474 475 if (dp->set_rate) { 476 switch (dp->link_rate) { 477 case 1620: 478 case 2700: 479 case 5400: 480 break; 481 default: 482 return -EINVAL; 483 } 484 } 485 486 switch (dp->lanes) { 487 case 1: 488 case 2: 489 case 4: 490 break; 491 default: 492 return -EINVAL; 493 } 494 495 if (dp->set_voltages) { 496 for (i = 0; i < dp->lanes; i++) { 497 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 498 return -EINVAL; 499 500 if (dp->voltage[i] + dp->pre[i] > 3) 501 return -EINVAL; 502 } 503 } 504 505 return 0; 506 } 507 508 static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, 509 struct phy_configure_opts_dp *dp, 510 u8 lane) 511 { 512 const struct tx_drv_ctrl *ctrl; 513 514 phy_update_bits(hdptx, LANE_REG(lane, 0x0c28), LN_ANA_TX_JEQ_EN, 515 FIELD_PREP(LN_ANA_TX_JEQ_EN, 0x1)); 516 517 switch (dp->link_rate) { 518 case 1620: 519 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; 520 phy_update_bits(hdptx, LANE_REG(lane, 0x0c28), 521 LN_TX_JEQ_EVEN_CTRL_RBR, 522 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR, 0x7)); 523 phy_update_bits(hdptx, LANE_REG(lane, 0x0c30), 524 LN_TX_JEQ_ODD_CTRL_RBR, 525 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR, 0x7)); 526 phy_update_bits(hdptx, LANE_REG(lane, 0x0c44), 527 LN_TX_SER_40BIT_EN_RBR, 528 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1)); 529 break; 530 case 2700: 531 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; 532 phy_update_bits(hdptx, LANE_REG(lane, 0x0c2c), 533 LN_TX_JEQ_EVEN_CTRL_HBR, 534 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR, 0x7)); 535 phy_update_bits(hdptx, LANE_REG(lane, 0x0c34), 536 LN_TX_JEQ_ODD_CTRL_HBR, 537 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, 0x7)); 538 phy_update_bits(hdptx, LANE_REG(lane, 0x0c44), 539 LN_TX_SER_40BIT_EN_HBR, 540 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1)); 541 break; 542 case 5400: 543 default: 544 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]]; 545 phy_update_bits(hdptx, LANE_REG(lane, 0x0c2c), 546 LN_TX_JEQ_EVEN_CTRL_HBR2, 547 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, 0x7)); 548 phy_update_bits(hdptx, LANE_REG(lane, 0x0c34), 549 LN_TX_JEQ_ODD_CTRL_HBR2, 550 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, 0x7)); 551 phy_update_bits(hdptx, LANE_REG(lane, 0x0c44), 552 LN_TX_SER_40BIT_EN_HBR2, 553 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1)); 554 break; 555 } 556 557 phy_update_bits(hdptx, LANE_REG(lane, 0x0c0c), 558 OVRD_LN_TX_DRV_LVL_CTRL | LN_TX_DRV_LVL_CTRL, 559 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL, 0x1) | 560 FIELD_PREP(LN_TX_DRV_LVL_CTRL, ctrl->tx_drv_lvl_ctrl)); 561 562 phy_update_bits(hdptx, LANE_REG(lane, 0x0c10), 563 OVRD_LN_TX_DRV_POST_LVL_CTRL | LN_TX_DRV_POST_LVL_CTRL, 564 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL, 0x1) | 565 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL, 566 ctrl->tx_drv_post_lvl_ctrl)); 567 568 phy_update_bits(hdptx, LANE_REG(lane, 0x0c18), 569 LN_ANA_TX_DRV_IDRV_IDN_CTRL | 570 LN_ANA_TX_DRV_IDRV_IUP_CTRL | LN_ANA_TX_DRV_ACCDRV_EN, 571 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL, 572 ctrl->ana_tx_drv_idrv_idn_ctrl) | 573 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL, 574 ctrl->ana_tx_drv_idrv_iup_ctrl) | 575 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN, 576 ctrl->ana_tx_drv_accdrv_en)); 577 578 phy_update_bits(hdptx, LANE_REG(lane, 0x0c1c), 579 LN_ANA_TX_DRV_ACCDRV_POL_SEL | LN_ANA_TX_DRV_ACCDRV_CTRL, 580 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL, 0x1) | 581 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL, 582 ctrl->ana_tx_drv_accdrv_ctrl)); 583 phy_update_bits(hdptx, LANE_REG(lane, 0x0c6c), LN_ANA_TX_RESERVED, 584 FIELD_PREP(LN_ANA_TX_RESERVED, 0x1)); 585 phy_update_bits(hdptx, LANE_REG(lane, 0x0c58), 586 LN_ANA_TX_SER_VREG_GAIN_CTRL, 587 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL, 0x2)); 588 phy_update_bits(hdptx, LANE_REG(lane, 0x0c40), 589 LN_ANA_TX_SYNC_LOSS_DET_MODE, 590 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE, 0x3)); 591 } 592 593 static int rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy *hdptx, 594 struct phy_configure_opts_dp *dp) 595 { 596 u8 lane; 597 598 for (lane = 0; lane < dp->lanes; lane++) 599 rockchip_hdptx_phy_set_voltage(hdptx, dp, lane); 600 601 return 0; 602 } 603 604 static int rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy *hdptx, 605 struct phy_configure_opts_dp *dp) 606 { 607 u32 bw, status; 608 int ret; 609 610 reset_assert(&hdptx->lane_reset); 611 udelay(10); 612 reset_assert(&hdptx->cmn_reset); 613 udelay(10); 614 grf_write(hdptx, HDPTXPHY_GRF_CON0, PLL_EN, FIELD_PREP(PLL_EN, 0x0)); 615 udelay(10); 616 phy_update_bits(hdptx, 0x081c, LANE_EN, FIELD_PREP(LANE_EN, 0x0)); 617 618 switch (dp->link_rate) { 619 case 1620: 620 bw = DP_BW_RBR; 621 break; 622 case 2700: 623 bw = DP_BW_HBR; 624 break; 625 case 5400: 626 bw = DP_BW_HBR2; 627 break; 628 default: 629 return -EINVAL; 630 } 631 632 phy_update_bits(hdptx, 0x0254, DP_TX_LINK_BW, 633 FIELD_PREP(DP_TX_LINK_BW, bw)); 634 635 if (dp->ssc) { 636 phy_update_bits(hdptx, 0x01d0, OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, 637 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) | 638 FIELD_PREP(ROPLL_SSC_EN, 0x1)); 639 phy_update_bits(hdptx, 0x01d4, ANA_ROPLL_SSC_FM_DEVIATION, 640 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0xc)); 641 phy_update_bits(hdptx, 0x01d8, ANA_ROPLL_SSC_FM_FREQ, 642 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0x1f)); 643 phy_update_bits(hdptx, 0x0264, SSC_EN, FIELD_PREP(SSC_EN, 0x2)); 644 } else { 645 phy_update_bits(hdptx, 0x01d0, OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, 646 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) | 647 FIELD_PREP(ROPLL_SSC_EN, 0x0)); 648 phy_update_bits(hdptx, 0x01d4, ANA_ROPLL_SSC_FM_DEVIATION, 649 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0x20)); 650 phy_update_bits(hdptx, 0x01d8, ANA_ROPLL_SSC_FM_FREQ, 651 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0xc)); 652 phy_update_bits(hdptx, 0x0264, SSC_EN, FIELD_PREP(SSC_EN, 0x0)); 653 } 654 655 grf_write(hdptx, HDPTXPHY_GRF_CON0, PLL_EN, FIELD_PREP(PLL_EN, 0x1)); 656 udelay(10); 657 reset_deassert(&hdptx->cmn_reset); 658 udelay(10); 659 660 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 661 status, FIELD_GET(PLL_LOCK_DONE, status), 662 50, 1000); 663 if (ret) { 664 dev_err(hdptx->dev, "timeout waiting for pll_lock_done\n"); 665 return ret; 666 } 667 668 phy_update_bits(hdptx, 0x081c, LANE_EN, 669 FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0))); 670 671 reset_deassert(&hdptx->lane_reset); 672 udelay(10); 673 674 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 675 status, FIELD_GET(PHY_RDY, status), 676 50, 1000); 677 if (ret) { 678 dev_err(hdptx->dev, "timeout waiting for phy_rdy\n"); 679 return ret; 680 } 681 682 return 0; 683 } 684 685 static int rockchip_hdptx_phy_configure(struct phy *phy, 686 union phy_configure_opts *opts) 687 { 688 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 689 enum phy_mode mode = generic_phy_get_mode(phy); 690 int ret; 691 692 if (mode != PHY_MODE_DP) 693 return -EINVAL; 694 695 ret = rockchip_hdptx_phy_verify_config(hdptx, &opts->dp); 696 if (ret) { 697 dev_err(hdptx->dev, "invalid params for phy configure\n"); 698 return ret; 699 } 700 701 if (opts->dp.set_rate) { 702 ret = rockchip_hdptx_phy_set_rate(hdptx, &opts->dp); 703 if (ret) { 704 dev_err(hdptx->dev, "failed to set rate: %d\n", ret); 705 return ret; 706 } 707 } 708 709 if (opts->dp.set_voltages) { 710 ret = rockchip_hdptx_phy_set_voltages(hdptx, &opts->dp); 711 if (ret) { 712 dev_err(hdptx->dev, "failed to set voltages: %d\n", 713 ret); 714 return ret; 715 } 716 } 717 718 return 0; 719 } 720 721 static void rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy *hdptx) 722 { 723 phy_update_bits(hdptx, 0x0020, OVRD_LCPLL_EN | LCPLL_EN, 724 FIELD_PREP(OVRD_LCPLL_EN, 0x1) | 725 FIELD_PREP(LCPLL_EN, 0x0)); 726 phy_update_bits(hdptx, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN, 727 FIELD_PREP(OVRD_ROPLL_EN, 0x1) | 728 FIELD_PREP(ROPLL_EN, 0x1)); 729 phy_update_bits(hdptx, 0x0138, ANA_ROPLL_PI_EN, 730 FIELD_PREP(ANA_ROPLL_PI_EN, 0x1)); 731 732 phy_write(hdptx, 0x0144, FIELD_PREP(ROPLL_PMS_MDIV, 0x87)); 733 phy_write(hdptx, 0x0148, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); 734 phy_write(hdptx, 0x014c, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); 735 736 phy_write(hdptx, 0x0154, FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x87)); 737 phy_write(hdptx, 0x0158, FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71)); 738 phy_write(hdptx, 0x015c, FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71)); 739 740 phy_write(hdptx, 0x0164, FIELD_PREP(ANA_ROPLL_PMS_PDIV, 0x1) | 741 FIELD_PREP(ANA_ROPLL_PMS_REFDIV, 0x1)); 742 743 phy_write(hdptx, 0x0168, FIELD_PREP(ROPLL_PMS_SDIV_RBR, 0x3) | 744 FIELD_PREP(ROPLL_PMS_SDIV_HBR, 0x1)); 745 phy_update_bits(hdptx, 0x016c, ROPLL_PMS_SDIV_HBR2, 746 FIELD_PREP(ROPLL_PMS_SDIV_HBR2, 0x0)); 747 748 phy_update_bits(hdptx, 0x0178, ANA_ROPLL_SDM_EN, 749 FIELD_PREP(ANA_ROPLL_SDM_EN, 0x1)); 750 phy_update_bits(hdptx, 0x0178, OVRD_ROPLL_SDM_RSTN | ROPLL_SDM_RSTN, 751 FIELD_PREP(OVRD_ROPLL_SDM_RSTN, 0x1) | 752 FIELD_PREP(ROPLL_SDM_RSTN, 0x1)); 753 phy_update_bits(hdptx, 0x0178, ROPLL_SDC_FRACTIONAL_EN_RBR, 754 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_RBR, 0x1)); 755 phy_update_bits(hdptx, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR, 756 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR, 0x1)); 757 phy_update_bits(hdptx, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR2, 758 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR2, 0x1)); 759 phy_update_bits(hdptx, 0x017c, OVRD_ROPLL_SDC_RSTN | ROPLL_SDC_RSTN, 760 FIELD_PREP(OVRD_ROPLL_SDC_RSTN, 0x1) | 761 FIELD_PREP(ROPLL_SDC_RSTN, 0x1)); 762 763 phy_write(hdptx, 0x0180, FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x21)); 764 phy_write(hdptx, 0x0184, FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27)); 765 phy_write(hdptx, 0x0188, FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27)); 766 767 phy_update_bits(hdptx, 0x0190, ROPLL_SDM_NUMERATOR_SIGN_RBR | 768 ROPLL_SDM_NUMERATOR_SIGN_HBR | 769 ROPLL_SDM_NUMERATOR_SIGN_HBR2, 770 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_RBR, 0x0) | 771 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR, 0x1) | 772 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR2, 0x1)); 773 774 phy_write(hdptx, 0x0194, FIELD_PREP(ROPLL_SDM_NUMERATOR, 0x0)); 775 phy_write(hdptx, 0x0198, FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd)); 776 phy_write(hdptx, 0x019c, FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd)); 777 778 phy_update_bits(hdptx, 0x01a4, ROPLL_SDC_N_RBR, 779 FIELD_PREP(ROPLL_SDC_N_RBR, 0x2)); 780 phy_update_bits(hdptx, 0x01a8, ROPLL_SDC_N_HBR | ROPLL_SDC_N_HBR2, 781 FIELD_PREP(ROPLL_SDC_N_HBR, 0x1) | 782 FIELD_PREP(ROPLL_SDC_N_HBR2, 0x1)); 783 784 phy_write(hdptx, 0x01b0, FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x3)); 785 phy_write(hdptx, 0x01b4, FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7)); 786 phy_write(hdptx, 0x01b8, FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7)); 787 788 phy_write(hdptx, 0x01c0, FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x8)); 789 phy_write(hdptx, 0x01c4, FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18)); 790 phy_write(hdptx, 0x01c8, FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18)); 791 792 phy_update_bits(hdptx, 0x01d0, OVRD_ROPLL_SDC_NDIV_RSTN | 793 ROPLL_SDC_NDIV_RSTN, 794 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN, 0x1) | 795 FIELD_PREP(ROPLL_SDC_NDIV_RSTN, 0x1)); 796 phy_update_bits(hdptx, 0x01dc, ANA_ROPLL_SSC_CLK_DIV_SEL, 797 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL, 0x1)); 798 799 phy_update_bits(hdptx, 0x0118, ROPLL_ANA_CPP_CTRL_COARSE | 800 ROPLL_ANA_CPP_CTRL_FINE, 801 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE, 0xe) | 802 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE, 0xe)); 803 phy_update_bits(hdptx, 0x011c, ROPLL_ANA_LPF_C_SEL_COARSE | 804 ROPLL_ANA_LPF_C_SEL_FINE, 805 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE, 0x4) | 806 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE, 0x4)); 807 808 phy_update_bits(hdptx, 0x0204, ANA_PLL_CD_TX_SER_RATE_SEL, 809 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL, 0x0)); 810 811 phy_update_bits(hdptx, 0x025c, DIG_CLK_SEL, 812 FIELD_PREP(DIG_CLK_SEL, 0x1)); 813 phy_update_bits(hdptx, 0x021c, ANA_PLL_TX_HS_CLK_EN, 814 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN, 0x1)); 815 phy_update_bits(hdptx, 0x0204, ANA_PLL_CD_HSCLK_EAST_EN | 816 ANA_PLL_CD_HSCLK_WEST_EN, 817 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN, 0x1) | 818 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN, 0x0)); 819 phy_update_bits(hdptx, 0x0264, CMN_ROPLL_ALONE_MODE, 820 FIELD_PREP(CMN_ROPLL_ALONE_MODE, 0x1)); 821 phy_update_bits(hdptx, 0x0208, ANA_PLL_CD_VREG_GAIN_CTRL, 822 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL, 0x4)); 823 phy_update_bits(hdptx, 0x00f0, ANA_LCPLL_RESERVED7, 824 FIELD_PREP(ANA_LCPLL_RESERVED7, 0x1)); 825 phy_update_bits(hdptx, 0x020c, ANA_PLL_CD_VREG_ICTRL, 826 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL, 0x1)); 827 phy_update_bits(hdptx, 0x0214, ANA_PLL_SYNC_LOSS_DET_MODE, 828 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE, 0x3)); 829 phy_update_bits(hdptx, 0x0210, PLL_LCRO_CLK_SEL, 830 FIELD_PREP(PLL_LCRO_CLK_SEL, 0x1)); 831 phy_update_bits(hdptx, 0x0268, HS_SPEED_SEL, 832 FIELD_PREP(HS_SPEED_SEL, 0x1)); 833 phy_update_bits(hdptx, 0x026c, LS_SPEED_SEL, 834 FIELD_PREP(LS_SPEED_SEL, 0x1)); 835 } 836 837 static int rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy *hdptx) 838 { 839 u32 status; 840 int ret; 841 842 phy_update_bits(hdptx, 0x0414, ANA_SB_TX_HLVL_PROG, 843 FIELD_PREP(ANA_SB_TX_HLVL_PROG, 0x7)); 844 phy_update_bits(hdptx, 0x0418, ANA_SB_TX_LLVL_PROG, 845 FIELD_PREP(ANA_SB_TX_LLVL_PROG, 0x7)); 846 847 phy_update_bits(hdptx, 0x044c, SB_RX_RCAL_OPT_CODE | SB_RX_RTERM_CTRL, 848 FIELD_PREP(SB_RX_RCAL_OPT_CODE, 0x1) | 849 FIELD_PREP(SB_RX_RTERM_CTRL, 0x3)); 850 phy_update_bits(hdptx, 0x0450, SB_TG_SB_EN_DELAY_TIME | 851 SB_TG_RXTERN_EN_DELAY_TIME, 852 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME, 0x2) | 853 FIELD_PREP(SB_TG_RXTERN_EN_DELAY_TIME, 0x2)); 854 phy_update_bits(hdptx, 0x0454, SB_READY_DELAY_TIME | 855 SB_TG_OSC_EN_DELAY_TIME, 856 FIELD_PREP(SB_READY_DELAY_TIME, 0x2) | 857 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME, 0x2)); 858 phy_update_bits(hdptx, 0x0458, SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 859 FIELD_PREP(SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 0x2)); 860 phy_update_bits(hdptx, 0x045c, SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 861 FIELD_PREP(SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 0x4)); 862 phy_update_bits(hdptx, 0x0460, SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 863 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 0xa)); 864 phy_update_bits(hdptx, 0x0468, SB_TG_CNT_RUN_NO_7_0, 865 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0, 0x3)); 866 phy_update_bits(hdptx, 0x046c, SB_EARC_SIG_DET_BYPASS | SB_AFC_TOL, 867 FIELD_PREP(SB_EARC_SIG_DET_BYPASS, 0x1) | 868 FIELD_PREP(SB_AFC_TOL, 0x3)); 869 phy_update_bits(hdptx, 0x0470, SB_AFC_STB_NUM, 870 FIELD_PREP(SB_AFC_STB_NUM, 0x4)); 871 phy_update_bits(hdptx, 0x0474, SB_TG_OSC_CNT_MIN, 872 FIELD_PREP(SB_TG_OSC_CNT_MIN, 0x67)); 873 phy_update_bits(hdptx, 0x0478, SB_TG_OSC_CNT_MAX, 874 FIELD_PREP(SB_TG_OSC_CNT_MAX, 0x6a)); 875 phy_update_bits(hdptx, 0x047c, SB_PWM_AFC_CTRL, 876 FIELD_PREP(SB_PWM_AFC_CTRL, 0x5)); 877 phy_update_bits(hdptx, 0x0434, ANA_SB_DMRX_LPBK_DATA, 878 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA, 0x1)); 879 phy_update_bits(hdptx, 0x0440, ANA_SB_VREG_OUT_SEL | 880 ANA_SB_VREG_REF_SEL, 881 FIELD_PREP(ANA_SB_VREG_OUT_SEL, 0x1) | 882 FIELD_PREP(ANA_SB_VREG_REF_SEL, 0x1)); 883 phy_update_bits(hdptx, 0x043c, ANA_SB_VREG_GAIN_CTRL, 884 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL, 0x0)); 885 phy_update_bits(hdptx, 0x0408, ANA_SB_RXTERM_OFFSP, 886 FIELD_PREP(ANA_SB_RXTERM_OFFSP, 0x3)); 887 phy_update_bits(hdptx, 0x040c, ANA_SB_RXTERM_OFFSN, 888 FIELD_PREP(ANA_SB_RXTERM_OFFSN, 0x3)); 889 phy_update_bits(hdptx, 0x047c, SB_RCAL_RSTN, 890 FIELD_PREP(SB_RCAL_RSTN, 0x1)); 891 phy_update_bits(hdptx, 0x0410, SB_AUX_EN, 892 FIELD_PREP(SB_AUX_EN, 0x1)); 893 phy_update_bits(hdptx, 0x0480, SB_AUX_EN_IN, 894 FIELD_PREP(SB_AUX_EN_IN, 0x1)); 895 phy_update_bits(hdptx, 0x040c, OVRD_SB_RX_RESCAL_DONE, 896 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE, 0x1)); 897 phy_update_bits(hdptx, 0x0410, OVRD_SB_EN, 898 FIELD_PREP(OVRD_SB_EN, 0x1)); 899 phy_update_bits(hdptx, 0x0408, OVRD_SB_RXTERM_EN, 900 FIELD_PREP(OVRD_SB_RXTERM_EN, 0x1)); 901 phy_update_bits(hdptx, 0x043c, OVRD_SB_VREG_EN, 902 FIELD_PREP(OVRD_SB_VREG_EN, 0x1)); 903 phy_update_bits(hdptx, 0x0410, OVRD_SB_AUX_EN, 904 FIELD_PREP(OVRD_SB_AUX_EN, 0x1)); 905 906 grf_write(hdptx, HDPTXPHY_GRF_CON0, BGR_EN, FIELD_PREP(BGR_EN, 0x1)); 907 grf_write(hdptx, HDPTXPHY_GRF_CON0, BIAS_EN, FIELD_PREP(BIAS_EN, 0x1)); 908 udelay(10); 909 reset_deassert(&hdptx->init_reset); 910 udelay(1000); 911 reset_deassert(&hdptx->cmn_reset); 912 udelay(20); 913 914 phy_update_bits(hdptx, 0x040c, SB_RX_RESCAL_DONE, 915 FIELD_PREP(SB_RX_RESCAL_DONE, 0x1)); 916 udelay(100); 917 phy_update_bits(hdptx, 0x0410, SB_EN, FIELD_PREP(SB_EN, 0x1)); 918 udelay(100); 919 phy_update_bits(hdptx, 0x0408, SB_RXRERM_EN, 920 FIELD_PREP(SB_RXRERM_EN, 0x1)); 921 udelay(10); 922 phy_update_bits(hdptx, 0x043c, SB_VREG_EN, FIELD_PREP(SB_VREG_EN, 0x1)); 923 udelay(10); 924 phy_update_bits(hdptx, 0x0410, SB_AUX_EN, FIELD_PREP(SB_AUX_EN, 0x1)); 925 udelay(100); 926 927 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 928 status, FIELD_GET(SB_RDY, status), 929 50, 1000); 930 if (ret) { 931 dev_err(hdptx->dev, "timeout waiting for sb_rdy\n"); 932 return ret; 933 } 934 935 return 0; 936 } 937 938 static void rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy *hdptx) 939 { 940 u32 lane; 941 942 reset_assert(&hdptx->lane_reset); 943 reset_assert(&hdptx->cmn_reset); 944 reset_assert(&hdptx->init_reset); 945 946 reset_assert(&hdptx->apb_reset); 947 udelay(10); 948 reset_deassert(&hdptx->apb_reset); 949 950 for (lane = 0; lane < 4; lane++) 951 phy_update_bits(hdptx, LANE_REG(lane, 0x0c04), 952 OVRD_LN_TX_DRV_EI_EN | LN_TX_DRV_EI_EN, 953 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN, 1) | 954 FIELD_PREP(LN_TX_DRV_EI_EN, 0)); 955 956 grf_write(hdptx, HDPTXPHY_GRF_CON0, PLL_EN, FIELD_PREP(PLL_EN, 0)); 957 grf_write(hdptx, HDPTXPHY_GRF_CON0, BIAS_EN, FIELD_PREP(BIAS_EN, 0)); 958 grf_write(hdptx, HDPTXPHY_GRF_CON0, BGR_EN, FIELD_PREP(BGR_EN, 0)); 959 } 960 961 static int rockchip_hdptx_phy_power_on(struct phy *phy) 962 { 963 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 964 enum phy_mode mode = generic_phy_get_mode(phy); 965 u32 lane; 966 967 rockchip_hdptx_phy_reset(hdptx); 968 969 for (lane = 0; lane < 4; lane++) { 970 u32 invert = hdptx->lane_polarity_invert[lane]; 971 972 phy_update_bits(hdptx, LANE_REG(lane, 0x0c78), LN_POLARITY_INV, 973 FIELD_PREP(LN_POLARITY_INV, invert)); 974 } 975 976 if (mode == PHY_MODE_DP) { 977 grf_write(hdptx, HDPTXPHY_GRF_CON0, HDPTX_MODE_SEL, 978 FIELD_PREP(HDPTX_MODE_SEL, 0x1)); 979 980 phy_update_bits(hdptx, 0x0800, PROTOCOL_SEL, 981 FIELD_PREP(PROTOCOL_SEL, 0x0)); 982 phy_update_bits(hdptx, 0x0818, DATA_BUS_WIDTH, 983 FIELD_PREP(DATA_BUS_WIDTH, 0x1)); 984 phy_update_bits(hdptx, 0x0818, BUS_WIDTH_SEL, 985 FIELD_PREP(BUS_WIDTH_SEL, 0x0)); 986 987 rockchip_hdptx_phy_dp_pll_init(hdptx); 988 rockchip_hdptx_phy_dp_aux_init(hdptx); 989 } else { 990 grf_write(hdptx, HDPTXPHY_GRF_CON0, HDPTX_MODE_SEL, 991 FIELD_PREP(HDPTX_MODE_SEL, 0x0)); 992 993 phy_update_bits(hdptx, 0x0800, PROTOCOL_SEL, 994 FIELD_PREP(PROTOCOL_SEL, 0x1)); 995 } 996 997 return 0; 998 } 999 1000 static int rockchip_hdptx_phy_power_off(struct phy *phy) 1001 { 1002 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 1003 1004 rockchip_hdptx_phy_reset(hdptx); 1005 1006 return 0; 1007 } 1008 1009 static const struct phy_ops rockchip_hdptx_phy_ops = { 1010 .set_mode = rockchip_hdptx_phy_set_mode, 1011 .configure = rockchip_hdptx_phy_configure, 1012 .power_on = rockchip_hdptx_phy_power_on, 1013 .power_off = rockchip_hdptx_phy_power_off, 1014 }; 1015 1016 static int rockchip_hdptx_phy_probe(struct udevice *dev) 1017 { 1018 struct rockchip_hdptx_phy *hdptx = dev_get_priv(dev); 1019 struct udevice *syscon; 1020 int ret; 1021 1022 hdptx->base = dev_read_addr_ptr(dev); 1023 if (!hdptx->base) 1024 return -ENOENT; 1025 1026 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1027 &syscon); 1028 if (ret) 1029 return ret; 1030 1031 hdptx->grf = syscon_get_regmap(syscon); 1032 if (IS_ERR(hdptx->grf)) { 1033 ret = PTR_ERR(hdptx->grf); 1034 dev_err(dev, "unable to find regmap: %d\n", ret); 1035 return ret; 1036 } 1037 1038 hdptx->dev = dev; 1039 1040 ret = reset_get_by_name(dev, "apb", &hdptx->apb_reset); 1041 if (ret < 0) { 1042 dev_err(dev, "failed to get apb reset: %d\n", ret); 1043 return ret; 1044 } 1045 1046 ret = reset_get_by_name(dev, "init", &hdptx->init_reset); 1047 if (ret < 0) { 1048 dev_err(dev, "failed to get init reset: %d\n", ret); 1049 return ret; 1050 } 1051 1052 ret = reset_get_by_name(dev, "cmn", &hdptx->cmn_reset); 1053 if (ret < 0) { 1054 dev_err(dev, "failed to get cmn reset: %d\n", ret); 1055 return ret; 1056 } 1057 1058 ret = reset_get_by_name(dev, "lane", &hdptx->lane_reset); 1059 if (ret < 0) { 1060 dev_err(dev, "failed to get lane reset: %d\n", ret); 1061 return ret; 1062 } 1063 1064 dev_read_u32_array(dev, "lane-polarity-invert", 1065 hdptx->lane_polarity_invert, 4); 1066 1067 return 0; 1068 } 1069 1070 static const struct udevice_id rockchip_hdptx_phy_ids[] = { 1071 { .compatible = "rockchip,rk3588-hdptx-phy", }, 1072 {} 1073 }; 1074 1075 U_BOOT_DRIVER(rockchip_hdptx_phy) = { 1076 .name = "rockchip_hdptx_phy", 1077 .id = UCLASS_PHY, 1078 .ops = &rockchip_hdptx_phy_ops, 1079 .of_match = rockchip_hdptx_phy_ids, 1080 .probe = rockchip_hdptx_phy_probe, 1081 .priv_auto_alloc_size = sizeof(struct rockchip_hdptx_phy), 1082 }; 1083