1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip HDMI/DP Combo PHY with Samsung IP block 4 * 5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <generic-phy.h> 11 #include <reset.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <linux/bitfield.h> 16 #include <linux/iopoll.h> 17 #include <asm/arch/clock.h> 18 19 #define HDPTXPHY_GRF_CON0 0x0000 20 #define RO_REF_CLK_SEL GENMASK(11, 10) 21 #define LC_REF_CLK_SEL GENMASK(9, 8) 22 #define PLL_EN BIT(7) 23 #define BIAS_EN BIT(6) 24 #define BGR_EN BIT(5) 25 #define HDPTX_MODE_SEL BIT(0) 26 #define HDPTXPHY_GRF_STATUS0 0x0080 27 #define PLL_LOCK_DONE BIT(3) 28 #define PHY_CLK_RDY BIT(2) 29 #define PHY_RDY BIT(1) 30 #define SB_RDY BIT(0) 31 32 /* cmn_reg0008 */ 33 #define OVRD_LCPLL_EN BIT(7) 34 #define LCPLL_EN BIT(6) 35 36 /* cmn_reg003C */ 37 #define ANA_LCPLL_RESERVED7 BIT(7) 38 39 /* cmn_reg003D */ 40 #define OVRD_ROPLL_EN BIT(7) 41 #define ROPLL_EN BIT(6) 42 43 /* cmn_reg0046 */ 44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4) 45 #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0) 46 47 /* cmn_reg0047 */ 48 #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3) 49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0) 50 51 /* cmn_reg004E */ 52 #define ANA_ROPLL_PI_EN BIT(5) 53 54 /* cmn_reg0051 */ 55 #define ROPLL_PMS_MDIV GENMASK(7, 0) 56 57 /* cmn_reg0055 */ 58 #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0) 59 60 /* cmn_reg0059 */ 61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4) 62 #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0) 63 64 /* cmn_reg005A */ 65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4) 66 #define ROPLL_PMS_SDIV_HBR GENMASK(3, 0) 67 68 /* cmn_reg005B */ 69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4) 70 #define ROPLL_PMS_SDIV_HBR3 GENMASK(3, 0) 71 72 /* cmn_reg005D */ 73 #define OVRD_ROPLL_REF_CLK_SEL BIT(5) 74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3) 75 76 /* cmn_reg005E */ 77 #define ANA_ROPLL_SDM_EN BIT(6) 78 #define OVRD_ROPLL_SDM_RSTN BIT(5) 79 #define ROPLL_SDM_RSTN BIT(4) 80 #define ROPLL_SDC_FRACTIONAL_EN_RBR BIT(3) 81 #define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2) 82 #define ROPLL_SDC_FRACTIONAL_EN_HBR2 BIT(1) 83 #define ROPLL_SDC_FRACTIONAL_EN_HBR3 BIT(0) 84 85 /* cmn_reg005F */ 86 #define OVRD_ROPLL_SDC_RSTN BIT(5) 87 #define ROPLL_SDC_RSTN BIT(4) 88 89 /* cmn_reg0060 */ 90 #define ROPLL_SDM_DENOMINATOR GENMASK(7, 0) 91 92 /* cmn_reg0064 */ 93 #define ROPLL_SDM_NUMERATOR_SIGN_RBR BIT(3) 94 #define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2) 95 #define ROPLL_SDM_NUMERATOR_SIGN_HBR2 BIT(1) 96 #define ROPLL_SDM_NUMERATOR_SIGN_HBR3 BIT(0) 97 98 /* cmn_reg0065 */ 99 #define ROPLL_SDM_NUMERATOR GENMASK(7, 0) 100 101 /* cmn_reg0069 */ 102 #define ROPLL_SDC_N_RBR GENMASK(2, 0) 103 104 /* cmn_reg006A */ 105 #define ROPLL_SDC_N_HBR GENMASK(5, 3) 106 #define ROPLL_SDC_N_HBR2 GENMASK(2, 0) 107 108 /* cmn_reg006B */ 109 #define ROPLL_SDC_N_HBR3 GENMASK(3, 1) 110 111 /* cmn_reg006C */ 112 #define ROPLL_SDC_NUMERATOR GENMASK(5, 0) 113 114 /* cmn_reg0070 */ 115 #define ROPLL_SDC_DENOMINATOR GENMASK(5, 0) 116 117 /* cmn_reg0074 */ 118 #define OVRD_ROPLL_SDC_NDIV_RSTN BIT(3) 119 #define ROPLL_SDC_NDIV_RSTN BIT(2) 120 #define OVRD_ROPLL_SSC_EN BIT(1) 121 #define ROPLL_SSC_EN BIT(0) 122 123 /* cmn_reg0075 */ 124 #define ANA_ROPLL_SSC_FM_DEVIATION GENMASK(5, 0) 125 126 /* cmn_reg0076 */ 127 #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2) 128 129 /* cmn_reg0077 */ 130 #define ANA_ROPLL_SSC_CLK_DIV_SEL GENMASK(6, 3) 131 132 /* cmn_reg0081 */ 133 #define ANA_PLL_CD_TX_SER_RATE_SEL BIT(3) 134 #define ANA_PLL_CD_HSCLK_WEST_EN BIT(1) 135 #define ANA_PLL_CD_HSCLK_EAST_EN BIT(0) 136 137 /* cmn_reg0082 */ 138 #define ANA_PLL_CD_VREG_GAIN_CTRL GENMASK(3, 0) 139 140 /* cmn_reg0083 */ 141 #define ANA_PLL_CD_VREG_ICTRL GENMASK(6, 5) 142 143 /* cmn_reg0084 */ 144 #define PLL_LCRO_CLK_SEL BIT(5) 145 146 /* cmn_reg0085 */ 147 #define ANA_PLL_SYNC_LOSS_DET_MODE GENMASK(1, 0) 148 149 /* cmn_reg0087 */ 150 #define ANA_PLL_TX_HS_CLK_EN BIT(2) 151 152 /* cmn_reg0095 */ 153 #define DP_TX_LINK_BW GENMASK(1, 0) 154 155 /* cmn_reg0097 */ 156 #define DIG_CLK_SEL BIT(1) 157 158 /* cmn_reg0099 */ 159 #define SSC_EN GENMASK(7, 6) 160 #define CMN_ROPLL_ALONE_MODE BIT(2) 161 162 /* cmn_reg009A */ 163 #define HS_SPEED_SEL BIT(0) 164 165 /* cmn_reg009B */ 166 #define LS_SPEED_SEL BIT(4) 167 168 /* sb_reg0102 */ 169 #define OVRD_SB_RXTERM_EN BIT(5) 170 #define SB_RXRERM_EN BIT(4) 171 #define ANA_SB_RXTERM_OFFSP GENMASK(3, 0) 172 173 /* sb_reg0103 */ 174 #define ANA_SB_RXTERM_OFFSN GENMASK(6, 3) 175 #define OVRD_SB_RX_RESCAL_DONE BIT(1) 176 #define SB_RX_RESCAL_DONE BIT(0) 177 178 /* sb_reg0104 */ 179 #define OVRD_SB_EN BIT(5) 180 #define SB_EN BIT(4) 181 #define OVRD_SB_AUX_EN BIT(1) 182 #define SB_AUX_EN BIT(0) 183 184 /* sb_reg0105 */ 185 #define ANA_SB_TX_HLVL_PROG GENMASK(2, 0) 186 187 /* sb_reg0106 */ 188 #define ANA_SB_TX_LLVL_PROG GENMASK(6, 4) 189 190 /* sb_reg010D */ 191 #define ANA_SB_DMRX_LPBK_DATA BIT(4) 192 193 /* sb_reg010F */ 194 #define OVRD_SB_VREG_EN BIT(7) 195 #define SB_VREG_EN BIT(6) 196 #define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0) 197 198 /* sb_reg0110 */ 199 #define ANA_SB_VREG_OUT_SEL BIT(1) 200 #define ANA_SB_VREG_REF_SEL BIT(0) 201 202 /* sb_reg0113 */ 203 #define SB_RX_RCAL_OPT_CODE GENMASK(5, 4) 204 #define SB_RX_RTERM_CTRL GENMASK(3, 0) 205 206 /* sb_reg0114 */ 207 #define SB_TG_SB_EN_DELAY_TIME GENMASK(5, 3) 208 #define SB_TG_RXTERN_EN_DELAY_TIME GENMASK(2, 0) 209 210 /* sb_reg0115 */ 211 #define SB_READY_DELAY_TIME GENMASK(5, 3) 212 #define SB_TG_OSC_EN_DELAY_TIME GENMASK(2, 0) 213 214 /* sb_reg0116 */ 215 #define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4) 216 217 /* sb_reg0117 */ 218 #define SB_TG_PLL_CD_VREG_FAST_PULSE_TIME GENMASK(3, 0) 219 220 /* sb_reg0118 */ 221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT GENMASK(7, 0) 222 223 /* sb_reg011A */ 224 #define SB_TG_CNT_RUN_NO_7_0 GENMASK(7, 0) 225 226 /* sb_reg011B */ 227 #define SB_EARC_SIG_DET_BYPASS BIT(4) 228 #define SB_AFC_TOL GENMASK(3, 0) 229 230 /* sb_reg011C */ 231 #define SB_AFC_STB_NUM GENMASK(3, 0) 232 233 /* sb_reg011D */ 234 #define SB_TG_OSC_CNT_MIN GENMASK(7, 0) 235 236 /* sb_reg011E */ 237 #define SB_TG_OSC_CNT_MAX GENMASK(7, 0) 238 239 /* sb_reg011F */ 240 #define SB_PWM_AFC_CTRL GENMASK(7, 2) 241 #define SB_RCAL_RSTN BIT(1) 242 243 /* sb_reg0120 */ 244 #define SB_AUX_EN_IN BIT(7) 245 246 /* sb_reg0123 */ 247 #define OVRD_SB_READY BIT(5) 248 #define SB_READY BIT(4) 249 250 /* lntop_reg0200 */ 251 #define PROTOCOL_SEL BIT(2) 252 253 /* lntop_reg0206 */ 254 #define DATA_BUS_WIDTH GENMASK(2, 1) 255 #define BUS_WIDTH_SEL BIT(0) 256 257 /* lntop_reg0207 */ 258 #define LANE_EN GENMASK(3, 0) 259 260 /* lane_reg0301 */ 261 #define OVRD_LN_TX_DRV_EI_EN BIT(7) 262 #define LN_TX_DRV_EI_EN BIT(6) 263 264 /* lane_reg0303 */ 265 #define OVRD_LN_TX_DRV_LVL_CTRL BIT(5) 266 #define LN_TX_DRV_LVL_CTRL GENMASK(4, 0) 267 268 /* lane_reg0304 */ 269 #define OVRD_LN_TX_DRV_POST_LVL_CTRL BIT(4) 270 #define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0) 271 272 /* lane_reg0305 */ 273 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL BIT(6) 274 #define LN_TX_DRV_PRE_LVL_CTRL GENMASK(5, 2) 275 276 /* lane_reg0306 */ 277 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL GENMASK(7, 5) 278 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL GENMASK(4, 2) 279 #define LN_ANA_TX_DRV_ACCDRV_EN BIT(0) 280 281 /* lane_reg0307 */ 282 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL BIT(6) 283 #define LN_ANA_TX_DRV_ACCDRV_CTRL GENMASK(5, 3) 284 285 /* lane_reg030A */ 286 #define LN_ANA_TX_JEQ_EN BIT(4) 287 #define LN_TX_JEQ_EVEN_CTRL_RBR GENMASK(3, 0) 288 289 /* lane_reg030B */ 290 #define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4) 291 #define LN_TX_JEQ_EVEN_CTRL_HBR2 GENMASK(3, 0) 292 293 /* lane_reg030C */ 294 #define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4) 295 #define LN_TX_JEQ_ODD_CTRL_RBR GENMASK(3, 0) 296 297 /* lane_reg030D */ 298 #define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4) 299 #define LN_TX_JEQ_ODD_CTRL_HBR2 GENMASK(3, 0) 300 301 /* lane_reg030E */ 302 #define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4) 303 304 /* lane_reg0310 */ 305 #define LN_ANA_TX_SYNC_LOSS_DET_MODE GENMASK(1, 0) 306 307 /* lane_reg0311 */ 308 #define LN_TX_SER_40BIT_EN_RBR BIT(3) 309 #define LN_TX_SER_40BIT_EN_HBR BIT(2) 310 #define LN_TX_SER_40BIT_EN_HBR2 BIT(1) 311 #define LN_TX_SER_40BIT_EN_HBR3 BIT(0) 312 313 /* lane_reg0316 */ 314 #define LN_ANA_TX_SER_VREG_GAIN_CTRL GENMASK(3, 0) 315 316 /* lane_reg031B */ 317 #define LN_ANA_TX_RESERVED GENMASK(7, 0) 318 319 /* lane_reg031E */ 320 #define LN_POLARITY_INV BIT(2) 321 322 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset)) 323 324 struct rockchip_hdptx_phy { 325 struct udevice *dev; 326 void __iomem *base; 327 struct regmap *grf; 328 329 struct reset_ctl apb_reset; 330 struct reset_ctl cmn_reset; 331 struct reset_ctl init_reset; 332 struct reset_ctl lane_reset; 333 u32 lane_polarity_invert[4]; 334 }; 335 336 enum { 337 DP_BW_RBR, 338 DP_BW_HBR, 339 DP_BW_HBR2, 340 DP_BW_HBR3, 341 }; 342 343 struct tx_drv_ctrl { 344 u8 tx_drv_lvl_ctrl; 345 u8 tx_drv_post_lvl_ctrl; 346 u8 ana_tx_drv_idrv_idn_ctrl; 347 u8 ana_tx_drv_idrv_iup_ctrl; 348 u8 ana_tx_drv_accdrv_en; 349 u8 ana_tx_drv_accdrv_ctrl; 350 } __packed; 351 352 static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = { 353 /* voltage swing 0, pre-emphasis 0->3 */ 354 { 355 { 0x1, 0x0, 0x4, 0x6, 0x0, 0x4 }, 356 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4 }, 357 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4 }, 358 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 359 }, 360 361 /* voltage swing 1, pre-emphasis 0->2 */ 362 { 363 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4 }, 364 { 0xa, 0x5, 0x4, 0x6, 0x0, 0x4 }, 365 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 366 }, 367 368 /* voltage swing 2, pre-emphasis 0->1 */ 369 { 370 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4 }, 371 { 0xd, 0x5, 0x7, 0x7, 0x1, 0x7 }, 372 }, 373 374 /* voltage swing 3, pre-emphasis 0 */ 375 { 376 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 }, 377 } 378 }; 379 380 static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = { 381 /* voltage swing 0, pre-emphasis 0->3 */ 382 { 383 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 }, 384 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 }, 385 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4 }, 386 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 387 }, 388 389 /* voltage swing 1, pre-emphasis 0->2 */ 390 { 391 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 }, 392 { 0xb, 0x6, 0x4, 0x6, 0x0, 0x4 }, 393 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 394 }, 395 396 /* voltage swing 2, pre-emphasis 0->1 */ 397 { 398 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 }, 399 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 }, 400 }, 401 402 /* voltage swing 3, pre-emphasis 0 */ 403 { 404 { 0xd, 0x1, 0x7, 0x7, 0x1, 0x4 }, 405 } 406 }; 407 408 static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = { 409 /* voltage swing 0, pre-emphasis 0->3 */ 410 { 411 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 }, 412 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 }, 413 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4 }, 414 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 415 }, 416 417 /* voltage swing 1, pre-emphasis 0->2 */ 418 { 419 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 }, 420 { 0xc, 0x7, 0x4, 0x6, 0x0, 0x4 }, 421 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 422 }, 423 424 /* voltage swing 2, pre-emphasis 0->1 */ 425 { 426 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 }, 427 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 }, 428 }, 429 430 /* voltage swing 3, pre-emphasis 0 */ 431 { 432 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 }, 433 } 434 }; 435 436 static int rockchip_hdptx_phy_parse_training_table(struct udevice *dev) 437 { 438 int size = sizeof(struct tx_drv_ctrl) * 10; 439 const uint8_t *prop; 440 u8 *buf, *training_table; 441 int i, j; 442 443 prop = dev_read_u8_array_ptr(dev, "training-table", size); 444 if (!prop) 445 return 0; 446 447 buf = kzalloc(size, GFP_KERNEL); 448 if (!buf) 449 return -ENOMEM; 450 451 memcpy(buf, prop, size); 452 453 training_table = buf; 454 455 for (i = 0; i < 4; i++) { 456 for (j = 0; j < 4; j++) { 457 struct tx_drv_ctrl *ctrl; 458 459 if (i + j > 3) 460 continue; 461 462 ctrl = (struct tx_drv_ctrl *)training_table; 463 tx_drv_ctrl_rbr[i][j] = *ctrl; 464 tx_drv_ctrl_hbr[i][j] = *ctrl; 465 tx_drv_ctrl_hbr2[i][j] = *ctrl; 466 training_table += sizeof(*ctrl); 467 } 468 } 469 470 kfree(buf); 471 472 return 0; 473 } 474 475 static inline void phy_write(struct rockchip_hdptx_phy *hdptx, uint reg, 476 uint val) 477 { 478 writel(val, hdptx->base + reg); 479 } 480 481 static inline uint phy_read(struct rockchip_hdptx_phy *hdptx, uint reg) 482 { 483 return readl(hdptx->base + reg); 484 } 485 486 static void phy_update_bits(struct rockchip_hdptx_phy *hdptx, uint reg, 487 uint mask, uint val) 488 { 489 uint orig, tmp; 490 491 orig = phy_read(hdptx, reg); 492 tmp = orig & ~mask; 493 tmp |= val & mask; 494 phy_write(hdptx, reg, tmp); 495 } 496 497 static void grf_write(struct rockchip_hdptx_phy *hdptx, uint reg, 498 uint mask, uint val) 499 { 500 regmap_write(hdptx->grf, reg, (mask << 16) | (val & mask)); 501 } 502 503 static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, 504 int submode) 505 { 506 return 0; 507 } 508 509 static int rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy *hdptx, 510 struct phy_configure_opts_dp *dp) 511 { 512 int i; 513 514 if (dp->set_rate) { 515 switch (dp->link_rate) { 516 case 1620: 517 case 2700: 518 case 5400: 519 break; 520 default: 521 return -EINVAL; 522 } 523 } 524 525 switch (dp->lanes) { 526 case 1: 527 case 2: 528 case 4: 529 break; 530 default: 531 return -EINVAL; 532 } 533 534 if (dp->set_voltages) { 535 for (i = 0; i < dp->lanes; i++) { 536 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 537 return -EINVAL; 538 539 if (dp->voltage[i] + dp->pre[i] > 3) 540 return -EINVAL; 541 } 542 } 543 544 return 0; 545 } 546 547 static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, 548 struct phy_configure_opts_dp *dp, 549 u8 lane) 550 { 551 const struct tx_drv_ctrl *ctrl; 552 553 switch (dp->link_rate) { 554 case 1620: 555 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; 556 phy_update_bits(hdptx, LANE_REG(lane, 0x0c44), 557 LN_TX_SER_40BIT_EN_RBR, 558 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1)); 559 break; 560 case 2700: 561 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; 562 phy_update_bits(hdptx, LANE_REG(lane, 0x0c44), 563 LN_TX_SER_40BIT_EN_HBR, 564 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1)); 565 break; 566 case 5400: 567 default: 568 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]]; 569 phy_update_bits(hdptx, LANE_REG(lane, 0x0c44), 570 LN_TX_SER_40BIT_EN_HBR2, 571 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1)); 572 break; 573 } 574 575 phy_update_bits(hdptx, LANE_REG(lane, 0x0c0c), 576 OVRD_LN_TX_DRV_LVL_CTRL | LN_TX_DRV_LVL_CTRL, 577 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL, 0x1) | 578 FIELD_PREP(LN_TX_DRV_LVL_CTRL, ctrl->tx_drv_lvl_ctrl)); 579 580 phy_update_bits(hdptx, LANE_REG(lane, 0x0c10), 581 OVRD_LN_TX_DRV_POST_LVL_CTRL | LN_TX_DRV_POST_LVL_CTRL, 582 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL, 0x1) | 583 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL, 584 ctrl->tx_drv_post_lvl_ctrl)); 585 586 phy_update_bits(hdptx, LANE_REG(lane, 0x0c18), 587 LN_ANA_TX_DRV_IDRV_IDN_CTRL | 588 LN_ANA_TX_DRV_IDRV_IUP_CTRL | LN_ANA_TX_DRV_ACCDRV_EN, 589 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL, 590 ctrl->ana_tx_drv_idrv_idn_ctrl) | 591 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL, 592 ctrl->ana_tx_drv_idrv_iup_ctrl) | 593 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN, 594 ctrl->ana_tx_drv_accdrv_en)); 595 596 phy_update_bits(hdptx, LANE_REG(lane, 0x0c1c), 597 LN_ANA_TX_DRV_ACCDRV_POL_SEL | LN_ANA_TX_DRV_ACCDRV_CTRL, 598 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL, 0x1) | 599 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL, 600 ctrl->ana_tx_drv_accdrv_ctrl)); 601 phy_update_bits(hdptx, LANE_REG(lane, 0x0c6c), LN_ANA_TX_RESERVED, 602 FIELD_PREP(LN_ANA_TX_RESERVED, 0x1)); 603 phy_update_bits(hdptx, LANE_REG(lane, 0x0c58), 604 LN_ANA_TX_SER_VREG_GAIN_CTRL, 605 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL, 0x2)); 606 phy_update_bits(hdptx, LANE_REG(lane, 0x0c40), 607 LN_ANA_TX_SYNC_LOSS_DET_MODE, 608 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE, 0x3)); 609 } 610 611 static int rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy *hdptx, 612 struct phy_configure_opts_dp *dp) 613 { 614 u8 lane; 615 616 for (lane = 0; lane < dp->lanes; lane++) 617 rockchip_hdptx_phy_set_voltage(hdptx, dp, lane); 618 619 return 0; 620 } 621 622 static int rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy *hdptx, 623 struct phy_configure_opts_dp *dp) 624 { 625 u32 bw, status; 626 int ret; 627 628 reset_assert(&hdptx->lane_reset); 629 udelay(10); 630 reset_assert(&hdptx->cmn_reset); 631 udelay(10); 632 grf_write(hdptx, HDPTXPHY_GRF_CON0, PLL_EN, FIELD_PREP(PLL_EN, 0x0)); 633 udelay(10); 634 phy_update_bits(hdptx, 0x081c, LANE_EN, FIELD_PREP(LANE_EN, 0x0)); 635 636 switch (dp->link_rate) { 637 case 1620: 638 bw = DP_BW_RBR; 639 break; 640 case 2700: 641 bw = DP_BW_HBR; 642 break; 643 case 5400: 644 bw = DP_BW_HBR2; 645 break; 646 default: 647 return -EINVAL; 648 } 649 650 phy_update_bits(hdptx, 0x0254, DP_TX_LINK_BW, 651 FIELD_PREP(DP_TX_LINK_BW, bw)); 652 653 if (dp->ssc) { 654 phy_update_bits(hdptx, 0x01d0, OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, 655 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) | 656 FIELD_PREP(ROPLL_SSC_EN, 0x1)); 657 phy_update_bits(hdptx, 0x01d4, ANA_ROPLL_SSC_FM_DEVIATION, 658 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0xc)); 659 phy_update_bits(hdptx, 0x01d8, ANA_ROPLL_SSC_FM_FREQ, 660 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0x1f)); 661 phy_update_bits(hdptx, 0x0264, SSC_EN, FIELD_PREP(SSC_EN, 0x2)); 662 } else { 663 phy_update_bits(hdptx, 0x01d0, OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, 664 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) | 665 FIELD_PREP(ROPLL_SSC_EN, 0x0)); 666 phy_update_bits(hdptx, 0x01d4, ANA_ROPLL_SSC_FM_DEVIATION, 667 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0x20)); 668 phy_update_bits(hdptx, 0x01d8, ANA_ROPLL_SSC_FM_FREQ, 669 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0xc)); 670 phy_update_bits(hdptx, 0x0264, SSC_EN, FIELD_PREP(SSC_EN, 0x0)); 671 } 672 673 grf_write(hdptx, HDPTXPHY_GRF_CON0, PLL_EN, FIELD_PREP(PLL_EN, 0x1)); 674 udelay(10); 675 reset_deassert(&hdptx->cmn_reset); 676 udelay(10); 677 678 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 679 status, FIELD_GET(PLL_LOCK_DONE, status), 680 50, 1000); 681 if (ret) { 682 dev_err(hdptx->dev, "timeout waiting for pll_lock_done\n"); 683 return ret; 684 } 685 686 phy_update_bits(hdptx, 0x081c, LANE_EN, 687 FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0))); 688 689 reset_deassert(&hdptx->lane_reset); 690 udelay(10); 691 692 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 693 status, FIELD_GET(PHY_RDY, status), 694 50, 1000); 695 if (ret) { 696 dev_err(hdptx->dev, "timeout waiting for phy_rdy\n"); 697 return ret; 698 } 699 700 return 0; 701 } 702 703 static int rockchip_hdptx_phy_configure(struct phy *phy, 704 union phy_configure_opts *opts) 705 { 706 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 707 enum phy_mode mode = generic_phy_get_mode(phy); 708 int ret; 709 710 if (mode != PHY_MODE_DP) 711 return -EINVAL; 712 713 ret = rockchip_hdptx_phy_verify_config(hdptx, &opts->dp); 714 if (ret) { 715 dev_err(hdptx->dev, "invalid params for phy configure\n"); 716 return ret; 717 } 718 719 if (opts->dp.set_rate) { 720 ret = rockchip_hdptx_phy_set_rate(hdptx, &opts->dp); 721 if (ret) { 722 dev_err(hdptx->dev, "failed to set rate: %d\n", ret); 723 return ret; 724 } 725 } 726 727 if (opts->dp.set_voltages) { 728 ret = rockchip_hdptx_phy_set_voltages(hdptx, &opts->dp); 729 if (ret) { 730 dev_err(hdptx->dev, "failed to set voltages: %d\n", 731 ret); 732 return ret; 733 } 734 } 735 736 return 0; 737 } 738 739 static void rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy *hdptx) 740 { 741 phy_update_bits(hdptx, 0x0020, OVRD_LCPLL_EN | LCPLL_EN, 742 FIELD_PREP(OVRD_LCPLL_EN, 0x1) | 743 FIELD_PREP(LCPLL_EN, 0x0)); 744 phy_update_bits(hdptx, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN, 745 FIELD_PREP(OVRD_ROPLL_EN, 0x1) | 746 FIELD_PREP(ROPLL_EN, 0x1)); 747 phy_update_bits(hdptx, 0x0138, ANA_ROPLL_PI_EN, 748 FIELD_PREP(ANA_ROPLL_PI_EN, 0x1)); 749 750 phy_write(hdptx, 0x0144, FIELD_PREP(ROPLL_PMS_MDIV, 0x87)); 751 phy_write(hdptx, 0x0148, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); 752 phy_write(hdptx, 0x014c, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); 753 754 phy_write(hdptx, 0x0154, FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x87)); 755 phy_write(hdptx, 0x0158, FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71)); 756 phy_write(hdptx, 0x015c, FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71)); 757 758 phy_write(hdptx, 0x0164, FIELD_PREP(ANA_ROPLL_PMS_PDIV, 0x1) | 759 FIELD_PREP(ANA_ROPLL_PMS_REFDIV, 0x1)); 760 761 phy_write(hdptx, 0x0168, FIELD_PREP(ROPLL_PMS_SDIV_RBR, 0x3) | 762 FIELD_PREP(ROPLL_PMS_SDIV_HBR, 0x1)); 763 phy_update_bits(hdptx, 0x016c, ROPLL_PMS_SDIV_HBR2, 764 FIELD_PREP(ROPLL_PMS_SDIV_HBR2, 0x0)); 765 766 phy_update_bits(hdptx, 0x0178, ANA_ROPLL_SDM_EN, 767 FIELD_PREP(ANA_ROPLL_SDM_EN, 0x1)); 768 phy_update_bits(hdptx, 0x0178, OVRD_ROPLL_SDM_RSTN | ROPLL_SDM_RSTN, 769 FIELD_PREP(OVRD_ROPLL_SDM_RSTN, 0x1) | 770 FIELD_PREP(ROPLL_SDM_RSTN, 0x1)); 771 phy_update_bits(hdptx, 0x0178, ROPLL_SDC_FRACTIONAL_EN_RBR, 772 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_RBR, 0x1)); 773 phy_update_bits(hdptx, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR, 774 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR, 0x1)); 775 phy_update_bits(hdptx, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR2, 776 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR2, 0x1)); 777 phy_update_bits(hdptx, 0x017c, OVRD_ROPLL_SDC_RSTN | ROPLL_SDC_RSTN, 778 FIELD_PREP(OVRD_ROPLL_SDC_RSTN, 0x1) | 779 FIELD_PREP(ROPLL_SDC_RSTN, 0x1)); 780 781 phy_write(hdptx, 0x0180, FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x21)); 782 phy_write(hdptx, 0x0184, FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27)); 783 phy_write(hdptx, 0x0188, FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27)); 784 785 phy_update_bits(hdptx, 0x0190, ROPLL_SDM_NUMERATOR_SIGN_RBR | 786 ROPLL_SDM_NUMERATOR_SIGN_HBR | 787 ROPLL_SDM_NUMERATOR_SIGN_HBR2, 788 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_RBR, 0x0) | 789 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR, 0x1) | 790 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR2, 0x1)); 791 792 phy_write(hdptx, 0x0194, FIELD_PREP(ROPLL_SDM_NUMERATOR, 0x0)); 793 phy_write(hdptx, 0x0198, FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd)); 794 phy_write(hdptx, 0x019c, FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd)); 795 796 phy_update_bits(hdptx, 0x01a4, ROPLL_SDC_N_RBR, 797 FIELD_PREP(ROPLL_SDC_N_RBR, 0x2)); 798 phy_update_bits(hdptx, 0x01a8, ROPLL_SDC_N_HBR | ROPLL_SDC_N_HBR2, 799 FIELD_PREP(ROPLL_SDC_N_HBR, 0x1) | 800 FIELD_PREP(ROPLL_SDC_N_HBR2, 0x1)); 801 802 phy_write(hdptx, 0x01b0, FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x3)); 803 phy_write(hdptx, 0x01b4, FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7)); 804 phy_write(hdptx, 0x01b8, FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7)); 805 806 phy_write(hdptx, 0x01c0, FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x8)); 807 phy_write(hdptx, 0x01c4, FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18)); 808 phy_write(hdptx, 0x01c8, FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18)); 809 810 phy_update_bits(hdptx, 0x01d0, OVRD_ROPLL_SDC_NDIV_RSTN | 811 ROPLL_SDC_NDIV_RSTN, 812 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN, 0x1) | 813 FIELD_PREP(ROPLL_SDC_NDIV_RSTN, 0x1)); 814 phy_update_bits(hdptx, 0x01dc, ANA_ROPLL_SSC_CLK_DIV_SEL, 815 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL, 0x1)); 816 817 phy_update_bits(hdptx, 0x0118, ROPLL_ANA_CPP_CTRL_COARSE | 818 ROPLL_ANA_CPP_CTRL_FINE, 819 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE, 0xe) | 820 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE, 0xe)); 821 phy_update_bits(hdptx, 0x011c, ROPLL_ANA_LPF_C_SEL_COARSE | 822 ROPLL_ANA_LPF_C_SEL_FINE, 823 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE, 0x4) | 824 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE, 0x4)); 825 826 phy_update_bits(hdptx, 0x0204, ANA_PLL_CD_TX_SER_RATE_SEL, 827 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL, 0x0)); 828 829 phy_update_bits(hdptx, 0x025c, DIG_CLK_SEL, 830 FIELD_PREP(DIG_CLK_SEL, 0x1)); 831 phy_update_bits(hdptx, 0x021c, ANA_PLL_TX_HS_CLK_EN, 832 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN, 0x1)); 833 phy_update_bits(hdptx, 0x0204, ANA_PLL_CD_HSCLK_EAST_EN | 834 ANA_PLL_CD_HSCLK_WEST_EN, 835 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN, 0x1) | 836 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN, 0x0)); 837 phy_update_bits(hdptx, 0x0264, CMN_ROPLL_ALONE_MODE, 838 FIELD_PREP(CMN_ROPLL_ALONE_MODE, 0x1)); 839 phy_update_bits(hdptx, 0x0208, ANA_PLL_CD_VREG_GAIN_CTRL, 840 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL, 0x4)); 841 phy_update_bits(hdptx, 0x00f0, ANA_LCPLL_RESERVED7, 842 FIELD_PREP(ANA_LCPLL_RESERVED7, 0x1)); 843 phy_update_bits(hdptx, 0x020c, ANA_PLL_CD_VREG_ICTRL, 844 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL, 0x1)); 845 phy_update_bits(hdptx, 0x0214, ANA_PLL_SYNC_LOSS_DET_MODE, 846 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE, 0x3)); 847 phy_update_bits(hdptx, 0x0210, PLL_LCRO_CLK_SEL, 848 FIELD_PREP(PLL_LCRO_CLK_SEL, 0x1)); 849 phy_update_bits(hdptx, 0x0268, HS_SPEED_SEL, 850 FIELD_PREP(HS_SPEED_SEL, 0x1)); 851 phy_update_bits(hdptx, 0x026c, LS_SPEED_SEL, 852 FIELD_PREP(LS_SPEED_SEL, 0x1)); 853 } 854 855 static int rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy *hdptx) 856 { 857 u32 status; 858 int ret; 859 860 phy_update_bits(hdptx, 0x0414, ANA_SB_TX_HLVL_PROG, 861 FIELD_PREP(ANA_SB_TX_HLVL_PROG, 0x7)); 862 phy_update_bits(hdptx, 0x0418, ANA_SB_TX_LLVL_PROG, 863 FIELD_PREP(ANA_SB_TX_LLVL_PROG, 0x7)); 864 865 phy_update_bits(hdptx, 0x044c, SB_RX_RCAL_OPT_CODE | SB_RX_RTERM_CTRL, 866 FIELD_PREP(SB_RX_RCAL_OPT_CODE, 0x1) | 867 FIELD_PREP(SB_RX_RTERM_CTRL, 0x3)); 868 phy_update_bits(hdptx, 0x0450, SB_TG_SB_EN_DELAY_TIME | 869 SB_TG_RXTERN_EN_DELAY_TIME, 870 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME, 0x2) | 871 FIELD_PREP(SB_TG_RXTERN_EN_DELAY_TIME, 0x2)); 872 phy_update_bits(hdptx, 0x0454, SB_READY_DELAY_TIME | 873 SB_TG_OSC_EN_DELAY_TIME, 874 FIELD_PREP(SB_READY_DELAY_TIME, 0x2) | 875 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME, 0x2)); 876 phy_update_bits(hdptx, 0x0458, SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 877 FIELD_PREP(SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 0x2)); 878 phy_update_bits(hdptx, 0x045c, SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 879 FIELD_PREP(SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 0x4)); 880 phy_update_bits(hdptx, 0x0460, SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 881 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 0xa)); 882 phy_update_bits(hdptx, 0x0468, SB_TG_CNT_RUN_NO_7_0, 883 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0, 0x3)); 884 phy_update_bits(hdptx, 0x046c, SB_EARC_SIG_DET_BYPASS | SB_AFC_TOL, 885 FIELD_PREP(SB_EARC_SIG_DET_BYPASS, 0x1) | 886 FIELD_PREP(SB_AFC_TOL, 0x3)); 887 phy_update_bits(hdptx, 0x0470, SB_AFC_STB_NUM, 888 FIELD_PREP(SB_AFC_STB_NUM, 0x4)); 889 phy_update_bits(hdptx, 0x0474, SB_TG_OSC_CNT_MIN, 890 FIELD_PREP(SB_TG_OSC_CNT_MIN, 0x67)); 891 phy_update_bits(hdptx, 0x0478, SB_TG_OSC_CNT_MAX, 892 FIELD_PREP(SB_TG_OSC_CNT_MAX, 0x6a)); 893 phy_update_bits(hdptx, 0x047c, SB_PWM_AFC_CTRL, 894 FIELD_PREP(SB_PWM_AFC_CTRL, 0x5)); 895 phy_update_bits(hdptx, 0x0434, ANA_SB_DMRX_LPBK_DATA, 896 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA, 0x1)); 897 phy_update_bits(hdptx, 0x0440, ANA_SB_VREG_OUT_SEL | 898 ANA_SB_VREG_REF_SEL, 899 FIELD_PREP(ANA_SB_VREG_OUT_SEL, 0x1) | 900 FIELD_PREP(ANA_SB_VREG_REF_SEL, 0x1)); 901 phy_update_bits(hdptx, 0x043c, ANA_SB_VREG_GAIN_CTRL, 902 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL, 0x0)); 903 phy_update_bits(hdptx, 0x0408, ANA_SB_RXTERM_OFFSP, 904 FIELD_PREP(ANA_SB_RXTERM_OFFSP, 0x3)); 905 phy_update_bits(hdptx, 0x040c, ANA_SB_RXTERM_OFFSN, 906 FIELD_PREP(ANA_SB_RXTERM_OFFSN, 0x3)); 907 phy_update_bits(hdptx, 0x047c, SB_RCAL_RSTN, 908 FIELD_PREP(SB_RCAL_RSTN, 0x1)); 909 phy_update_bits(hdptx, 0x0410, SB_AUX_EN, 910 FIELD_PREP(SB_AUX_EN, 0x1)); 911 phy_update_bits(hdptx, 0x0480, SB_AUX_EN_IN, 912 FIELD_PREP(SB_AUX_EN_IN, 0x1)); 913 phy_update_bits(hdptx, 0x040c, OVRD_SB_RX_RESCAL_DONE, 914 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE, 0x1)); 915 phy_update_bits(hdptx, 0x0410, OVRD_SB_EN, 916 FIELD_PREP(OVRD_SB_EN, 0x1)); 917 phy_update_bits(hdptx, 0x0408, OVRD_SB_RXTERM_EN, 918 FIELD_PREP(OVRD_SB_RXTERM_EN, 0x1)); 919 phy_update_bits(hdptx, 0x043c, OVRD_SB_VREG_EN, 920 FIELD_PREP(OVRD_SB_VREG_EN, 0x1)); 921 phy_update_bits(hdptx, 0x0410, OVRD_SB_AUX_EN, 922 FIELD_PREP(OVRD_SB_AUX_EN, 0x1)); 923 924 grf_write(hdptx, HDPTXPHY_GRF_CON0, BGR_EN, FIELD_PREP(BGR_EN, 0x1)); 925 grf_write(hdptx, HDPTXPHY_GRF_CON0, BIAS_EN, FIELD_PREP(BIAS_EN, 0x1)); 926 udelay(10); 927 reset_deassert(&hdptx->init_reset); 928 udelay(1000); 929 reset_deassert(&hdptx->cmn_reset); 930 udelay(20); 931 932 phy_update_bits(hdptx, 0x040c, SB_RX_RESCAL_DONE, 933 FIELD_PREP(SB_RX_RESCAL_DONE, 0x1)); 934 udelay(100); 935 phy_update_bits(hdptx, 0x0410, SB_EN, FIELD_PREP(SB_EN, 0x1)); 936 udelay(100); 937 phy_update_bits(hdptx, 0x0408, SB_RXRERM_EN, 938 FIELD_PREP(SB_RXRERM_EN, 0x1)); 939 udelay(10); 940 phy_update_bits(hdptx, 0x043c, SB_VREG_EN, FIELD_PREP(SB_VREG_EN, 0x1)); 941 udelay(10); 942 phy_update_bits(hdptx, 0x0410, SB_AUX_EN, FIELD_PREP(SB_AUX_EN, 0x1)); 943 udelay(100); 944 945 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 946 status, FIELD_GET(SB_RDY, status), 947 50, 1000); 948 if (ret) { 949 dev_err(hdptx->dev, "timeout waiting for sb_rdy\n"); 950 return ret; 951 } 952 953 return 0; 954 } 955 956 static void rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy *hdptx) 957 { 958 u32 lane; 959 960 reset_assert(&hdptx->lane_reset); 961 reset_assert(&hdptx->cmn_reset); 962 reset_assert(&hdptx->init_reset); 963 964 reset_assert(&hdptx->apb_reset); 965 udelay(10); 966 reset_deassert(&hdptx->apb_reset); 967 968 for (lane = 0; lane < 4; lane++) 969 phy_update_bits(hdptx, LANE_REG(lane, 0x0c04), 970 OVRD_LN_TX_DRV_EI_EN | LN_TX_DRV_EI_EN, 971 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN, 1) | 972 FIELD_PREP(LN_TX_DRV_EI_EN, 0)); 973 974 grf_write(hdptx, HDPTXPHY_GRF_CON0, PLL_EN, FIELD_PREP(PLL_EN, 0)); 975 grf_write(hdptx, HDPTXPHY_GRF_CON0, BIAS_EN, FIELD_PREP(BIAS_EN, 0)); 976 grf_write(hdptx, HDPTXPHY_GRF_CON0, BGR_EN, FIELD_PREP(BGR_EN, 0)); 977 } 978 979 static int rockchip_hdptx_phy_power_on(struct phy *phy) 980 { 981 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 982 enum phy_mode mode = generic_phy_get_mode(phy); 983 u32 lane; 984 985 rockchip_hdptx_phy_reset(hdptx); 986 987 for (lane = 0; lane < 4; lane++) { 988 u32 invert = hdptx->lane_polarity_invert[lane]; 989 990 phy_update_bits(hdptx, LANE_REG(lane, 0x0c78), LN_POLARITY_INV, 991 FIELD_PREP(LN_POLARITY_INV, invert)); 992 } 993 994 if (mode == PHY_MODE_DP) { 995 grf_write(hdptx, HDPTXPHY_GRF_CON0, HDPTX_MODE_SEL, 996 FIELD_PREP(HDPTX_MODE_SEL, 0x1)); 997 998 phy_update_bits(hdptx, 0x0800, PROTOCOL_SEL, 999 FIELD_PREP(PROTOCOL_SEL, 0x0)); 1000 phy_update_bits(hdptx, 0x0818, DATA_BUS_WIDTH, 1001 FIELD_PREP(DATA_BUS_WIDTH, 0x1)); 1002 phy_update_bits(hdptx, 0x0818, BUS_WIDTH_SEL, 1003 FIELD_PREP(BUS_WIDTH_SEL, 0x0)); 1004 1005 rockchip_hdptx_phy_dp_pll_init(hdptx); 1006 rockchip_hdptx_phy_dp_aux_init(hdptx); 1007 } else { 1008 grf_write(hdptx, HDPTXPHY_GRF_CON0, HDPTX_MODE_SEL, 1009 FIELD_PREP(HDPTX_MODE_SEL, 0x0)); 1010 1011 phy_update_bits(hdptx, 0x0800, PROTOCOL_SEL, 1012 FIELD_PREP(PROTOCOL_SEL, 0x1)); 1013 } 1014 1015 return 0; 1016 } 1017 1018 static int rockchip_hdptx_phy_power_off(struct phy *phy) 1019 { 1020 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 1021 1022 rockchip_hdptx_phy_reset(hdptx); 1023 1024 return 0; 1025 } 1026 1027 static const struct phy_ops rockchip_hdptx_phy_ops = { 1028 .set_mode = rockchip_hdptx_phy_set_mode, 1029 .configure = rockchip_hdptx_phy_configure, 1030 .power_on = rockchip_hdptx_phy_power_on, 1031 .power_off = rockchip_hdptx_phy_power_off, 1032 }; 1033 1034 static int rockchip_hdptx_phy_probe(struct udevice *dev) 1035 { 1036 struct rockchip_hdptx_phy *hdptx = dev_get_priv(dev); 1037 struct udevice *syscon; 1038 u32 prop[4]; 1039 int ret; 1040 1041 hdptx->base = dev_read_addr_ptr(dev); 1042 if (!hdptx->base) 1043 return -ENOENT; 1044 1045 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1046 &syscon); 1047 if (ret) 1048 return ret; 1049 1050 hdptx->grf = syscon_get_regmap(syscon); 1051 if (IS_ERR(hdptx->grf)) { 1052 ret = PTR_ERR(hdptx->grf); 1053 dev_err(dev, "unable to find regmap: %d\n", ret); 1054 return ret; 1055 } 1056 1057 hdptx->dev = dev; 1058 1059 ret = reset_get_by_name(dev, "apb", &hdptx->apb_reset); 1060 if (ret < 0) { 1061 dev_err(dev, "failed to get apb reset: %d\n", ret); 1062 return ret; 1063 } 1064 1065 ret = reset_get_by_name(dev, "init", &hdptx->init_reset); 1066 if (ret < 0) { 1067 dev_err(dev, "failed to get init reset: %d\n", ret); 1068 return ret; 1069 } 1070 1071 ret = reset_get_by_name(dev, "cmn", &hdptx->cmn_reset); 1072 if (ret < 0) { 1073 dev_err(dev, "failed to get cmn reset: %d\n", ret); 1074 return ret; 1075 } 1076 1077 ret = reset_get_by_name(dev, "lane", &hdptx->lane_reset); 1078 if (ret < 0) { 1079 dev_err(dev, "failed to get lane reset: %d\n", ret); 1080 return ret; 1081 } 1082 1083 ret = rockchip_hdptx_phy_parse_training_table(dev); 1084 if (ret) { 1085 dev_err(dev, "failed to parse training table: %d\n", ret); 1086 return ret; 1087 } 1088 1089 if (!dev_read_u32_array(dev, "lane-polarity-invert", prop, ARRAY_SIZE(prop))) { 1090 hdptx->lane_polarity_invert[0] = prop[0]; 1091 hdptx->lane_polarity_invert[1] = prop[1]; 1092 hdptx->lane_polarity_invert[2] = prop[2]; 1093 hdptx->lane_polarity_invert[3] = prop[3]; 1094 } 1095 1096 return 0; 1097 } 1098 1099 static const struct udevice_id rockchip_hdptx_phy_ids[] = { 1100 { .compatible = "rockchip,rk3588-hdptx-phy", }, 1101 {} 1102 }; 1103 1104 U_BOOT_DRIVER(rockchip_hdptx_phy) = { 1105 .name = "rockchip_hdptx_phy", 1106 .id = UCLASS_PHY, 1107 .ops = &rockchip_hdptx_phy_ops, 1108 .of_match = rockchip_hdptx_phy_ids, 1109 .probe = rockchip_hdptx_phy_probe, 1110 .priv_auto_alloc_size = sizeof(struct rockchip_hdptx_phy), 1111 }; 1112