1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip HDMI/DP Combo PHY with Samsung IP block 4 * 5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <generic-phy.h> 11 #include <reset.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <linux/bitfield.h> 16 #include <linux/iopoll.h> 17 #include <asm/arch/clock.h> 18 19 #define HDPTXPHY_GRF_CON0 0x0000 20 #define RO_REF_CLK_SEL GENMASK(11, 10) 21 #define LC_REF_CLK_SEL GENMASK(9, 8) 22 #define PLL_EN BIT(7) 23 #define BIAS_EN BIT(6) 24 #define BGR_EN BIT(5) 25 #define HDPTX_MODE_SEL BIT(0) 26 #define HDPTXPHY_GRF_STATUS0 0x0080 27 #define PLL_LOCK_DONE BIT(3) 28 #define PHY_CLK_RDY BIT(2) 29 #define PHY_RDY BIT(1) 30 #define SB_RDY BIT(0) 31 32 /* cmn_reg0008 */ 33 #define OVRD_LCPLL_EN BIT(7) 34 #define LCPLL_EN BIT(6) 35 36 /* cmn_reg003C */ 37 #define ANA_LCPLL_RESERVED7 BIT(7) 38 39 /* cmn_reg003D */ 40 #define OVRD_ROPLL_EN BIT(7) 41 #define ROPLL_EN BIT(6) 42 43 /* cmn_reg0046 */ 44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4) 45 #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0) 46 47 /* cmn_reg0047 */ 48 #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3) 49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0) 50 51 /* cmn_reg004E */ 52 #define ANA_ROPLL_PI_EN BIT(5) 53 54 /* cmn_reg0051 */ 55 #define ROPLL_PMS_MDIV GENMASK(7, 0) 56 57 /* cmn_reg0055 */ 58 #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0) 59 60 /* cmn_reg0059 */ 61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4) 62 #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0) 63 64 /* cmn_reg005A */ 65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4) 66 #define ROPLL_PMS_SDIV_HBR GENMASK(3, 0) 67 68 /* cmn_reg005B */ 69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4) 70 #define ROPLL_PMS_SDIV_HBR3 GENMASK(3, 0) 71 72 /* cmn_reg005D */ 73 #define OVRD_ROPLL_REF_CLK_SEL BIT(5) 74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3) 75 76 /* cmn_reg005E */ 77 #define ANA_ROPLL_SDM_EN BIT(6) 78 #define OVRD_ROPLL_SDM_RSTN BIT(5) 79 #define ROPLL_SDM_RSTN BIT(4) 80 #define ROPLL_SDC_FRACTIONAL_EN_RBR BIT(3) 81 #define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2) 82 #define ROPLL_SDC_FRACTIONAL_EN_HBR2 BIT(1) 83 #define ROPLL_SDC_FRACTIONAL_EN_HBR3 BIT(0) 84 85 /* cmn_reg005F */ 86 #define OVRD_ROPLL_SDC_RSTN BIT(5) 87 #define ROPLL_SDC_RSTN BIT(4) 88 89 /* cmn_reg0060 */ 90 #define ROPLL_SDM_DENOMINATOR GENMASK(7, 0) 91 92 /* cmn_reg0064 */ 93 #define ROPLL_SDM_NUMERATOR_SIGN_RBR BIT(3) 94 #define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2) 95 #define ROPLL_SDM_NUMERATOR_SIGN_HBR2 BIT(1) 96 #define ROPLL_SDM_NUMERATOR_SIGN_HBR3 BIT(0) 97 98 /* cmn_reg0065 */ 99 #define ROPLL_SDM_NUMERATOR GENMASK(7, 0) 100 101 /* cmn_reg0069 */ 102 #define ROPLL_SDC_N_RBR GENMASK(2, 0) 103 104 /* cmn_reg006A */ 105 #define ROPLL_SDC_N_HBR GENMASK(5, 3) 106 #define ROPLL_SDC_N_HBR2 GENMASK(2, 0) 107 108 /* cmn_reg006B */ 109 #define ROPLL_SDC_N_HBR3 GENMASK(3, 1) 110 111 /* cmn_reg006C */ 112 #define ROPLL_SDC_NUMERATOR GENMASK(5, 0) 113 114 /* cmn_reg0070 */ 115 #define ROPLL_SDC_DENOMINATOR GENMASK(5, 0) 116 117 /* cmn_reg0074 */ 118 #define OVRD_ROPLL_SDC_NDIV_RSTN BIT(3) 119 #define ROPLL_SDC_NDIV_RSTN BIT(2) 120 #define OVRD_ROPLL_SSC_EN BIT(1) 121 #define ROPLL_SSC_EN BIT(0) 122 123 /* cmn_reg0075 */ 124 #define ANA_ROPLL_SSC_FM_DEVIATION GENMASK(5, 0) 125 126 /* cmn_reg0076 */ 127 #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2) 128 129 /* cmn_reg0077 */ 130 #define ANA_ROPLL_SSC_CLK_DIV_SEL GENMASK(6, 3) 131 132 /* cmn_reg0081 */ 133 #define ANA_PLL_CD_TX_SER_RATE_SEL BIT(3) 134 #define ANA_PLL_CD_HSCLK_WEST_EN BIT(1) 135 #define ANA_PLL_CD_HSCLK_EAST_EN BIT(0) 136 137 /* cmn_reg0082 */ 138 #define ANA_PLL_CD_VREG_GAIN_CTRL GENMASK(3, 0) 139 140 /* cmn_reg0083 */ 141 #define ANA_PLL_CD_VREG_ICTRL GENMASK(6, 5) 142 143 /* cmn_reg0084 */ 144 #define PLL_LCRO_CLK_SEL BIT(5) 145 146 /* cmn_reg0085 */ 147 #define ANA_PLL_SYNC_LOSS_DET_MODE GENMASK(1, 0) 148 149 /* cmn_reg0087 */ 150 #define ANA_PLL_TX_HS_CLK_EN BIT(2) 151 152 /* cmn_reg0095 */ 153 #define DP_TX_LINK_BW GENMASK(1, 0) 154 155 /* cmn_reg0097 */ 156 #define DIG_CLK_SEL BIT(1) 157 158 /* cmn_reg0099 */ 159 #define SSC_EN GENMASK(7, 6) 160 #define CMN_ROPLL_ALONE_MODE BIT(2) 161 162 /* cmn_reg009A */ 163 #define HS_SPEED_SEL BIT(0) 164 165 /* cmn_reg009B */ 166 #define LS_SPEED_SEL BIT(4) 167 168 /* sb_reg0102 */ 169 #define OVRD_SB_RXTERM_EN BIT(5) 170 #define SB_RXRERM_EN BIT(4) 171 #define ANA_SB_RXTERM_OFFSP GENMASK(3, 0) 172 173 /* sb_reg0103 */ 174 #define ANA_SB_RXTERM_OFFSN GENMASK(6, 3) 175 #define OVRD_SB_RX_RESCAL_DONE BIT(1) 176 #define SB_RX_RESCAL_DONE BIT(0) 177 178 /* sb_reg0104 */ 179 #define OVRD_SB_EN BIT(5) 180 #define SB_EN BIT(4) 181 #define OVRD_SB_AUX_EN BIT(1) 182 #define SB_AUX_EN BIT(0) 183 184 /* sb_reg0105 */ 185 #define ANA_SB_TX_HLVL_PROG GENMASK(2, 0) 186 187 /* sb_reg0106 */ 188 #define ANA_SB_TX_LLVL_PROG GENMASK(6, 4) 189 190 /* sb_reg010D */ 191 #define ANA_SB_DMRX_LPBK_DATA BIT(4) 192 193 /* sb_reg010F */ 194 #define OVRD_SB_VREG_EN BIT(7) 195 #define SB_VREG_EN BIT(6) 196 #define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0) 197 198 /* sb_reg0110 */ 199 #define ANA_SB_VREG_OUT_SEL BIT(1) 200 #define ANA_SB_VREG_REF_SEL BIT(0) 201 202 /* sb_reg0113 */ 203 #define SB_RX_RCAL_OPT_CODE GENMASK(5, 4) 204 #define SB_RX_RTERM_CTRL GENMASK(3, 0) 205 206 /* sb_reg0114 */ 207 #define SB_TG_SB_EN_DELAY_TIME GENMASK(5, 3) 208 #define SB_TG_RXTERN_EN_DELAY_TIME GENMASK(2, 0) 209 210 /* sb_reg0115 */ 211 #define SB_READY_DELAY_TIME GENMASK(5, 3) 212 #define SB_TG_OSC_EN_DELAY_TIME GENMASK(2, 0) 213 214 /* sb_reg0116 */ 215 #define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4) 216 217 /* sb_reg0117 */ 218 #define SB_TG_PLL_CD_VREG_FAST_PULSE_TIME GENMASK(3, 0) 219 220 /* sb_reg0118 */ 221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT GENMASK(7, 0) 222 223 /* sb_reg011A */ 224 #define SB_TG_CNT_RUN_NO_7_0 GENMASK(7, 0) 225 226 /* sb_reg011B */ 227 #define SB_EARC_SIG_DET_BYPASS BIT(4) 228 #define SB_AFC_TOL GENMASK(3, 0) 229 230 /* sb_reg011C */ 231 #define SB_AFC_STB_NUM GENMASK(3, 0) 232 233 /* sb_reg011D */ 234 #define SB_TG_OSC_CNT_MIN GENMASK(7, 0) 235 236 /* sb_reg011E */ 237 #define SB_TG_OSC_CNT_MAX GENMASK(7, 0) 238 239 /* sb_reg011F */ 240 #define SB_PWM_AFC_CTRL GENMASK(7, 2) 241 #define SB_RCAL_RSTN BIT(1) 242 243 /* sb_reg0120 */ 244 #define SB_AUX_EN_IN BIT(7) 245 246 /* sb_reg0123 */ 247 #define OVRD_SB_READY BIT(5) 248 #define SB_READY BIT(4) 249 250 /* lntop_reg0200 */ 251 #define PROTOCOL_SEL BIT(2) 252 253 /* lntop_reg0206 */ 254 #define DATA_BUS_WIDTH GENMASK(2, 1) 255 #define BUS_WIDTH_SEL BIT(0) 256 257 /* lntop_reg0207 */ 258 #define LANE_EN GENMASK(3, 0) 259 260 /* lane_reg0301 */ 261 #define OVRD_LN_TX_DRV_EI_EN BIT(7) 262 #define LN_TX_DRV_EI_EN BIT(6) 263 264 /* lane_reg0303 */ 265 #define OVRD_LN_TX_DRV_LVL_CTRL BIT(5) 266 #define LN_TX_DRV_LVL_CTRL GENMASK(4, 0) 267 268 /* lane_reg0304 */ 269 #define OVRD_LN_TX_DRV_POST_LVL_CTRL BIT(4) 270 #define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0) 271 272 /* lane_reg0305 */ 273 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL BIT(6) 274 #define LN_TX_DRV_PRE_LVL_CTRL GENMASK(5, 2) 275 276 /* lane_reg0306 */ 277 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL GENMASK(7, 5) 278 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL GENMASK(4, 2) 279 #define LN_ANA_TX_DRV_ACCDRV_EN BIT(0) 280 281 /* lane_reg0307 */ 282 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL BIT(6) 283 #define LN_ANA_TX_DRV_ACCDRV_CTRL GENMASK(5, 3) 284 285 /* lane_reg030A */ 286 #define LN_ANA_TX_JEQ_EN BIT(4) 287 #define LN_TX_JEQ_EVEN_CTRL_RBR GENMASK(3, 0) 288 289 /* lane_reg030B */ 290 #define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4) 291 #define LN_TX_JEQ_EVEN_CTRL_HBR2 GENMASK(3, 0) 292 293 /* lane_reg030C */ 294 #define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4) 295 #define LN_TX_JEQ_ODD_CTRL_RBR GENMASK(3, 0) 296 297 /* lane_reg030D */ 298 #define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4) 299 #define LN_TX_JEQ_ODD_CTRL_HBR2 GENMASK(3, 0) 300 301 /* lane_reg030E */ 302 #define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4) 303 304 /* lane_reg0310 */ 305 #define LN_ANA_TX_SYNC_LOSS_DET_MODE GENMASK(1, 0) 306 307 /* lane_reg0311 */ 308 #define LN_TX_SER_40BIT_EN_RBR BIT(3) 309 #define LN_TX_SER_40BIT_EN_HBR BIT(2) 310 #define LN_TX_SER_40BIT_EN_HBR2 BIT(1) 311 #define LN_TX_SER_40BIT_EN_HBR3 BIT(0) 312 313 /* lane_reg0316 */ 314 #define LN_ANA_TX_SER_VREG_GAIN_CTRL GENMASK(3, 0) 315 316 /* lane_reg031B */ 317 #define LN_ANA_TX_RESERVED GENMASK(7, 0) 318 319 /* lane_reg031E */ 320 #define LN_POLARITY_INV BIT(2) 321 #define LN_LANE_MODE BIT(1) 322 323 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset)) 324 325 struct rockchip_hdptx_phy { 326 struct udevice *dev; 327 struct regmap *regmap; 328 struct regmap *grf; 329 330 struct reset_ctl apb_reset; 331 struct reset_ctl cmn_reset; 332 struct reset_ctl init_reset; 333 struct reset_ctl lane_reset; 334 u32 lane_polarity_invert[4]; 335 }; 336 337 enum { 338 DP_BW_RBR, 339 DP_BW_HBR, 340 DP_BW_HBR2, 341 DP_BW_HBR3, 342 }; 343 344 struct tx_drv_ctrl { 345 u8 tx_drv_lvl_ctrl; 346 u8 tx_drv_post_lvl_ctrl; 347 u8 ana_tx_drv_idrv_idn_ctrl; 348 u8 ana_tx_drv_idrv_iup_ctrl; 349 u8 ana_tx_drv_accdrv_en; 350 u8 ana_tx_drv_accdrv_ctrl; 351 } __packed; 352 353 static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = { 354 /* voltage swing 0, pre-emphasis 0->3 */ 355 { 356 { 0x1, 0x0, 0x4, 0x6, 0x0, 0x4 }, 357 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4 }, 358 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4 }, 359 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 360 }, 361 362 /* voltage swing 1, pre-emphasis 0->2 */ 363 { 364 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4 }, 365 { 0xa, 0x5, 0x4, 0x6, 0x0, 0x4 }, 366 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 367 }, 368 369 /* voltage swing 2, pre-emphasis 0->1 */ 370 { 371 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4 }, 372 { 0xd, 0x5, 0x7, 0x7, 0x1, 0x7 }, 373 }, 374 375 /* voltage swing 3, pre-emphasis 0 */ 376 { 377 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 }, 378 } 379 }; 380 381 static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = { 382 /* voltage swing 0, pre-emphasis 0->3 */ 383 { 384 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 }, 385 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 }, 386 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4 }, 387 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 388 }, 389 390 /* voltage swing 1, pre-emphasis 0->2 */ 391 { 392 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 }, 393 { 0xb, 0x6, 0x4, 0x6, 0x0, 0x4 }, 394 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 395 }, 396 397 /* voltage swing 2, pre-emphasis 0->1 */ 398 { 399 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 }, 400 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 }, 401 }, 402 403 /* voltage swing 3, pre-emphasis 0 */ 404 { 405 { 0xd, 0x1, 0x7, 0x7, 0x1, 0x4 }, 406 } 407 }; 408 409 static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = { 410 /* voltage swing 0, pre-emphasis 0->3 */ 411 { 412 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 }, 413 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 }, 414 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4 }, 415 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, 416 }, 417 418 /* voltage swing 1, pre-emphasis 0->2 */ 419 { 420 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 }, 421 { 0xc, 0x7, 0x4, 0x6, 0x0, 0x4 }, 422 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, 423 }, 424 425 /* voltage swing 2, pre-emphasis 0->1 */ 426 { 427 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 }, 428 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 }, 429 }, 430 431 /* voltage swing 3, pre-emphasis 0 */ 432 { 433 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 }, 434 } 435 }; 436 437 static int rockchip_hdptx_phy_parse_training_table(struct udevice *dev) 438 { 439 int size = sizeof(struct tx_drv_ctrl) * 10; 440 const uint8_t *prop; 441 u8 *buf, *training_table; 442 int i, j; 443 444 prop = dev_read_u8_array_ptr(dev, "training-table", size); 445 if (!prop) 446 return 0; 447 448 buf = kzalloc(size, GFP_KERNEL); 449 if (!buf) 450 return -ENOMEM; 451 452 memcpy(buf, prop, size); 453 454 training_table = buf; 455 456 for (i = 0; i < 4; i++) { 457 for (j = 0; j < 4; j++) { 458 struct tx_drv_ctrl *ctrl; 459 460 if (i + j > 3) 461 continue; 462 463 ctrl = (struct tx_drv_ctrl *)training_table; 464 tx_drv_ctrl_rbr[i][j] = *ctrl; 465 tx_drv_ctrl_hbr[i][j] = *ctrl; 466 tx_drv_ctrl_hbr2[i][j] = *ctrl; 467 training_table += sizeof(*ctrl); 468 } 469 } 470 471 kfree(buf); 472 473 return 0; 474 } 475 476 static inline void rockchip_grf_write(struct regmap *grf, uint reg, uint mask, 477 uint val) 478 { 479 regmap_write(grf, reg, (mask << 16) | (val & mask)); 480 } 481 482 static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, 483 int submode) 484 { 485 return 0; 486 } 487 488 static int rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy *hdptx, 489 struct phy_configure_opts_dp *dp) 490 { 491 int i; 492 493 if (dp->set_rate) { 494 switch (dp->link_rate) { 495 case 1620: 496 case 2700: 497 case 5400: 498 break; 499 default: 500 return -EINVAL; 501 } 502 } 503 504 switch (dp->lanes) { 505 case 1: 506 case 2: 507 case 4: 508 break; 509 default: 510 return -EINVAL; 511 } 512 513 if (dp->set_voltages) { 514 for (i = 0; i < dp->lanes; i++) { 515 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 516 return -EINVAL; 517 518 if (dp->voltage[i] + dp->pre[i] > 3) 519 return -EINVAL; 520 } 521 } 522 523 return 0; 524 } 525 526 static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, 527 struct phy_configure_opts_dp *dp, 528 u8 lane) 529 { 530 const struct tx_drv_ctrl *ctrl; 531 532 switch (dp->link_rate) { 533 case 1620: 534 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; 535 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), 536 LN_TX_SER_40BIT_EN_RBR, 537 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1)); 538 break; 539 case 2700: 540 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; 541 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), 542 LN_TX_SER_40BIT_EN_HBR, 543 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1)); 544 break; 545 case 5400: 546 default: 547 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]]; 548 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), 549 LN_TX_SER_40BIT_EN_HBR2, 550 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1)); 551 break; 552 } 553 554 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c0c), 555 OVRD_LN_TX_DRV_LVL_CTRL | LN_TX_DRV_LVL_CTRL, 556 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL, 0x1) | 557 FIELD_PREP(LN_TX_DRV_LVL_CTRL, 558 ctrl->tx_drv_lvl_ctrl)); 559 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c10), 560 OVRD_LN_TX_DRV_POST_LVL_CTRL | 561 LN_TX_DRV_POST_LVL_CTRL, 562 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL, 0x1) | 563 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL, 564 ctrl->tx_drv_post_lvl_ctrl)); 565 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c18), 566 LN_ANA_TX_DRV_IDRV_IDN_CTRL | 567 LN_ANA_TX_DRV_IDRV_IUP_CTRL | 568 LN_ANA_TX_DRV_ACCDRV_EN, 569 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL, 570 ctrl->ana_tx_drv_idrv_idn_ctrl) | 571 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL, 572 ctrl->ana_tx_drv_idrv_iup_ctrl) | 573 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN, 574 ctrl->ana_tx_drv_accdrv_en)); 575 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c1c), 576 LN_ANA_TX_DRV_ACCDRV_POL_SEL | 577 LN_ANA_TX_DRV_ACCDRV_CTRL, 578 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL, 0x1) | 579 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL, 580 ctrl->ana_tx_drv_accdrv_ctrl)); 581 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c6c), 582 LN_ANA_TX_RESERVED, 583 FIELD_PREP(LN_ANA_TX_RESERVED, 0x1)); 584 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c58), 585 LN_ANA_TX_SER_VREG_GAIN_CTRL, 586 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL, 0x2)); 587 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c40), 588 LN_ANA_TX_SYNC_LOSS_DET_MODE, 589 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE, 0x3)); 590 } 591 592 static int rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy *hdptx, 593 struct phy_configure_opts_dp *dp) 594 { 595 u8 lane; 596 u32 status; 597 int ret; 598 599 for (lane = 0; lane < dp->lanes; lane++) 600 rockchip_hdptx_phy_set_voltage(hdptx, dp, lane); 601 602 reset_deassert(&hdptx->lane_reset); 603 604 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 605 status, FIELD_GET(PHY_RDY, status), 606 50, 5000); 607 if (ret) { 608 dev_err(hdptx->dev, "timeout waiting for phy_rdy\n"); 609 return ret; 610 } 611 612 return 0; 613 } 614 615 static int rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy *hdptx, 616 struct phy_configure_opts_dp *dp) 617 { 618 u32 bw, status; 619 int ret; 620 621 reset_assert(&hdptx->lane_reset); 622 udelay(10); 623 reset_assert(&hdptx->cmn_reset); 624 udelay(10); 625 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN, 626 FIELD_PREP(PLL_EN, 0x0)); 627 udelay(10); 628 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN, 629 FIELD_PREP(LANE_EN, 0x0)); 630 631 switch (dp->link_rate) { 632 case 1620: 633 bw = DP_BW_RBR; 634 break; 635 case 2700: 636 bw = DP_BW_HBR; 637 break; 638 case 5400: 639 bw = DP_BW_HBR2; 640 break; 641 default: 642 return -EINVAL; 643 } 644 645 regmap_update_bits(hdptx->regmap, 0x0254, DP_TX_LINK_BW, 646 FIELD_PREP(DP_TX_LINK_BW, bw)); 647 648 if (dp->ssc) { 649 regmap_update_bits(hdptx->regmap, 0x01d0, 650 OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, 651 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) | 652 FIELD_PREP(ROPLL_SSC_EN, 0x1)); 653 regmap_update_bits(hdptx->regmap, 0x01d4, 654 ANA_ROPLL_SSC_FM_DEVIATION, 655 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0xc)); 656 regmap_update_bits(hdptx->regmap, 0x01d8, 657 ANA_ROPLL_SSC_FM_FREQ, 658 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0x1f)); 659 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN, 660 FIELD_PREP(SSC_EN, 0x2)); 661 } else { 662 regmap_update_bits(hdptx->regmap, 0x01d0, 663 OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, 664 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) | 665 FIELD_PREP(ROPLL_SSC_EN, 0x0)); 666 regmap_update_bits(hdptx->regmap, 0x01d4, 667 ANA_ROPLL_SSC_FM_DEVIATION, 668 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0x20)); 669 regmap_update_bits(hdptx->regmap, 0x01d8, 670 ANA_ROPLL_SSC_FM_FREQ, 671 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0xc)); 672 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN, 673 FIELD_PREP(SSC_EN, 0x0)); 674 } 675 676 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN, 677 FIELD_PREP(PLL_EN, 0x1)); 678 udelay(10); 679 reset_deassert(&hdptx->cmn_reset); 680 udelay(10); 681 682 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 683 status, FIELD_GET(PLL_LOCK_DONE, status), 684 50, 1000); 685 if (ret) { 686 dev_err(hdptx->dev, "timeout waiting for pll_lock_done\n"); 687 return ret; 688 } 689 690 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN, 691 FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0))); 692 693 return 0; 694 } 695 696 static int rockchip_hdptx_phy_configure(struct phy *phy, 697 union phy_configure_opts *opts) 698 { 699 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 700 enum phy_mode mode = generic_phy_get_mode(phy); 701 int ret; 702 703 if (mode != PHY_MODE_DP) 704 return -EINVAL; 705 706 ret = rockchip_hdptx_phy_verify_config(hdptx, &opts->dp); 707 if (ret) { 708 dev_err(hdptx->dev, "invalid params for phy configure\n"); 709 return ret; 710 } 711 712 if (opts->dp.set_rate) { 713 ret = rockchip_hdptx_phy_set_rate(hdptx, &opts->dp); 714 if (ret) { 715 dev_err(hdptx->dev, "failed to set rate: %d\n", ret); 716 return ret; 717 } 718 } 719 720 if (opts->dp.set_voltages) { 721 ret = rockchip_hdptx_phy_set_voltages(hdptx, &opts->dp); 722 if (ret) { 723 dev_err(hdptx->dev, "failed to set voltages: %d\n", 724 ret); 725 return ret; 726 } 727 } 728 729 return 0; 730 } 731 732 static void rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy *hdptx) 733 { 734 regmap_update_bits(hdptx->regmap, 0x0020, OVRD_LCPLL_EN | LCPLL_EN, 735 FIELD_PREP(OVRD_LCPLL_EN, 0x1) | 736 FIELD_PREP(LCPLL_EN, 0x0)); 737 regmap_update_bits(hdptx->regmap, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN, 738 FIELD_PREP(OVRD_ROPLL_EN, 0x1) | 739 FIELD_PREP(ROPLL_EN, 0x1)); 740 regmap_update_bits(hdptx->regmap, 0x0138, ANA_ROPLL_PI_EN, 741 FIELD_PREP(ANA_ROPLL_PI_EN, 0x1)); 742 regmap_write(hdptx->regmap, 0x0144, FIELD_PREP(ROPLL_PMS_MDIV, 0x87)); 743 regmap_write(hdptx->regmap, 0x0148, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); 744 regmap_write(hdptx->regmap, 0x014c, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); 745 regmap_write(hdptx->regmap, 0x0154, 746 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x87)); 747 regmap_write(hdptx->regmap, 0x0158, 748 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71)); 749 regmap_write(hdptx->regmap, 0x015c, 750 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71)); 751 regmap_write(hdptx->regmap, 0x0164, 752 FIELD_PREP(ANA_ROPLL_PMS_PDIV, 0x1) | 753 FIELD_PREP(ANA_ROPLL_PMS_REFDIV, 0x1)); 754 regmap_write(hdptx->regmap, 0x0168, 755 FIELD_PREP(ROPLL_PMS_SDIV_RBR, 0x3) | 756 FIELD_PREP(ROPLL_PMS_SDIV_HBR, 0x1)); 757 regmap_update_bits(hdptx->regmap, 0x016c, ROPLL_PMS_SDIV_HBR2, 758 FIELD_PREP(ROPLL_PMS_SDIV_HBR2, 0x0)); 759 regmap_update_bits(hdptx->regmap, 0x0178, ANA_ROPLL_SDM_EN, 760 FIELD_PREP(ANA_ROPLL_SDM_EN, 0x1)); 761 regmap_update_bits(hdptx->regmap, 0x0178, 762 OVRD_ROPLL_SDM_RSTN | ROPLL_SDM_RSTN, 763 FIELD_PREP(OVRD_ROPLL_SDM_RSTN, 0x1) | 764 FIELD_PREP(ROPLL_SDM_RSTN, 0x1)); 765 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_RBR, 766 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_RBR, 0x1)); 767 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR, 768 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR, 0x1)); 769 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR2, 770 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR2, 0x1)); 771 regmap_update_bits(hdptx->regmap, 0x017c, 772 OVRD_ROPLL_SDC_RSTN | ROPLL_SDC_RSTN, 773 FIELD_PREP(OVRD_ROPLL_SDC_RSTN, 0x1) | 774 FIELD_PREP(ROPLL_SDC_RSTN, 0x1)); 775 regmap_write(hdptx->regmap, 0x0180, 776 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x21)); 777 regmap_write(hdptx->regmap, 0x0184, 778 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27)); 779 regmap_write(hdptx->regmap, 0x0188, 780 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27)); 781 regmap_update_bits(hdptx->regmap, 0x0190, 782 ROPLL_SDM_NUMERATOR_SIGN_RBR | 783 ROPLL_SDM_NUMERATOR_SIGN_HBR | 784 ROPLL_SDM_NUMERATOR_SIGN_HBR2, 785 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_RBR, 0x0) | 786 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR, 0x1) | 787 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR2, 0x1)); 788 regmap_write(hdptx->regmap, 0x0194, 789 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0x0)); 790 regmap_write(hdptx->regmap, 0x0198, 791 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd)); 792 regmap_write(hdptx->regmap, 0x019c, 793 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd)); 794 regmap_update_bits(hdptx->regmap, 0x01a4, ROPLL_SDC_N_RBR, 795 FIELD_PREP(ROPLL_SDC_N_RBR, 0x2)); 796 regmap_update_bits(hdptx->regmap, 0x01a8, 797 ROPLL_SDC_N_HBR | ROPLL_SDC_N_HBR2, 798 FIELD_PREP(ROPLL_SDC_N_HBR, 0x2) | 799 FIELD_PREP(ROPLL_SDC_N_HBR2, 0x2)); 800 regmap_write(hdptx->regmap, 0x01b0, 801 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x3)); 802 regmap_write(hdptx->regmap, 0x01b4, 803 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7)); 804 regmap_write(hdptx->regmap, 0x01b8, 805 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7)); 806 regmap_write(hdptx->regmap, 0x01c0, 807 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x8)); 808 regmap_write(hdptx->regmap, 0x01c4, 809 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18)); 810 regmap_write(hdptx->regmap, 0x01c8, 811 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18)); 812 regmap_update_bits(hdptx->regmap, 0x01d0, 813 OVRD_ROPLL_SDC_NDIV_RSTN | ROPLL_SDC_NDIV_RSTN, 814 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN, 0x1) | 815 FIELD_PREP(ROPLL_SDC_NDIV_RSTN, 0x1)); 816 regmap_update_bits(hdptx->regmap, 0x01dc, ANA_ROPLL_SSC_CLK_DIV_SEL, 817 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL, 0x1)); 818 regmap_update_bits(hdptx->regmap, 0x0118, 819 ROPLL_ANA_CPP_CTRL_COARSE | ROPLL_ANA_CPP_CTRL_FINE, 820 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE, 0xe) | 821 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE, 0xe)); 822 regmap_update_bits(hdptx->regmap, 0x011c, 823 ROPLL_ANA_LPF_C_SEL_COARSE | 824 ROPLL_ANA_LPF_C_SEL_FINE, 825 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE, 0x4) | 826 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE, 0x4)); 827 regmap_update_bits(hdptx->regmap, 0x0204, ANA_PLL_CD_TX_SER_RATE_SEL, 828 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL, 0x0)); 829 regmap_update_bits(hdptx->regmap, 0x025c, DIG_CLK_SEL, 830 FIELD_PREP(DIG_CLK_SEL, 0x1)); 831 regmap_update_bits(hdptx->regmap, 0x021c, ANA_PLL_TX_HS_CLK_EN, 832 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN, 0x1)); 833 regmap_update_bits(hdptx->regmap, 0x0204, 834 ANA_PLL_CD_HSCLK_EAST_EN | ANA_PLL_CD_HSCLK_WEST_EN, 835 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN, 0x1) | 836 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN, 0x0)); 837 regmap_update_bits(hdptx->regmap, 0x0264, CMN_ROPLL_ALONE_MODE, 838 FIELD_PREP(CMN_ROPLL_ALONE_MODE, 0x1)); 839 regmap_update_bits(hdptx->regmap, 0x0208, ANA_PLL_CD_VREG_GAIN_CTRL, 840 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL, 0x4)); 841 regmap_update_bits(hdptx->regmap, 0x00f0, ANA_LCPLL_RESERVED7, 842 FIELD_PREP(ANA_LCPLL_RESERVED7, 0x1)); 843 regmap_update_bits(hdptx->regmap, 0x020c, ANA_PLL_CD_VREG_ICTRL, 844 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL, 0x1)); 845 regmap_update_bits(hdptx->regmap, 0x0214, ANA_PLL_SYNC_LOSS_DET_MODE, 846 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE, 0x3)); 847 regmap_update_bits(hdptx->regmap, 0x0210, PLL_LCRO_CLK_SEL, 848 FIELD_PREP(PLL_LCRO_CLK_SEL, 0x1)); 849 regmap_update_bits(hdptx->regmap, 0x0268, HS_SPEED_SEL, 850 FIELD_PREP(HS_SPEED_SEL, 0x1)); 851 regmap_update_bits(hdptx->regmap, 0x026c, LS_SPEED_SEL, 852 FIELD_PREP(LS_SPEED_SEL, 0x1)); 853 } 854 855 static int rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy *hdptx) 856 { 857 u32 status; 858 int ret; 859 860 regmap_update_bits(hdptx->regmap, 0x0414, ANA_SB_TX_HLVL_PROG, 861 FIELD_PREP(ANA_SB_TX_HLVL_PROG, 0x7)); 862 regmap_update_bits(hdptx->regmap, 0x0418, ANA_SB_TX_LLVL_PROG, 863 FIELD_PREP(ANA_SB_TX_LLVL_PROG, 0x7)); 864 regmap_update_bits(hdptx->regmap, 0x044c, 865 SB_RX_RCAL_OPT_CODE | SB_RX_RTERM_CTRL, 866 FIELD_PREP(SB_RX_RCAL_OPT_CODE, 0x1) | 867 FIELD_PREP(SB_RX_RTERM_CTRL, 0x3)); 868 regmap_update_bits(hdptx->regmap, 0x0450, 869 SB_TG_SB_EN_DELAY_TIME | SB_TG_RXTERN_EN_DELAY_TIME, 870 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME, 0x2) | 871 FIELD_PREP(SB_TG_RXTERN_EN_DELAY_TIME, 0x2)); 872 regmap_update_bits(hdptx->regmap, 0x0454, 873 SB_READY_DELAY_TIME | SB_TG_OSC_EN_DELAY_TIME, 874 FIELD_PREP(SB_READY_DELAY_TIME, 0x2) | 875 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME, 0x2)); 876 regmap_update_bits(hdptx->regmap, 0x0458, 877 SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 878 FIELD_PREP(SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 0x2)); 879 regmap_update_bits(hdptx->regmap, 0x045c, 880 SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 881 FIELD_PREP(SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 0x4)); 882 regmap_update_bits(hdptx->regmap, 0x0460, 883 SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 884 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 0xa)); 885 regmap_update_bits(hdptx->regmap, 0x0468, SB_TG_CNT_RUN_NO_7_0, 886 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0, 0x3)); 887 regmap_update_bits(hdptx->regmap, 0x046c, 888 SB_EARC_SIG_DET_BYPASS | SB_AFC_TOL, 889 FIELD_PREP(SB_EARC_SIG_DET_BYPASS, 0x1) | 890 FIELD_PREP(SB_AFC_TOL, 0x3)); 891 regmap_update_bits(hdptx->regmap, 0x0470, SB_AFC_STB_NUM, 892 FIELD_PREP(SB_AFC_STB_NUM, 0x4)); 893 regmap_update_bits(hdptx->regmap, 0x0474, SB_TG_OSC_CNT_MIN, 894 FIELD_PREP(SB_TG_OSC_CNT_MIN, 0x67)); 895 regmap_update_bits(hdptx->regmap, 0x0478, SB_TG_OSC_CNT_MAX, 896 FIELD_PREP(SB_TG_OSC_CNT_MAX, 0x6a)); 897 regmap_update_bits(hdptx->regmap, 0x047c, SB_PWM_AFC_CTRL, 898 FIELD_PREP(SB_PWM_AFC_CTRL, 0x5)); 899 regmap_update_bits(hdptx->regmap, 0x0434, ANA_SB_DMRX_LPBK_DATA, 900 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA, 0x1)); 901 regmap_update_bits(hdptx->regmap, 0x0440, 902 ANA_SB_VREG_OUT_SEL | ANA_SB_VREG_REF_SEL, 903 FIELD_PREP(ANA_SB_VREG_OUT_SEL, 0x1) | 904 FIELD_PREP(ANA_SB_VREG_REF_SEL, 0x1)); 905 regmap_update_bits(hdptx->regmap, 0x043c, ANA_SB_VREG_GAIN_CTRL, 906 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL, 0x0)); 907 regmap_update_bits(hdptx->regmap, 0x0408, ANA_SB_RXTERM_OFFSP, 908 FIELD_PREP(ANA_SB_RXTERM_OFFSP, 0x3)); 909 regmap_update_bits(hdptx->regmap, 0x040c, ANA_SB_RXTERM_OFFSN, 910 FIELD_PREP(ANA_SB_RXTERM_OFFSN, 0x3)); 911 regmap_update_bits(hdptx->regmap, 0x047c, SB_RCAL_RSTN, 912 FIELD_PREP(SB_RCAL_RSTN, 0x1)); 913 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN, 914 FIELD_PREP(SB_AUX_EN, 0x1)); 915 regmap_update_bits(hdptx->regmap, 0x0480, SB_AUX_EN_IN, 916 FIELD_PREP(SB_AUX_EN_IN, 0x1)); 917 regmap_update_bits(hdptx->regmap, 0x040c, OVRD_SB_RX_RESCAL_DONE, 918 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE, 0x1)); 919 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_EN, 920 FIELD_PREP(OVRD_SB_EN, 0x1)); 921 regmap_update_bits(hdptx->regmap, 0x0408, OVRD_SB_RXTERM_EN, 922 FIELD_PREP(OVRD_SB_RXTERM_EN, 0x1)); 923 regmap_update_bits(hdptx->regmap, 0x043c, OVRD_SB_VREG_EN, 924 FIELD_PREP(OVRD_SB_VREG_EN, 0x1)); 925 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_AUX_EN, 926 FIELD_PREP(OVRD_SB_AUX_EN, 0x1)); 927 928 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN, 929 FIELD_PREP(BGR_EN, 0x1)); 930 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN, 931 FIELD_PREP(BIAS_EN, 0x1)); 932 udelay(10); 933 reset_deassert(&hdptx->init_reset); 934 udelay(1000); 935 reset_deassert(&hdptx->cmn_reset); 936 udelay(20); 937 938 regmap_update_bits(hdptx->regmap, 0x040c, SB_RX_RESCAL_DONE, 939 FIELD_PREP(SB_RX_RESCAL_DONE, 0x1)); 940 udelay(100); 941 regmap_update_bits(hdptx->regmap, 0x0410, SB_EN, 942 FIELD_PREP(SB_EN, 0x1)); 943 udelay(100); 944 regmap_update_bits(hdptx->regmap, 0x0408, SB_RXRERM_EN, 945 FIELD_PREP(SB_RXRERM_EN, 0x1)); 946 udelay(10); 947 regmap_update_bits(hdptx->regmap, 0x043c, SB_VREG_EN, 948 FIELD_PREP(SB_VREG_EN, 0x1)); 949 udelay(10); 950 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN, 951 FIELD_PREP(SB_AUX_EN, 0x1)); 952 udelay(100); 953 954 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 955 status, FIELD_GET(SB_RDY, status), 956 50, 1000); 957 if (ret) { 958 dev_err(hdptx->dev, "timeout waiting for sb_rdy\n"); 959 return ret; 960 } 961 962 return 0; 963 } 964 965 static void rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy *hdptx) 966 { 967 u32 lane; 968 969 reset_assert(&hdptx->lane_reset); 970 reset_assert(&hdptx->cmn_reset); 971 reset_assert(&hdptx->init_reset); 972 973 reset_assert(&hdptx->apb_reset); 974 udelay(10); 975 reset_deassert(&hdptx->apb_reset); 976 977 for (lane = 0; lane < 4; lane++) 978 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c04), 979 OVRD_LN_TX_DRV_EI_EN | LN_TX_DRV_EI_EN, 980 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN, 1) | 981 FIELD_PREP(LN_TX_DRV_EI_EN, 0)); 982 983 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN, 984 FIELD_PREP(PLL_EN, 0)); 985 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN, 986 FIELD_PREP(BIAS_EN, 0)); 987 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN, 988 FIELD_PREP(BGR_EN, 0)); 989 } 990 991 static int rockchip_hdptx_phy_power_on(struct phy *phy) 992 { 993 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 994 enum phy_mode mode = generic_phy_get_mode(phy); 995 u32 lane; 996 997 rockchip_hdptx_phy_reset(hdptx); 998 999 for (lane = 0; lane < 4; lane++) { 1000 u32 invert = hdptx->lane_polarity_invert[lane]; 1001 1002 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c78), 1003 LN_POLARITY_INV | LN_LANE_MODE, 1004 FIELD_PREP(LN_POLARITY_INV, invert) | 1005 FIELD_PREP(LN_LANE_MODE, 1)); 1006 } 1007 1008 if (mode == PHY_MODE_DP) { 1009 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, 1010 HDPTX_MODE_SEL, 1011 FIELD_PREP(HDPTX_MODE_SEL, 0x1)); 1012 1013 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL, 1014 FIELD_PREP(PROTOCOL_SEL, 0x0)); 1015 regmap_update_bits(hdptx->regmap, 0x0818, DATA_BUS_WIDTH, 1016 FIELD_PREP(DATA_BUS_WIDTH, 0x1)); 1017 regmap_update_bits(hdptx->regmap, 0x0818, BUS_WIDTH_SEL, 1018 FIELD_PREP(BUS_WIDTH_SEL, 0x0)); 1019 1020 rockchip_hdptx_phy_dp_pll_init(hdptx); 1021 rockchip_hdptx_phy_dp_aux_init(hdptx); 1022 } else { 1023 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, 1024 HDPTX_MODE_SEL, 1025 FIELD_PREP(HDPTX_MODE_SEL, 0x0)); 1026 1027 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL, 1028 FIELD_PREP(PROTOCOL_SEL, 0x1)); 1029 } 1030 1031 return 0; 1032 } 1033 1034 static int rockchip_hdptx_phy_power_off(struct phy *phy) 1035 { 1036 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 1037 1038 rockchip_hdptx_phy_reset(hdptx); 1039 1040 return 0; 1041 } 1042 1043 static const struct phy_ops rockchip_hdptx_phy_ops = { 1044 .set_mode = rockchip_hdptx_phy_set_mode, 1045 .configure = rockchip_hdptx_phy_configure, 1046 .power_on = rockchip_hdptx_phy_power_on, 1047 .power_off = rockchip_hdptx_phy_power_off, 1048 }; 1049 1050 static int rockchip_hdptx_phy_probe(struct udevice *dev) 1051 { 1052 struct rockchip_hdptx_phy *hdptx = dev_get_priv(dev); 1053 struct udevice *syscon; 1054 u32 prop[4]; 1055 int ret; 1056 1057 ret = regmap_init_mem(dev, &hdptx->regmap); 1058 if (ret) 1059 return ret; 1060 1061 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1062 &syscon); 1063 if (ret) 1064 return ret; 1065 1066 hdptx->grf = syscon_get_regmap(syscon); 1067 if (IS_ERR(hdptx->grf)) { 1068 ret = PTR_ERR(hdptx->grf); 1069 dev_err(dev, "unable to find regmap: %d\n", ret); 1070 return ret; 1071 } 1072 1073 hdptx->dev = dev; 1074 1075 ret = reset_get_by_name(dev, "apb", &hdptx->apb_reset); 1076 if (ret < 0) { 1077 dev_err(dev, "failed to get apb reset: %d\n", ret); 1078 return ret; 1079 } 1080 1081 ret = reset_get_by_name(dev, "init", &hdptx->init_reset); 1082 if (ret < 0) { 1083 dev_err(dev, "failed to get init reset: %d\n", ret); 1084 return ret; 1085 } 1086 1087 ret = reset_get_by_name(dev, "cmn", &hdptx->cmn_reset); 1088 if (ret < 0) { 1089 dev_err(dev, "failed to get cmn reset: %d\n", ret); 1090 return ret; 1091 } 1092 1093 ret = reset_get_by_name(dev, "lane", &hdptx->lane_reset); 1094 if (ret < 0) { 1095 dev_err(dev, "failed to get lane reset: %d\n", ret); 1096 return ret; 1097 } 1098 1099 ret = rockchip_hdptx_phy_parse_training_table(dev); 1100 if (ret) { 1101 dev_err(dev, "failed to parse training table: %d\n", ret); 1102 return ret; 1103 } 1104 1105 if (!dev_read_u32_array(dev, "lane-polarity-invert", prop, ARRAY_SIZE(prop))) { 1106 hdptx->lane_polarity_invert[0] = prop[0]; 1107 hdptx->lane_polarity_invert[1] = prop[1]; 1108 hdptx->lane_polarity_invert[2] = prop[2]; 1109 hdptx->lane_polarity_invert[3] = prop[3]; 1110 } 1111 1112 return 0; 1113 } 1114 1115 static const struct udevice_id rockchip_hdptx_phy_ids[] = { 1116 { .compatible = "rockchip,rk3588-hdptx-phy", }, 1117 {} 1118 }; 1119 1120 U_BOOT_DRIVER(rockchip_hdptx_phy) = { 1121 .name = "rockchip_hdptx_phy", 1122 .id = UCLASS_PHY, 1123 .ops = &rockchip_hdptx_phy_ops, 1124 .of_match = rockchip_hdptx_phy_ids, 1125 .probe = rockchip_hdptx_phy_probe, 1126 .priv_auto_alloc_size = sizeof(struct rockchip_hdptx_phy), 1127 }; 1128