1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip HDMI/DP Combo PHY with Samsung IP block 4 * 5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <generic-phy.h> 11 #include <reset.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <linux/bitfield.h> 16 #include <linux/iopoll.h> 17 #include <asm/arch/clock.h> 18 19 #define HDPTXPHY_GRF_CON0 0x0000 20 #define RO_REF_CLK_SEL GENMASK(11, 10) 21 #define LC_REF_CLK_SEL GENMASK(9, 8) 22 #define PLL_EN BIT(7) 23 #define BIAS_EN BIT(6) 24 #define BGR_EN BIT(5) 25 #define HDPTX_MODE_SEL BIT(0) 26 #define HDPTXPHY_GRF_STATUS0 0x0080 27 #define PLL_LOCK_DONE BIT(3) 28 #define PHY_CLK_RDY BIT(2) 29 #define PHY_RDY BIT(1) 30 #define SB_RDY BIT(0) 31 32 /* cmn_reg0008 */ 33 #define OVRD_LCPLL_EN BIT(7) 34 #define LCPLL_EN BIT(6) 35 36 /* cmn_reg003C */ 37 #define ANA_LCPLL_RESERVED7 BIT(7) 38 39 /* cmn_reg003D */ 40 #define OVRD_ROPLL_EN BIT(7) 41 #define ROPLL_EN BIT(6) 42 43 /* cmn_reg0046 */ 44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4) 45 #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0) 46 47 /* cmn_reg0047 */ 48 #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3) 49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0) 50 51 /* cmn_reg004E */ 52 #define ANA_ROPLL_PI_EN BIT(5) 53 54 /* cmn_reg0051 */ 55 #define ROPLL_PMS_MDIV GENMASK(7, 0) 56 57 /* cmn_reg0055 */ 58 #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0) 59 60 /* cmn_reg0059 */ 61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4) 62 #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0) 63 64 /* cmn_reg005A */ 65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4) 66 #define ROPLL_PMS_SDIV_HBR GENMASK(3, 0) 67 68 /* cmn_reg005B */ 69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4) 70 #define ROPLL_PMS_SDIV_HBR3 GENMASK(3, 0) 71 72 /* cmn_reg005D */ 73 #define OVRD_ROPLL_REF_CLK_SEL BIT(5) 74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3) 75 76 /* cmn_reg005E */ 77 #define ANA_ROPLL_SDM_EN BIT(6) 78 #define OVRD_ROPLL_SDM_RSTN BIT(5) 79 #define ROPLL_SDM_RSTN BIT(4) 80 #define ROPLL_SDC_FRACTIONAL_EN_RBR BIT(3) 81 #define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2) 82 #define ROPLL_SDC_FRACTIONAL_EN_HBR2 BIT(1) 83 #define ROPLL_SDC_FRACTIONAL_EN_HBR3 BIT(0) 84 85 /* cmn_reg005F */ 86 #define OVRD_ROPLL_SDC_RSTN BIT(5) 87 #define ROPLL_SDC_RSTN BIT(4) 88 89 /* cmn_reg0060 */ 90 #define ROPLL_SDM_DENOMINATOR GENMASK(7, 0) 91 92 /* cmn_reg0064 */ 93 #define ROPLL_SDM_NUMERATOR_SIGN_RBR BIT(3) 94 #define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2) 95 #define ROPLL_SDM_NUMERATOR_SIGN_HBR2 BIT(1) 96 #define ROPLL_SDM_NUMERATOR_SIGN_HBR3 BIT(0) 97 98 /* cmn_reg0065 */ 99 #define ROPLL_SDM_NUMERATOR GENMASK(7, 0) 100 101 /* cmn_reg0069 */ 102 #define ROPLL_SDC_N_RBR GENMASK(2, 0) 103 104 /* cmn_reg006A */ 105 #define ROPLL_SDC_N_HBR GENMASK(5, 3) 106 #define ROPLL_SDC_N_HBR2 GENMASK(2, 0) 107 108 /* cmn_reg006B */ 109 #define ROPLL_SDC_N_HBR3 GENMASK(3, 1) 110 111 /* cmn_reg006C */ 112 #define ROPLL_SDC_NUMERATOR GENMASK(5, 0) 113 114 /* cmn_reg0070 */ 115 #define ROPLL_SDC_DENOMINATOR GENMASK(5, 0) 116 117 /* cmn_reg0074 */ 118 #define OVRD_ROPLL_SDC_NDIV_RSTN BIT(3) 119 #define ROPLL_SDC_NDIV_RSTN BIT(2) 120 #define OVRD_ROPLL_SSC_EN BIT(1) 121 #define ROPLL_SSC_EN BIT(0) 122 123 /* cmn_reg0075 */ 124 #define ANA_ROPLL_SSC_FM_DEVIATION GENMASK(5, 0) 125 126 /* cmn_reg0076 */ 127 #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2) 128 129 /* cmn_reg0077 */ 130 #define ANA_ROPLL_SSC_CLK_DIV_SEL GENMASK(6, 3) 131 132 /* cmn_reg0081 */ 133 #define ANA_PLL_CD_TX_SER_RATE_SEL BIT(3) 134 #define ANA_PLL_CD_HSCLK_WEST_EN BIT(1) 135 #define ANA_PLL_CD_HSCLK_EAST_EN BIT(0) 136 137 /* cmn_reg0082 */ 138 #define ANA_PLL_CD_VREG_GAIN_CTRL GENMASK(3, 0) 139 140 /* cmn_reg0083 */ 141 #define ANA_PLL_CD_VREG_ICTRL GENMASK(6, 5) 142 143 /* cmn_reg0084 */ 144 #define PLL_LCRO_CLK_SEL BIT(5) 145 146 /* cmn_reg0085 */ 147 #define ANA_PLL_SYNC_LOSS_DET_MODE GENMASK(1, 0) 148 149 /* cmn_reg0087 */ 150 #define ANA_PLL_TX_HS_CLK_EN BIT(2) 151 152 /* cmn_reg0095 */ 153 #define DP_TX_LINK_BW GENMASK(1, 0) 154 155 /* cmn_reg0097 */ 156 #define DIG_CLK_SEL BIT(1) 157 158 /* cmn_reg0099 */ 159 #define SSC_EN GENMASK(7, 6) 160 #define CMN_ROPLL_ALONE_MODE BIT(2) 161 162 /* cmn_reg009A */ 163 #define HS_SPEED_SEL BIT(0) 164 165 /* cmn_reg009B */ 166 #define LS_SPEED_SEL BIT(4) 167 168 /* sb_reg0102 */ 169 #define OVRD_SB_RXTERM_EN BIT(5) 170 #define SB_RXRERM_EN BIT(4) 171 #define ANA_SB_RXTERM_OFFSP GENMASK(3, 0) 172 173 /* sb_reg0103 */ 174 #define ANA_SB_RXTERM_OFFSN GENMASK(6, 3) 175 #define OVRD_SB_RX_RESCAL_DONE BIT(1) 176 #define SB_RX_RESCAL_DONE BIT(0) 177 178 /* sb_reg0104 */ 179 #define OVRD_SB_EN BIT(5) 180 #define SB_EN BIT(4) 181 #define OVRD_SB_AUX_EN BIT(1) 182 #define SB_AUX_EN BIT(0) 183 184 /* sb_reg010D */ 185 #define ANA_SB_DMRX_LPBK_DATA BIT(4) 186 187 /* sb_reg010F */ 188 #define OVRD_SB_VREG_EN BIT(7) 189 #define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0) 190 191 /* sb_reg0110 */ 192 #define ANA_SB_VREG_OUT_SEL BIT(1) 193 #define ANA_SB_VREG_REF_SEL BIT(0) 194 195 /* sb_reg0113 */ 196 #define SB_VREG_EN BIT(6) 197 #define SB_RX_RCAL_OPT_CODE GENMASK(5, 4) 198 #define SB_RX_RTERM_CTRL GENMASK(3, 0) 199 200 /* sb_reg0114 */ 201 #define SB_TG_SB_EN_DELAY_TIME GENMASK(5, 3) 202 #define SB_TG_RXTERN_EN_DELAY_TIME GENMASK(2, 0) 203 204 /* sb_reg0115 */ 205 #define SB_READY_DELAY_TIME GENMASK(5, 3) 206 #define SB_TG_OSC_EN_DELAY_TIME GENMASK(2, 0) 207 208 /* sb_reg0116 */ 209 #define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4) 210 211 /* sb_reg0117 */ 212 #define SB_TG_PLL_CD_VREG_FAST_PULSE_TIME GENMASK(3, 0) 213 214 /* sb_reg0118 */ 215 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT GENMASK(7, 0) 216 217 /* sb_reg011A */ 218 #define SB_TG_CNT_RUN_NO_7_0 GENMASK(7, 0) 219 220 /* sb_reg011B */ 221 #define SB_EARC_SIG_DET_BYPASS BIT(4) 222 #define SB_AFC_TOL GENMASK(3, 0) 223 224 /* sb_reg011C */ 225 #define SB_AFC_STB_NUM GENMASK(3, 0) 226 227 /* sb_reg011D */ 228 #define SB_TG_OSC_CNT_MIN GENMASK(7, 0) 229 230 /* sb_reg011E */ 231 #define SB_TG_OSC_CNT_MAX GENMASK(7, 0) 232 233 /* sb_reg011F */ 234 #define SB_PWM_AFC_CTRL GENMASK(7, 2) 235 #define SB_RCAL_RSTN BIT(1) 236 237 /* sb_reg0120 */ 238 #define SB_AUX_EN_IN BIT(7) 239 240 /* sb_reg0123 */ 241 #define OVRD_SB_READY BIT(5) 242 #define SB_READY BIT(4) 243 244 /* lntop_reg0200 */ 245 #define PROTOCOL_SEL BIT(2) 246 247 /* lntop_reg0206 */ 248 #define DATA_BUS_WIDTH GENMASK(2, 1) 249 #define BUS_WIDTH_SEL BIT(0) 250 251 /* lntop_reg0207 */ 252 #define LANE_EN GENMASK(3, 0) 253 254 /* lane_reg0303 */ 255 #define OVRD_LN_TX_DRV_LVL_CTRL BIT(5) 256 #define LN_TX_DRV_LVL_CTRL GENMASK(4, 0) 257 258 /* lane_reg0304 */ 259 #define OVRD_LN_TX_DRV_POST_LVL_CTRL BIT(4) 260 #define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0) 261 262 /* lane_reg0305 */ 263 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL BIT(6) 264 #define LN_TX_DRV_PRE_LVL_CTRL GENMASK(5, 2) 265 266 /* lane_reg030A */ 267 #define LN_ANA_TX_JEQ_EN BIT(4) 268 #define LN_TX_JEQ_EVEN_CTRL_RBR GENMASK(3, 0) 269 270 /* lane_reg030B */ 271 #define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4) 272 #define LN_TX_JEQ_EVEN_CTRL_HBR2 GENMASK(3, 0) 273 274 /* lane_reg030C */ 275 #define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4) 276 #define LN_TX_JEQ_ODD_CTRL_RBR GENMASK(3, 0) 277 278 /* lane_reg030D */ 279 #define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4) 280 #define LN_TX_JEQ_ODD_CTRL_HBR2 GENMASK(3, 0) 281 282 /* lane_reg030E */ 283 #define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4) 284 285 /* lane_reg0307 */ 286 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL BIT(6) 287 #define LN_ANA_TX_DRV_ACCDRV_CTRL GENMASK(5, 3) 288 289 /* lane_reg0310 */ 290 #define LN_ANA_TX_SYNC_LOSS_DET_MODE GENMASK(1, 0) 291 292 /* lane_reg0311 */ 293 #define LN_TX_SER_40BIT_EN_RBR BIT(3) 294 #define LN_TX_SER_40BIT_EN_HBR BIT(2) 295 #define LN_TX_SER_40BIT_EN_HBR2 BIT(1) 296 #define LN_TX_SER_40BIT_EN_HBR3 BIT(0) 297 298 /* lane_reg0316 */ 299 #define LN_ANA_TX_SER_VREG_GAIN_CTRL GENMASK(3, 0) 300 301 /* lane_reg031B */ 302 #define LN_ANA_TX_RESERVED GENMASK(7, 0) 303 304 /* lane_reg031E */ 305 #define LN_POLARITY_INV BIT(2) 306 307 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset)) 308 309 struct rockchip_hdptx_phy { 310 struct udevice *dev; 311 void __iomem *base; 312 struct regmap *grf; 313 314 struct reset_ctl apb_reset; 315 struct reset_ctl cmn_reset; 316 struct reset_ctl init_reset; 317 struct reset_ctl lane_reset; 318 u32 lane_polarity_invert[4]; 319 }; 320 321 enum { 322 DP_BW_RBR, 323 DP_BW_HBR, 324 DP_BW_HBR2, 325 DP_BW_HBR3, 326 }; 327 328 static struct { 329 u8 tx_amp; 330 u8 tx_de_emp; 331 u8 tx_pre_emp; 332 } training_table[4][4] = { 333 /* voltage swing 0, pre-emphasis 0->3 */ 334 { 335 { .tx_amp = 0x3, .tx_de_emp = 0x1, .tx_pre_emp = 0x1 }, 336 { .tx_amp = 0x9, .tx_de_emp = 0x7, .tx_pre_emp = 0x0 }, 337 { .tx_amp = 0xc, .tx_de_emp = 0xa, .tx_pre_emp = 0x0 }, 338 { .tx_amp = 0xd, .tx_de_emp = 0xc, .tx_pre_emp = 0x0 } 339 }, 340 341 /* voltage swing 1, pre-emphasis 0->2 */ 342 { 343 { .tx_amp = 0x6, .tx_de_emp = 0x1, .tx_pre_emp = 0x1 }, 344 { .tx_amp = 0xc, .tx_de_emp = 0x7, .tx_pre_emp = 0x0 }, 345 { .tx_amp = 0xd, .tx_de_emp = 0x9, .tx_pre_emp = 0x0 }, 346 }, 347 348 /* voltage swing 2, pre-emphasis 0->1 */ 349 { 350 { .tx_amp = 0x9, .tx_de_emp = 0x1, .tx_pre_emp = 0x1 }, 351 { .tx_amp = 0xd, .tx_de_emp = 0x6, .tx_pre_emp = 0x0 }, 352 }, 353 354 /* voltage swing 3, pre-emphasis 0 */ 355 { 356 { .tx_amp = 0xd, .tx_de_emp = 0x1, .tx_pre_emp = 0x1 }, 357 } 358 }; 359 360 static inline void phy_write(struct rockchip_hdptx_phy *hdptx, uint reg, 361 uint val) 362 { 363 writel(val, hdptx->base + reg); 364 } 365 366 static inline uint phy_read(struct rockchip_hdptx_phy *hdptx, uint reg) 367 { 368 return readl(hdptx->base + reg); 369 } 370 371 static void phy_update_bits(struct rockchip_hdptx_phy *hdptx, uint reg, 372 uint mask, uint val) 373 { 374 uint orig, tmp; 375 376 orig = phy_read(hdptx, reg); 377 tmp = orig & ~mask; 378 tmp |= val & mask; 379 phy_write(hdptx, reg, tmp); 380 } 381 382 static void grf_write(struct rockchip_hdptx_phy *hdptx, uint reg, 383 uint mask, uint val) 384 { 385 regmap_write(hdptx->grf, reg, (mask << 16) | (val & mask)); 386 } 387 388 static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, 389 int submode) 390 { 391 return 0; 392 } 393 394 static int rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy *hdptx, 395 struct phy_configure_opts_dp *dp) 396 { 397 int i; 398 399 if (dp->set_rate) { 400 switch (dp->link_rate) { 401 case 1620: 402 case 2700: 403 case 5400: 404 break; 405 default: 406 return -EINVAL; 407 } 408 } 409 410 switch (dp->lanes) { 411 case 1: 412 case 2: 413 case 4: 414 break; 415 default: 416 return -EINVAL; 417 } 418 419 if (dp->set_voltages) { 420 for (i = 0; i < dp->lanes; i++) { 421 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 422 return -EINVAL; 423 424 if (dp->voltage[i] + dp->pre[i] > 3) 425 return -EINVAL; 426 } 427 } 428 429 return 0; 430 } 431 432 static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, 433 struct phy_configure_opts_dp *dp, 434 u8 lane) 435 { 436 u32 val; 437 438 phy_update_bits(hdptx, LANE_REG(lane, 0x0c28), LN_ANA_TX_JEQ_EN, 439 FIELD_PREP(LN_ANA_TX_JEQ_EN, 0x1)); 440 441 switch (dp->link_rate) { 442 case 1620: 443 phy_update_bits(hdptx, LANE_REG(lane, 0x0c28), 444 LN_TX_JEQ_EVEN_CTRL_RBR, 445 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR, 0x7)); 446 phy_update_bits(hdptx, LANE_REG(lane, 0x0c30), 447 LN_TX_JEQ_ODD_CTRL_RBR, 448 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR, 0x7)); 449 phy_update_bits(hdptx, LANE_REG(lane, 0x0c44), 450 LN_TX_SER_40BIT_EN_RBR, 451 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1)); 452 break; 453 case 2700: 454 phy_update_bits(hdptx, LANE_REG(lane, 0x0c2c), 455 LN_TX_JEQ_EVEN_CTRL_HBR, 456 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR, 0x7)); 457 phy_update_bits(hdptx, LANE_REG(lane, 0x0c34), 458 LN_TX_JEQ_ODD_CTRL_HBR, 459 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, 0x7)); 460 phy_update_bits(hdptx, LANE_REG(lane, 0x0c44), 461 LN_TX_SER_40BIT_EN_HBR, 462 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1)); 463 break; 464 case 5400: 465 phy_update_bits(hdptx, LANE_REG(lane, 0x0c2c), 466 LN_TX_JEQ_EVEN_CTRL_HBR2, 467 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, 0x7)); 468 phy_update_bits(hdptx, LANE_REG(lane, 0x0c34), 469 LN_TX_JEQ_ODD_CTRL_HBR2, 470 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, 0x7)); 471 phy_update_bits(hdptx, LANE_REG(lane, 0x0c44), 472 LN_TX_SER_40BIT_EN_HBR2, 473 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1)); 474 break; 475 } 476 477 val = training_table[dp->voltage[lane]][dp->pre[lane]].tx_amp; 478 phy_update_bits(hdptx, LANE_REG(lane, 0x0c0c), 479 OVRD_LN_TX_DRV_LVL_CTRL | LN_TX_DRV_LVL_CTRL, 480 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL, 0x1) | 481 FIELD_PREP(LN_TX_DRV_LVL_CTRL, val)); 482 483 val = training_table[dp->voltage[lane]][dp->pre[lane]].tx_de_emp; 484 phy_update_bits(hdptx, LANE_REG(lane, 0x0c10), 485 OVRD_LN_TX_DRV_POST_LVL_CTRL | LN_TX_DRV_POST_LVL_CTRL, 486 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL, 0x1) | 487 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL, val)); 488 489 val = training_table[dp->voltage[lane]][dp->pre[lane]].tx_pre_emp; 490 phy_update_bits(hdptx, LANE_REG(lane, 0x0c14), 491 OVRD_LN_TX_DRV_PRE_LVL_CTRL | LN_TX_DRV_PRE_LVL_CTRL, 492 FIELD_PREP(OVRD_LN_TX_DRV_PRE_LVL_CTRL, 0x1) | 493 FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL, val)); 494 495 phy_update_bits(hdptx, LANE_REG(lane, 0x0c1c), 496 LN_ANA_TX_DRV_ACCDRV_POL_SEL | LN_ANA_TX_DRV_ACCDRV_CTRL, 497 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL, 0x1) | 498 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL, 0x4)); 499 phy_update_bits(hdptx, LANE_REG(lane, 0x0c6c), LN_ANA_TX_RESERVED, 500 FIELD_PREP(LN_ANA_TX_RESERVED, 0x1)); 501 phy_update_bits(hdptx, LANE_REG(lane, 0x0c58), 502 LN_ANA_TX_SER_VREG_GAIN_CTRL, 503 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL, 0x2)); 504 phy_update_bits(hdptx, LANE_REG(lane, 0x0c40), 505 LN_ANA_TX_SYNC_LOSS_DET_MODE, 506 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE, 0x3)); 507 } 508 509 static int rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy *hdptx, 510 struct phy_configure_opts_dp *dp) 511 { 512 u8 lane; 513 514 for (lane = 0; lane < dp->lanes; lane++) 515 rockchip_hdptx_phy_set_voltage(hdptx, dp, lane); 516 517 return 0; 518 } 519 520 static int rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy *hdptx, 521 struct phy_configure_opts_dp *dp) 522 { 523 u32 bw, status; 524 int ret; 525 526 reset_assert(&hdptx->lane_reset); 527 udelay(10); 528 reset_assert(&hdptx->cmn_reset); 529 udelay(10); 530 grf_write(hdptx, HDPTXPHY_GRF_CON0, PLL_EN, FIELD_PREP(PLL_EN, 0x0)); 531 udelay(10); 532 phy_update_bits(hdptx, 0x081c, LANE_EN, FIELD_PREP(LANE_EN, 0x0)); 533 534 switch (dp->link_rate) { 535 case 1620: 536 bw = DP_BW_RBR; 537 break; 538 case 2700: 539 bw = DP_BW_HBR; 540 break; 541 case 5400: 542 bw = DP_BW_HBR2; 543 break; 544 default: 545 return -EINVAL; 546 } 547 548 phy_update_bits(hdptx, 0x0254, DP_TX_LINK_BW, 549 FIELD_PREP(DP_TX_LINK_BW, bw)); 550 551 if (dp->ssc) { 552 phy_update_bits(hdptx, 0x01d0, OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, 553 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) | 554 FIELD_PREP(ROPLL_SSC_EN, 0x1)); 555 phy_update_bits(hdptx, 0x01d4, ANA_ROPLL_SSC_FM_DEVIATION, 556 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0xe)); 557 phy_update_bits(hdptx, 0x01d8, ANA_ROPLL_SSC_FM_FREQ, 558 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0x1a)); 559 phy_update_bits(hdptx, 0x0264, SSC_EN, FIELD_PREP(SSC_EN, 0x2)); 560 } else { 561 phy_update_bits(hdptx, 0x01d0, OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, 562 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) | 563 FIELD_PREP(ROPLL_SSC_EN, 0x0)); 564 phy_update_bits(hdptx, 0x01d4, ANA_ROPLL_SSC_FM_DEVIATION, 565 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0x20)); 566 phy_update_bits(hdptx, 0x01d8, ANA_ROPLL_SSC_FM_FREQ, 567 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0xc)); 568 phy_update_bits(hdptx, 0x0264, SSC_EN, FIELD_PREP(SSC_EN, 0x0)); 569 } 570 571 grf_write(hdptx, HDPTXPHY_GRF_CON0, PLL_EN, FIELD_PREP(PLL_EN, 0x1)); 572 udelay(10); 573 reset_deassert(&hdptx->cmn_reset); 574 udelay(10); 575 576 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 577 status, FIELD_GET(PLL_LOCK_DONE, status), 578 50, 1000); 579 if (ret) { 580 dev_err(hdptx->dev, "timeout waiting for pll_lock_done\n"); 581 return ret; 582 } 583 584 phy_update_bits(hdptx, 0x081c, LANE_EN, 585 FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0))); 586 587 reset_deassert(&hdptx->lane_reset); 588 udelay(10); 589 590 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 591 status, FIELD_GET(PHY_RDY, status), 592 50, 1000); 593 if (ret) { 594 dev_err(hdptx->dev, "timeout waiting for phy_rdy\n"); 595 return ret; 596 } 597 598 return 0; 599 } 600 601 static int rockchip_hdptx_phy_configure(struct phy *phy, 602 union phy_configure_opts *opts) 603 { 604 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 605 enum phy_mode mode = generic_phy_get_mode(phy); 606 int ret; 607 608 if (mode != PHY_MODE_DP) 609 return -EINVAL; 610 611 ret = rockchip_hdptx_phy_verify_config(hdptx, &opts->dp); 612 if (ret) { 613 dev_err(hdptx->dev, "invalid params for phy configure\n"); 614 return ret; 615 } 616 617 if (opts->dp.set_rate) { 618 ret = rockchip_hdptx_phy_set_rate(hdptx, &opts->dp); 619 if (ret) { 620 dev_err(hdptx->dev, "failed to set rate: %d\n", ret); 621 return ret; 622 } 623 } 624 625 if (opts->dp.set_voltages) { 626 ret = rockchip_hdptx_phy_set_voltages(hdptx, &opts->dp); 627 if (ret) { 628 dev_err(hdptx->dev, "failed to set voltages: %d\n", 629 ret); 630 return ret; 631 } 632 } 633 634 return 0; 635 } 636 637 static void rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy *hdptx) 638 { 639 phy_update_bits(hdptx, 0x0020, OVRD_LCPLL_EN | LCPLL_EN, 640 FIELD_PREP(OVRD_LCPLL_EN, 0x1) | 641 FIELD_PREP(LCPLL_EN, 0x0)); 642 phy_update_bits(hdptx, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN, 643 FIELD_PREP(OVRD_ROPLL_EN, 0x1) | 644 FIELD_PREP(ROPLL_EN, 0x1)); 645 phy_update_bits(hdptx, 0x0138, ANA_ROPLL_PI_EN, 646 FIELD_PREP(ANA_ROPLL_PI_EN, 0x1)); 647 648 phy_write(hdptx, 0x0144, FIELD_PREP(ROPLL_PMS_MDIV, 0x87)); 649 phy_write(hdptx, 0x0148, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); 650 phy_write(hdptx, 0x014c, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); 651 652 phy_write(hdptx, 0x0154, FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x87)); 653 phy_write(hdptx, 0x0158, FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71)); 654 phy_write(hdptx, 0x015c, FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71)); 655 656 phy_write(hdptx, 0x0164, FIELD_PREP(ANA_ROPLL_PMS_PDIV, 0x1) | 657 FIELD_PREP(ANA_ROPLL_PMS_REFDIV, 0x1)); 658 659 phy_write(hdptx, 0x0168, FIELD_PREP(ROPLL_PMS_SDIV_RBR, 0x3) | 660 FIELD_PREP(ROPLL_PMS_SDIV_HBR, 0x1)); 661 phy_update_bits(hdptx, 0x016c, ROPLL_PMS_SDIV_HBR2, 662 FIELD_PREP(ROPLL_PMS_SDIV_HBR2, 0x0)); 663 664 phy_update_bits(hdptx, 0x0178, ANA_ROPLL_SDM_EN, 665 FIELD_PREP(ANA_ROPLL_SDM_EN, 0x1)); 666 phy_update_bits(hdptx, 0x0178, OVRD_ROPLL_SDM_RSTN | ROPLL_SDM_RSTN, 667 FIELD_PREP(OVRD_ROPLL_SDM_RSTN, 0x1) | 668 FIELD_PREP(ROPLL_SDM_RSTN, 0x1)); 669 phy_update_bits(hdptx, 0x0178, ROPLL_SDC_FRACTIONAL_EN_RBR, 670 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_RBR, 0x1)); 671 phy_update_bits(hdptx, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR, 672 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR, 0x1)); 673 phy_update_bits(hdptx, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR2, 674 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR2, 0x1)); 675 phy_update_bits(hdptx, 0x017c, OVRD_ROPLL_SDC_RSTN | ROPLL_SDC_RSTN, 676 FIELD_PREP(OVRD_ROPLL_SDC_RSTN, 0x1) | 677 FIELD_PREP(ROPLL_SDC_RSTN, 0x1)); 678 679 phy_write(hdptx, 0x0180, FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x21)); 680 phy_write(hdptx, 0x0184, FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27)); 681 phy_write(hdptx, 0x0188, FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27)); 682 683 phy_update_bits(hdptx, 0x0190, ROPLL_SDM_NUMERATOR_SIGN_RBR | 684 ROPLL_SDM_NUMERATOR_SIGN_HBR | 685 ROPLL_SDM_NUMERATOR_SIGN_HBR2, 686 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_RBR, 0x0) | 687 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR, 0x1) | 688 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR2, 0x1)); 689 690 phy_write(hdptx, 0x0194, FIELD_PREP(ROPLL_SDM_NUMERATOR, 0x0)); 691 phy_write(hdptx, 0x0198, FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd)); 692 phy_write(hdptx, 0x019c, FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd)); 693 694 phy_update_bits(hdptx, 0x01a4, ROPLL_SDC_N_RBR, 695 FIELD_PREP(ROPLL_SDC_N_RBR, 0x2)); 696 phy_update_bits(hdptx, 0x01a8, ROPLL_SDC_N_HBR | ROPLL_SDC_N_HBR2, 697 FIELD_PREP(ROPLL_SDC_N_HBR, 0x1) | 698 FIELD_PREP(ROPLL_SDC_N_HBR2, 0x1)); 699 700 phy_write(hdptx, 0x01b0, FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x3)); 701 phy_write(hdptx, 0x01b4, FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7)); 702 phy_write(hdptx, 0x01b8, FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7)); 703 704 phy_write(hdptx, 0x01c0, FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x8)); 705 phy_write(hdptx, 0x01c4, FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18)); 706 phy_write(hdptx, 0x01c8, FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18)); 707 708 phy_update_bits(hdptx, 0x01d0, OVRD_ROPLL_SDC_NDIV_RSTN | 709 ROPLL_SDC_NDIV_RSTN, 710 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN, 0x1) | 711 FIELD_PREP(ROPLL_SDC_NDIV_RSTN, 0x1)); 712 phy_update_bits(hdptx, 0x01dc, ANA_ROPLL_SSC_CLK_DIV_SEL, 713 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL, 0x1)); 714 715 phy_update_bits(hdptx, 0x0118, ROPLL_ANA_CPP_CTRL_COARSE | 716 ROPLL_ANA_CPP_CTRL_FINE, 717 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE, 0xe) | 718 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE, 0xe)); 719 phy_update_bits(hdptx, 0x011c, ROPLL_ANA_LPF_C_SEL_COARSE | 720 ROPLL_ANA_LPF_C_SEL_FINE, 721 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE, 0x4) | 722 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE, 0x4)); 723 724 phy_update_bits(hdptx, 0x0204, ANA_PLL_CD_TX_SER_RATE_SEL, 725 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL, 0x0)); 726 727 phy_update_bits(hdptx, 0x025c, DIG_CLK_SEL, 728 FIELD_PREP(DIG_CLK_SEL, 0x1)); 729 phy_update_bits(hdptx, 0x021c, ANA_PLL_TX_HS_CLK_EN, 730 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN, 0x1)); 731 phy_update_bits(hdptx, 0x0204, ANA_PLL_CD_HSCLK_EAST_EN | 732 ANA_PLL_CD_HSCLK_WEST_EN, 733 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN, 0x1) | 734 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN, 0x0)); 735 phy_update_bits(hdptx, 0x0264, CMN_ROPLL_ALONE_MODE, 736 FIELD_PREP(CMN_ROPLL_ALONE_MODE, 0x1)); 737 phy_update_bits(hdptx, 0x0208, ANA_PLL_CD_VREG_GAIN_CTRL, 738 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL, 0x4)); 739 phy_update_bits(hdptx, 0x00f0, ANA_LCPLL_RESERVED7, 740 FIELD_PREP(ANA_LCPLL_RESERVED7, 0x1)); 741 phy_update_bits(hdptx, 0x020c, ANA_PLL_CD_VREG_ICTRL, 742 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL, 0x1)); 743 phy_update_bits(hdptx, 0x0214, ANA_PLL_SYNC_LOSS_DET_MODE, 744 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE, 0x3)); 745 phy_update_bits(hdptx, 0x0210, PLL_LCRO_CLK_SEL, 746 FIELD_PREP(PLL_LCRO_CLK_SEL, 0x1)); 747 phy_update_bits(hdptx, 0x0268, HS_SPEED_SEL, 748 FIELD_PREP(HS_SPEED_SEL, 0x1)); 749 phy_update_bits(hdptx, 0x026c, LS_SPEED_SEL, 750 FIELD_PREP(LS_SPEED_SEL, 0x1)); 751 } 752 753 static int rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy *hdptx) 754 { 755 u32 status; 756 int ret; 757 758 phy_update_bits(hdptx, 0x044c, SB_RX_RCAL_OPT_CODE | SB_RX_RTERM_CTRL, 759 FIELD_PREP(SB_RX_RCAL_OPT_CODE, 0x1) | 760 FIELD_PREP(SB_RX_RTERM_CTRL, 0x3)); 761 phy_update_bits(hdptx, 0x0450, SB_TG_SB_EN_DELAY_TIME | 762 SB_TG_RXTERN_EN_DELAY_TIME, 763 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME, 0x2) | 764 FIELD_PREP(SB_TG_RXTERN_EN_DELAY_TIME, 0x2)); 765 phy_update_bits(hdptx, 0x0454, SB_READY_DELAY_TIME | 766 SB_TG_OSC_EN_DELAY_TIME, 767 FIELD_PREP(SB_READY_DELAY_TIME, 0x2) | 768 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME, 0x2)); 769 phy_update_bits(hdptx, 0x0458, SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 770 FIELD_PREP(SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 0x2)); 771 phy_update_bits(hdptx, 0x045c, SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 772 FIELD_PREP(SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 0x4)); 773 phy_update_bits(hdptx, 0x0460, SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 774 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 0xa)); 775 phy_update_bits(hdptx, 0x0468, SB_TG_CNT_RUN_NO_7_0, 776 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0, 0x3)); 777 phy_update_bits(hdptx, 0x046c, SB_EARC_SIG_DET_BYPASS | SB_AFC_TOL, 778 FIELD_PREP(SB_EARC_SIG_DET_BYPASS, 0x1) | 779 FIELD_PREP(SB_AFC_TOL, 0x3)); 780 phy_update_bits(hdptx, 0x0470, SB_AFC_STB_NUM, 781 FIELD_PREP(SB_AFC_STB_NUM, 0x4)); 782 phy_update_bits(hdptx, 0x0474, SB_TG_OSC_CNT_MIN, 783 FIELD_PREP(SB_TG_OSC_CNT_MIN, 0x67)); 784 phy_update_bits(hdptx, 0x0478, SB_TG_OSC_CNT_MAX, 785 FIELD_PREP(SB_TG_OSC_CNT_MAX, 0x6a)); 786 phy_update_bits(hdptx, 0x047c, SB_PWM_AFC_CTRL, 787 FIELD_PREP(SB_PWM_AFC_CTRL, 0x5)); 788 phy_update_bits(hdptx, 0x0434, ANA_SB_DMRX_LPBK_DATA, 789 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA, 0x1)); 790 phy_update_bits(hdptx, 0x0440, ANA_SB_VREG_OUT_SEL | 791 ANA_SB_VREG_REF_SEL, 792 FIELD_PREP(ANA_SB_VREG_OUT_SEL, 0x1) | 793 FIELD_PREP(ANA_SB_VREG_REF_SEL, 0x1)); 794 phy_update_bits(hdptx, 0x043c, ANA_SB_VREG_GAIN_CTRL, 795 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL, 0x0)); 796 phy_update_bits(hdptx, 0x0408, ANA_SB_RXTERM_OFFSP, 797 FIELD_PREP(ANA_SB_RXTERM_OFFSP, 0x3)); 798 phy_update_bits(hdptx, 0x040c, ANA_SB_RXTERM_OFFSN, 799 FIELD_PREP(ANA_SB_RXTERM_OFFSN, 0x3)); 800 phy_update_bits(hdptx, 0x047c, SB_RCAL_RSTN, 801 FIELD_PREP(SB_RCAL_RSTN, 0x1)); 802 phy_update_bits(hdptx, 0x0410, SB_AUX_EN, 803 FIELD_PREP(SB_AUX_EN, 0x1)); 804 phy_update_bits(hdptx, 0x0480, SB_AUX_EN_IN, 805 FIELD_PREP(SB_AUX_EN_IN, 0x1)); 806 phy_update_bits(hdptx, 0x040c, OVRD_SB_RX_RESCAL_DONE, 807 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE, 0x1)); 808 phy_update_bits(hdptx, 0x0410, OVRD_SB_EN, 809 FIELD_PREP(OVRD_SB_EN, 0x1)); 810 phy_update_bits(hdptx, 0x0408, OVRD_SB_RXTERM_EN, 811 FIELD_PREP(OVRD_SB_RXTERM_EN, 0x1)); 812 phy_update_bits(hdptx, 0x043c, OVRD_SB_VREG_EN, 813 FIELD_PREP(OVRD_SB_VREG_EN, 0x1)); 814 phy_update_bits(hdptx, 0x0410, OVRD_SB_AUX_EN, 815 FIELD_PREP(OVRD_SB_AUX_EN, 0x1)); 816 817 grf_write(hdptx, HDPTXPHY_GRF_CON0, BGR_EN, FIELD_PREP(BGR_EN, 0x1)); 818 grf_write(hdptx, HDPTXPHY_GRF_CON0, BIAS_EN, FIELD_PREP(BIAS_EN, 0x1)); 819 udelay(10); 820 reset_deassert(&hdptx->init_reset); 821 udelay(1000); 822 reset_deassert(&hdptx->cmn_reset); 823 udelay(20); 824 825 phy_update_bits(hdptx, 0x040c, SB_RX_RESCAL_DONE, 826 FIELD_PREP(SB_RX_RESCAL_DONE, 0x1)); 827 udelay(100); 828 phy_update_bits(hdptx, 0x0410, SB_EN, FIELD_PREP(SB_EN, 0x1)); 829 udelay(100); 830 phy_update_bits(hdptx, 0x0408, SB_RXRERM_EN, 831 FIELD_PREP(SB_RXRERM_EN, 0x1)); 832 udelay(10); 833 phy_update_bits(hdptx, 0x043c, SB_VREG_EN, FIELD_PREP(SB_VREG_EN, 0x1)); 834 udelay(10); 835 phy_update_bits(hdptx, 0x0410, SB_AUX_EN, FIELD_PREP(SB_AUX_EN, 0x1)); 836 udelay(100); 837 838 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, 839 status, FIELD_GET(SB_RDY, status), 840 50, 1000); 841 if (ret) { 842 dev_err(hdptx->dev, "timeout waiting for sb_rdy\n"); 843 return ret; 844 } 845 846 return 0; 847 } 848 849 static void rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy *hdptx) 850 { 851 reset_assert(&hdptx->lane_reset); 852 reset_assert(&hdptx->cmn_reset); 853 reset_assert(&hdptx->init_reset); 854 855 grf_write(hdptx, HDPTXPHY_GRF_CON0, PLL_EN, FIELD_PREP(PLL_EN, 0)); 856 grf_write(hdptx, HDPTXPHY_GRF_CON0, BIAS_EN, FIELD_PREP(BIAS_EN, 0)); 857 grf_write(hdptx, HDPTXPHY_GRF_CON0, BGR_EN, FIELD_PREP(BGR_EN, 0)); 858 } 859 860 static int rockchip_hdptx_phy_power_on(struct phy *phy) 861 { 862 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 863 enum phy_mode mode = generic_phy_get_mode(phy); 864 u32 lane; 865 866 rockchip_hdptx_phy_reset(hdptx); 867 868 reset_assert(&hdptx->apb_reset); 869 udelay(10); 870 reset_deassert(&hdptx->apb_reset); 871 872 for (lane = 0; lane < 4; lane++) { 873 u32 invert = hdptx->lane_polarity_invert[lane]; 874 875 phy_update_bits(hdptx, LANE_REG(lane, 0x0c78), LN_POLARITY_INV, 876 FIELD_PREP(LN_POLARITY_INV, invert)); 877 } 878 879 if (mode == PHY_MODE_DP) { 880 grf_write(hdptx, HDPTXPHY_GRF_CON0, HDPTX_MODE_SEL, 881 FIELD_PREP(HDPTX_MODE_SEL, 0x1)); 882 883 phy_update_bits(hdptx, 0x0800, PROTOCOL_SEL, 884 FIELD_PREP(PROTOCOL_SEL, 0x0)); 885 phy_update_bits(hdptx, 0x0818, DATA_BUS_WIDTH, 886 FIELD_PREP(DATA_BUS_WIDTH, 0x1)); 887 phy_update_bits(hdptx, 0x0818, BUS_WIDTH_SEL, 888 FIELD_PREP(BUS_WIDTH_SEL, 0x0)); 889 890 rockchip_hdptx_phy_dp_pll_init(hdptx); 891 rockchip_hdptx_phy_dp_aux_init(hdptx); 892 } else { 893 grf_write(hdptx, HDPTXPHY_GRF_CON0, HDPTX_MODE_SEL, 894 FIELD_PREP(HDPTX_MODE_SEL, 0x0)); 895 896 phy_update_bits(hdptx, 0x0800, PROTOCOL_SEL, 897 FIELD_PREP(PROTOCOL_SEL, 0x1)); 898 } 899 900 return 0; 901 } 902 903 static int rockchip_hdptx_phy_power_off(struct phy *phy) 904 { 905 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); 906 907 rockchip_hdptx_phy_reset(hdptx); 908 909 return 0; 910 } 911 912 static const struct phy_ops rockchip_hdptx_phy_ops = { 913 .set_mode = rockchip_hdptx_phy_set_mode, 914 .configure = rockchip_hdptx_phy_configure, 915 .power_on = rockchip_hdptx_phy_power_on, 916 .power_off = rockchip_hdptx_phy_power_off, 917 }; 918 919 static int rockchip_hdptx_phy_probe(struct udevice *dev) 920 { 921 struct rockchip_hdptx_phy *hdptx = dev_get_priv(dev); 922 struct udevice *syscon; 923 int ret; 924 925 hdptx->base = dev_read_addr_ptr(dev); 926 if (!hdptx->base) 927 return -ENOENT; 928 929 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 930 &syscon); 931 if (ret) 932 return ret; 933 934 hdptx->grf = syscon_get_regmap(syscon); 935 if (IS_ERR(hdptx->grf)) { 936 ret = PTR_ERR(hdptx->grf); 937 dev_err(dev, "unable to find regmap: %d\n", ret); 938 return ret; 939 } 940 941 hdptx->dev = dev; 942 943 ret = reset_get_by_name(dev, "apb", &hdptx->apb_reset); 944 if (ret < 0) { 945 dev_err(dev, "failed to get apb reset: %d\n", ret); 946 return ret; 947 } 948 949 ret = reset_get_by_name(dev, "init", &hdptx->init_reset); 950 if (ret < 0) { 951 dev_err(dev, "failed to get init reset: %d\n", ret); 952 return ret; 953 } 954 955 ret = reset_get_by_name(dev, "cmn", &hdptx->cmn_reset); 956 if (ret < 0) { 957 dev_err(dev, "failed to get cmn reset: %d\n", ret); 958 return ret; 959 } 960 961 ret = reset_get_by_name(dev, "lane", &hdptx->lane_reset); 962 if (ret < 0) { 963 dev_err(dev, "failed to get lane reset: %d\n", ret); 964 return ret; 965 } 966 967 dev_read_u32_array(dev, "lane-polarity-invert", 968 hdptx->lane_polarity_invert, 4); 969 970 return 0; 971 } 972 973 static const struct udevice_id rockchip_hdptx_phy_ids[] = { 974 { .compatible = "rockchip,rk3588-hdptx-phy", }, 975 {} 976 }; 977 978 U_BOOT_DRIVER(rockchip_hdptx_phy) = { 979 .name = "rockchip_hdptx_phy", 980 .id = UCLASS_PHY, 981 .ops = &rockchip_hdptx_phy_ops, 982 .of_match = rockchip_hdptx_phy_ids, 983 .probe = rockchip_hdptx_phy_probe, 984 .priv_auto_alloc_size = sizeof(struct rockchip_hdptx_phy), 985 }; 986