1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 15 #include "../usb/gadget/dwc2_udc_otg_priv.h" 16 17 #define U2PHY_BIT_WRITEABLE_SHIFT 16 18 #define CHG_DCD_MAX_RETRIES 6 19 #define CHG_PRI_MAX_RETRIES 2 20 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 21 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 22 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 23 24 struct rockchip_usb2phy; 25 26 enum power_supply_type { 27 POWER_SUPPLY_TYPE_UNKNOWN = 0, 28 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 29 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 30 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 31 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 32 }; 33 34 enum rockchip_usb2phy_port_id { 35 USB2PHY_PORT_OTG, 36 USB2PHY_PORT_HOST, 37 USB2PHY_NUM_PORTS, 38 }; 39 40 struct usb2phy_reg { 41 u32 offset; 42 u32 bitend; 43 u32 bitstart; 44 u32 disable; 45 u32 enable; 46 }; 47 48 /** 49 * struct rockchip_chg_det_reg: usb charger detect registers 50 * @cp_det: charging port detected successfully. 51 * @dcp_det: dedicated charging port detected successfully. 52 * @dp_det: assert data pin connect successfully. 53 * @idm_sink_en: open dm sink curren. 54 * @idp_sink_en: open dp sink current. 55 * @idp_src_en: open dm source current. 56 * @rdm_pdwn_en: open dm pull down resistor. 57 * @vdm_src_en: open dm voltage source. 58 * @vdp_src_en: open dp voltage source. 59 * @opmode: utmi operational mode. 60 */ 61 struct rockchip_chg_det_reg { 62 struct usb2phy_reg cp_det; 63 struct usb2phy_reg dcp_det; 64 struct usb2phy_reg dp_det; 65 struct usb2phy_reg idm_sink_en; 66 struct usb2phy_reg idp_sink_en; 67 struct usb2phy_reg idp_src_en; 68 struct usb2phy_reg rdm_pdwn_en; 69 struct usb2phy_reg vdm_src_en; 70 struct usb2phy_reg vdp_src_en; 71 struct usb2phy_reg opmode; 72 }; 73 74 /** 75 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 76 * @phy_sus: phy suspend register. 77 * @bvalid_det_en: vbus valid rise detection enable register. 78 * @bvalid_det_st: vbus valid rise detection status register. 79 * @bvalid_det_clr: vbus valid rise detection clear register. 80 * @ls_det_en: linestate detection enable register. 81 * @ls_det_st: linestate detection state register. 82 * @ls_det_clr: linestate detection clear register. 83 * @iddig_output: iddig output from grf. 84 * @iddig_en: utmi iddig select between grf and phy, 85 * 0: from phy; 1: from grf 86 * @idfall_det_en: id fall detection enable register. 87 * @idfall_det_st: id fall detection state register. 88 * @idfall_det_clr: id fall detection clear register. 89 * @idrise_det_en: id rise detection enable register. 90 * @idrise_det_st: id rise detection state register. 91 * @idrise_det_clr: id rise detection clear register. 92 * @utmi_avalid: utmi vbus avalid status register. 93 * @utmi_bvalid: utmi vbus bvalid status register. 94 * @utmi_iddig: otg port id pin status register. 95 * @utmi_ls: utmi linestate state register. 96 * @utmi_hstdet: utmi host disconnect register. 97 * @vbus_det_en: vbus detect function power down register. 98 */ 99 struct rockchip_usb2phy_port_cfg { 100 struct usb2phy_reg phy_sus; 101 struct usb2phy_reg bvalid_det_en; 102 struct usb2phy_reg bvalid_det_st; 103 struct usb2phy_reg bvalid_det_clr; 104 struct usb2phy_reg ls_det_en; 105 struct usb2phy_reg ls_det_st; 106 struct usb2phy_reg ls_det_clr; 107 struct usb2phy_reg iddig_output; 108 struct usb2phy_reg iddig_en; 109 struct usb2phy_reg idfall_det_en; 110 struct usb2phy_reg idfall_det_st; 111 struct usb2phy_reg idfall_det_clr; 112 struct usb2phy_reg idrise_det_en; 113 struct usb2phy_reg idrise_det_st; 114 struct usb2phy_reg idrise_det_clr; 115 struct usb2phy_reg utmi_avalid; 116 struct usb2phy_reg utmi_bvalid; 117 struct usb2phy_reg utmi_iddig; 118 struct usb2phy_reg utmi_ls; 119 struct usb2phy_reg utmi_hstdet; 120 struct usb2phy_reg vbus_det_en; 121 }; 122 123 /** 124 * struct rockchip_usb2phy_cfg: usb-phy configuration. 125 * @reg: the address offset of grf for usb-phy config. 126 * @num_ports: specify how many ports that the phy has. 127 * @phy_tuning: phy default parameters tunning. 128 * @clkout_ctl: keep on/turn off output clk of phy. 129 * @chg_det: charger detection registers. 130 */ 131 struct rockchip_usb2phy_cfg { 132 u32 reg; 133 u32 num_ports; 134 int (*phy_tuning)(struct rockchip_usb2phy *); 135 struct usb2phy_reg clkout_ctl; 136 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 137 const struct rockchip_chg_det_reg chg_det; 138 }; 139 140 /** 141 * @dcd_retries: The retry count used to track Data contact 142 * detection process. 143 * @primary_retries: The retry count used to do usb bc detection 144 * primary stage. 145 * @grf: General Register Files register base. 146 * @usbgrf_base : USB General Register Files register base. 147 * @phy_cfg: phy register configuration, assigned by driver data. 148 */ 149 struct rockchip_usb2phy { 150 u8 dcd_retries; 151 u8 primary_retries; 152 void __iomem *grf_base; 153 void __iomem *usbgrf_base; 154 const struct rockchip_usb2phy_cfg *phy_cfg; 155 }; 156 157 static inline void __iomem *get_reg_base(struct rockchip_usb2phy *rphy) 158 { 159 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 160 } 161 162 static inline int property_enable(void __iomem *base, 163 const struct usb2phy_reg *reg, bool en) 164 { 165 u32 val, mask, tmp; 166 167 tmp = en ? reg->enable : reg->disable; 168 mask = GENMASK(reg->bitend, reg->bitstart); 169 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 170 171 return writel(val, base + reg->offset); 172 } 173 174 static inline bool property_enabled(void __iomem *base, 175 const struct usb2phy_reg *reg) 176 { 177 u32 tmp, orig; 178 u32 mask = GENMASK(reg->bitend, reg->bitstart); 179 180 orig = readl(base + reg->offset); 181 182 tmp = (orig & mask) >> reg->bitstart; 183 184 return tmp == reg->enable; 185 } 186 187 static const char *chg_to_string(enum power_supply_type chg_type) 188 { 189 switch (chg_type) { 190 case POWER_SUPPLY_TYPE_USB: 191 return "USB_SDP_CHARGER"; 192 case POWER_SUPPLY_TYPE_USB_DCP: 193 return "USB_DCP_CHARGER"; 194 case POWER_SUPPLY_TYPE_USB_CDP: 195 return "USB_CDP_CHARGER"; 196 case POWER_SUPPLY_TYPE_USB_FLOATING: 197 return "USB_FLOATING_CHARGER"; 198 default: 199 return "INVALID_CHARGER"; 200 } 201 } 202 203 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 204 bool en) 205 { 206 void __iomem *base = get_reg_base(rphy); 207 208 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 209 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 210 } 211 212 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 213 bool en) 214 { 215 void __iomem *base = get_reg_base(rphy); 216 217 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 218 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 219 } 220 221 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 222 bool en) 223 { 224 void __iomem *base = get_reg_base(rphy); 225 226 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 227 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 228 } 229 230 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 231 { 232 bool vout = false; 233 234 while (rphy->primary_retries--) { 235 /* voltage source on DP, probe on DM */ 236 rockchip_chg_enable_primary_det(rphy, true); 237 mdelay(CHG_PRIMARY_DET_TIME); 238 vout = property_enabled(rphy->grf_base, 239 &rphy->phy_cfg->chg_det.cp_det); 240 if (vout) 241 break; 242 } 243 244 rockchip_chg_enable_primary_det(rphy, false); 245 return vout; 246 } 247 248 int rockchip_chg_get_type(void) 249 { 250 const struct rockchip_usb2phy_port_cfg *port_cfg; 251 enum power_supply_type chg_type; 252 struct rockchip_usb2phy *rphy; 253 struct udevice *udev; 254 void __iomem *base; 255 bool is_dcd, vout; 256 int ret; 257 258 ret = uclass_get_device(UCLASS_PHY, 0, &udev); 259 if (ret == -ENODEV) { 260 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 261 return ret; 262 } 263 264 rphy = dev_get_priv(udev); 265 base = get_reg_base(rphy); 266 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 267 268 /* Check USB-Vbus status first */ 269 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 270 pr_info("%s: no charger found\n", __func__); 271 return POWER_SUPPLY_TYPE_UNKNOWN; 272 } 273 274 /* Suspend USB-PHY and put the controller in non-driving mode */ 275 property_enable(base, &port_cfg->phy_sus, true); 276 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 277 278 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 279 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 280 281 /* stage 1, start DCD processing stage */ 282 rockchip_chg_enable_dcd(rphy, true); 283 284 while (rphy->dcd_retries--) { 285 mdelay(CHG_DCD_POLL_TIME); 286 287 /* get data contact detection status */ 288 is_dcd = property_enabled(rphy->grf_base, 289 &rphy->phy_cfg->chg_det.dp_det); 290 291 if (is_dcd || !rphy->dcd_retries) { 292 /* 293 * stage 2, turn off DCD circuitry, then 294 * voltage source on DP, probe on DM. 295 */ 296 rockchip_chg_enable_dcd(rphy, false); 297 rockchip_chg_enable_primary_det(rphy, true); 298 break; 299 } 300 } 301 302 mdelay(CHG_PRIMARY_DET_TIME); 303 vout = property_enabled(rphy->grf_base, 304 &rphy->phy_cfg->chg_det.cp_det); 305 rockchip_chg_enable_primary_det(rphy, false); 306 if (vout) { 307 /* stage 3, voltage source on DM, probe on DP */ 308 rockchip_chg_enable_secondary_det(rphy, true); 309 } else { 310 if (!rphy->dcd_retries) { 311 /* floating charger found */ 312 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 313 goto out; 314 } else { 315 /* 316 * Retry some times to make sure that it's 317 * really a USB SDP charger. 318 */ 319 vout = rockchip_chg_primary_det_retry(rphy); 320 if (vout) { 321 /* stage 3, voltage source on DM, probe on DP */ 322 rockchip_chg_enable_secondary_det(rphy, true); 323 } else { 324 /* USB SDP charger found */ 325 chg_type = POWER_SUPPLY_TYPE_USB; 326 goto out; 327 } 328 } 329 } 330 331 mdelay(CHG_SECONDARY_DET_TIME); 332 vout = property_enabled(rphy->grf_base, 333 &rphy->phy_cfg->chg_det.dcp_det); 334 /* stage 4, turn off voltage source */ 335 rockchip_chg_enable_secondary_det(rphy, false); 336 if (vout) 337 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 338 else 339 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 340 341 out: 342 /* Resume USB-PHY and put the controller in normal mode */ 343 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 344 property_enable(base, &port_cfg->phy_sus, false); 345 346 debug("charger is %s\n", chg_to_string(chg_type)); 347 348 return chg_type; 349 } 350 351 int rockchip_u2phy_vbus_detect(void) 352 { 353 return (rockchip_chg_get_type() == POWER_SUPPLY_TYPE_USB) ? 1 : 0; 354 } 355 356 void otg_phy_init(struct dwc2_udc *dev) 357 { 358 const struct rockchip_usb2phy_port_cfg *port_cfg; 359 struct rockchip_usb2phy *rphy; 360 struct udevice *udev; 361 void __iomem *base; 362 int ret; 363 364 ret = uclass_get_device(UCLASS_PHY, 0, &udev); 365 if (ret == -ENODEV) { 366 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 367 return; 368 } 369 370 rphy = dev_get_priv(udev); 371 base = get_reg_base(rphy); 372 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 373 374 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 375 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); 376 377 /* Reset USB-PHY */ 378 property_enable(base, &port_cfg->phy_sus, true); 379 udelay(20); 380 property_enable(base, &port_cfg->phy_sus, false); 381 mdelay(2); 382 } 383 384 static int rockchip_usb2phy_init(struct phy *phy) 385 { 386 struct udevice *parent = phy->dev->parent; 387 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 388 const struct rockchip_usb2phy_port_cfg *port_cfg; 389 void __iomem *base = get_reg_base(rphy); 390 391 if (phy->id == USB2PHY_PORT_OTG) { 392 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 393 } else if (phy->id == USB2PHY_PORT_HOST) { 394 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 395 } else { 396 dev_err(phy->dev, "phy id %lu not support", phy->id); 397 return -EINVAL; 398 } 399 400 property_enable(base, &port_cfg->phy_sus, false); 401 402 /* waiting for the utmi_clk to become stable */ 403 udelay(2000); 404 405 return 0; 406 } 407 408 static int rockchip_usb2phy_exit(struct phy *phy) 409 { 410 struct udevice *parent = phy->dev->parent; 411 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 412 const struct rockchip_usb2phy_port_cfg *port_cfg; 413 void __iomem *base = get_reg_base(rphy); 414 415 if (phy->id == USB2PHY_PORT_OTG) { 416 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 417 } else if (phy->id == USB2PHY_PORT_HOST) { 418 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 419 } else { 420 dev_err(phy->dev, "phy id %lu not support", phy->id); 421 return -EINVAL; 422 } 423 424 property_enable(base, &port_cfg->phy_sus, true); 425 426 return 0; 427 } 428 429 static int rockchip_usb2phy_of_xlate(struct phy *phy, 430 struct ofnode_phandle_args *args) 431 { 432 const char *dev_name = phy->dev->name; 433 434 if (!strcasecmp(dev_name, "host-port")) { 435 phy->id = USB2PHY_PORT_HOST; 436 } else if (!strcasecmp(dev_name, "otg-port")) { 437 phy->id = USB2PHY_PORT_OTG; 438 } else { 439 pr_err("%s: invalid dev name\n", __func__); 440 return -EINVAL; 441 } 442 443 return 0; 444 } 445 446 static int rockchip_usb2phy_bind(struct udevice *dev) 447 { 448 struct udevice *child; 449 ofnode subnode; 450 const char *node_name; 451 int ret; 452 453 dev_for_each_subnode(subnode, dev) { 454 if (!ofnode_valid(subnode)) { 455 debug("%s: %s subnode not found", __func__, dev->name); 456 return -ENXIO; 457 } 458 459 node_name = ofnode_get_name(subnode); 460 debug("%s: subnode %s\n", __func__, node_name); 461 462 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 463 node_name, subnode, &child); 464 if (ret) { 465 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 466 __func__, node_name); 467 return ret; 468 } 469 } 470 471 return 0; 472 } 473 474 static int rockchip_usb2phy_probe(struct udevice *dev) 475 { 476 const struct rockchip_usb2phy_cfg *phy_cfgs; 477 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 478 struct udevice *parent = dev->parent; 479 u32 reg, index; 480 481 if (!strncmp(parent->name, "root_driver", 11) && 482 dev_read_bool(dev, "rockchip,grf")) 483 rphy->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 484 else 485 rphy->grf_base = (void __iomem *)dev_read_addr(parent); 486 487 if (rphy->grf_base <= 0) { 488 dev_err(dev, "get syscon grf failed\n"); 489 return -EINVAL; 490 } 491 492 if (dev_read_bool(dev, "rockchip,usbgrf")) { 493 rphy->usbgrf_base = 494 syscon_get_first_range(ROCKCHIP_SYSCON_USBGRF); 495 if (rphy->usbgrf_base <= 0) { 496 dev_err(dev, "get syscon usbgrf failed\n"); 497 return -EINVAL; 498 } 499 } else { 500 rphy->usbgrf_base = NULL; 501 } 502 503 if (ofnode_read_u32(dev_ofnode(dev), "reg", ®)) { 504 dev_err(dev, "could not read reg\n"); 505 return -EINVAL; 506 } 507 508 phy_cfgs = 509 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 510 if (!phy_cfgs) { 511 dev_err(dev, "unable to get phy_cfgs\n"); 512 return -EINVAL; 513 } 514 515 /* find out a proper config which can be matched with dt. */ 516 index = 0; 517 while (phy_cfgs[index].reg) { 518 if (phy_cfgs[index].reg == reg) { 519 rphy->phy_cfg = &phy_cfgs[index]; 520 break; 521 } 522 ++index; 523 } 524 525 if (!rphy->phy_cfg) { 526 dev_err(dev, "no phy-config can be matched\n"); 527 return -EINVAL; 528 } 529 530 return 0; 531 } 532 533 static struct phy_ops rockchip_usb2phy_ops = { 534 .init = rockchip_usb2phy_init, 535 .exit = rockchip_usb2phy_exit, 536 .of_xlate = rockchip_usb2phy_of_xlate, 537 }; 538 539 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 540 { 541 .reg = 0x17c, 542 .num_ports = 2, 543 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 544 .port_cfgs = { 545 [USB2PHY_PORT_OTG] = { 546 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 547 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 548 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 549 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 550 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 551 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 552 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 553 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 554 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 555 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 556 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 557 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 558 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 559 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 560 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 561 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 562 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 563 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 564 }, 565 [USB2PHY_PORT_HOST] = { 566 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 567 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 568 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 569 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 570 } 571 }, 572 .chg_det = { 573 .opmode = { 0x017c, 3, 0, 5, 1 }, 574 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 575 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 576 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 577 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 578 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 579 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 580 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 581 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 582 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 583 }, 584 }, 585 { /* sentinel */ } 586 }; 587 588 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 589 { 590 .reg = 0x100, 591 .num_ports = 2, 592 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 593 .port_cfgs = { 594 [USB2PHY_PORT_OTG] = { 595 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 596 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 597 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 598 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 599 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 600 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 601 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 602 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 603 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 604 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 605 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 606 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 607 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 608 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 609 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 610 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 611 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 612 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 613 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 614 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 615 }, 616 [USB2PHY_PORT_HOST] = { 617 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 618 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 619 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 620 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 621 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 622 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 623 } 624 }, 625 .chg_det = { 626 .opmode = { 0x0100, 3, 0, 5, 1 }, 627 .cp_det = { 0x0120, 24, 24, 0, 1 }, 628 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 629 .dp_det = { 0x0120, 25, 25, 0, 1 }, 630 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 631 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 632 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 633 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 634 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 635 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 636 }, 637 }, 638 { /* sentinel */ } 639 }; 640 641 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 642 { 643 .reg = 0x100, 644 .num_ports = 2, 645 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 646 .port_cfgs = { 647 [USB2PHY_PORT_OTG] = { 648 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 649 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 650 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 651 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 652 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 653 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 654 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 655 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 656 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 657 }, 658 [USB2PHY_PORT_HOST] = { 659 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 660 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 661 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 662 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 663 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 664 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 665 } 666 }, 667 .chg_det = { 668 .opmode = { 0x0100, 3, 0, 5, 1 }, 669 .cp_det = { 0x0804, 1, 1, 0, 1 }, 670 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 671 .dp_det = { 0x0804, 2, 2, 0, 1 }, 672 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 673 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 674 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 675 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 676 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 677 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 678 }, 679 }, 680 { /* sentinel */ } 681 }; 682 683 static const struct udevice_id rockchip_usb2phy_ids[] = { 684 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 685 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 686 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 687 { } 688 }; 689 690 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 691 .name = "rockchip_usb2phy_port", 692 .id = UCLASS_PHY, 693 .ops = &rockchip_usb2phy_ops, 694 }; 695 696 U_BOOT_DRIVER(rockchip_usb2phy) = { 697 .name = "rockchip_usb2phy", 698 .id = UCLASS_PHY, 699 .of_match = rockchip_usb2phy_ids, 700 .probe = rockchip_usb2phy_probe, 701 .bind = rockchip_usb2phy_bind, 702 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 703 }; 704